SI4704-D50-GM - Silicon Labs

Si4704/05-D50

BROADCAST FM RADIO RECEIVER FOR CONSUMER

ELECTRONICS

Features

Applications

Description

The Si4704/05-D50 FM/RDS/RDBS receivers provide the highest performance

and lowest power consumption available for portable devices today. The 100%

CMOS IC integrates the complete FM and data receiver function from antenna to

analog or digital audio and data out in a single 3 x 3 mm 20-pin QFN.

Functional Block Diagram

Worldwide FM band support

(64–108 MHz)

RDS/RBDS decoding engine

(Si4705 only)

Lowest power consumption

Received signal quality indicators

On-chip tuned resonance for

embedded antenna support

Multipath detection and mitigation

FM Hi-cut control

Advanced FM stereo-mono blend

Advanced audio processing

Not EN 55020 compliant*

Automatic gain control (AGC)

Integrated FM LNA

Image-rejection mixer

Frequency synthesizer with

integrated VCO

Low-IF direct conversion with no

external ceramic filters

2.7 to 5.5 V supply voltage

Dual 1.8 and 2.7 V power supplies

Stereo audio out

I2S Digital audio out

20-pin 3 x 3 mm QFN package

Pb-free/RoHS compliant

*Note: *For consumer electronics applications that require EN 55020 compliance,

use Si4704/05-D60.

Cellular handsets

Portab l e medi a de v ic es

Dedicated data receiver

Personal navigation devices (PND)

GPS-enabled handsets and portable

devices

ADC

Si4704/05

DSP

DAC

DAC ROUT

LOUT

AFC

DIGITAL INTERFACE

GPO

RFGND LNA

FMI

AGC

PGA

(TYP)

RCLK

REG

2.7–5.5 V

FM Antenna

XTAL

OSC

LPI

32.768 kHz

0/90

DOUT

DCLK

DFS

1.62–3.6 V

SCLK

SDIO

CONTROL

INTERFACE

SEN

RSSI

RST

RDS

(Si4705)

This product, its features, and/or its

architecture is covered by one or

more of the following p atent s, as we ll

as other patents, pending and

issued, both foreign and domestic:

7,127,217; 7,272,373; 7,272,375;

7,321,324; 7,355,476; 7,426,376;

7,471,940; 7,339,503; 7,339,504.

Ordering Information:

See page 27.

Pin Assignments

GND

PAD

17181920

6789

GPO2/INT

DOUT

LOUT

ROUT

GNDRST

LPI

RCLK

SDIO

FMI

RFGND

GPO3/DCLK

GPO1

DFS

SCLK

SEN

Si4704/05-GM

(Top View)

Si4704/05-D50

2 Rev. 1.0

Si4704/05-D50

Rev. 1.0 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.3. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.4. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.5. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.6. Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.7. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.8. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.9. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.10. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.11. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.12. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.13. Embedded Antenna Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.14. RDS Decoder (Si4705 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.15. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.16. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.17. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.18. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.19. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6. Pin Descriptions: Si4704/05-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

8. Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

8.1. Si4704 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

8.2. Si4705 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

8.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

9. Package Outline: Si4704/05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

10. PCB Land Pattern: Si4704/05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Document Change List: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Si4704/05-D50

4 Rev. 1.0

1. Electrical Specifications

Table 1. Recommended Operating Conditions*

Parameter Symbol Test Condition Min Typ Max Unit

Analog Supply Voltage VA 2.7 — 5.5 V

Digital and Interface Supply Voltage VD1.62 — 3.6 V

Analog Power Supply Powerup Rise

Time VARISE 10 — — µs

Digital Power Supply Powerup Rise

Time VDRISE 10 — — µs

Ambient Temperature TA–20 25 85 C

*Note: All minimum and maximum specifications are guara nteed and apply across the recommended operating conditions.

Typical values apply at VA= 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless

otherwise stated.

Table 2. Absolute Maximum Ratings1,2

Parameter Symbol Value Unit

Analog Supply Voltage VA –0.5 to 5.8 V

Digital and Interface Supply Voltage VD–0.5 to 3.9 V

Input Current3IIN 10 mA

Input Voltage3VIN –0.3 to (VIO + 0.3) V

Operating Temperature TOP –40 to 95 C

Storage Temperature TSTG –55 to 150 C

RF Input Level40.4 VpK

Notes:

1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functi onal operation

should be restricted to the conditions as specified in th e operational sections of this data sheet. Exposure beyond

recommended operating conditions for exte nded periods may affect device reliability.

2. The Si4704/05 devices are hi gh-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV

HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.

3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, GPO3, and DCLK.

4. At RF input pins FMI and LPI.

Si4704/05-D50

Rev. 1.0 5

Table 3. DC Characteristics

(VA= 2.7 to 5.5 V, VD= 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

FM Receiver to Line Output

VA Supply Current IFMVA —7.59.7mA

VD Supply Current IFMVD Digital Output Mode1— 8.5 11.1 mA

VD Supply Current IFMVD Analog Output Mode — 8.4 11.1 mA

Powerdown and Interface

VA Powerdown Current IDDPD —415 µA

VD Powerdown Current IIOPD SCLK, RCLK inactive — 3 10 µA

High Level Input Voltage2VIH 0.7 x VD—V

D+0.3 V

Low Level Input Voltage2VIL –0.3 — 0.3 x VDV

High Level Input Current2IIH VIN =V

D=3.6V –10 — 10 µA

Low Level Input Current2IIL VIN =0V,

VD=3.6V –10 — 10 µA

High Level Output Voltage3VOH IOUT = 500 µA 0.8 x VD——V

Low Level Output Voltage3VOL IOUT = –500 µA — — 0.2 x VDV

Notes:

1. Guaranteed by characterization.

2. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.

3. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.

Si4704/05-D50

6 Rev. 1.0

Figure 1. Reset Timing Parameters for Busmode Select Method

Table 4. Reset Timing Characteristics1,2,3

(VA= 2.7 to 5.5 V, VD= 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Min Typ Max Unit

RST Pulse Width and GPO1, GPO2/INT Setup to RSTtSRST 100 — — µs

GPO1, GPO2/INT Hold from RSTtHRST 30 — — ns

Important Notes:

1. When selecting 2-wire mode, the user must ensu r e that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until

after the first start condition.

3. When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the

rising edge of RST.

4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is high

impedance, then minimum tSRST is 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull

GPO1 high and GPO2 low.

70%

30%

GPO1 70%

30%

GPO2 70%

30%

tSRST

RST

tHRST

Si4704/05-D50

Rev. 1.0 7

Table 5. 2-Wire Control Interface Characteristics1,2,3

(VA= 2.7 to 5.5 V, VD= 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fSCL 0 — 400 kHz

SCLK Low Time tLOW 1.3 — — µs

SCLK High Time tHIGH 0.6 — — µs

SCLK Input to SDIO  Setup

(START) tSU:STA 0.6 — — µs

SCLK Input to SDIO  Hold

(START) tHD:STA 0.6 — — µs

SDIO Input to SCLK  Setup tSU:DAT 100 — — ns

SDIO Input to SCLK  Hold 4, 5 tHD:DAT 0 — 900 ns

SCLK Input to SDIO  Setup

(STOP) tSU:STO 0.6 — — µs

STOP to START Time tBUF 1.3 — — µs

SDIO Output Fall Time tf:OUT — 250 ns

SDIO Input, SCLK Rise/Fall Time tf:IN

tr:IN

— 300 ns

SCLK, SDIO Capacitive Loading Cb——50pF

Input Filter Pulse Suppression tSP — — 50 ns

Notes:

1. When VD= 0 V, SCLK and SDIO are low impedance.

2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high

until after the first start condition.

4. The Si4704/05 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimu m

tHD:DAT specification.

5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 kHz, tHD:DAT may be violated

as long as all other timing parameters are met.

20 0.1 Cb

1pF

-----------

20 0.1 Cb

1pF

-----------

Si4704/05-D50

8 Rev. 1.0

Figure 2. 2-Wire Control Interface Read and Write Timing Parameters

Figure 3. 2-Wire Control Interface Read and Write Timing Diagram

SCLK 70%

30%

SDIO 70%

30%

START STARTSTOP

tf:IN

tr:IN

tLOW tHIGH

tHD:STA

tSU:STA tSU:STO

tSP tBUF

tSU:DAT

tr:IN tHD:DAT tf:IN ,

tf:OUT

SCLK

SDIO

START STOPADDRESS + R/W ACK DATA ACK DATA ACK

A6-A0,

R/W D7-D0 D7-D0

Si4704/05-D50

Rev. 1.0 9

Figure 4. 3-Wire Control Interface Write Timing Parameters

Figure 5. 3-Wire Control Interface Read Timing Parameters

Table 6. 3-Wire Control Interface Characteristics

(VA= 2.7 to 5.5 V, VD= 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Co ndit io n Mi n Typ Max Unit

SCLK Frequency fCLK 0—2.5MHz

SCLK High Time tHIGH 25 — — ns

SCLK Low Time tLOW 25 — — ns

SDIO Input, SEN to SCLK Setup tS20 — — ns

SDIO Input to SCLK Hold tHSDIO 10 — — ns

SEN Input to SCLK Hold tHSEN 10 — — ns

SCLK to SDIO Output Valid tCDV Read 2 — 25 ns

SCLK to SDIO Output High Z tCDZ Read 2 — 25 ns

SCLK, SEN, SDIO, Rise/Fall Time tR, tF— — 10 ns

SCLK 70%

30%

SEN 70%

30%

SDIO A7 A0

70%

30%

tHSDIO tHSEN

A6-A5,

R/W,

A4-A1

Address In Data In

D15 D14-D1 D0

tHIGH tLOW

tRtF

½ C ycle Bus

Turnaround

SCLK 70%

30%

SEN 70%

30%

SDIO 70%

30%

tHSDIO tCDV tCDZ

Address In Data O u t

A7 A0

A6-A5,

R/W,

A4-A1 D15 D14-D1 D0

tStHSEN

Si4704/05-D50

10 Rev. 1.0

Figure 6. Digital Audio Interface Timing Parameters, I2S Mode

Table 7. Digital Audio Interface Characteristics

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

DCLK Cycle Time tDCT 26 — 1000 ns

DCLK Pulse Width High tDCH 10 — — ns

DCLK Pulse Width Low tDCL 10 — — ns

DFS Setup T ime to DCLK Rising Edge tSU:DFS 5—— ns

DFS Hold Time from DCLK Rising Edge tHD:DFS 5—— ns

DOUT Propagation Delay from DCLK Falling

Edge tPD:DOUT 0—12ns

DCLK

DFS

tDCT

tPD:OUT

tSU:DFS

tHD:DFS

DOUT

tDCH tDCL

Si4704/05-D50

Rev. 1.0 11

Table 8. FM Receiver Characteristics1,2

(VA= 2.7 to 5.5 V, VD= 1.62 to 3.6 V, TA= –20 to 85 °C, 76–108 MHz)

Parameter Symbol Test Condition Min Typ Max Unit

Input Frequency fRF 76 — 108 MHz

Sensitivity3,4,5 (S+N)/N = 26 dB — 2.2 3.5 µV EMF

RDS Sensitivity6f = 2 k Hz,

RDS BLER < 5% —11—µV EMF

LNA Input Resistance6,7 345k

LNA Input Capacitance6,7 456pF

Input IP36,8 100 105 — dBµV EMF

AM Suppression3,4,6,7 m = 0.3 40 50 — dB

Adjacent Channel Selectivity ±200 kHz 35 50 — dB

Alternate Channel Selectivity ±400 kHz 60 70 — dB

Spurious Response Rejection6In-band 35 — — dB

Audio Output Voltage3,4,7 72 80 90 mVRMS

Audio Output L/R Imbalance3,7,9 —— 1 dB

Audio Frequency Response Low6–3 dB — — 30 Hz

Audio Frequency Response High6–3 dB 15 — — kHz

Audio Stereo Separation7,9 35 42 — dB

Audio Mono S/N3,4,5,7 55 63 — dB

Audio Stereo S/N4,5,6,7 —58— dB

Audio THD3,7,9 —0.10.5 %

De-emphasis Time Constant6FM_DEEMPHASIS = 2 70 75 80 µs

FM_DEEMPHASIS = 1 45 50 54 µs

Blocking Sensitivity3,4,5,6,12,13 f = ±400 kHz — 34 — dBµV

f = ±4 MHz — 30 — dBµV

Notes:

1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”

Volume = maximum for all tests. Tested at RF = 98.1 MHz.

2. To ensure proper operation and receiver performance, follo w the guidelines in “AN383: Si47xx Antenna, Schematic,

Layout, and Design Guidelines.” Sili con Laboratories will evaluate schematics and layouts for qualified custome r s.

3. FMOD =1kHz, 75µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.

4. f = 22.5 kHz.

5. BAF = 300 Hz to 15 kHz, A-weighted.

6. Guaranteed by characterization.

7. VEMF =1 mV.

8. |f2 – f1| > 2 MHz, f0=2xf

1 – f2. AGC is disabled.

9. f = 75 kHz.

10. At LOUT and ROUT pins.

11. Analog audio output mode.

12. Blocker Amplitude = 100 dBµV

13. Sensitivity measured at (S+N)/N = 26 dB.

14. At temperature (25°C).

Si4704/05-D50

12 Rev. 1.0

Intermod Sensitivity3,4,5,6,12,13 f = ±400 kHz, ±800 kHz — 40 — dBµV

f = ±4 MHz, ±8 MHz — 35 — dBµV

Audio Output Load Resistance6,10 RLSingle-ended 10 — — k

Audio Output Load Capacitance6,10 CLSingle-ended — — 50 pF

Seek/Tune Tim e 6RCLK tolerance

=100ppm — — 60 ms/channel

Powerup Time6From powerdown — — 110 ms

RSSI Offset14 Input levels of 8 and

60 dBµV at RF Input –3 — 3 dB

Table 8. FM Receiver Characteristics1,2 (Continued)

(VA= 2.7 to 5.5 V, VD= 1.62 to 3.6 V, TA= –20 to 85 °C, 76–108 MHz)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”

Volume = maximum for all tests. Tested at RF = 98.1 MHz.

2. To ensure proper operation and receiver performance, follo w the guidelines in “AN383: Si47xx Antenna, Schematic,

Layout, and Design Guidelines.” Sili con Laboratories will evaluate schematics and layouts for qualified custome r s.

3. FMOD =1kHz, 75µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.

4. f = 22.5 kHz.

5. BAF = 300 Hz to 15 kHz, A-weighted.

6. Guaranteed by characterization.

7. VEMF =1 mV.

8. |f2 – f1| > 2 MHz, f0=2xf

1 – f2. AGC is disabled.

9. f = 75 kHz.

10. At LOUT and ROUT pins.

11. Analog audio output mode.

12. Blocker Amplitude = 100 dBµV

13. Sensitivity measured at (S+N)/N = 26 dB.

14. At temperature (25°C).

Si4704/05-D50

Rev. 1.0 13

Table 9. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,6

(VA= 2.7 to 5.5 V, VD= 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Input Frequency fRF 64 — 75.9 MHz

Sensitivity3,4,5 (S+N)/N = 26 dB — 3.5 — µV EMF

LNA Input Resistance7345k

LNA Input Capacitance7456pF

Input IP38— 105 — dBµV EMF

AM Suppression3,4,7 m = 0.3 — 50 — dB

Adjacent Channel Selectivity ±200 kHz — 50 — dB

Alternate Channel Selectivity ±400 kHz — 70 — dB

Audio Output Voltage3,4,7 72 80 90 mVRMS

Audio Output L/R Imbalance3,7,9 —— 1 dB

Audio Frequency Response Low –3 dB — — 30 Hz

Audio Frequency Response High –3 dB 15 — — kHz

Audio Mono S/N3,4,5,7,10 —63— dB

Audio THD3,7,9 —0.1— %

De-emphasis Time Constant FM_DEEMPHASIS = 2 70 75 80 µs

FM_DEEMPHASIS = 1 45 50 54 µs

Audio Output Load Resistance10 RLSingle-ended 10 — — k

Audio Output Load Capacitance10 CLSingle-ended — — 50 pF

Seek/Tune Time RCLK tolerance

=100ppm — — 60 ms/channel

Powerup Time From powerdown — — 110 ms

RSSI Offset11 Input levels of 8 and

60 dBµV EMF –3 — 3 dB

Notes:

1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.”

Volume = maximum for all tests. Tested at RF = 98.1 MHz.

2. To ensure proper operation and receiver performance, follo w the guidelines in “AN383: Si47xx Antenna, Schematic,

Layout, and Design Guidelines.” Sili con Laboratories will evaluate schematics and layouts for qualified custome r s.

3. FMOD =1kHz, 75µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.

4. f = 22.5 kHz.

5. BAF = 300 Hz to 15 kHz, A-weighted.

6. Guaranteed by characterization.

7. VEMF =1 mV.

8. |f2 – f1| > 2 MHz, f0=2xf

1 – f2. AGC is disabled.

9. f = 75 kHz.

10. At LOUT and ROUT pins.

11. At temperature (25 °C).

Si4704/05-D50

14 Rev. 1.0

Table 10. Reference Clock and Crystal Characteristics

(VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Reference Clo c k

RCLK Supported Frequencies1,2 31.130 32.768 40,000 kHz

RCLK Frequency Tolerance1,3 –100 — 100 ppm

REFCLK_PRESCALE1,2 1 — 4095

REFCLK131.130 32.768 34.406 kHz

Crystal Oscillator

Crystal Oscillator Frequency1— 32.768 — kHz

Crystal Frequency Tolerance1,3 –100 — 100 ppm

Board Capacitance1——3.5pF

ESR 40 k

CL Single-ended 12 pF

Notes:

1. Guaranteed by characterization.

2. The Si4704/05 divide the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies

between 31.130 kHz and 40 MHz that are not supporte d. Se e “AN332: Si47xx Programming Guide,” Table 6 for more

details.

3. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.

Si4704/05-D50

Rev. 1.0 15

2. Typical Application Schematic

Notes:

1. Place C1 close to V A pin.

2. Pins 1 and 20 are no connects, leave floating.

3. Place C4 close to DFS pin.

4. To ensure proper operation and receiver performance, follo w the guidelines in “AN383: Si47xx Antenna, Schematic,

Layout, and Design Guidelines.” Sili con Laboratories will evaluate schematics and layouts for qualified custo me r s.

5. Pin 2 or Pin 4 connects to the FM antenna interface. Pin 2 is for a half-wave antenna. Pin 4 is for an embedded antenna.

6. Place Si4704/05 as close as possible to antenna jack and keep th e FMI and LPI traces as short as possi ble.

1NC

FMI

RFGND

LPI

RSTB

SENB

SCLK

SDIO

RCLK

GND

ROUT

LOUT

DOUT

GPO1

GPO2/INT

GPO3/DCLK

DFS

Si4704/05

RCLKGPO3

2.7 to 5.5 V

OPMODE: 0xB0, 0xB5

Optional: Digital Audio Out

GPO1

GPO3/DCLK

DOUT

DFS

SCLK

SDIO

RCLK

1.62 to 3.6 V

ROUT

SENB

D50

Embedded Antenna

FM Antenna

Optional: For Crystal OSC

LOUT

RSTB

GPO2/INT

Si4704/05-D50

16 Rev. 1.0

3. Bill of Materials

Table 11. Si4704/05-D50 Bill of Materials

Component(s) Value/Description Supplier

C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata

C2 Coupling capacitor, 1 nF, ±20%, Z5U/X7R Murata

C4 Supply bypass capacitor, 100 nF, 10%, Z5U/X7R Murata

U1 Si4704/05 FM Radio Tuner Silicon Laboratories

R1 Resistor, 600 

(Optional for digital audio) Venkel

R2 Resistor, 2 k

(Optional for digital audio) Venkel

R3 Resistor, 2 k

(Optional for digital audio) Venkel

C5, C6 Crystal load capacitors, 22 pF, ±5%, COG

(Optional for crystal oscillator option) Venkel

C9 Noise mitigating capacitor, 2~5 pF

(Optional for digital audio) Murata

X1 32.768 kHz crystal

(Optional for crystal oscillator option) Epson

Si4704/05-D50

Rev. 1.0 17

4. Functional Description

4.1. Overview

Figure 7. Functional Block Diagram

The Si4704/05-D50 offers advanced audio processing

plus advanced RDS processing in a very small, 100%

CMOS receiver integrated circuit. The device provides

both analog and digital audio out, and a highly flexible

RDS pre-processor and 100 block RDS buffer. It is an

ideal product for handsets and portable devices seeking

to optimize both sound and data receiver performance.

For sound, the advanced audio processing is

unprecedented in portable devices. For RDS data

applications such as song-tagging, meta-data, traffic

message channel, or other open data applications, the

advanced and patented R(B)DS decoding engine offers

outstanding data synchronization and integrity. The

RDS engine includes demodulation, symbol decoding,

advanced error correction, detailed visibility to block-

error rates (BLER), advanced decoder reliability, and

synchronization status. The Si4704/05 provides

complete, decoded and error-corrected RDS groups

(100 blocks), up to 25 groups at a time. The Si4704/05

offers several modes of operation for various

applications which require more or less visibility to the

RDS status and group data.

*Note: The term “RDS” will be used to mean “RDS/RBDS”

throughout the document.

The Si4704/05 receiver draws on Silicon Laboratories’

broadcast audio expertise and patent portfolio, using a

digital low intermediate frequency (low-IF) receiver

architecture proven by hundreds of millions of Silicon

Laboratories’ broadcast audio receivers shipped

worldwide.

Silicon Labs has shipped 1/2 billion broadcast audio

receivers worldwide using this architecture. The low-IF

architecture allows the Si4704/05 to deliver superior

performance while integrating the great majority of

external components required by competing solutions.

The Si4704/05 digital integration reduces the required

external components of traditional offerings, resulting in

a solution requiring only an external bypass capacitor

and occupying board space of approximately 15 mm2.

The Si4704/05 is the first FM radio receiver IC to

support embedded a ntenna technology, allowing the FM

antenna to be integrated into the enclosure or PCB of a

portable device. Refer to “AN383: Si47xx Antenna,

Schematic, Layout, And Design Guidelines” for antenna

design guidelines.

The Si4704/05 is feature-rich, providing highly

automated performance with default settings and

extensive programmability and flexibility for customized

system performance.

ADC

Si4704/05

DSP

DAC

DAC ROUT

LOUT

AFC

DIGITAL INTERFACE

GPO

RFGND LNA

FMI

AGC

PGA

(TYP)

RCLK

REG

2.7–5.5 V

FM Antenna

XTAL

OSC

LPI

32.768 kHz

0/90

DOUT

DCLK

DFS

1.62–3.6 V

SCLK

SDIO

CONTROL

INTERFACE

SEN

RSSI

RST

RDS

(Si4705)

Si4704/05-D50

18 Rev. 1.0

The Si4704/05 performs much of the FM demodulation

digitally to achieve high fidelity, optimal performance

versus power consumption, and flexibility of design. The

on-board DSP provides unmatched pilot rejection,

selectivity, and optimum sound quality. The integrated

micro-controller offers both the manufacturer and the

end-user unmatched programmability and flexibility in

the listening experience.

4.2. FM Receiver

The

Si4704/05

FM receiver is based on the proven

Si4700/01/02/03/04/05 FM radio receiver.

The part

leverages Silicon Laboratories' proven and patented FM

broadcast radio receiver digital architecture, delivering

excellent RF performance and interference rejection.

The proven digital techniques provide good sensitivity in

weak signal environments while allowing superb

selectivity and inter-modulation immunity in strong signal

environments.

The part supp ort s the worldwide FM broadcast ban d (64

to 108 MHz) with channel spacings of 50–200 kHz. The

low-IF architecture utilizes a single converter stage and

digitizes the signal using a high-resolution analog-to-

digital converter. The audio output can be directed

either to an external headphone amplifier via analog

in/out or to other system ICs through digital audio

interface (I2S) (Si4705 only).

4.3. Stereo Audio Processing

The output of the FM demodulator is a stereo

multiplexed (MPX) signal. The MPX standard was

developed in 1961, and is used worldwide. Today's

MPX signal format consists of left + right (L+R) audio,

left – right (L–R) audio, a 19 kHz pilot tone, and

RDS/RBDS data as shown in Figure 8.

Figure 8. MPX Signal Spectrum

4.3.1. Stereo Dec oder

The Si4704/05 integrated stereo decoder automatically

decodes the MPX signal using DSP techniques. The 0

to 15 kHz (L+R) signal is the mono output of the FM

tuner. Stereo is generated from the (L+R), (L–R), and a

19 kHz pilot tone. The pilot tone is used as a reference

to recover the (L–R) signal. Output left and right

channels are obtained by adding and subtracting the

(L+R) and (L–R) signals, respectively.

4.3.2. Stereo-Mono Blending

Adaptive noise suppression is employed to gradually

combine the stereo left and right audio channels to a

mono (L+R) audio signal as the signal quality degrades

to maintain optimum sound fidelity under varying

reception conditions. Three metrics, received signal

strength indicator (RSSI), signal-to-noise ratio (SNR),

and multipath interference, are monitored

simultaneously in forcing a blend from stereo to mono.

The metric which reflects the minimum signal quality

takes precedence and the signal is blended

appropriately.

All three metrics have programmable stereo/mono

thresholds and attack/release rates detailed in “AN332:

Si47xx Programming Guide.” If a metric falls below its

mono threshold, the signal is blended from stereo to full

mono. If all metrics are above their respective stereo

thresholds, then no action is taken to blend the signal. If

a metric falls between its mono and stereo thresholds,

then the signal is blended to the level proportional to the

metric’s value between its mono and stereo thresholds,

with an associated attack and release rate.

Stereo/mono status can be monitored with the

FM_RSQ_STATUS command.

4.4. Received Signal Qualifiers

The quality of a tuned signal can vary depending on

many factors including envir onmenta l conditions, time of

day, and position of the ante nna. To adequately manage

the audio output and avoid unplea sant audibl e ef fe ct s to

the end-user, the Si4704/05-D50 monitors and provides

indicators of the signal quality, allowing the host

processor to perform additional processing if required

by the customer. The Si4704/05-D50 monitors signal

quality metrics including RSSI, SNR, and multipath

interference on FM signals. These metrics are used to

optimize signal processing and are also reported to the

host processor. The signal processing algorithms can

use either Silicon Labs' optimized settings

(recommended) or be customized to modify

performance.

0575338231915 Frequency (kHz)

Modulation Level

Stereo Audio

Left - Right RDS/

RBDS

Mono Audio

Left + Right Stereo

Pilot

Si4704/05-D50

Rev. 1.0 19

4.5. De-emphasis

Pre-emphasis and de-emphasis is a technique used by

FM broadcasters to improve the signal-to-noise ratio of

FM receivers by reducing the effects of high-frequency

interference and noise. When the FM signal is

transmitted, a pre-emphasis filter is applied to

accentuate the high audio frequencies. The Si4704/05

incorporates a de-emphasis filter that attenuates high

frequencies to restore a flat frequency response. Two

time constants are used in various regions. The de-

emphasis time constant is programmable to 50 or 75 µs

and is set by the FM_DEEMPHASIS property.

4.6. Volume Control

The audio output may be muted. Volume is adjusted

digitally by th e RX_VOLUME property.

4.7. Stereo DAC

High-fidelity stereo digital-to-analog converters (DACs)

drive analog audio signals onto the LOUT and ROUT

pins. The audio output may be muted. Volume is

adjusted digitally with the RX_VOLUME property.

4.8. Soft Mute

The sof t mute feature is available to attenuate the audio

outputs and minimize audible noise in very weak signal

conditions. The soft mute feature is triggered by the

SNR metric. The SNR threshold for activating soft mute

is programmable, as are soft mute attenuation levels

and attack and release rates.

4.9. FM Hi-Cut Control

Hi-cut control is employed on audio outputs with

degradation of the signal due to low SNR and/or

multipath interference. Two metrics, SNR and multipath

interference , are monitored concurrently in forcing hi-cut

of the audio outputs. Programmable minimum and

maximum thresholds are available for both metrics. The

transition frequency for hi- cut is also programmable with

up to seven hi-cut filter settings. A single set of attack

and release rates for hi-cut are programmable for both

metrics from a range of 2 ms to 64 s. The level of hi-cut

applied can be monitored with the FM_RSQ_STATUS

command. Hi-cut can be disabled by setting the hi-cut

filter to audio bandwidth of 15 kHz.

4.10. Tuning

The frequency synthesizer uses Silicon Laboratories’

proven technology, including a completely integrated

VCO. The frequency synthesizer generates the

quadrature local oscillator signal used to downconvert

the RF input to a low intermediate frequency. The VCO

frequency is locked to the re ference clock an d adjusted

with an automatic frequency control (AFC) servo loop

during reception. The tuning frequency can be directly

programmed using the FM_TUNE_FREQ. The

Si4704/05 supports channel spacing of 50, 100, or

200 kHz in FM mode.

4.11. Seek

The Si4704/05 seek functionality is performed

completely on-chip and will search up or down the

selected frequency band for a valid channel. A valid

channel is qualified according to a series of

programmable signal indicators and thresholds. The

seek function can be made to stop at the band edge and

provide an interrupt, or wrap the band and continue

seeking until arriving at th e original dep arture frequ ency.

The device sets interrupts with found valid stations or, if

the seek results in zero found valid stations, the device

indicates failure and again sets an interrupt.(Refer to

“AN332: Si47xx Programming Guide”.

The Si4704/05-D50 uses RSSI, SNR, and AFC to

qualify stations. Most of these variables have

programmable thresholds for modifying the seek

function according to customer needs.

RSSI is employed first to screen all possible candidate

stations. SNR and AFC are subsequently used in

screening the RSSI qualified stations. The more

thresholds the system engages, the higher the

confidence that any found stations will indeed be valid

broadcast stations. The Si4704/05-D50 defaults set

RSSI to a mid-level threshold and add an SNR

threshold set to a level delivering acceptable audio

performance. This trade-off will eliminate very low RSSI

stations while keeping the seek time to acceptable

levels. Generally, the time to auto-scan and store valid

channels for an entire FM band with all thresholds

engaged is very short depending on the band content.

Seek is initiated using the FM_SEEK_START

command. The RSSI, SNR, and AFC threshold settings

are adjustable using properties.

Si4704/05-D50

20 Rev. 1.0

4.12. Digital Audio Interface

The digital audio interface operates in slave mode and

supports a variety of MSB-first audio data formats

including I2S and left-justified modes. The interface has

three pins: digital data input (DIN), digital frame

synchronization input (DFS), and a digital bit

synchronization input clock (DCLK). The Si4705

supports a number of industry-standard sampling rates

including 32, 40, 44.1, and 48 kHz. The digital audio

interface enables low-power operation by eliminating

the need for redundant DACs and ADCs on the audio

baseband pr oc essor.

4.12.1. Audio Data Formats

The digital audio interface operates in slave mode and

supports three different aud i o da ta formats:

I2S

Left-Justified

DSP Mode

In I2S mode, by default the MSB is captured on the

second rising edge of DCLK following each DFS

transition. The remaining bits of the word are sent in

order, down to the LSB. The left channel is transferred

first when the DFS is low, and the right channel is

transferred when the DFS is high.

In left-justified mode, by default the MSB is captured on

the first rising edge of DCLK following each DFS

transition. The remaining bits of the word are sent in

order, down to the LSB. The left channel is transferred

first when the DFS is high, and the right channel is

transferred when the DFS is low.

In DSP mode, the DFS becomes a pulse with a width of

1DCLK period. The left channel is transferred first,

followed right away by the right channel. There are two

options in transferring the digital audio data in DSP

mode: the M SB of the left channel can be tr ansferred on

the first rising edge of DCL K following the DFS pulse or

on the second rising edge.

In all audio formats, depending on the word size, DCLK

frequency, and sample rates, there may be unused

DCLK cycles after the L SB of e ach word befo re the next

DFS transition and MSB of the next word. In addition, if

preferred, the user can configure the MSB to be

captured on the falling edge of DCLK via properties.

The number of audio bits can be configured for 8, 16,

20, or 24 bits.

4.12.2. Audio Sample Rates

The device supports a number of industry-standard

sampling rates including 32, 40, 44.1, and 48 kHz. The

digital audio interface enables low-power operation by

eliminating the need for redundant DACs on the audio

baseband processor.

Si4704/05-D50

Rev. 1.0 21

Figure 9. I2S Digital Audio Format

Figure 10. Left-Justified Digital Audio Format

Figure 11. DSP Digital Audio Format

LEFT CHANNEL RIGHT CHANNEL

1 DCLK 1 DCLK

132nn-1

n-2 132n

n-1n-2

LSBMSB

DCLK

DOUT

DFS

INVERTED

DCLK

(OFALL = 1)

(OFALL = 0)

I2S

(OMODE = 0000 )

LEFT CHANNEL RIGHT CHANNEL

132nn-1n-2 132nn-1

n-2

LSBMSB

DCLK

DOUT

DFS

INVERTED

DCLK

(OFALL = 1)

(OFALL = 0)

Left-Justified

(OMODE = 0110)

132nn-1n-2 nn-1n-2

LSBMSB

DCLK

DOUT

(MSB at 1st rising edge)

DFS

132

LEFT CHANNEL RIGHT CHANNEL

1 DCLK

(OFALL = 0)

(OMODE = 1100)

132nn-1n-2 nn-1n-2

LSBMSB

132

LEFT CHANNEL RIGHT CHANNEL

DOUT

(MSB at 2nd rising edge)

(OMODE = 1000)

Si4704/05-D50

22 Rev. 1.0

4.13. Embedded Antenna Support

The Si4704/05 is the first FM receiver to support the fa st

growing trend to integrate the FM receiver antenna into

the device enclosure. The chip is designed with this

function in mind from the outset, with multiple

international patents pending, th us it is superior to many

other option s in price , bo ar d space, and pe rf or m an ce .

Testing indicates that, when using Silicon Laboratories'

patented techniques, embedded antenna performance

can be very similar in many key metrics to a standard

half-wavelength antenna. Refer to “AN383: Si47XX

Antenna, Schematic, Layout, And Design Guidelines”

for additional details on the implementation of support

for an embedded antenna.

Figure 12 shows a conceptual block diagram of the

Si4704/05 architecture used to support the embedded

antenna. The half-wavelength FM receive antenna is

therefore optional. Host software can detect the

presence of an external antenna and switch between

the embedded antenna if desired.

Figure 12. Conceptual Block Diagram of the

Si4704/05 Embedded Antenna Support

4.14. RDS Decoder (Si4705 Only)

The Si4705 implements an RDS processor for symbol

decoding, block synchronization, error detection, and

error correction.

The Si4705 device is user configurable and provides an

optional interrupt when RDS is synchronized, loses

synchronization, and/or the user configurable RDS

FIFO threshold has been met.

The Si4705 reports RDS decoder synchronization

status and detailed bit errors in the information word for

each RDS block with the FM_RDS _STAT US comm and.

The range of reportable block errors is 0, 1–2, 3–5, or

6+. More than six errors indicates that the

corresponding block information word contains six or

more non-co rrect able err ors or that the block checkword

contains errors.

4.15. Reference Clock

The Si4704/05 reference clock is programmable,

supporting RCLK frequencies in Table 10. Refer to

Table 3, “DC Characteristics” on page 5 for switching

voltage levels and Table 10, “Reference Clock and

Crystal Characteristics” on page 14 for frequency

tolerance information.

An onboard crystal oscillator is available to generate the

32.768 kHz reference when an external crystal and load

capacitors are provid ed. Refer to "2. Typical Application

Schematic" on page 15. This mode is enabled using the

POWER_UP command. Refer to Refer to “AN332:

Si47xx Programming Guide”.

The Si4704/05 performance may be affected by data

activity on the SDIO bus when using the integrated

internal oscillator. SDIO activity results from polling the

tuner for status or communicating with other devices

that share the SDIO bus. If there is SDIO bus activity

while the Si4704/05 is performing the seek/tune

function, the crystal oscillator may experience jitter,

which may result in mistunes, false stops, and/or lower

SNR.

For best seek/tune results, Silicon Laboratories

recommends that all SDIO data traffic be suspended

during Si4704/05 seek and tune operations. This is

achieved by keeping the bus quiet for all other devices

on the bus, and delaying tuner polling until the tune or

seek operation is complete. The seek/tune complete

(STC) interrupt should be used instead of polling to

determine when a seek/tune operation is complete.

Si4704/05

RFGND

LNA

FMI

AGC

Half-wavelength

antenna

LPI

Integrated

antenna

Si4704/05-D50

Rev. 1.0 23

4.16. Control Interface

A serial port slave interface is provided, which allows an

external controller to send commands to the Si4704/05

and receive responses from the device. The serial port

can operate in two bus modes: 2-wire mode and 3-wire

mode. The Si4 704/05 select s the b us mode by samplin g

the state of the GPO1 and GPO2 pins on the rising

edge of RST. The GPO1 pin includes an internal pull-up

resistor, which is connected while RST is low, and the

GPO2 pin includes an internal pull-down resistor, which

is connected while RST is low. Therefore, it is only

necessary fo r the user to activ ely drive pins wh ich differ

from these states. See Table 12.

After the rising edge of RST, the pins GPO1 and GPO2

are used as general purpose output (O) pins as

described in Section “4.17. GPO Outputs”. In any bus

mode, commands may only be sent after VIO and VDD

supplies are applied.

In any bus mode, before sendin g a command or readin g

a response, the user must first read the status byte to

ensure that the device is ready (CTS bit is high).

4.16.1. 2-Wire C on t rol Interface Mode

When selecting 2-wire mode, the user must ensure that

SCLK is high during the rising edge of RST, and stays

high until after the first start condition. Also, a start

condition must not occur within 300 ns before the rising

edge of RST.

The 2-wire bus mode uses only the SCLK and SDIO

pins for signaling. A transaction begins with the START

condition, which occurs when SDIO falls while SCLK is

high. Next, the us er drives an 8-bit control word se rially

on SDIO, which is captured by the device on rising

edges of SCLK. The control word consists of a 7-bit

device address, followed by a read/write bit (read = 1,

write = 0). The Si4704/05 acknowledges the control

word by driving SDIO low on the next falling edge of

SCLK.

Although the Si4704/05 will respond to only a single

device address, this address can be changed with the

SEN pin (note that the SEN pin is not used for signaling

in 2-wire mode). When SEN = 0, the 7-bit device

address is 0010001b. When SEN = 1, the address is

1100011b.

For write operations, the user then sends an 8-bit data

byte on SDIO, which is captured by the device on rising

edges of SCLK. The Si4704/05 acknowledges each

data byte by driving SDIO low for one cycle, on the next

falling edge of SCLK. The user may write up to 8 data

bytes in a single 2-wire transaction. The first byte is a

command, and the next seven bytes ar e arguments.

For read operations, after the Si4704/05 has

acknowledged the control byte, it will drive an 8-bit data

byte on SDIO, changing the state of SDIO on the falling

edge of SCLK. The user acknowledges each data byte

by driving SDIO low for one cycle, on the next falling

edge of SCLK. If a data byte is not acknowledged, the

transaction will end. The user may read up to 16 data

bytes in a single 2-wire transaction. The se bytes cont ain

the response data from the Si4704/05.

A 2-wire transaction ends with the STOP condition,

which occurs when SDIO rises while SCLK is high. For

details on timing specifications and diagrams, refer to

Table 5, “2-Wire Control Interface Characteristics” on

page 7; Figure 2, “2-Wire Control Interface Read and

Write Timing Parameters,” on page 8, and Figure 3, “2-

Wire Control Interface Read a nd Write Timing Diagram,”

on page 8.

4.16.2. 3-Wire Control Interface Mode

When selectin g 3-wire mode , the user must ensure tha t

a rising edge of SCLK does not occur within 300 ns

before the rising edge of RST.

The 3-wire bus mode uses the SCLK, SDIO, and SEN_

pins. A transaction begins when the user drives SEN

low. Next, the user drives a 9-bit control word on SDIO,

which is captured by the device on rising edges of

SCLK. The control word consists of a 3-bit device

address (A7:A5 = 101b), a read/write bit (read = 1, write

= 0), and a 5-bit register address (A4 :A0).

For write operations, the control word is followed by a

16-bit data word, which is captured by the device on

rising edges of SCLK.

For read operations, the control word is followed by a

delay of one-half SCLK cycle for bus turn-around. Next,

the Si4704/05 will drive the 16-bit read data word

serially on SDIO, changing the state of SDIO on each

rising edge of SCLK.

A transaction ends when the user sets SEN high, then

pulses SCLK high and low one final time. SCLK may

either stop or continue to toggle while SEN is high.

In 3-wire mode, command s are sent by first wr iting each

argument to register(s) 0xA1–0xA3, then writing the

command word to register 0xA0. A response is

retrieved by reading re gisters 0xA8–0xAF.

Table 12. Bus Mode Select on Rising Edge of

RST

Bus Mode GPO1 GPO2

2-Wire 1 0

3-Wire 0 (must drive) 0

Si4704/05-D50

24 Rev. 1.0

For details on timing specifications and diagrams, refer

to Table 6, “3-Wire Control Interface Characteristics” on

page 9; F ig ure 4, “3-W ire Co ntro l Inte rfac e Write Timing

Parameters,” on page 9, and Figure 5, “3-Wire Control

Interface Read Timing Parameters,” on page 9.

4.17. GPO Outputs

The Si4704/05 provides three general-purpose output

pins. The GPO pins can be configured to output a

constant low, constant high, or high-Z. The GPO pins

are multiplexed with the bus mode pins or DCLK,

depending on the application schematic of the device.

GPO2/INT can be configured to provide interrupts for

seek and tune complete, receive signal quality, and

RDS.

4.18. Reset, Powerup, and Powerdown

Setting the RST pin low will disable analog and digital

circuitry, reset the registers to their default settings, and

disable the bus. Setting the RST pin high will bring the

device out of reset. A powerdown mode is available to

reduce power consumption when the p art is idle. Putting

the device in powerdown mode will disable analog and

digital circuitry while keeping the bus active.

4.19. Programming with Commands

To ease development time and offer maximum

customization, the Si4704/05 provides a simple yet

powerful sof tware interface to prog ram th e receiver. The

device is programmed using commands, arguments,

properties, and responses. To perform an action, the

user writes a command byte and associated arguments,

causing the chip to execute the given command.

Commands control an action such as powerup the

device, shut down the device, or tune to a station.

Arguments are specific to a given command and are

used to modify the command. A complete list of

commands is available in “AN332: Si47xx Programming

Guide”.

Properties are a special command argument used to

modify the default chip operation and are generally

configured immediately after powerup. Examples of

properties are de-emphasis level, RSSI seek threshold,

and sof t mute attenua tion thresh old. Response s provide

the user information and are echoed after a command

and associated arguments are issued. All commands

provide a one-byte status update indicating interrupt

and clear-to-send status information. For a detailed

description of the commands and properties for the

Si4704/05, see “AN332: Si47xx Programmin g Guide”.

Si4704/05-D50

Rev. 1.0 25

5. Commands and Properties

Refer to “AN332: Si47xx Pro gramming Guide”.

Si4704/05-D50

26 Rev. 1.0

6. Pin Descriptions: Si4704/05-GM

Pin Number(s) Name Description

1, 20 NC No connect. Leave floating.

2 FMI FM RF input.

3 RFGND RF ground. Connect to ground plane on PCB.

4 LPI Loop antenna RF input.

5RST Device reset input (active low).

6SEN Serial enable input ( active low).

7 SCLK Serial clock input.

8 SDIO Serial data input/output.

9 RCLK External reference or crystal oscillator input.

10 VDDigital and I/O supply voltage.

11 VAAnalog supply voltage. May be connected directly to battery.

13 ROUT Right audio analog line output.

14 LOUT Left audio analog line output.

15 DOUT Digital audio output data.

16 DFS Digital frame synchronization.

17 GPO3/DCLK General purpose output/digital bit synchronous clock or crystal oscillator

input.

18 GPO2/INT General purpose output/interrupt.

19 GPO1 General purpose output.

12, GND PAD GND Ground. Connect to ground plane on PCB.

GND

PAD

17181920

6789

GPO2/INT

DOUT

LOUT

ROUT

GNDRST

LPI

RCLK

SDIO

FMI

RFGND

GPO3/DCLK

GPO1

DFS

SCLK

SEN

Si4704/05-D50

Rev. 1.0 27

7. Ordering Guide

Part Number* Description Package

Type Operating

Temperature

Si4704-D50-GM FM Broadcast Radio Receiver QFN

Pb-free –20 to 85 °C

Si4705-D50-GM FM RDS Broadcast Radio Receiver QFN

Pb-free –20 to 85 °C

*Note: Add an “(R)” at the end of the device part number to denote tape and reel option.

Si4704/05-D50

28 Rev. 1.0

8. Package Markings

8.1. Si4704 Top Mark

Figure 13. Si4704 Top Mark

8.2. Si4705 Top Mark

Figure 14. Si4705 Top Mark

8.3. Top Mark Explanation

Mark Method: YAG Laser

Line 1 Marking: Part Number 04 = Si4704

05 = Si4705

Firmware Revision 50 = Firmw are Revision 5. 0

Line 2 Marking: R = Die Revision D = Revision D Die.

TTT = Internal Code Intern al tracking code.

Line 3 Marking: Circle = 0.5 mm Diameter

(Bottom-Left Justified) Pin 1 Identifier.

Y = Year

WW = Workweek Assigned by the Assembly House. Corresponds to the last

significant digit of the year and workweek of the mold date.

0450

DTTT

YWW

0550

DTTT

YWW

Si4704/05-D50

Rev. 1.0 29

9. Package Outline: Si4704/05

Figure 15 illustrates the package details for the Si4704/05. Table 13 lists the values for the dimensions shown in

the illustration.

Figure 15. 20-pin Quad Flat No-Lead (QFN)

Table 13. Package Dimensions

Symbol Millimeters Symbol Millimeters

Min Nom Max Min Nom Max

A 0.500.550.60 f 2.53 BSC

A1 0.00 0.02 0.05 L 0.35 0.40 0.45

b 0.18 0.25 0.30 L1 0.00 — 0.10

c 0.27 0.32 0.37 aaa — — 0.05

D 3.00 BSC bbb — — 0.05

D2 1.60 1.70 1.80 ccc — — 0.08

e 0.50 BSC ddd — — 0.10

E 3.00 BSC eee — — 0.10

E2 1.60 1.70 1.80

Notes:

1. All dimensions are shown in millimeters unless otherwise noted.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

Si4704/05-D50

30 Rev. 1.0

10. PCB Land Pattern: Si4704/05

Figure 16 illustrates the PCB land pattern det ails for the Si4704/05-GM. Table 14 lists the values for the dimensions

shown in the illustration.

Figure 16. PCB Land Pattern

Si4704/05-D50

Rev. 1.0 31

Table 14. PCB Land Pattern Dimensions

Symbol Millimeters Symbol Millimeters

Min Max Min Max

D 2.71 REF GE 2.10 —

D2 1.60 1.80 W — 0.34

e 0.5 0 BSC X — 0.28

E 2.71 REF Y 0.61 REF

E2 1.60 1.80 ZE — 3.31

f 2 .53 BSC ZD — 3.31

GD 2.10 —

Notes: General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification.

3. This land pattern design is based on IPC-SM-782 guidelin es.

4. All dimensions shown are at maximum material condition (MMC). Least material

condition (LMC) is calculated based on a fabrication allowance of 0.05 mm.

Notes: Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the

pad.

Notes: Stencil Design

1. A stainless steel, laser-cut and electro-p olished stencil with trapezoidal walls

should be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.

4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This

provides approximately 70% solder paste coverage on the pad, which is optimum

to assure correct component stand-off.

Notes: Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020

specification for small body components.

Si4704/05-D50

32 Rev. 1.0

11. Additional Reference Resources

Customer Support Site:

This site contain s all application notes, evaluation board schema tics and layouts, and evaluation sof tware. NDA

is required for complete access. Please visit the Silicon Labs Technical Support web page:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support

request.

AN332: Si47xx Programming Guide

AN342: Quick Start Guide

AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines

AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure

Si47xx EVB User’s Guide

Si4704/05-D50

Rev. 1.0 33

DOCUMENT CHANGE LIST:

Revision 0.2 to Revision 1.0

Updated functional block diagram

Updated spec ifica tio n tables, remo ve d TBDs

Updated “2. Typical Application Schematic”

Updated“3. Bill of Materials”

Added support for FM for 64–75.9 MHz frequency

range

Added Section “4 .6 . Volume Control”

Digital audio output now available in Si4704 -D50

Removed references to "AN344: Si4706/07/4x

Programming Guide"

Si4704/05-D50

34 Rev. 1.0

CONTACT INFORMATION

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Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Email: FMinfo@silabs.com

Internet: www.silabs.com

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the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

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