DATA SH EET
Product specification
File under Integrated Circuits, IC04 January 1995
INTEGRATED CIRCUITS
HEF4520B
MSI
Dual binary counter
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Dual binary counter HEF4520B
MSI
DESCRIPTION
The HEF4520B is a dual 4-bit internally synchronous
binary counter. The counter has an active HIGH clock
input (CP0) and an active LOW clock input (CP1), buffered
outputs from all four bit positions (O0to O3) and an active
HIGH overriding asynchronous master reset input (MR).
The counter advances on either the LOW to HIGH
transition of the CP0input if CP1is HIGH or the HIGH to
LOW transition of theCP1input if CP0 is low. Either CP0or
CP1may be used as the clock input to the counter and the
other clock input may be used as a clock enable input. A
HIGH on MR resets the counter (O0to O3= LOW)
independent of CP0, CP1.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
HEF4520BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4520BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4520BT(D): 16-lead SO; plastic (SOT109-1)
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
CP0A,CP
0B clock inputs (L to H triggered)
CP1A, CP1B clock inputs (H to L triggered)
MRA,MR
Bmaster reset inputs
O0A to O3A outputs
O0B to O3B outputs
January 1995 3
Philips Semiconductors Product specification
Dual binary counter HEF4520B
MSI
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FUNCTION TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
= negative-going transition
CP0CP1MR MODE
H L counter advances
L L counter advances
X L no change
X L no change
L L no change
H L no change
XXHO
0
to O3= LOW
Fig.3 Logic diagram (one counter).
January 1995 4
Philips Semiconductors Product specification
Dual binary counter HEF4520B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25°C; CL= 50 pF; input transition times ≤20 ns
VDD
VSYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
CP0, CP1→On5 110 220 ns 83 ns +(0,55 ns/pF) CL
HIGH to LOW 10 tPHL 50 100 ns 39 ns +(0,23 ns/pF) CL
15 40 80 ns 32 ns +(0,16 ns/pF) CL
5 110 220 ns 83 ns +(0,55 ns/pF) CL
LOW to HIGH 10 tPLH 50 100 ns 39 ns +(0,23 ns/pF) CL
15 40 80 ns 32 ns +(0,16 ns/pF) CL
MR →On5 75 150 ns 48 ns +(0,55 ns/pF) CL
HIGH to LOW 10 tPHL 35 70 ns 24 ns +(0,23 ns/pF) CL
15 25 50 ns 17 ns +(0,16 ns/pF) CL
Output transition
times 5 60 120 ns 10 ns +(1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
5 60 120 ns 10 ns +(1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
Minimum CP056030ns
see also waveforms
Figs 4 and 5
pulse width; LOW 10 tWCPL 30 15 ns
15 20 10 ns
Minimum CP156030ns
pulse width; HIGH 10 tWCPH 30 15 ns
15 20 10 ns
Minimum MR 5 30 15 ns
pulse width; HIGH 10 tWMRH 20 10 ns
15 16 8 ns
Recovery time 5 50 25 ns
for MR 10 tRMR 30 15 ns
15 20 10 ns
Set-up times 5 50 25 ns
CP0→CP110 tsu 30 15 ns
15 20 10 ns
55025ns
CP1→CP010 tsu 30 15 ns
15 20 10 ns
Maximum clock 5 8 16 MHz
pulse frequency 10 fmax 15 30 MHz
15 20 40 MHz
January 1995 5
Philips Semiconductors Product specification
Dual binary counter HEF4520B
MSI
AC CHARACTERISTICS
VSS = 0 V; Tamb =25°C; input transition times ≤20 ns
VDD
VTYPICAL FORMULA FOR P (µW)
Dynamic power 5 850 fi+∑(foCL)×VDD2where
dissipation per 10 3 800 fi+∑(foCL)×VDD2fi= input freq. (MHz)
package (P) 15 10 200 fi+∑(foCL)×VDD2fo= output freq. (MHz)
CL= load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
Fig.4 Waveforms showing recovery time for MR; minimum CP0, CP1and MR pulse widths.
January 1995 6
Philips Semiconductors Product specification
Dual binary counter HEF4520B
MSI
Fig.5 Waveforms showing set-up times for CP0to CP1and CP1 to CP0, and propagation delays.
January 1995 7
Philips Semiconductors Product specification
Dual binary counter HEF4520B
MSI
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Fig.6 Timing diagram.
