Data Sheet April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier Features Functional Description 6 mVp-p (single-ended) input sensitivity, BER =10-10 34 dB gain, 40 dB differential Complementary 50 I/Os Adjustable threshold control Single -5.2 V power supply 24-lead, surface-mount package The Agere Systems TLMA0110G5XE4 is a wideband limiting amplifier with differential inputs and outputs. It provides 34 dB of gain (40 dB differential) and 10 GHz of bandwidth in a 50 environment. The TLMA0110G5XE4 consists of a 50 input buffer followed by three gain stages and a 50 output buffer. The threshold level can be adjusted by inserting an external voltage source into the amplifier's positive or negative feedback loops. At input levels below 30 mVp-p (single-ended), the device acts as a linear amplifier. For input levels from 30 mVp-p up to 800 mVp-p, the device operates in its limiting mode, providing a constant typical output of 550 mVp-p (single-ended). Applications Data/clock main amplifier in SONET/SDH OC-192/STM-64 transmission systems and DWDM systems Digital video transmission SONET/SDH test equipment The TLMA0110G5XE4 is designed for use in SONET OC-192 and SDH STM-64 receiver/regenerator applications. Amplifier operation is from a single -5.2 V power supply. The TLMA0110G5XE4 is available in a 24-lead, hermetic, surface-mount package. An evaluation board is available, allowing a complete performance evaluation of the amplifier. FPI 50 FPO GND 150 pF 50 + VINP + INPUT BUFFER VINN - - 5 k + - - + + - - + 50 + - - + + - VOUTP OUTPUT BUFFER - VOUTN + BIAS GEN 5 k 50 27 k 150 pF 150 pF FNI FNO Figure 1. Block Diagram 150 pF VSS BG2P5 Data Sheet April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier GND FNI FPI FPO FNO GND Pin Information 24 19 1 18 GND GND GND GND TLMA 10G5XE4 XXXXXX VOUTP GND VOUTN VINP GND VINN GND GND 6 13 GND BG2P5 VSS VSS DNC 12 GND 7 Note: XXXXXX represents the serial number. Figure 2. Package Pinout (Top View) Table 1. Pin Descriptions Symbol Pin GND 1, 2, 4, 6, 7, 12, 13, 15, 17, 18, 19, 24, Package Bottom VOUTP 3 5 VOUTN DNC 8 VSS 9, 10 BG2P5 11 VINN VINP FNI FPI FPO FNO 14 16 20 21 22 23 Description Ground. For optimal performance, the package bottom must be soldered to the ground plane. Data Output. ac coupling required. Complementary Data Output. ac coupling required. Do Not Connect. Reserved for testing or future use. Power Supply Voltage. -5.2 V dc nominal supply voltage. -2.5 V Bandgap Reference. Connect to Si bandgap reference, such as National Semiconductor (R) part number LM4040EIM3-2.5. Complementary Data Input. ac coupling required. Data Input. ac coupling required. Feedback Negative Input. Threshold level control. Feedback Positive Input. Threshold level control. Feedback Positive Output. Threshold level control. Feedback Negative Output. Threshold level control. Note: Nodes FPI, FPO, FNI, and FNO complete the positive and negative internal feedback loops that are used to control the threshold level. FPI should be shorted to FPO, and FNI should be shorted to FNO. This configuration will center the threshold level. The threshold level can be shifted by forcing a change in voltage on either side of the feedback loop using a voltage source. 2 Agere Systems Inc. Data Sheet April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. TAMBIENT = 25 C unless otherwise specified. Table 2. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Power Dissipation Storage Temperature Range Case Temperature Range Symbol Min Max Unit VSS VIN PD Tstg TCASE -7 GND -- -40 -5 0.5 VSS 1.0 125 100 V V W C C Handling Precautions Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. Table 3. ESD Protection Characteristics Method Voltage HBM CDM >150 V >175 V Recommended Operating Conditions Table 4. Recommended Operating Conditions Parameter Power Supply Voltage Operating Case Temperature Range Agere Systems Inc. Symbol Min Max Unit VSS TCASE -4.94 0 -5.5 85 V C 3 Data Sheet April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier Electrical Characteristics TCASE = 0 C to 85 C, VSS = -5.2 V 5%, and RLOAD = 50 . Inputs and outputs are ac-coupled and tested as shown in Figure 7 and the package bottom is electrically and thermally connected to ground. Bit rate = 9953.28 Mbits/s NRZ and data pattern = 231 - 1 PRBS, unless otherwise indicated. Minimum and maximum values are testing requirements. Typical values are characteristics of the device and are the result of engineering evaluations. Typical values are for information purposes only and are not part of the testing requirements. Table 5. Limiting Amplifier Characteristics Parameter Symbol Conditions Single-ended, BER = 10 -10 Min Typ Max Unit -- 6 10 mVp-p -- -- 800 mVp-p 1600 mVp-p Input Sensitivity SEN Maximum Input Voltage VIN Single-ended Differential -- -- Output Voltage VOUT Single-ended, VIN 30 mVp-p 400 550 700 mVp-p Eye Crossing -- 30 mVp-p VIN 800 mVp-p 35 50 65 % Rise/Fall Time 20%--80% tR, tF VIN = 100 mVp-p -- 20 35 ps Jitter (rms) -- VIN = 100 mVp-p -- 2 3 ps Small Signal Gain G Single-ended, PIN = -35 dBm 30 34 -- dB Small Signal Bandwidth f3dB PIN = -35 dBm 8 10 -- GHz Input Return Loss S11 50 MHz--8 GHz 8 10 -- dB Output Return Loss S22 50 MHz--8 GHz 8 10 -- dB Supply Current ISS VSS = -5.2 V 100 135 170 mA Note: 100% of the devices are production tested at Tcase = 45 C and Vss = -5.2 V, to the minimum and maximum limits listed in Table 5. The specifications listed in Table 5 are guaranteed from 0 C to 85 C and for Vss = -5.2V 5% based on device characterization. Sensitivity, Input Return Loss, and Output Return Loss are guaranteed by characterization and are not production tested. VINP 3 mV - 800 mV VINN VINP - VINN 6 mV - 1600 mV Figure 3. Differential Input Voltage Definitions 4 Agere Systems Inc. Data Sheet April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier Electrical Characteristics (continued) 100 mV/div 20 ps/div Figure 4. Output Eye Diagram, VIN = 10 mVp-p (Single-Ended) 100 mV/div 20 ps/div Figure 5. Output Eye Diagram, VIN = 100 mVp-p (Single-Ended) Agere Systems Inc. 5 Data Sheet April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier Electrical Characteristics (continued) Output Voltage (mVp-p) 1000 100 10 1 10 100 1000 Input Vo ltage (mVp-p) Figure 6. Output Limiting Characteristics 6 Agere Systems Inc. Data Sheet April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier Test Circuit FPO FPI 50 GND 150 pF 50 0.047 F VINP 50 5 k 0.047 F + + INPUT BUFFER VINN - - + - - + + - - + + - + - + VOUTP - OUTPUT BUFFER - VOUTN + 0.047 F XX 0.047 F 50 50 BIAS GEN 5 k 50 50 50 27 k 150 pF 150 pF 150 pF PATTERN GENERATOR FNI VSS FNO 0.1 F BG2P5 0.1 F 0.1 F 5.2 V CONNECT TO POSITIVE SIDE OF FEEDBACK LOOP LM4040EIM3-2.5 + 5-8197.b(F) Figure 7. Test Circuit Agere Systems Inc. 7 Data Sheet April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier Outline Diagram 24-Pin, Surface-Mount Package (Top, Side Views) Dimensions are in inches.* 0.382 0.274 0.062 0.224 0.025 0.073 TLMA 10G5XE4 XXXXXX 0.438 0.332 0.282 0.016 TYP 0.030 TYP 0.109 0.025 LID 0.025 0.058 0--8 0.000--0.004 HEAT SINK 0.054 0.029 5-8199.b(F) * Leads are solder dipped. All lead dimensions are prior to solder dipping. 8 Agere Systems Inc. Data Sheet April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier Ordering Information Device Type Comcode TLMA0110G5XE4 EB10GLMTAMP5XE4 24-Pin Package Evaluation Board 700012251 700010836 Agere Systems Inc. 9 National Semiconductor is a registered trademark of National Semiconductor Corporation. For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere. Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. Copyright (c) 2003 Agere Systems Inc. All Rights Reserved April 2003 DS03-103HSPL (Replaces DS02-404HSPL)