EB10GLMTAMP5YP1 - Agere Systems, Inc.

Data Sheet

April 2003

TLMA0110G5XE4 10 Gbits/s Limiting Amplifier

Features

■6 mVp-p (single-ended) input sensitivity,

BER =10–10

■34 dB gain, 40 dB differential

■Comple men tary 50 Ω I/Os

■Adjustable thr es hol d con trol

■Single –5.2 V power supply

■24-lead, surface-mount package

Applications

■Data/clock main amplifier in SONET/SDH

OC-192/STM-64 transmission systems and

DWDM systems

■Digital video transmission

■SONET/SDH test equipment

Functional Description

The Agere Systems TLMA0110G5XE4 is a wideband

limiting amplifier with differential inputs and outputs.

It provides 34 dB of gain (40 dB differential) and

10 GHz of bandwidth in a 50 Ω environment. The

TLMA0110G5XE4 consists of a 50 Ω input buffer

followed by three gain stages and a 50 Ω output

buffer. The threshold level can be adjust ed by

inserting an external voltage source into the

amplifier’s positive or negative feedback loops. At

input levels below 30 mVp-p (single-ended), the

device acts as a linear amplifier . For input levels from

30 mVp-p up to 800 mVp-p, the device operates in its

limiting mode, providing a constant typical output of

550 mVp-p (sin gl e- ende d).

The TLMA01 10G5XE4 is designed for use in SONET

OC-192 and SDH STM-64 receiver/regenerator

applications. Amplifier operation is from a single

–5.2 V power supply. The TLMA0110G5XE4 is

available in a 24-lead, hermetic, surface-mount

package. An evaluation board is available, allowing a

complete performance evaluation of the amplifier.

Figure 1. Block Diagra m

OUTPUT

BUFFER

INPUT

OUTN

OUTP

INN

INP

BUFFER

FPI

FNI

FPO GND

FNO

150 pF

Ω

5 k

Ω

––

+–

–+ +–

–+

+–

–+

150 pF

Ω

5 k

Ω

150 pF

BG2P5

150 pF

27 k

Ω

BIAS

GEN

2Agere Systems Inc.

Data Sheet

April 2003

TLMA0110G5XE4 10 Gbits/s Limiting Amplifier

Pin Information

Note: XXXXXX represents the serial number.

Figure 2. Package Pinout (Top View)

Table 1. Pin Descriptions

Note: Nodes FPI, FPO, FNI, and FNO complete the positive and negative internal feedback loops that are used to control the threshold level.

FPI should be shorted to FPO, and FNI should be shorted to FNO. This configuration will center the threshold level. The threshold level

can be shifted by forcing a change in voltage on either side of the feedback loop using a voltage source.

Symbol Pin Description

GND 1, 2, 4, 6, 7, 12, 13, 15, 17,

18, 19, 24, Package Bottom Ground. For optimal performance, the package bottom must be soldered

to the ground plane.

VOUTP 3Data Output. ac coupling required.

VOUTN 5Complementary Data Output. ac coupling required.

DNC 8 Do Not Connect. Reserved for testing or future use.

VSS 9, 10 Power Supply Voltage. –5.2 V dc nominal supply voltage.

BG2P5 11 –2.5 V Bandgap Reference. Connect to Si bandgap reference, such as

National Semiconductor® part number LM4040EIM3-2.5.

VINN 14 Complementa ry Data Input. ac coupling required.

VINP 16 Data Input. ac coupling required.

FNI 20 Feedback Negative Input. Threshold level control.

FPI 21 Feedback Positive Input. Threshold level control.

FPO 22 Feedback Positive Output. Threshold level control.

FNO 23 Feedback Negative Output. Threshold level control.

GND

OUTP

GND

OUTN

GND

DNC

BG2P5

GND

INP

GND

INN

GND

FNO

FPO

FPI

FNI

GND

712

TLMA

10G5XE4

XXXXXX

24 19

Agere Systems Inc. 3

Dat a Sheet

April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

TAMBIENT = 25 °C unless otherwise specified.

Handling Precautions

Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions

must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test

operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification

requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresh-

olds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114

(HBM) and JESD22-C101 (CDM) standards.

Recommended Operating Conditions

Table 2. Absolute Maximum Ratings

Parameter Symbol Min Max Unit

Supply Voltage VSS –7 0.5 V

Input Voltage VIN GND VSS V

Power Dissipation PD—1.0W

Storage Temperature Range Tstg –40 125 °C

Case Temperature Range TCASE –5 100 °C

Table 3. ESD Protection Characteristics

Method Voltage

HBM >150 V

CDM >175 V

Table 4. Recommended Operating Conditions

Parameter Symbol Min Max Unit

Power Su ppl y Voltage VSS –4.94 –5.5 V

Operating Case Temperature Range TCASE 085°C

4Agere Systems Inc.

Data Sheet

April 2003

TLMA0110G5XE4 10 Gbits/s Limiting Amplifier

Electrical Characteristics

TCASE = 0 °C to 85 °C, VSS = –5.2 V ± 5%, and RLOAD =50Ω. Inputs and outputs are ac-coupled and tested as

shown in Figure 7 and the package bottom is electrically and thermally connected to ground.

Bit rate = 9953.28 Mbits/s NRZ and data pattern = 231 – 1 PRBS, unless otherwise indicated. Minimum and maxi-

mum values are testing requirements. Typical values are characteristics of the device and are the result of engi-

neering evaluations. Typical values are for information purposes only and are not part of the testing

requirements.

Note: 100% of the devices are production tested at Tcase = 45 °C and Vss = –5.2 V, to the minimum and maximum limits listed in Table 5. The

specifications listed in Table 5 are guaranteed from 0 °C to 85 °C and for Vss = –5.2V ± 5% based on device characterization. Sen sitivity,

Input Return Loss, and Output Return Loss are guaranteed by characterization and are not production tested.

Figure 3. Differential Input Voltage Definitions

Table 5. Limiting Amplifier Characteristics

Parameter Symbol Conditions Min Typ Max Unit

Input Sensitivity SEN Single-ended, BER = 10–10 —610mVp-p

Maxi mum Input

Voltage VIN Single-ended — — 800 mVp-p

Differential — — 1600 mVp-p

Output Voltage VOUT Single-ended, VIN ≥ 30 mVp-p 400 550 700 mVp-p

Eye Crossing — 30 mVp-p ≤ VIN ≤800 mVp-p 35 50 65 %

Rise/Fall Time

20%—80% tR, tFVIN = 100 mVp-p — 20 35 ps

Jitter (rms) — VIN =100mVp-p — 2 3 ps

Small Signal Gain G Single-ended, PIN = –35 dBm 30 34 — dB

Small Signal

Bandwidth f3dB PIN = –35 dBm 8 10 — GHz

Input Return Loss S11 50 MHz—8 GHz 8 10 — dB

Output Retu rn Loss S22 50 MHz—8 GHz 8 10 — dB

Supply Current ISS VSS = –5.2 V 100 135 170 mA

VINN

VINP

3 mV – 800 mV

VINP - VINN 6 mV – 1600 mV

Agere Systems Inc. 5

Dat a Sheet

April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier

Electrical Characteristics (continued)

Figure 4. Output Eye Diagram, VIN = 10 mVp-p (Single-Ended)

Figure 5. Output Eye Diagram, VIN = 100 mVp-p (Single-Ended)

100 mV/div

20 ps/div

100 mV/div

20 ps/div

6Agere Systems Inc.

Data Sheet

April 2003

TLMA0110G5XE4 10 Gbits/s Limiting Amplifier

Electrical Characteristics (continued)

Figure 6. Output Limiting Characteristics

10 0

10 0 0

1 10 100 1000

I nput Voltage (mVp-p)

Output Voltage (mVp–p)

Agere Systems Inc. 7

Dat a Sheet

April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier

Test Circuit

5-8197.b(F)

Figure 7. Test Circuit

OUTPUT

BUFFER

INPUT

OUTN

OUTP

INN

INP

BUFFER

FPI

FNI

FPO GND

FNO

150 pF

Ω

5 k

Ω

––

+–

–+ +–

–+

+–

–+

150 pF

Ω

5 k

Ω

150 pF

BG2P5

150 pF

Ω

0.1

CONNECT TO POSITIVE

SIDE OF FEEDBACK LOOP

0.1

F0.1

5.2 V LM4040EIM3-2.5

0.047

Ω

0.047

Ω

PATTERN

GENERATOR

27 kΩ

BIAS

GEN

8Agere Systems Inc.

Data Sheet

April 2003

TLMA0110G5XE4 10 Gbits/s Limiting Amplifier

Outline Diagram

24-Pin, Surface-Mount Package (Top, Side Views)

Dimensions are in inches.*

5-8199.b(F)

* Leads are solder dipped. All lead dimensions are prior to solder dipping.

0.382

0.332

0.062

0.073

0.016 TYP

0.030 TYP

0.058

0.054 0.029

0°—8°

0.000—0.004 HEAT SINK

LID

0.025

TLMA

10G5XE4

XXXXXX

0.438

0.282

0.109

0.025

0.274

0.224

0.025

Agere Systems Inc. 9

Dat a Sheet

April 2003 TLMA0110G5XE4 10 Gbits/s Limiting Amplifier

Ordering Information

Device Type Comcode

TLMA0 110G5XE4 24-Pin Pack age 700012251

EB10GLM TAMP5XE4 Evalu ati on Boa rd 700010 836

April 2003

DS03-103HSPL (Replaces DS02-404HSPL)

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere.

Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-76 7- 1850 (Seoul), SINGAPORE: (65 ) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

EUROPE: Tel. (44) 1344 296 400

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