TN12, TS12 and TYNx12 Series
5/10
Fig. 3-2: Relative variation of thermal
impedance junction to ambient versus pulse
duration (recommended pad layout, FR4 PC
board).
Fig. 4-1: Relative variation of gate trigger
current, holding current and latching versus
junction temperature for TS12 series.
Fig. 4-2: Relative variation of gate trigger
current, holding current and latching current
versus junction temperature for TN12 & TYN
series.
Fig. 5: Relative variation of holding current
versus gate-cathode resistance (typical values)
for TS12 series.
Fig. 6: Relative variation of dV/dt immunity
versus gate-cathode resistance (typical values)
for TS12 series.
Fig. 7: Relative variation of dV/dt immunity
versus gate-cathode capacitance (typical values)
for TS12 series.
1E-2 1E-1 1E+0 1E+1 1E+2 5E+2
0.01
0.10
1.00 K = [Zth(j-a)/Rth(j-a)]
DPAK
TO-220AB
D2PAK
tp(s)
-40 -20 0 20 40 60 80 100 120 140
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0 IGT,IH,IL [Tj] / IGT,IH,IL [Tj = 25°C]
IGT
IH & IL
Rgk = 1kΩ
Tj(°C)
-40 -20 0 20 40 60 80 100 120 140
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4 IGT,IH,IL [Tj] / IGT,IH,IL [Tj = 25°C]
IGT
IH & IL
Tj(°C)
1E-2 1E-1 1E+0 1E+1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0 IH[Rgk] / IH[Rgk = 1kΩ]
Tj = 25°C
Rgk(kΩ)
dV/dt[Rgk] / dV/dt [Rgk = 220 ]Ω
Rgk(k )Ω
Tj = 125°C
VD = 0.67 x VDRM
0.1
1.0
10.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 25 50 75 100 125 150
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0 VD = 0.67 x VDRM
Tj = 125°C
Rgk = 220Ω
dV/dt[Cgk] / dV/dt [Rgk = 220 ]Ω
Cgk(nF)