This is information on a product in full production.
March 2012 Doc ID 13794 Rev 4 1/52
52
L6566A
Multi-mode controller for SMPS with PFC front-end
Datasheet − production data
Features
■Selectable multi-mode operation: fixed
frequency or quasi-resonant
■Onboard 700 V high-voltage startup
■Advanced light load management
■Low quiescent current (< 3 mA)
■Adaptive UVLO
■Line feedforward for constant power capability
vs. mains voltage
■Pulse-by-pulse OCP, shutdown on overload
(latched or auto-restart)
■Transformer saturation detection
■Switched supply rail for PFC controller
■Latched or auto-restart OVP
■Brownout protection
■-600/+800 mA totem pole gate-driver with
active pull-down during UVLO
■SO16N package
Applications
■Notebook, TV and LCD monitor adapters
■High power chargers
■PDP/LCD TVs
■Consumer appliances, such as DVD players,
VCRs, set-top boxes
■IT equipment, games, auxiliary power supplies
■Power supplies in excess of 150 W
Figure 1. Block diagram
SO16N
+-
+
-
ZERO CURRENT
DETECTOR
50 mV
100 mV
V
CC
915
7
ZCD
COMP VFF
CS
GD
4
11
GND
3
LINE VOLTAGE
FEEDFORWARD
1.5 V
+-
+
-
4.5V
DIS
8
LATCH
LEB
14V
Reference
voltages
5
V
CC
10
Internal supply
VREF
UVLO
VOLTAGE
REGULATOR
&
ADAPTIVE UVLO
Vcc_PFC
6
IC_LATCH
DISAB LE
UVLO
IC_LATCH
Q
12
+
-
AC_FAIL
13
AC_FAIL
UVLO_SHF
V
CC
5.7V
1
HV
SOFT-START
&
FAULT MNGT
14
SS
OSC
MODE/SC
+-
OSCILLATOR R
S
Q
MODE SELECTION
&
TURN-ON LOGIC
OVERVOLTAGE
PROTECTION
7.7V
OCPPWM
TIME
OUT
TIME
OUT
+
-
Vth
BURST-MODE
LOW CLAMP
&DISABLE
OFF2
OFF2
I
charge
Hiccup-mode
OCP logic
400 uA
DRIVER
OCP2
+
-
6.4V
V
CC
1mA
OVPL
OVP
OVPL
OVP
OCP2
+
-
0.450V
0.485V
AC_OK
16
15 µA
3V
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Contents L6566A
2/52 Doc ID 13794 Rev 4
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 High-voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Zero current detection and triggering block; oscillator block . . . . . . . . . . 19
5.3 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 22
5.4 Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.5 PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.6 PWM comparator, PWM latch and voltage feedforward blocks . . . . . . . . 25
5.7 Hiccup-mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.8 PFC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9 Latched disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.10 Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 31
5.11 OVP block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.12 Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.13 Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.14 Summary of L6566A power management functions . . . . . . . . . . . . . . . . 38
6 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
List of tables L6566A
4/52 Doc ID 13794 Rev 4
List of tables
Table 1. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. L6566A light load management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6. L6566A protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7. External circuits that determine IC behavior upon OVP and OCP . . . . . . . . . . . . . . . . . . . 44
Table 8. SO16N dimentions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 9. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
L6566A List of figures
Doc ID 13794 Rev 4 5/52
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Pin connection (through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Multi-mode operation with QR option active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. High-voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5 V) . . . . . . . . . . . . . . 19
Figure 8. Zero current detection block, triggering block, oscillator block and related logic . . . . . . . . 19
Figure 9. Drain ringing cycle skipping as the load is gradually reduced . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Operation of ZCD, triggering and oscillator blocks (QR option active) . . . . . . . . . . . . . . . . 22
Figure 11. Load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Addition of an offset to the current sense lowers the burst-mode operation threshold . . . . 24
Figure 13. Adaptive UVLO block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Possible feedback configurations that can be used with the L6566A. . . . . . . . . . . . . . . . . 25
Figure 15. Externally controlled burst-mode operation by driving the COMP pin: timing diagram. . . . 26
Figure 16. Typical power capability change vs. input voltage in QR flyback converters . . . . . . . . . . . 27
Figure 17. Left: overcurrent setpoint vs. VFF voltage; right: line feedforward function block. . . . . . . . 28
Figure 18. Hiccup-mode OCP: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. Possible interfaces between the L6566A and a PFC controller . . . . . . . . . . . . . . . . . . . . . 31
Figure 20. Operation after latched disable activation: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21. Soft-start pin operation under different operating conditions and settings . . . . . . . . . . . . . 33
Figure 22. OVP function: internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23. OVP function: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 24. Maximum allowed duty cycle vs. switching frequency for correct OVP detection. . . . . . . . 36
Figure 25. Brownout protection: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . . 37
Figure 26. AC voltage sensing with the L6566A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 27. Slope compensation waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 28. Typical low-cost application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 29. Typical full-feature application schematic (QR operation) . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 30. Typical full-feature application schematic (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 31. Frequency foldback at light load (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 32. Latched shutdown upon mains overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 33. Package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 34. Recommended footprint (dimensions are in mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Description L6566A
6/52 Doc ID 13794 Rev 4
1 Description
The L6566A is an extremely versatile current-mode primary controller IC specifically
designed for high-performance offline flyback converters operated from front-end power
factor correction (PFC) stages in applications in compliance with EN61000-3-2 or JEITA-
MITI regulations.
Both fixed-frequency (FF) and quasi-resonant (QR) operation are supported. The user can
choose either of the two depending on application needs.
The device features an externally programmable oscillator; it defines the converter's
switching frequency in FF mode and the maximum allowed switching frequency in QR
mode.
When FF operation is selected, the IC works like a standard current-mode controller with a
maximum duty cycle limited to 70% (min.).
QR operation, when selected, occurs and is achieved through a transformer
demagnetization sensing input that triggers MOSFET turn-on. Under some conditions, ZVS
(zero-voltage switching) can be achieved. The converter's power capability rise with the
input voltage is compensated by line voltage feedforward. At medium and light load, as the
QR operating frequency equals the oscillator frequency, a function (valley skipping) is
activated to prevent further frequency rise and keep the operation as close to ZVS as
possible.
With either FF or QR operation, at very light load the IC enters a controlled burst-mode
operation that, along with the built-in non-dissipative high-voltage startup circuit and a
reduced quiescent current, helps keep the consumption from the mains low and meet
energy saving recommendations.
To allow the meeting of energy saving recommendations in two-stage power-factor-
corrected systems as well, the L6566A provides an interface with the PFC controller that
enables the re-regulator to be turned off at light load.
An innovative adaptive UVLO helps minimize the issues related to fluctuations in the self-
supply voltage due to transformer parasites.
The protection functions included in this device are: not-latched input undervoltage
(brownout), output OVP (auto-restart or latch-mode selectable), a first-level OCP with
delayed shutdown to protect the system during overload or short-circuit conditions (auto-
restart or latch-mode selectable), and a second-level OCP which is invoked when the
transformer saturates or the secondary diode fails short. A latched disable input allows easy
implementation of OTP with an external NTC, while an internal thermal shutdown prevents
IC overheating.
Programmable soft-start, leading-edge blanking on the current sense input for greater noise
immunity, slope compensation (in FF mode only), and a shutdown function for externally
controlled burst-mode operation or remote ON/OFF control are all features of this device.
L6566A Description
Doc ID 13794 Rev 4 7/52
Figure 2. Typical system block diagram
Rectified
Mains
Voltage
Voutdc
L6562A
L6563S
L6564
PWM/QR controller is turned off in case of PFC's
anomalous operation, for safety
PFC is automatically turned off at light
load to ease compliance with
energy saving specifications.
L6566A
PFC PRE-REGULATOR FLYBACK DC-DC CONVERTER
Pin settings L6566A
8/52 Doc ID 13794 Rev 4
2 Pin settings
2.1 Connections
Figure 3. Pin connection (through top view)
2.2 Pin description
N.C.
GND
GD
Vcc
Vcc_PFC
DIS
VFF
SS
OSC
MODE/SC
COMP
CS VREF
HVS AC_OK
ZCD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N.C.
GND
GD
Vcc
Vcc_PFC
DIS
VFF
SS
OSC
MODE/SC
COMP
CS VREF
HVS AC_OK
ZCD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Table 1. Pin functions
N° Pin Function
1HVS
High-voltage startup. The pin, able to withstand 700 V, is to be tied directly to the
rectified mains voltage. A 1 mA internal current source charges the capacitor
connected between the Vcc pin (5) and GND pin (3) until the voltage on the Vcc pin
reaches the turn-on threshold, it is then shut down. Normally, the generator is re-
enabled when the Vcc voltage falls below 5 V, to ensure a low power throughput
during short-circuit. Otherwise, when a latched protection is tripped, the generator
is re-enabled 0.5 V below the turn-on threshold, to keep the latch supplied; or,
when the IC is turned off by the COMP pin (9) pulled low, the generator is active
just below the UVLO threshold to allow a faster restart.
2N.C.
Not internally connected. Provision for clearance on the PCB to meet safety
requirements.
3GND
Ground. Current return for both the signal part of the IC and the gate-drive. All of
the ground connections of the bias components should be tied to a track going to
this pin and kept separate from any pulsed current return.
4GD
Gate driver output. The totem pole output stage is able to drive power MOSFETs
and IGBTs with a peak current capability of 800 mA source/sink.
L6566A Pin settings
Doc ID 13794 Rev 4 9/52
5Vcc
Supply voltage of both the signal part of the IC and the gate-driver. The internal
high-voltage generator charges an electrolytic capacitor connected between this
pin and GND (pin 3) as long as the voltage on the pin is below the turn-on threshold
of the IC, after which it is disabled and the chip is turned on. The IC is disabled as
the voltage on the pin falls below the UVLO threshold. This threshold is reduced at
light load to counteract the natural reduction of the self-supply voltage. Sometimes
a small bypass capacitor (0.1 µF typ.) to GND may be useful in order to get a clean
bias voltage for the signal part of the IC.
6Vcc_PFC
Supply pin output. This pin is intended for supplying the PFC controller IC in
systems comprising a PFC pre-regulator or other compatible circuitry. It is internally
connected to the Vcc pin (5) via a controlled switch. The switch is closed as the IC
starts up and opens when the voltage at the COMP pin is lower than a threshold
(light load), whenever the IC is shut down (either latched or not) and during UVLO.
If not used, the pin is left floating.
7CS
Input to the PWM comparator. The current flowing in the MOSFET is sensed
through a resistor, the resulting voltage is applied to this pin and compared with an
internal reference to determine MOSFET turn-off. The pin is equipped with 150 ns
min. blanking time after the gate-drive output goes high for improved noise
immunity. A second comparison level located at 1.5 V latches the device off and
reduces its consumption in case of transformer saturation or secondary diode
short-circuit. The information is latched until the voltage on the Vcc pin (5) goes
below the UVLO threshold, and so resulting in intermittent operation. A logic circuit
improves sensitivity to temporary disturbances.
8DIS
IC’s latched disable input. Internally, the pin connects a comparator that, when the
voltage on the pin exceeds 4.5 V, latches off the IC and brings its consumption to a
lower value. The latch is cleared as the voltage on the Vcc pin (5) goes below the
UVLO threshold, but the HV generator keeps the Vcc voltage high (see pin 1
description). It is then necessary to recycle the input power to restart the IC. For a
quick restart, pull pin 16 (AC_OK) below the disable threshold (see pin 16
description). Bypass the pin with a capacitor to GND (pin 3) to reduce noise pick-
up. Ground the pin if the function is not used.
9COMP
Control input for loop regulation. The pin is driven by the phototransistor (emitter-
grounded) of an optocoupler to modulate its voltage by modulating the current
sunk. A capacitor placed between the pin and GND (3), as close to the IC as
possible to reduce noise pick-up, sets a pole in the output-to-control transfer
function. The dynamic of the pin is in the 2.5 to 5 V range. A voltage below an
internally defined threshold activates burst-mode operation. The voltage at the pin
is bottom-clamped at about 2 V. If the clamp is externally overridden and the
voltage is pulled below 1.4 V, the IC shuts down.
10 VREF
An internal generator furnishes an accurate voltage reference (5 V ± 2%) that can
be used to supply few mA to an external circuit. A small film capacitor (0.1 µF typ.),
connected between this pin and GND (3), is recommended to ensure the stability of
the generator and to prevent noise from affecting the reference. This reference is
internally monitored by a separate auxiliary reference and any failure or drift causes
the IC to latch off.
Table 1. Pin functions (continued)
N° Pin Function
Pin settings L6566A
10/52 Doc ID 13794 Rev 4
11 ZCD
Transformer demagnetization sensing input for quasi-resonant operation and OVP
input. The pin is externally connected to the transformer’s auxiliary winding through
a resistor divider. A negative-going edge triggers MOSFET turn-on if QR mode is
selected.
A voltage exceeding 5 V shuts the IC down and brings its consumption to a lower
value (OVP). Latch-off or auto-restart mode is selectable externally. This function is
strobed and digitally filtered to increase noise immunity.
12 MODE/SC
Operating mode selection. If the pin is connected to the VREF pin (7)
quasi-resonant operation is selected and the oscillator (pin 13, OSC) determines
the maximum allowed operating frequency.
Fixed-frequency operation is selected if the pin is not tied to VREF, in which case
the oscillator determines the actual operating frequency, the maximum allowed
duty cycle is set at 70% min. and the pin delivers a voltage ramp synchronized to
the oscillator when the gate-drive output is high; the voltage delivered is zero while
the gate-drive output is low. The pin is to be connected to pin CS (7) via a resistor
for slope compensation.
13 OSC
Oscillator pin. The pin is an accurate 1 V voltage source, and a resistor connected
from the pin to GND (pin 3) defines a current. This current is internally used to set
the oscillator frequency that defines the maximum allowed switching frequency of
the L6566A, if working in QR mode, or the operating switching frequency if working
in FF mode.
14 SS
Soft-start current source. At startup, a capacitor Css between this pin and GND
(pin 3) is charged with an internal current generator. During the ramp, the internal
reference clamp on the current sense pin (7, CS) rises linearly starting from zero to
its final value, therefore causing the duty cycle to increase progressively, starting
also from zero. During soft-start the adaptive UVLO function and all functions
monitoring the COMP pin are disabled. The soft-start capacitor is discharged
whenever the supply voltage of the IC falls below the UVLO threshold. The same
capacitor is used to delay IC shutdown (latch-off or auto-restart mode selectable)
after detecting an overload condition (OLP).
15 VFF
Line voltage feedforward input. The information on the converter’s input voltage is
fed into the pin through a resistor divider and is used to change the setpoint of the
pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint).
The linear dynamics of the pin ranges from 0 to 3 V. A voltage higher than 3 V
makes the IC stop switching. If feedforward is not desired, tie the pin to GND (pin 3)
directly if a latch-mode OVP is not required (see pin 11, ZCD) or through a resistor
if a latch-mode OVP is required. Bypass the pin with a capacitor to GND (pin 3) to
reduce noise pick-up.
16 AC_OK
Brownout protection input. A voltage below 0.45 V shuts down (not latched) the IC,
lowers its consumption, opens the Vcc_PFC pin (6), and clears the latch set by
latched protection (DIS > 4.5 V, SS > 6.4 V, VFF > 6.4 V). IC operation is re-
enabled as the voltage exceeds 0.45 V. The comparator is provided with current
hysteresis: an internal 15 µA current generator is ON as long as the voltage on the
pin is below 0.45 V and is OFF if this value is exceeded. Bypass the pin with a
capacitor to GND (pin 3) to reduce noise pick-up. Tie to Vcc with a 220 to 680 kΩ
resistor if the function is not used.
Table 1. Pin functions (continued)
N° Pin Function
L6566A Electrical data
Doc ID 13794 Rev 4 11/52
3 Electrical data
3.1 Maximum rating
3.2 Thermal data
Table 2. Absolute maximum ratings
Symbol Pin Parameter Value Unit
VHVS 1 Voltage range (referred to ground) -0.3 to 700 V
IHVS 1 Startup current Self-limited
VCC 5 IC supply voltage (Icc = 20 mA) Self-limited
VVcc_PFC 6 Voltage range -0.3 to Vcc V
IVcc_PFC 6 Max. source current (continuous) 30 mA
Vmax 7, 8, 10, 14 Analog inputs and outputs -0.3 to 7 V
Vmax 9, 15, 16 Maximum pin voltage (Ipin ≤ 1 mA) Self-limited
IZCD 11 Zero current detector max. current ±5 mA
VMODE/SC 12 Voltage range -0.3 to 5.3 V
VOSC 13 Voltage range -0.3 to 3.3 V
PTOT Power dissipation @TA = 50 °C 0.75 W
TSTG Storage temperature -55 to 150 °C
T
J
Junction operating temperature range -40 to 150 °C
Table 3. Thermal data
Symbol Parameter Value Unit
R
thJA
Thermal resistance junction to ambient 120 °C/W
Electrical characteristics L6566A
12/52 Doc ID 13794 Rev 4
4 Electrical characteristics
(TJ = -25 to 125 °C, VCC = 12 V, CO = 1 nF; MODE/SC = VREF
, RT = 20 kΩ from OSC to
GND, unless otherwise specified.)
Table 4. Electrical characteristics
Symbol Parameter Test condition Min. Typ. Max. Unit
Supply voltage
Vcc Operating range after turn-on VCOMP > VCOMPL 10.6 23 V
VCOMP = VCOMPO 823
VccOn Turn-on threshold (1) 13 14 15 V
VccOff Turn-off threshold
(1) VCOMP > VCOMPL 9.4 10 10.6 V
(1) VCOMP = VCOMPO 7.2 7.6 8.0
Hys Hysteresis VCOMP > VCOMPL 4V
VZZener voltage Icc = 20 mA, IC disabled 23 25 27 V
Supply current
Istart-up Startup current Before turn-on, Vcc = 13 V 200 250 µA
IqQuiescent current After turn-on, VZCD = VCS = 1 V 2.6 2.8 mA
Icc Operating supply current MODE/SC open 4 4.6 mA
Iqdis Quiescent current IC disabled (2) 330 2500 µA
IC latched off 440 500
High-voltage startup generator
VHV Breakdown voltage IHV < 100 µA 700 V
VHVstart Start voltage IVcc < 100 µA 65 80 100 V
Icharge Vcc charge current VHV > VHvstart, Vcc > 3 V 0.55 0.85 1 mA
IHV, ON ON-state current VHV > VHvstart, Vcc > 3 V 1.6 mA
VHV > VHvstart, Vcc = 0 0.8
IHV, OFF OFF-state leakage current VHV = 400 V 40 µA
VCCrestart Vcc restart voltage
Vcc falling 4.4 5 5.6
V
(1) IC latched off 12.5 13.5 14.5
(1) Disabled by
VCOMP < VCOMPOFF
9.4 10 10.6
Reference voltage
VREF Output voltage (1) TJ = 25 °C; IREF = 1 mA 4.95 5 5.05 V
VREF To t a l va r ia t io n IREF = 1 to 5 mA,
Vcc = 10.6 to 23 V 4.9 5.1 V
L6566A Electrical characteristics
Doc ID 13794 Rev 4 13/52
IREF Short-circuit current VREF = 0 10 30 mA
Sink capability in UVLO Vcc = 6 V; Isink = 0.5 mA 0.2 0.5 V
VOV Overvoltage threshold 5.3 5.7 V
Internal oscillator
fsw Oscillation frequency
Operating range 10 300
kHz
TJ = 25 °C, VZCD = 0,
MODE/SC = open 95 100 105
Vcc=12 to 23 V, VZCD = 0,
MODE/SC = open 93 100 107
VOSC Voltage reference (1) 0.9711.03V
Dmax Maximum duty cycle MODE/SC = open,
VCOMP = 5 V 70 75 %
Brownout protection
Vth Threshold voltage
Voltage falling (turn-off) 0.432 0.450 0.468 V
Voltage rising (turn-on) 0.452 0.485 0.518 V
IHys Current hysteresis Vcc > 5 V, VVFF = 0.3 V 121518µA
VAC_OK_CL Clamp level (1) IAC_OK = 100 µA 3 3.15 3.3 V
Line voltage feedforward
IVFF Input bias current VVFF = 0 to 3 V, VZCD < VZCDth -1 µA
VZCD > VZCDth -0.7 -1 mA
VVFF Linear operation range 0 to 3 V
VOFF IC disable voltage 3 3.15 3.3 V
VVFFlatch Latch-off/clamp level VZCD > VZCDth 6.4 V
Kc Control voltage gain (3) VVFF = 1 V, VCOMP = 4 V 0.4 V/V
KFF Feedforward gain (3) VVFF = 1 V, VCOMP = 4 V 0.04 V/V
Current sense comparator
ICS Input bias current VCS = 0 -1 µA
tLEB Leading edge blanking 150 250 300 ns
td(H-L) Delay to output 100 ns
VCSx Overcurrent setpoint
VCOMP = VCOMPHI, VVFF = 0 V 0.92 1 1.08
VVCOMP = VCOMPHI, VVFF = 1.5 V 0.45 0.5 0.55
VCOMP = VCOMPHI, VVFF = 3.0 V 0 0.1
VCSdis Hiccup-mode OCP level (1) 1.4 1.5 1.6 V
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
Electrical characteristics L6566A
14/52 Doc ID 13794 Rev 4
PWM control
VCOMPHI Upper clamp voltage ICOMP = 0 5.7 V
VCOMPLO Lower clamp voltage ISOURCE = -1 mA 2.0 V
VCOMPSH Linear dynamics upper limit (1) VVFF = 0 V 4.855.2V
ICOMP Max. source current VCOMP = 3.3 V 320 400 480 µA
RCOMP Dynamic resistance VCOMP = 2.6 to 4.8 V 25 kΩ
VCOMPBM Burst-mode threshold
(1) 2.52 2.65 2.78 V
(1) MODE/SC = open 2.7 2.85 3
Hys Burst-mode hysteresis 20 mV
ICLAMPL Lower clamp capability VCOMP = 2 V -3.5 -1.5 mA
VCOMPOFF Disable threshold Voltage falling 1.4 V
Zero current detector/overvoltage protection
VZCDH Upper clamp voltage IZCD = 3 mA 5.4 5.7 6 V
VZCDL Lower clamp voltage IZCD = - 3 mA -0.4 V
VZCDA Arming voltage (1) positive-going edge 85 100 115 mV
VZCDT Triggering voltage (1) negative-going edge 30 50 70 mV
IZCD Internal pull-up VCOMP < VCOMPSH -1 µA
VZCD < 2 V, VCOMP = VCOMPHI -130 -100 -70
IZCDsrc Source current capability VZCD = VZCDL -3 mA
IZCDsnk Sink current capability VZCD = VZCDH 3mA
TBLANK1 Turn-on inhibit time After gate-drive going low 2.5 µs
VZCDth OVP threshold 4.85 5 5.15 V
TBLANK2 OVP strobe delay After gate-drive going low 2 µs
Latched shutdown function
IOTP Input bias current VDIS = 0 to VOTP -1 µA
VOTP Disable threshold (1) 4.32 4.5 4.68 V
Thermal shutdown
Vth Shutdown threshold 180 °C
Hys Hysteresis 40 °C
VCC_PFC function
Ileak OFF-state leakage current VCOMP = 2.5 V, VVcc_PFC = 0 1 µA
VVcc -
VVcc_PFC
ON-state voltage dropout VCOMP = 4 V, I VCC_PFC = 10
mA 0.15 0.3 V
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
L6566A Electrical characteristics
Doc ID 13794 Rev 4 15/52
VCOMPO
Level for pin 6 open and lower
UVLO off threshold (COMP
voltage falling)
(1) 2.61 2.75 2.89 V
(1) MODE/SC = open 3.02 3.15 3.28
VCOMPL
Level for pin 6 closed and
higher UVLO off threshold
(COMP voltage rising)
(1) 2.93.053.2 V
(1) MODE/SC = open 3.41 3.55 3.69
Tdelay Pin 6 change of state delay Closed-to-open 10 ms
Mode selection/slope compensation
MODEth Threshold for QR operation 3 V
SCpk
Ramp peak
(MODE/SC = open)
RS-COMP = 3 kΩ to GND, GD
pin high, VCOMP = 5 V 1.7 V
SCvy
Ramp starting value
(MODE/SC = open)
RS-COMP = 3 kΩ to GND,
GD pin high 0.3 V
Ramp voltage
(MODE/SC = open) GD pin low 0 V
Source capability
(MODE/SC = open) VS-COMP = VS-COMPpk 0.8 mA
Soft-start
ISS1
Charge current
TJ = 25 °C, VSS < 2 V,
VCOMP = 4 V 14 20 26
µA
ISS2
TJ = 25 °C, VSS > 2 V,
VCOMP = VCOMPHi
3.556.5
ISSdis Discharge current VSS > 2 V 3.556.5µA
VSSclamp High saturation voltage VCOMP = 4 V 2 V
VSSDIS Disable level (1) VCOMP = VCOMPHi 4.8555.15V
VSSLAT Latch-off level VCOMP = VCOMPHi 6.4 V
Gate driver
VGDH Output high-voltage IGDsource = 5 mA, Vcc = 12 V 9.8 11 V
VGDL Output low-voltage IGDsink = 100 mA 0.75 V
Isourcepk Output source peak current -0.6 A
Isinkpk Output sink peak current 0.8 A
tfFall time 40 ns
trRise time 50 ns
VGDclamp Output clamp voltage IGDsource = 5 mA; Vcc = 20 V 10 11.3 15 V
UVLO saturation Vcc = 0 to Vccon, Isink = 1 mA 0.9 1.1 V
1. Parameters tracking one another.
2. See Table 6 on page 41 and Table 7 on page 45.
3. The voltage feedforward block output is given by:
Table 4. Electrical characteristics (continued)
Symbol Parameter Test condition Min. Typ. Max. Unit
()
VFFFFCOMPcs VK5.2VKc V −−=
Application information L6566A
16/52 Doc ID 13794 Rev 4
5 Application information
The L6566A is a versatile peak-current-mode PWM controller specific to offline flyback
converters. The device allows either fixed-frequency (FF) or quasi-resonant (QR) operation,
selectable with the MODE/SC pin (12): forcing the voltage on the pin over 3 V (e.g. by tying
it to the 5 V reference externally available at the VREF pin, 10) activates QR operation,
otherwise the device is FF-operated.
Irrespective of the operating option selected by pin 12, the device is able to work in different
modes, depending on the converter's load conditions. If QR operation is selected (see
Figure 4):
1. QR mode at heavy load. Quasi-resonant operation lies in synchronizing MOSFET turn-
on to the transformer's demagnetization by detecting the resulting negative-going edge
of the voltage across any winding of the transformer. The system then works close to
the boundary between discontinuous (DCM) and continuous conduction (CCM) of the
transformer. As a result, the switching frequency is different for different line/load
conditions (see the hyperbolic-like portion of the curves in Figure 4). Minimum turn-on
losses, low EMI emission, and safe behavior in short-circuit are the main benefits of
this kind of operation.
2. Valley-skipping mode at medium/light load. The externally programmable oscillator of
the L6566A, synchronized to MOSFET turn-on, enables the designer to define the
maximum operating frequency of the converter. As the load is reduced, MOSFET turn-
on no longer occurs on the first valley but on the second one, the third one, and so on.
In this way the switching frequency no longer increases (piecewise linear portion in
Figure 4).
3. Burst-mode with no or very light load. When the load is extremely light or disconnected,
the converter enters a controlled on/off operation with constant peak current.
Decreasing the load then results in frequency reduction, which can go down even to a
few hundred hertz, therefore minimizing all frequency-related losses and making it
easier to comply with energy saving regulations or recommendations. Having the peak
current very low, no issue of audible noise arises.
Figure 4. Multi-mode operation with QR option active
0
0
fsw
Pinmax
Input voltage
Pin
fosc
Burst-mode
Valley-skipping
mode
Quasi-resonant mode
L6566A Application information
Doc ID 13794 Rev 4 17/52
If FF operation is selected:
1. FF mode from heavy to light load. The system operates exactly like a standard current
mode, at a frequency fsw determined by the externally programmable oscillator: both
DCM and CCM transformer operations are possible, depending on whether the power
that it processes is greater or less than:
Equation 1
where Vin is the input voltage to the converter, VR the reflected voltage (i.e. the
regulated output voltage times the primary-to-secondary turn ratio) and Lp the
inductance of the primary winding. PinT is the power level that marks the transition from
continuous to discontinuous operation mode of the transformer.
2. Burst-mode with no or very light load. This kind of operation is activated in the same
way and results in the same behavior as previously described for QR operation.
The L6566A is specifically designed for flyback converters operated from front-end power
factor correction (PFC) stages in applications in compliance with EN61000-3-2 or JEITA-
MITI regulations. Pin 6 (Vcc_PFC) provides the supply voltage to the PFC control IC.
5.1 High-voltage startup generator
Figure 5 shows the internal schematic of the high-voltage startup generator (HV generator).
It is made up of a high-voltage N-channel FET, with a gate biased by a 15 MΩ resistor, with
a temperature-compensated current generator connected to its source.
Figure 5. High-voltage startup generator: internal schematic
Lpf2
VVin
VVin
Pin
sw
2
R
R
T
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
=
L6566A 15 MΩ
GND
HV
Vcc5
3
1
I
char
g
e
Vcc_OK
IHV
CONTRO
L
HV_EN
Application information L6566A
18/52 Doc ID 13794 Rev 4
With reference to the timing diagram of Figure 6, when power is first applied to the converter
the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV generator is
enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, minus
the device’s consumption, charges the bypass capacitor connected from pin Vcc (5) to
ground and causes its voltage to rise almost linearly.
Figure 6. Timing diagram: normal power-up and power-down sequences
As the Vcc voltage reaches the startup threshold (14 V typ.) the low-voltage chip starts
operating and the HV generator is cut off by the Vcc_OK signal asserted high. The device is
powered by the energy stored in the Vcc capacitor until the self-supply circuit (typically an
auxiliary winding of the transformer and a steering diode) develops a voltage high enough to
sustain the operation. The residual consumption of this circuit is just the one on the 15 MΩ
resistor (≈10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as
compared to a standard startup circuit made with external dropping resistors.
At converter power-down the system loses regulation as soon as the input voltage is so low
that either peak current or maximum duty cycle limitation is tripped. Vcc then drops and
stops IC activity as it falls below the UVLO threshold (10 V typ.). The Vcc_OK signal is de-
asserted as the Vcc voltage goes below a threshold Vccrestart located at about 5 V. The HV
generator can now restart. However, if Vin < Vinstart, as illustrated in Figure 6, HV_EN is de-
asserted too and the HV generator is disabled. This prevents converter restart attempts and
ensures monotonic output voltage decay at power-down in systems where brownout
protection (see Section 5.12) is not used.
The low restart threshold Vccrestart ensures that, during short-circuits, the restart attempts of
the device have a very low repetition rate, as shown in the timing diagram of Figure 7 on
page 19, and that the converter works safely with extremely low power throughput.
Vcc
(pin 5)
GD
(pin 4)
HV_EN
Vcc ON
Vcc OFF
Vccrestart
t
t
t
t
Vin
VHVstart
Icharge
0.85 mA
t
t
Vcc_OK
Power-on Power-off
Normal
operation
regulation is lost here
Vcc_PFC
(pin 6) heavy load
light load
L6566A Application information
Doc ID 13794 Rev 4 19/52
Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5 V)
Figure 8. Zero current detection block, triggering block, oscillator block and
related logic
Vcc
(pin 5)
GD
(pin 4)
Vcc_OK
VccON
VccOFF
Vccre sta rt
Icharge
0.85 mA
Short circuit occurs here
t
t
t
t
Trep
< 0.03Trep
100 mV
50 mV
DRIV ER
+
-
5.7V
ZCD PWM
GD
R
SQ
BLANKING
TIME
COMP
+Vin
Q
L6566A
5V
-
+
MONO
STABLE
RZ1
blanking
START
RZ2
CS
VFF
TURN-ON
LOGIC
4:1
Counter
Strobe
FAULT
S/H
Reset
line
FFWD
OSCILLATOR
OSC
RT
915
7
4
13
11
Rs
Application information L6566A
20/52 Doc ID 13794 Rev 4
5.2 Zero current detection and triggering block; oscillator block
The zero current detection (ZCD) and triggering blocks switch on the external MOSFET if a
negative-going edge falling below 50 mV is applied to the input (pin 11, ZCD). To do so the
triggering block must be previously armed by a positive-going edge exceeding 100 mV.
This feature is typically used to detect transformer demagnetization for QR operation, where
the signal for the ZCD input is obtained from the transformer’s auxiliary winding used also to
supply the L6566A. The triggering block is blanked for TBLANK = 2.5 µs after MOSFET turn-
off to prevent any negative-going edge that follows leakage inductance demagnetization
from triggering the ZCD circuit erroneously.
The voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the
internal diagram of the ZCD block of Figure 8. The upper clamp is typically located at 5.7 V,
while the lower clamp is located at -0.4 V. The interface between the pin and the auxiliary
winding is a resistor divider. Its resistance ratio is properly chosen (see Section 5.11) and
the individual resistance values (RZ1, RZ2) are such that the current sourced and sunk by
the pin be within the rated capability of the internal clamps (± 3 mA).
At converter power-up, when no signal is coming from the ZCD pin, the oscillator starts up
the system. The oscillator is programmed externally by means of a resistor (RT) connected
from pin OSC (13) to ground. With good approximation the oscillation frequency fosc is:
Equation 2
(with fosc in kHz and RT in kW). As the device is turned on, the oscillator starts immediately;
at the end of the first oscillator cycle, the voltage on the ZCD pin being zero, the MOSFET is
turned on, therefore starting the first switching cycle right at the beginning of the second
oscillator cycle. At any switching cycle, the MOSFET is turned off as the voltage on the
current sense pin (CS, 7) hits an internal reference set by the line feedforward block, and the
transformer starts demagnetization. If this completes (so a negative-going edge appears on
the ZCD pin) after a time exceeding one oscillation period Tosc=1/fosc from the previous turn-
on, the MOSFET is turned on again - with some delay to ensure minimum voltage at turn-on
– and the oscillator ramp is reset. If, instead, the negative-going edge appears before Tosc
has elapsed, it is ignored and only the first negative-going edge after Tosc turns on the
MOSFET and synchronizes the oscillator. In this way one or more drain ringing cycles are
skipped (“valley-skipping mode”, Figure 9) and the switching frequency is prevented from
exceeding fosc.
T
3
osc R
102
f⋅
≈
Figure 9. Drain ringing cycle skipping as the load is gradually reduced
Pin = Pin'
(limit condition) Pin = Pin'' < Pin' Pin = Pin''' < Pin''
t
V
DS
TFW
Tosc
TV
TON
t
VDS
T
osc
t
VDS
Tosc
L6566A Application information
Doc ID 13794 Rev 4 21/52
Note: When the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET
is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Therefore one or more longer switching
cycles is compensated by one or more shorter cycles, and vice versa. However, this
mechanism is absolutely normal and there is no appreciable effect on the performance of
the converter or on its output voltage.
If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is
smaller than the arming threshold for some reason (e.g. a heavy damping of drain
oscillations, like in some single-stage PFC topologies, or when a turn-off snubber is used),
MOSFET turn-on cannot be triggered. This case is identical to what happens at startup: at
the end of the next oscillator cycle the MOSFET is turned on, and a new switching cycle
takes place after skipping no more than one oscillator cycle.
The operation described so far does not consider the blanking time TBLANK after MOSFET
turn-off, and actually TBLANK does not come into play as long as the following condition is
met:
Equation 3
where D is the MOSFET duty cycle. If this condition is not met, nothing changes
substantially: the time during which MOSFET turn-on is inhibited is extended beyond Tosc by
a fraction of TBLANK. As a consequence, the maximum switching frequency is a little lower
than the programmed value fosc and valley-skipping mode may take place slightly earlier
than expected. However this is quite unusual: setting fosc = 150 kHz, the phenomenon can
be observed at duty cycles higher than 60%. See Section 5.11 for further implications of
TBLANK.
If the voltage on the COMP pin (9) saturates high, which reveals an open control loop, an
internal pull-up keeps the ZCD pin close to 2 V during MOSFET OFF-time to prevent noise
from false triggering the detection block. When this pull-up is active, the ZCD pin may not be
able to go below the triggering threshold, which would stop the converter. To allow auto-
restart operation, while ensuring minimum operating frequency in these conditions, the
oscillator frequency that retriggers MOSFET turn-on is that of the external oscillator divided
by 128. Additionally, to prevent malfunction at converter startup, the pull-up is disabled
during the initial soft-start (see Section 5.10). However, to ensure a correct startup, at the
end of the soft-start phase, the output voltage of the converter must meet the condition:
Equation 4
where Ns is the turn number of the secondary winding, Naux the turn number of the
auxiliary winding, and IZCD the maximum pull-up current (130 μA).
osc
BLANK
T
T
1D −≤
ZCD1Z IR
Naux
Ns
Vout >
Application information L6566A
22/52 Doc ID 13794 Rev 4
The operation described so far under different operating conditions for the converter is
illustrated in the timing diagrams of Figure 10.
If the FF option is selected, the operation is exactly equal to that of a standard current-mode
PWM controller. It works at a frequency fsw = fosc; both DCM and CCM transformer
operations are possible, depending on the operating conditions (input voltage and output
load) and on the design of the power stage. The MOSFET is turned on at the beginning of
each oscillator cycle and is turned off as the voltage on the current sense pin reaches an
internal reference set by the line feedforward block. The maximum duty cycle is limited at
70% minimum. The signal on the ZCD pin in this case is used only for detecting feedback
loop failures (see Section 5.11).
Figure 10. Operation of ZCD, triggering and oscillator blocks (QR option active)
a) full load
GD
(pin 4)
ZCD
blanking
time
ZCD
(pin 11)
Oscillator
ramp
PWM latch
Set
PWM latch
Reset
ON-enable
Ar m / Tr i g g e r
50 mV
100 mV
armed trigger
b) light load
ZCD
blanking
time
PWM latch
Set
PWM latch
Reset
ON-enable
Ar m / Tr i g ge r
50 mV
100 mV
Oscillator
ramp
GD
(pin 4)
ZCD
(pin 11)
c) start-up
ZCD
blanking
time
PWM latch
Set
PWM latch
Reset
ON-enable
Arm/Trigger
50 mV
100 mV
Oscillator
ramp
GD
(pin 4)
ZCD
(pin 11)
L6566A Application information
Doc ID 13794 Rev 4 23/52
5.3 Burst-mode operation at no load or very light load
When the voltage at the COMP pin (9) falls 20 mV below a threshold fixed internally at a
value, VCOMPBM, depending on the selected operating mode, the L6566A is disabled with
the MOSFET kept in OFF-state and its consumption reduced at a lower value to minimize
Vcc capacitor discharge.
The control voltage now increases as a result of the feedback reaction to the energy delivery
stop (the output voltage is slowly decaying), the threshold is exceeded and the device
restarts switching again. In this way the converter works in burst-mode with a nearly
constant peak current defined by the internal disable level. A load decreases and then
causes a frequency reduction, which can go down even to a few hundred hertz, therefore
minimizing all frequency-related losses and making it easier to comply with energy saving
regulations. This kind of operation, shown in the timing diagrams of Figure 11 along with the
others previously described, is noise-free since the peak current is low.
If it is necessary to decrease the intervention threshold of the burst-mode operation, this can
be done by adding a small DC offset on the current sense pin as shown in Figure 12.
Note: The offset reduces the available dynamics of the current signal; thereby, the value of the
sense resistor must be determined taking this offset into account.
Figure 11. Load-dependent operating modes: timing diagrams
GD
(pin 4)
VCOMPBM
t
t
t
COMP
(pin 9)
20 mV
hyster.
QR Mode
Valley-skipping Mode
Burst-mode
fsw
fosc
QR Mode
FF Mode Burst-mode FF Mode
MODE/SC=Open
MODE/SC=VREF
MODE/SC=Open
MODE/SC=VREF
Application information L6566A
24/52 Doc ID 13794 Rev 4
Figure 12. Addition of an offset to the current sense lowers the burst-mode
operation threshold
5.4 Adaptive UVLO
A major problem when optimizing a converter for minimum no-load consumption is that the
voltage generated by the auxiliary winding under these conditions falls considerably as
compared even to few mA load. This very often causes the supply voltage Vcc of the control
IC to drop and go below the UVLO threshold so that the operation becomes intermittent,
which is undesired. Furthermore, this must be traded off against the need of generating a
voltage not exceeding the maximum allowed by the control IC at full load.
To help the designer overcome this problem, the device, besides reducing its own
consumption during burst-mode operation, also features a proprietary adaptive UVLO
function. It consists of shifting the UVLO threshold downwards at light load, namely when
the voltage at the COMP pin falls below a threshold VCOMPO internally fixed (see
Section 5.8), so as to have more headroom. To prevent any malfunction during transients
from minimum to maximum load, the normal (higher) UVLO threshold is re-established
when the voltage at the COMP pin exceeds VCOMPL (see Section 5.8) and Vcc has
exceeded the normal UVLO threshold (see Figure 13). The normal UVLO threshold ensures
that at full load the MOSFET is driven with a proper gate-to-source voltage.
Rs
L6566A R
Vr ef
Rc
10
4
7
3
Vcso= Vref R
R + Rc
Figure 13. Adaptive UVLO block
VCOMPL
VCOMPO
VCOMP
(pin 9)
Vcc
(pin 5)
Q
VccOFF1
VccOFF2
t
t
t
t
Vcc_PFC
(pin 6) Tdelay
(*) VccOFF2 < VccOFF1 is selected when Q is high
+
-
UVLO
VccOFF 1
Vcc
L6566A
C
OMP
R
S Q
+
-
+
-
VccOFF2
(*)
SW
5
9
VCOMP L
VCOMP O
Vcc_PFC
logic
Vcc_PFC
6
L6566A Application information
Doc ID 13794 Rev 4 25/52
5.5 PWM control block
The device is specific to secondary feedback. Typically, there is a TL431 on the secondary
side and an optocoupler that transfers output voltage information to the PWM control on the
primary side, crossing the isolation barrier. The PWM control input (pin 9, COMP) is driven
directly by the phototransistor’s collector (the emitter is grounded to GND) to modulate the
duty cycle (Figure 14, left-hand side circuit).
In applications where a tight output regulation is not required, it is possible to use a primary-
sensing feedback technique. In this approach the voltage generated by the self-supply
winding is sensed and regulated. This solution, shown in Figure 14, right-hand side circuit,
is cheaper because no optocoupler or secondary reference is needed, but output voltage
regulation, especially as a result of load changes, is quite poor. Ideally, the voltage
generated by the self-supply winding and the output voltage should be related by the
Naux/Ns turn ratio only. In fact, numerous non-idealities, mainly transformer parasitics,
cause the actual ratio to deviate from the ideal one. Line regulation is quite good, in the
range of ± 2%, whereas load regulation is about ± 5% and output voltage tolerance is in the
range of ±10%.
The dynamic of the pin is in the 2.5 to 5 V range. The voltage at the pin is clamped
downwards at about 2 V. If the clamp is externally overridden and the voltage on the pin is
pulled below 1.4 V, the L6566A shuts down. This condition is latched as long as the device
is supplied. While the device is disabled, however, no energy is coming from the self-supply
circuit, therefore the voltage on the Vcc capacitor decays and crosses the UVLO threshold
after some time, which clears the latch and lets the HV generator restart. This function is
intended for an externally controlled burst-mode operation at light load with a reduced
output voltage, a technique typically used in multi-output SMPS, such as those for CRT TVs
or monitors (see the timing diagram Figure 15).
Figure 14. Possible feedback configurations that can be used with the L6566A
Vout
TL431
L6566A
9
COMP
L6566A
5 Vcc
Naux
9
COMP
Cs
Secondary feedback Primary feedback
Application information L6566A
26/52 Doc ID 13794 Rev 4
Figure 15. Externally controlled burst-mode operation by driving the COMP pin:
timing diagram
5.6 PWM comparator, PWM latch and voltage feedforward blocks
The PWM comparator senses the voltage across the current sense resistor Rs and, by
comparing it to the programming signal delivered by the feedforward block, determines the
exact instant when the external MOSFET must be switched off. Its output resets the PWM
latch, previously set by the oscillator or the ZCD triggering block, which asserts the gate-
driver output low. The use of PWM latch avoids spurious switching of the MOSFET that may
result from the noise generated (“double-pulse suppression”).
Cycle-by-cycle current limitation is realized with a second comparator (OCP comparator)
that also senses the voltage across the current sense resistor Rs and compares this voltage
to a reference value VCSX. Its output is OR-ed with that of the PWM comparator (see the
circuit schematic in Figure 17). In this way, if the programming signal delivered by the
feedforward block and sent to the PWM comparator exceeds VCSX, it is the OCP comparator
that first resets the PWM latch instead of the PWM comparator. The value of Vcsx, thereby,
determines the overcurrent setpoint along with the sense resistor Rs.
The power that QR flyback converters with a fixed overcurrent setpoint (like fixed-frequency
systems) are able to deliver changes considerably with the input voltage. Obviously, this is
not a problem if the flyback converter runs off a fixed voltage bus generated by the PFC pre-
regulator; however, with a tracking boost PFC (a “boost follower” PFC), the regulated output
voltage at maximum mains voltage can be even twice the value at minimum mains voltage.
In this case the issue remains, although it is not as great as without PFC and wide-range
mains. With a 1: 2 voltage change, the maximum transferable power at maximum line can
Vcc
(pin 5)
GD
(pin 4)
Vcc_OK
VccON
VccOFF
Vccresta rt
Icharge
0.85 mA
Standby is commanded here
t
t
t
t
t
Vcc_PFC
(pin 6)
t
COMP
(pin 9)
t
Vout
L6566A Application information
Doc ID 13794 Rev 4 27/52
be 50% higher than at minimum line, as shown by the upper curve in the diagram of
Figure 16. The L6566A has the line feedforward function available to solve this issue.
Figure 16. Typical power capability change vs. input voltage in QR flyback
converters
It acts on the overcurrent setpoint Vcsx, so that it is a function of the converter’s input voltage
Vin (output of the PFC pre-regulator) sensed through a dedicated pin (15, VFF): the higher
the input voltage, the lower the setpoint. This is illustrated in the diagram on the left-hand
side of Figure 17: it shows the relationship between the voltage on the VFF and Vcsx pin
(with the error amplifier saturated high in an attempt to maintain the output voltage
regulation):
Equation 5
Note: If the voltage on the pin exceeds 3 V, switching ceases but the soft-start capacitor is not
discharged. The schematic in Figure 17 also shows how the function is included in the
control loop.
With a proper selection of the external divider R1-R2, i.e. of the ratio k = R2 / (R1+R2), it is
possible to achieve the optimum compensation described by the lower curve in the diagram
of Figure 16.
The optimum value of k, kopt, which minimizes the power capability variation over the input
voltage range, is the one that provides equal power capability at the extremes of the range.
The exact calculation is complex, and non-idealities shift the real-world optimum value from
the theoretical one. It is therefore more practical to provide a first cut value, easily
calculated, and then to fine-tune experimentally.
Assuming that the system operates exactly at the boundary between DCM and CCM, and
neglecting propagation delays, the following expression for kopt can be found:
V
in
V
inmin
P
inlim
@ V
in
P
inlim
@ V
inmin
1 1.5 2 2.5 3 3.5 4
0.5
1
1.5
2
2.5
system optimally
compensated
system not
compensated
k = 0
k = k
opt
k
Vin
3
k
1
3
V
1V VFF
csx −=−=
Application information L6566A
28/52 Doc ID 13794 Rev 4
Equation 6
Experience shows that this value is typically lower than the real one. Once the maximum
peak primary current, IPKpmax, occurring at minimum input voltage Vinmin has been found,
the value of Rs can be determined from (2):
Equation 7
The converter is then bench tested to find the output power level Poutlim where regulation is
lost (because overcurrent is being tripped) both at Vin = Vinmin and Vin = Vinmax.
If Poutlim @ Vinmax > Poutlim @ Vinmin the system is still undercompensated and k needs to
increase; if Poutlim @ Vinmax < Poutlim @ Vinmin the system is overcompensated and k
needs to decrease. This continues until the difference between the two values is acceptably
low. Once the true kopt is found in this way, it is possible that Poutlim turns out slightly
different from the target; to correct this, the sense resistor Rs needs adjusting and the above
tuning process is repeated with the new Rs value. Typically, a satisfactory setting is achieved
in no more than a couple of iterations.
In applications where this function is not wanted, e.g. because the PFC stage regulates at a
fixed voltage, the VFF pin can be simply grounded, directly or through a resistor, depending
on whether one wants the OVP function to be auto-restart or latched mode (see
Section 5.11). The overcurrent setpoint is then fixed at the maximum value of 1 V. If a lower
setpoint is desired to reduce the power dissipation on Rs, the pin can be also biased at a
fixed voltage using a divider from VREF (pin 10).
()
Rmaxinmininmaxinminin
R
opt VVVVV
V
3k ⋅++⋅
⋅=
maxPKp
minin
opt
I
V
3
k
1
Rs
−
=
Figure 17. Left: overcurrent setpoint vs. VFF voltage; right: line feedforward function block
V
csx [V]
00.511.522.533.5
0
0.2
0.4
0.6
0.8
1
1.2
VVFF [V]
VCOMP = Upper clamp
7
9
15
Rs
PFC Output Bus
DRIVER
4
R
SQ
R1B
R2
COMP
VFF CS
GD
L6566A 1.5 V
+
-
Hiccup DISABLE
VOLTAGE
FEED
FORWARD
To PFC's OV
se n si n g Optional for
OVP settings
OCP
+
-
PWM
+
-
Vcsx Clock/ZCD
R1A
L6566A Application information
Doc ID 13794 Rev 4 29/52
If the FF option is selected, the line feedforward function can be still used to compensate for
the total propagation delay Td of the current sense chain (internal propagation delay td(H-L)
plus the turn-off delay of the external MOSFET), which in standard current mode PWM
controllers is done by adding an offset on the current sense pin proportional to the input
voltage. In that case, the divider ratio k, which is much smaller when compared to that used
with the QR option selected, can be calculated with the following equation:
Equation 8
where Lp is the inductance of the primary winding. In case a constant maximum power
capability vs. the input voltage is not required, the VFF pin can be grounded, directly or
through a resistor (see Section 5.11), therefore fixing the overcurrent setpoint at 1 V, or
biased at a fixed voltage through a divider from VREF to get a lower setpoint.
It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to ensure
a clean operation of the IC even in a noisy environment.
The pin is internally forced to ground during UVLO, after activating any latched protection
and when the COMP pin is pulled below its low clamp voltage (see Section 5.5).
5.7 Hiccup-mode OCP
A third comparator senses the voltage on the current sense input and shuts down the device
if the voltage on the pin exceeds 1.5 V, a level well above that of the maximum overcurrent
setpoint (1 V). Such an anomalous condition is typically generated by either a short-circuit of
the secondary rectifier or a shorted secondary winding, or a hard-saturated flyback
transformer.
To distinguish an actual malfunction from a disturbance (e.g. induced during ESD tests), the
first time the comparator is tripped, the protection circuit enters a “warning state”. If, in the
next switching cycle, the comparator is not tripped, a temporary disturbance is assumed and
the protection logic is reset in its idle state; if the comparator is tripped again a real
malfunction is assumed and the L6566A is stopped. Depending on the time relationship
between the detected event and the oscillator, occasionally the device may stop after the
third detection.
This condition is latched as long as the device is supplied. While it is disabled, however, no
energy is coming from the self-supply circuit; so the voltage on the Vcc capacitor decays
and crosses the UVLO threshold after some time, which clears the latch. If the internal
startup generator is still off, then the Vcc voltage still needs to go below its restart voltage
before the Vcc capacitor is charged again and the device restarted. Ultimately, this results in
a low-frequency intermittent operation (hiccup-mode operation), with very low stress on the
power circuit. This special condition is illustrated in the timing diagram of Figure 18.
LpRs
Td
3kopt =
Application information L6566A
30/52 Doc ID 13794 Rev 4
Figure 18. Hiccup-mode OCP: timing diagram
5.8 PFC interface
The device is specifically designed to minimize converter losses under light or no-load
conditions, and a special function has been provided to help the designer meet energy
saving requirements even in power-factor-corrected systems where a PFC pre-regulator
precedes the isolated DC-DC converter.
In fact, EMC regulations require compliance with low-frequency harmonic emission limits at
nominal load; no limit is envisaged when the converter operates with a light load. Then the
PFC pre-regulator can be turned off, therefore saving the no-load consumption of this stage
(0.5÷1 W).
To do so, the L6566A provides the Vcc_PFC pin (6): this pin is internally connected to the
Vcc pin (5) via a PNP transistor, normally closed, that opens when the voltage VCOMP falls
below VCOMPO, a threshold internally set at a value depending on whether QR operation or
FF operation is selected. This pin is intended for supplying the PFC controller of the pre-
regulator as shown in Figure 16. The switch is thermally protected, so that the IC stops if an
external failure causes the pin to be overloaded for too long a time or shorted to ground.
Vcc
(pin 5)
GD
(pin 4)
OCP latch
VccON
VccOFF
Vccrestart
Secondary diode is shorted here
t
t
t
t
VCS
(pin 7)
Vcc_OK
t
1.5 V
Vcc_PFC
(pin 6)
t
L6566A Application information
Doc ID 13794 Rev 4 31/52
Figure 19. Possible interfaces between the L6566A and a PFC controller
To prevent intermittent operation of the PFC stage, some hysteresis is provided: if the
internal switch is open, it is closed (which re-enables the PFC pre-regulator) when VCOMP
exceeds VCOMPL > VCOMPO. Additionally, to reject VCOMP undershoots during transients,
VCOMP must stay below VCOMPO for more than 1024 oscillator cycles in order for the
Vcc_PFC pin to open. Entering burst-mode (VCOMP < VCOMPBM) opens Vcc_PFC
immediately.
Besides pin 6 going open, when VCOMP falls below VCOMPO the UVLO threshold is set 2.4 V
below to compensate for the drop of the voltage delivered by the self-supply circuit that
occurs at light load (see Section 5.4).
5.9 Latched disable function
The device is equipped with a comparator having the non-inverting input externally available
at the DIS pin (8) and with the inverting input internally referenced to 4.5 V. As the voltage
on the pin exceeds the internal threshold, the device is immediately shut down and its
consumption reduced to a low value.
The information is latched and it is necessary to let the voltage on the Vcc pin go below the
UVLO threshold to reset the latch and restart the device. To keep the latch supplied as long
as the converter is connected to the input source, the HV generator is activated periodically
so that Vcc oscillates between the startup threshold VccON and VccON - 0.5 V. Activating the
HV generator in this way cuts its power dissipation approximately by three (as compared to
the case of continuous conduction) and keeps peak silicon temperature close to the average
value.
To let the L6566A restart it is then necessary to disconnect the converter from the input
source. Pulling pin 16 (AC_OK) below the disable threshold (see Section 5.12) stops the HV
generator until Vcc falls below Vccrestart, so that the latch can be cleared and a quicker
restart is allowed as the input source is removed. This operation is shown in the timing
diagram of Figure 20.
This function is useful to easily implement a latched overtemperature protection by biasing
the pin with a divider from VREF, where the upper resistor is an NTC physically located
close to a heating element like the MOSFET, or the transformer. The DIS pin is a high-
impedance input, it is therefore prone to pick-up noise, which might give origin to undesired
latch-off of the device. It is possible to bypass the pin to ground with a small film capacitor
(e.g. 1-10 nF) to prevent any malfunctioning of this kind.
L6566A
Vcc_PFC6
5
Vcc Vcc
L6566A
Vcc_PFC6L6563
5
Vcc RUN
4.7kΩ
22 kΩ
10
L6561
L6562
L6563
Application information L6566A
32/52 Doc ID 13794 Rev 4
Figure 20. Operation after latched disable activation: timing diagram
5.10 Soft-start and delayed latched shutdown upon overcurrent
At device startup, a capacitor (Css) connected between the SS pin (14) and ground is
charged by an internal current generator, ISS1, from zero up to about 2 V where it is
clamped. During this ramp, the overcurrent setpoint progressively rises from zero to the
value imposed by the voltage on the VFF pin 15, (see Section 5.6); MOSFET conduction
time increases gradually, therefore controlling the startup inrush current. The time needed
for the overcurrent setpoint to reach its steady-state value, referred to as soft-start time, is
approximately:
Equation 9
During the ramp (i.e. until VSS = 2 V) all the functions that monitor the voltage on the COMP
pin are disabled.
The soft-start pin is also invoked whenever the control voltage (COMP) saturates high,
which reveals an open-loop condition for the feedback system. This condition very often
occurs at startup, but may be also caused by either a control loop failure or a converter
overload/short-circuit. A control loop failure results in an output overvoltage that is handled
by the OVP function of the L6566A (see Section 5.11). In the case of QR operation, a short-
circuit causes the converter to run at a very low frequency, then with very low power
capability. This causes the self-supply system that powers the device to switch off, so that
Vcc
(pin 5)
GD
(pin 4)
Vin
Vcc ON
Vcc ON -0.5
t
t
t
t
4.5V
Vcc OFF
DIS
(pin 8)
Vcc restart
VHVstart
HV generator is turned on
HV generator turn-on is disabled here
Input source is removed here
Vcc_PFC
(pin 6)
t
AC_OK
(pin 16)
Vth
Disable latch is reset here
Restart is quicker
t
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−== 3
V
1
I
Css
)V(V
I
Css
TVFF
1SS
VFFcsx
1SS
SS
L6566A Application information
Doc ID 13794 Rev 4 33/52
the converter works intermittently, which is very safe. In case of overload the system has a
power capability lower than that at nominal load but the output current may be quite high
and overstressing the output rectifier. In the case of FF operation the capability is almost
unchanged and both short-circuit and overload conditions are more critical to handle.
The L6566A, regardless of the operating option selected, makes it easier to handle such
conditions: the 2 V clamp on the SS pin is removed and a second internal current generator
ISS2 = ISS1 /4 keeps on charging Css. As the voltage reaches 5 V, the device is disabled, if it
is allowed to reach 2 VBE over 5 V, the device is latched off. In the former case the resulting
behavior is identical to that under short-circuit illustrated in Figure 6; in the latter case the
result is identical to that of Figure 20. See Section 5.9 for additional details.
A diode, with the anode to the SS pin and the cathode connected to the VREF pin (10) is the
simplest way to select either auto-restart mode or latch-mode behavior upon overcurrent. If
the overload disappears before the Css voltage reaches 5 V, the ISS2 generator is turned off
and the voltage gradually brought back down to 2 V. Refer to Section 6 (Figure 7) for
additional hints.
If latch-mode behavior is desired also for converter short-circuit, make sure that the supply
voltage of the device does not fall below the UVLO threshold before activating the latch.
Figure 21 shows soft-start pin behavior under different operating conditions and with
different settings (latch-mode or auto-restart).
Note: Unlike other PWM controllers provided with a soft-start pin, in the L6566A, grounding the SS
pin does not guarantee that the gate-driver is disabled.
Figure 21. Soft-start pin operation under different operating conditions and settings
t
Vcc
(pin 5)
SS
(pin 14)
t
t
COMP
(pin 9)
ST ART -U P TE MP OR AR Y
OVERLOAD
OVERLOAD
t
GD
(pin 4)
NORMAL
OPERATION
NORMAL
OPERATION
RESTART
here the IC
shuts down
here the IC
latches off
Vcc falls below UVLO
before latching off
SHUTDOWN
LATC HED
AUTORESTART
UVLO
2V
5V
5V+2Vbe
t
V
cc_PFC
(pin 6)
Application information L6566A
34/52 Doc ID 13794 Rev 4
5.11 OVP block
The OVP function of the L6566A monitors the voltage on the ZCD pin (11) in the MOSFET
OFF-time, during which the voltage generated by the auxiliary winding tracks the converter
output voltage. If the voltage on the pin exceeds an internal 5 V reference, a comparator is
triggered, an overvoltage condition is assumed and the device is shut down. An internal
current generator is activated that sources 1 mA out of the VFF pin (15). If the VFF voltage
is allowed to reach 2 Vbe over 5 V, the L6566A is latched off. See Section 5.9 for more
details on the IC’s behavior under these conditions. If the impedance externally connected
to pin 15 is so low that the 5+2 VBE threshold cannot be reached or if some means is
provided to prevent that, the device is able to restart after the Vcc has dropped below 5 V.
Refer to Section 6 (Ta b l e 7 ) for additional hints.
Figure 22. OVP function: internal block diagram
Figure 23. OVP function: timing diagram
Fault
2-bit
counter
R Q1
S
Monostable
M1
STROBE
OVP
COUT
2 µ s 0.5 µ s
Monostable
M2
-
+
5 V
ZCD
Counter
reset
FF
40kΩ
5pF
PWM latch
Q
QS
R
11
to triggering
block L6566A
t
GD
(pin 4)
Vau x
5V
t
t
t
STROBE
t
C
OUN TER
RESET
t
C
OUN TER
STATUS
t
0
ZCD
(pin 11)
2 µ s 0.5 µs
OVP
t
FAULT
00 00
→11
→22
→00
→11
→22
→33
→40
NORMAL OPERATION TEMPORARY DISTURBANCE FEEDBACK LOOP FAILURE
t
COUT
Vcc_PFC
(pin 6) t
L6566A Application information
Doc ID 13794 Rev 4 35/52
The ZCD pin is connected to the auxiliary winding through a resistor divider RZ1, RZ2 (see
Figure 8). The divider ratio kOVP = RZ2 / (RZ1 + RZ2) is chosen equal to:
Equation 10
where VoutOVP is the output voltage value that is to activate the protection, Ns is the turn
number of the secondary winding and Naux is the turn number of the auxiliary winding. The
value of RZ1 is such that the current sourced by the ZCD pin be within the rated capability of
the internal clamp:
Equation 11
where Vinmax is the maximum DC input voltage and Ns the turn number of the primary
winding. See Section 5.2 for additional details.
To reduce sensitivity to noise and prevent the latch from being erroneously activated, first
the OVP comparator is active only for a small time window (typically, 0.5 µs), starting 2 µs
after MOSFET turn-off, to reject the voltage spike associated to the positive-going edges of
the voltage across the auxiliary winding Vaux; secondly, to stop the L6566A, the OVP
comparator must be triggered for four consecutive switching cycles. A counter, which is
reset every time the OVP comparator is not triggered in one switching cycle, is provided for
this purpose.
Figure 22 shows the internal block diagram, while the timing diagrams in Figure 23 illustrate
the operation.
Note: To use the OVP function effectively, i.e. to ensure that the OVP comparator is always
interrogated during MOSFET OFF-time, the duty cycle D under open-loop conditions must
fulfill the following inequality:
Equation 12
where TBLANK2 = 2 µs; this is also illustrated in the diagram of Figure 24.
Naux
Ns
Vout
5
k
OVP
OVP =
max
3
1Z Vin
Np
Naux
103
1
R−
⋅
≥
1fTD sw2BLANK ≤+
Application information L6566A
36/52 Doc ID 13794 Rev 4
Figure 24. Maximum allowed duty cycle vs. switching frequency for correct OVP
detection
5.1041.1051.5 .1052.1052.5.1053.1053.5 .1054.105
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.725
fsw [Hz]
Dmax
L6566A Application information
Doc ID 13794 Rev 4 37/52
5.12 Brownout protection
Brownout protection is basically a not-latched device shutdown function activated when a
condition of mains undervoltage is detected. There are several reasons why it may be
desirable to shut down a converter during a brownout condition, which occurs when the
mains voltage falls below the minimum specification of normal operation.
Firstly, a brownout condition may cause overheating of the PFC front-end due to an excess
of RMS current. Secondly, brownout can also cause the PFC pre-regulator to work open
loop. This could be dangerous to the PFC itself and the downstream converter, should the
input voltage return abruptly to its rated value, given the slow response of PFC to transient
events. Finally, spurious restarts may occur during converter power-down, therefore causing
the output voltage not to decay to zero monotonically.
The L6566A shutdown upon brownout is accomplished by means of an internal comparator,
as shown in the block diagram of Figure 25, which shows the basic circuit usage. The
inverting input of the comparator, available on the AC_OK pin (16), is supposed to sense a
voltage proportional to either the RMS or the peak mains voltage; the non-inverting input is
internally referenced to 0.485 V with 35 mV hysteresis. If the voltage applied on the AC_OK
pin before the device starts operating does not exceed 0.485 V or if it falls below 0.45 V
while the device is running, The AC_OK signal goes high, the Vcc_PFC pin is open and the
device shuts down, with the soft-start capacitor discharged and the gate-drive output low.
Additionally, in case the device has been latched off by some protection function (in which
case Vcc is oscillating between VccON and VccON - 0.5 V), the AC_OK voltage falling below
0.45 V clears the latch. This feature can be used to allow a quicker restart as the input
source is removed.
Figure 25. Brownout protection: internal block diagram and timing diagram
-
+
L6566A
AC_ FAIL
AC_OK
Vcc
16
5
0.485V
0.45V
15 µA
RH
RL
Sensed
voltage
Vcc
(pin 5)
GD
(pin 4)
Vout
VAC_OK
(pin 16)
0.45V
IHYS
15 µA
t
t
t
t
t
t
t
t
Vcc_PFC
(pin 6)
AC _ FAI L
Sensed voltage
VsenON
VsenOFF
0.485V
Application information L6566A
38/52 Doc ID 13794 Rev 4
While the brownout protection is active the startup generator keeps on working but, there
being no PWM activity, the Vcc voltage continuously oscillates between the startup and the
HV generator restart thresholds, as shown in the timing diagram of Figure 25.
The brownout comparator is provided with current hysteresis in addition to voltage
hysteresis: an internal 15 µA current sink is ON as long as the voltage applied on the
AC_OK pin is such that the AC_FAIL signal is high. This approach provides an additional
degree of freedom: it is possible to set the ON threshold and the OFF threshold separately
by properly choosing the resistors of the external divider (see Equation 13 and 14 below).
With just voltage hysteresis, instead, fixing one threshold automatically fixes the other one
depending on the built-in hysteresis of the comparator.
With reference to Figure 25, the following relationships can be established for the ON
(VsenON) and OFF (VsenOFF) thresholds of the sensed voltage:
Equation 13
which, solved for RH and RL, yield:
Equation 14
It is usually convenient to not use additional dividers connected to high-voltage rails
because this could make it difficult to meet no-load consumption targets envisaged by
energy-saving regulations. Figure 26 shows a simple voltage sensing technique that makes
use of the divider already used by the PFC control chip to sense the AC mains voltage with
just the addition of an extra tap.
The small-signal NPN Q and the capacitor CF create a peak detector, so that the information
of the RMS mains voltage can be found across CF
. The tap position determines the DC
voltage to be sensed by the AC_OK pin. It is convenient to use a level as high as possible to
minimize the effect of VBE changes with temperature. However, it may be necessary to limit
the maximum sensed voltage below 7 V to prevent Q’s emitter reverse breakdown; it would
not be destructive because the reverse current would be quite small (the resistors seen by
Figure 26. AC voltage sensing with the L6566A
LH
OFF
L
6
H
ON
R
45.0
R
45.0Vsen
R
485.0
1015
R
485.0Vsen =
−
+⋅=
−−
45.0Vsen
45.0
RR;
1015
Vsen078.1Vsen
R
OFF
HL
6
OFFON
H−
=
⋅
⋅−
=−
L6566A
Rectified
input voltage
RH
Sensed
voltage:
Vsen < 7V
RL
CF
3
MULT
L6561
L6562/A
L6563
Vcc
5
AC_OK
16
QQ
For minimum
temperature drift
L6566A Application information
Doc ID 13794 Rev 4 39/52
the base terminal are several ten kW) but this could distort the signal on the MULT pin of the
PFC chip and adversely affect the operation of the pre-regulator. CF needs to be quite a big
capacitor (in the μF) to have small residual ripple superimposed on the DC level; as a rule-
of-thumb, use a time constant (RL + RH)·CF at least 4-5 times the maximum line cycle
period, then fine-tune if needed, considering also transient conditions such as mains
missing cycles.
If temperature effects are critical, the NPN Q can be replaced by a PNP-NPN pair arranged
as shown in Figure 26 on the right-hand side; other sensing techniques may also be
adopted.
The voltage on the pin is clamped upwards at about 3.15 V; then, if the function is not used,
the pin must be connected to Vcc through a resistor (220 to 680 kΩ).
5.13 Slope compensation
The MODE/SC pin (12), when not connected to VREF, provides a voltage ramp during
MOSFET ON-time synchronous to that of the internal oscillator sawtooth, with 0.8 mA
minimum current capability. This ramp is intended for implementing additive slope
compensation on current sense. This is needed to avoid the sub-harmonic oscillation that
arises in all peak-current-mode-controlled converters working at fixed frequency in
continuous conduction mode with a duty cycle close to or exceeding 50%.
Figure 27. Slope compensation waveforms
The compensation is realized by connecting a programming resistor between this pin and
the current sense input (pin 7, CS). The CS pin must be connected to the sense resistor with
another resistor to make a summing node on the pin. Since no ramp is delivered during
MOSFET OFF-time (see Figure 27), no external component other than the programming
resistor is needed to ensure a clean operation at light loads.
Note: The addition of the slope compensation ramp reduces the available dynamics of the current
signal; therefore, the value of the sense resistor must be determined taking this into
account. Note also that the burst-mode threshold (in terms of power) changes slightly.
If slope compensation is not required with FF operation, the pin is left floating.
Internal
oscillator
GD
(pin 4)
MODE/ SC
(pin 12)
t
t
t
Application information L6566A
40/52 Doc ID 13794 Rev 4
5.14 Summary of L6566A power management functions
It has been seen that the device is provided with a number of power management functions:
multiple operating mode upon loading conditions, protection functions, as well as interaction
with the PFC pre-regulator. To help the user familiarize themselves with these functions, in
the following tables all of the themes are summarized with their respective activation
mechanisms and the resulting status of the most important pins. This may be useful not only
for the correct use of the IC but also for diagnostic purposes: especially at the
prototyping/debugging stage, it is quite common to bump into unwanted activation of some
functions, and the following tables can be used as a sort of quick troubleshooting guide.
Table 5. L6566A light load management features
Feature Description Caused
by
IC
behavior
Vcc_restar
t
(V)
Consump.
(Iqdis,mA)
VREF
(V) SS VCOMP
(V)
OSC
(V) FMOD
Burst
mode
Controlled
ON-OFF
operation for
low power
consumptio
n at light
load
VCOMP
<
VCOMPB
M - Hys
Pulse-
skipping
operation
N.A. 1.34 mA 5 Unchang
ed
VCOMPBM
-HYS to
VCOMPBM
0/1 0
PFC
manage
ment
PFC OFF at
light load,
ON at heavy
load
VCOMP
<
VCOMP
O
VCC_PFC
= 0 N.A. 5 Unchang
ed
unchange
d10
VCOMP
<
VCOMPL
VCC_PFC
= VCC
VCC
L6566A Application information
Doc ID 13794 Rev 4 41/52
Table 6. L6566A protection
Protection Description Caused by IC
behavior
Vcc
restart IC Iq VREF
SS
VCOMP OSC
FMOD VFF
(V) (mA) (V) (V) (V)
OVP
Output
overvoltage
protection
VZCD>VZCDth
for 4
consecutive
switching
cycles
Auto
restart(1) 52.25
(6) Unchanged(
6) 0 0 0 Unchanged
VFF >
VFFlatch Latched 13.5 0.33 0 0 0 0 0 0
OLP Output overload
protection
VCOMP
=VCOMPHi
VSS > VSSDIS
Auto
restart(2) 51.465
(6) VSS
<VSSLAT(3) VCOMPHi(6) 0 0 Unchanged
VCOMP
=VCOMPHi
VSS > VSSLAT
Latched 13.5 0.33 0 0 0 0 0 0
Short-circuit
protection
Output short-
circuit protection
VCOMP
=VCOMPHi
VSS >
VSSDIS(4)
Auto
restart 51.460 VSS
<VSSLAT(6) VCOMPHi(5) 0 Unchanged
VCOMP
=VCOMPHi
VSS >
VSSLAT(6)
Latched 13.5 0.33 0 0 0 0 0 0
2nd OCP
Transformer
saturation or
shorted
secondary diode
protection
VCS > VCSDIS
for 2-3
consecutive
switching
cycles
Latched 5 0.33 0 0 0 0 0 0
L6566A Application information
Doc ID 13794 Rev 4 42/52
OTP
Externally
settable
overtemperature
protection
VDIS>VOTP Latched 13.5 0.33 0 0 0 0 0 0
Internal thermal
shutdown Tj > 160 oCAuto
restart(5) 50.330 0 0 0 0 0
Brownout
Mains
undervoltage
protection
VAC_OK < Vth Auto restart 5 0.33 0 0 0 0 0 Unchanged
Reference drift VREF drift
protection VREF > Vov Latched 13.5 0.33 0 0 0 0 0 0
Shutdown1 Gate driver
disable VFF > Voff Auto restart 5 2.5 5 Unchanged Unchanged 1 Unchanged Unchanged
Shutdown2 Shutdown by
VCOMP low
VCOMP <
VCOMPOFF
Latched 10 0.33 0 0 0 0 0 0
Adaptive UVLO
Shutdown by Vcc
going
below Vccoff
(lowering of
Vccoff threshold
at light load)
Vcc < 9.4 V
(VCOMP >
VCOMPL)Auto restart 5V 0.18 0 0 0 0 0 0
Vcc < 7.2 V
(VCOMP >
VCOMPO)
1. Use One external diode from VFF (#15) to AC_OK (#16), cathode to AC_OK2
2. Use one external diode from SS (#14) to VREF (#10), cathode to VREF
3. If Css and the Vcc capacitor are such that Vcc falls below UVLO before latch tripping (Figure 21 on page 33)
4. If Css and the Vcc capacitor are such that the latch is tripped before Vcc falls below UVLO (Figure 21 on page 33)
5. When TJ < 110 oC
6. Discharged to zero by Vcc going below UVLO
Table 6. L6566A protection (continued)
Protection Description Caused by IC
behavior
Vcc
restart IC Iq VREF
SS
VCOMP OSC
FMOD VFF
(V) (mA) (V) (V) (V)
L6566A Application information
Doc ID 13794 Rev 4 43/52
It is worth remembering that “auto-restart” means that the device works intermittently as
long as the condition that is activating the function is not removed; “latched” means that the
device is stopped as long as the unit is connected to the input power source and the unit
must be disconnected for some time from the source in order for the device (and the unit) to
restart. Optionally, a restart can be forced by pulling the voltage of pin 16 (AC_OK) below
0.45 V.
Application examples and ideas L6566A
44/52 Doc ID 13794 Rev 4
6 Application examples and ideas
Figure 28. Typical low-cost application schematic
PFC Pre-regulator Output bus
IC1
L6566A
C3
Q1
R2
D2
R8
C9
D1
C7 2.2 nF Y1
R9
R10
C8A,B
T1
ZCD
GD
CS
VccAC_OK
GND
VFF
COMP
D4
IC3
R4
D3
1
2
3
4
C6
R5
C2
SS
C5
VREFMOD E/ SC
C4 R6
HVSFMOD
OSC
DIS
TL431
R1
R3 470k
R7
Vout
Optional f or
QR operation
4
7
3
5
11
15
16
91413
8
1012
16
Optional f or
QR operation
Output capacitor of boost
PFC Pre-regulator
Figure 29. Typical full-feature application schematic (QR operation)
4
7
3
511
6
8
IC1
L6566A
Vout
9
R4
C3
Q1
R2
D2
1N4148
R18
D1
C7 2.2 nF Y1
C8A,B
T1
ZCD
GD
CS
Vcc
DIS
GND
VFF
COMP
D4
IC3 PC817A
R3
D3 1N4148
3
4
C6
R5
C2
14
SS
13
C5
16
10
VREF
12
MODE/ SC
C4 R6
1
HVS
OSC
AC_OK
R1
R12
R1
3
R1
4
R8
C9
R9
R10
1
2
TL431
R7
NTC2
Vcc_PFC
to Vcc pin of
PFC controller
15
C1
PFC Pre-regulator Output bus
Output c apacitor of boos t
PFC Pre-regulator
to mains
v oltage sensing
L6566A Application examples and ideas
Doc ID 13794 Rev 4 45/52
Figure 30. Typical full-feature application schematic (FF operation)
4
7
3
511
6
8
IC1
L6566A
Vout
9
C3
Q1
R2
D2
1N4148
R18
D1
C7 2.2 nF Y1
C8A,B
T1
ZCD
GD
CS
Vcc
DIS
GNDCOMP
D4
IC3 PC817A
R3
R4
D3 1N4148
3
4
C6
R5
C2
14
SS
13
C5
10
VREF
12
MOD E/ SC
C4 R6
1
HVS
OSC
R1
R12
R1
3
R1
5
R16
R17
R8
C9
R9
R10
1
2
TL431
R7
NTC2
Vcc_PFC
to Vcc pin of
PFC controller
C1
PFC Pre-regulator Output bus
Output capacitor of boost
PFC Pre-regulator
VFF
16
AC_OK
15
to mains
v oltage sensing
Table 7. External circuits that determine IC behavior upon OVP and OCP
OVP latched OVP auto-restart
OCP latched
OCP auto-restart
L6566A
VFF 15
RL
RFF
RH
RFF needed if RL< 4.7 kΩ
SS VREF
14 10
L6566A
AC_OK
16
RH
VFF 15
RL
Diode needed if RL> 4.7 kΩ
SS VREF
14 10
L6566A
SS VREF
14 10
1N4148
VFF 15
RL
RFF
RH
RFF needed if RL< 4.7 kΩ
L6566A
16
15
SS VREF
14 10
1N4148
AC_OK
RH
VFF
RL
Diode needed if RL> 4.7 kΩ
Application examples and ideas L6566A
46/52 Doc ID 13794 Rev 4
Figure 31. Frequency foldback at light load (FF operation)
Figure 32. Latched shutdown upon mains overvoltage
R1
L6566A
Vr e f
RT
10
9
13
COMP
OSC
BC857
MODE/SC
12
R2
L6566A
Vcc
5
8
VFF
BC847
DIS
Vin
15 L6566A
8VFF
BC857
DIS
Vin
15
Vr ef
10
Rq
>10 Rq
L6566A Package mechanical data
Doc ID 13794 Rev 4 47/52
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 8. SO16N mechanical data
Dim.
mm
Min. Typ. Max.
A1.75
A1 0.10 0.25
A2 1.25
b0.31 0.51
c0.17 0.25
D 9.80 9.90 10.00
E5.806.006.20
E1 3.80 3.90 4.00
e1.27
h0.25 0.50
L0.40 1.27
k0 8°
ccc 0.10
Package mechanical data L6566A
48/52 Doc ID 13794 Rev 4
Figure 33. Package drawing
0016020_F
L6566A Package mechanical data
Doc ID 13794 Rev 4 49/52
Figure 34. Recommended footprint (dimensions are in mm)
Order codes L6566A
50/52 Doc ID 13794 Rev 4
8 Order codes
Table 9. Order codes
Order codes Package Packaging
L6566A SO16N Tube
L6566ATR SO16N Tape and reel
L6566A Revision history
Doc ID 13794 Rev 4 51/52
9 Revision history
Table 10. Document revision history
Date Revision Changes
20-Aug-2007 1 First release
29-May-2008 2 Updated VMODE/SC value Table 2 on page 11
02-Dec-2008 3 Updated Figure 1 on page 1 and Section 5.6 on page 27
14-Mar-2012 4
Modified: Table 4: Electrical characteristics and Table 8: SO16N
mechanical data; replaced Figure 33: Package drawing with a more
detailed version; added Figure 34: Recommended footprint
(dimensions are in mm)
L6566A
52/52 Doc ID 13794 Rev 4
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