LTC6240CS5#PBF - Linear Technology Corporation

LTC6240/LTC6241/LTC6242

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Single/Dual/Quad 18MHz,

Low Noise, Rail-to-Rail Output,

CMOS Op Amps

The LTC

6240/6241/LTC6242 are single, dual and quad

low noise, low offset, rail-to-rail output, unity gain stable

CMOS op amps that feature 1pA of input bias current. Input

bias current is guaranteed to be 1pA max on the single

LTC6240. The 0.1Hz to 10Hz noise of only 550nVP-P, along

with an offset of just 125µV are signiﬁ cant improvements

over traditional CMOS op amps. Additionally, noise is

guaranteed to be less than 10nV/√Hz at 1kHz. An 18MHz

gain bandwidth, and 10V/µs slew rate, along with the wide

supply range and low input capacitance, make them perfect

for use as fast signal processing ampliﬁ ers.

These op amps have an output stage that swings within

30mV of either supply rail to maximize the signal dynamic

range in low supply applications. The input common mode

range extends to the negative supply. They are fully speci-

ﬁ ed on 3V and 5V, and an HV version guarantees operation

on supplies up to ±5V.

The LTC6240 is available in the 8-pin SO and the 5-pin SOT-

23 packages. The LTC6241 is available in the 8-pin SO, and

for compact designs it is packaged in a tiny dual ﬁ ne pitch

leadless (DFN) package. The LTC6242 is available in the

16-pin SSOP as well as the 5mm × 3mm DFN package.

n Photo Diode Ampliﬁ ers

n Charge Coupled Ampliﬁ ers

n Low Noise Signal Processing

n Medical Instrumentation

n High Impedance Transducer Ampliﬁ er

n 0.1Hz to 10Hz Noise: 550nVP-P

n Input Bias Current:

0.2pA (Typ at 25°C)

1pA Max (LTC6240)

n Low Offset Voltage: 125μV Max

n Low Offset Drift: 2.5µV/°C Max

n Gain Bandwidth Product: 18MHz

n Output Swings Rail-to-Rail

n Supply Operation:

2.8V to 6V LTC6240/LTC6241/LTC6242

2.8V to ±5.5V LTC6240HV/LTC6241HV/LTC6242HV

n Low Input Capacitance

n H-Grade Temperature Range: –40°C to 125°C

n Single LTC6240 in 5-Pin Low Proﬁ le (1mm)

ThinSOT™ Package and 8-Pin SO for PCB Guard Ring

n Dual LTC6241 in 8-Pin SO and Tiny DFN Packages

n Quad LTC6242 in 16-Pin SSOP and 5mm × 3mm

DFN Packages

Low Noise Single-Ended Input to Differential Output Ampliﬁ er Noise Voltage vs Frequency

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

DESCRIPTION

FEATURES

APPLICATIONS

–

200k

10pF

+2.5V

–2.5V

6241 TA01a

4.99k

200k

VIN

VOUT+

VOUT–

1/2

LTC6241

–1/2

LTC6241

10pF

4.99k

10pF

FREQUENCY (Hz)

NOISE VOLTAGE (nV/√Hz)

1 100 1k 100k

6241 TA01b

010 10k

TA = 25°C

VS = ±2.5V

VCM = 0V

LTC6240/LTC6241/LTC6242

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Total Supply Voltage (V+ to V–)

LTC6240/LTC6241/LTC6242 ...................................7V

LTC6240HV/LTC6241HV/LTC6242HV ....................12V

Input Voltage .......................... (V+ + 0.3V) to (V– – 0.3V)

Input Current ........................................................±10mA

Output Short-Circuit Duration (Note 2) ............ Indeﬁ nite

Operating Temperature Range

LTC6240C/LTC6241C/LTC6242C ..........–40°C to 85°C

LTC6240I/LTC6241I/LTC6242I .............–40°C to 85°C

LTC6240H/LTC6241H/LTC6242H ....... –40°C to 125°C

(Note 1)

Speciﬁ ed Temperature Range (Note 3)

LTC6240C/LTC6241C/LTC6242C .............. 0°C to 70°C

LTC6240I/LTC6241I/LTC6242I .............–40°C to 85°C

LTC6240H/LTC6241H/LTC6242H ....... –40°C to 125°C

Junction Temperature ........................................... 150°C

DHC, DD Package ............................................. 125°C

Storage Temperature Range ..................–65°C to 150°C

DHC, DD Package .............................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec)...................300°C

ABSOLUTE MAXIMUM RATINGS

LTC6240 LTC6240

OUT 1

V– 2

TOP VIEW

S5 PACKAGE

5-LEAD PLASTIC TSOT-23

+IN 3

5 V+

4 –IN

–

TJMAX = 150°C, θJA = 250°C/W

TOP VIEW

V+

OUT

–IN

+IN

V–

S8 PACKAGE

8-LEAD PLASTIC SO

–

TJMAX = 150°C, θJA = 190°C/W

LTC6241 LTC6241

TOP VIEW

DD PACKAGE

8-LEAD (3mm s 3mm) PLASTIC DFN

1OUT A

–IN A

+IN A

V–

V+

OUT B

–IN B

+IN B

TJMAX = 125°C, θJA = 43°C/W

UNDERSIDE METAL CONNECTED TO V–

(PCB CONNECTION OPTIONAL)

TOP VIEW

V+

OUT B

–IN B

+IN B

OUT A

–IN A

+IN A

V–

S8 PACKAGE

8-LEAD PLASTIC SO

TJMAX = 150°C, θJA = 190°C/W

LTC6242 LTC6242

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

OUT A

–IN A

+IN A

V+

+IN B

–IN B

OUT B

TOP VIEW

DHC PACKAGE

16-LEAD (5mm s 3mm) PLASTIC DFN

TJMAX = 125°C, θJA = 43°C/W

UNDERSIDE METAL CONNECTED TO V– (PCB CONNECTION OPTIONAL)

GN PACKAGE

16-LEAD PLASTIC SSOP

TOP VIEW

OUT A

–IN A

+IN A

V+

+IN B

–IN B

OUT B

OUT D

–IN D

+IN D

V–

+IN C

–IN C

OUT C

TJMAX = 150°C, θJA = 135°C/W

PIN CONFIGURATION

LTC6240/LTC6241/LTC6242

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LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE

LTC6240CS5#PBF LTC6240CS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 0°C to 70°C

LTC6240HVCS5#PBF LTC6240HVCS5#TRPBF LTCRS 5-Lead Plastic TSOT-23 0°C to 70°C

LTC6240IS5#PBF LTC6240IS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 –40°C to 85°C

LTC6240HVIS5#PBF LTC6240HVIS5 #TRPBF LTCRS 5-Lead Plastic TSOT-23 –40°C to 85°C

LTC6240HS5#PBF LTC6240HS5#TRPBF LTCRR 5-Lead Plastic TSOT-23 –40°C to 125°C

LTC6240HVHS5#PBF LTC6240HVHS5#TRPBF LTCRS 5-Lead Plastic TSOT-23 –40°C to 125°C

LTC6240CS8#PBF LTC6240CS8#TRPBF 6240 8-Lead Plastic SO 0°C to 70°C

LTC6240HVCS8#PBF LTC6240HVCS8#TRPBF 6240HV 8-Lead Plastic SO 0°C to 70°C

LTC6240IS8#PBF LTC6240IS8#TRPBF 6240I 8-Lead Plastic SO –40°C to 85°C

LTC6240HVIS8#PBF LTC6240HVIS8#TRPBF 240HVI 8-Lead Plastic SO –40°C to 85°C

LTC6240HS8#PBF LTC6240HS8#TRPBF 6240H 8-Lead Plastic SO –40°C to 125°C

LTC6240HVHS8#PBF LTC6240HVHS8#TRPBF 240HVH 8-Lead Plastic SO –40°C to 125°C

LTC6241CDD#PBF LTC6241CDD#TRPBF LBPD 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C

LTC6241HVCDD#PBF LTC6241HVCDD#TRPBF LBRR 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C

LTC6241IDD#PBF LTC6241IDD#TRPBF LBPD 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LTC6241HVIDD#PBF LTC6241HVIDD#TRPBF LBRR 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LTC6241CS8#PBF LTC6241CS8#TRPBF 6241 8-Lead Plastic SO 0°C to 70°C

LTC6241HVCS8#PBF LTC6241HVCS8#TRPBF 6241HV 8-Lead Plastic SO 0°C to 70°C

LTC6241IS8#PBF LTC6241IS8#TRPBF 6241I 8-Lead Plastic SO –40°C to 85°C

LTC6241HVIS8#PBF LTC6241HVIS8#TRPBF 241HVI 8-Lead Plastic SO –40°C to 85°C

LTC6241HS8#PBF LTC6241HS8#TRPBF 6241H 8-Lead Plastic SO –40°C to 125°C

LTC6241HVHS8#PBF LTC6241HVHS8#TRPBF 241HVH 8-Lead Plastic SO –40°C to 125°C

LTC6242CDHC#PBF LTC6242CDHC#TRPBF 6242 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C

LTC6242HVCDHC#PBF LTC6242HVCDHC#TRPBF 6242HV 16-Lead (5mm × 3mm) Plastic DFN 0°C to 70°C

LTC6242IDHC#PBF LTC6242IDHC#TRPBF 6242 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C

LTC6242HVIDHC#PBF LTC6242HVIDHC#TRPBF 6242HV 16-Lead (5mm × 3mm) Plastic DFN –40°C to 85°C

LTC6242CGN#PBF LTC6242CGN#TRPBF 6242 16-Lead Plastic SSOP 0°C to 70°C

LTC6242HVCGN#PBF LTC6242HVCGN#TRPBF 6242HV 16-Lead Plastic SSOP 0°C to 70°C

LTC6242IGN#PBF LTC6242IGN#TRPBF 6242I 16-Lead Plastic SSOP –40°C to 85°C

LTC6242HVIGN#PBF LTC6242HVIGN#TRPBF 242HVI 16-Lead Plastic SSOP –40°C to 85°C

LTC6242HGN#PBF LTC6242HGN#TRPBF 6242H 16-Lead Plastic SSOP –40°C to 125°C

LTC6242HVHGN#PBF LTC6242HVHGN#TRPBF 242HVH 16-Lead Plastic SSOP –40°C to 125°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

ORDER INFORMATION

LTC6240/LTC6241/LTC6242

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AVAILABLE OPTIONS

PART NUMBER AMPS/PACKAGE SPECIFIED TEMP RANGE SPECIFIED SUPPLY VOLTAGE PACKAGE PART MARKING

LTC6240CS5 1 0°C to 70°C 3V, 5V SOT-23 LTCRR

LTC6240CS8 1 0°C to 70°C 3V, 5V SO-8 6240

LTC6240HVCS5 1 0°C to 70°C 3V, 5V, ±5V SOT-23 LTCRS

LTC6240HVCS8 1 0°C to 70°C 3V, 5V, ±5V SO-8 6240HV

LTC6240IS5 1 –40°C to 85°C 3V, 5V SOT-23 LTCRR

LTC6240IS8 1 –40°C to 85°C 3V, 5V SO-8 6240I

LTC6240HVIS5 1 –40°C to 85°C 3V, 5V, ±5V SOT-23 LTCRS

LTC6240HVIS8 1 –40°C to 85°C 3V, 5V, ±5V SO-8 240HVI

LTC6240HS5 1 –40°C to 125°C 3V, 5V SOT-23 LTCRR

LTC6240HS8 1 –40°C to 125°C 3V, 5V SO-8 6240H

LTC6240HVHS5 1 –40°C to 125°C 3V, 5V, ±5V SOT-23 LTCRS

LTC6240HVHS8 1 –40°C to 125°C 3V, 5V, ±5V SO-8 240HVH

LTC6241CS8 2 0°C to 70°C 3V, 5V SO-8 6241

LTC6241CDD 2 0°C to 70°C 3V, 5V DD LBPD

LTC6241HVCS8 2 0°C to 70°C 3V, 5V, ±5V SO-8 6241HV

LTC6241HVCDD 2 0°C to 70°C 3V, 5V, ±5V DD LBRR

LTC6241IS8 2 –40°C to 85°C 3V, 5V SO-8 6241I

LTC6241IDD 2 –40°C to 85°C 3V, 5V DD LBPD

LTC6241HVIS8 2 –40°C to 85°C 3V, 5V, ±5V SO-8 241HVI

LTC6241HVIDD 2 –40°C to 85°C 3V, 5V, ±5V DD LBRR

LTC6241HS8 2 –40°C to 125°C 3V, 5V SO-8 6241H

LTC6241HVHS8 2 –40°C to 125°C 3V, 5V, ±5V SO-8 241HVH

LTC6242CGN 4 0°C to 70°C 3V, 5V GN 6242

LTC6242CDHC 4 0°C to 70°C 3V, 5V DHC 6242

LTC6242HVCGN 4 0°C to 70°C 3V, 5V, ±5V GN 6242HV

LTC6242HVCDHC 4 0°C to 70°C 3V, 5V, ±5V DHC 6242HV

LTC6242IGN 4 –40°C to 85°C 3V, 5V GN 6242I

LTC6242IDHC 4 –40°C to 85°C 3V, 5V DHC 6242

LTC6242HVIGN 4 –40°C to 85°C 3V, 5V, ±5V GN 242HVI

LTC6242HVIDHC 4 –40°C to 85°C 3V, 5V, ±5V DHC 6242HV

LTC6242HGN 4 –40°C to 125°C 3V, 5V GN 6242H

LTC6242HVHGN 4 –40°C to 125°C 3V, 5V, ±5V GN 242HVH

LTC6240/LTC6241/LTC6242

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ELECTRICAL CHARACTERISTICS

(LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,

LTC6242HVC/I) The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at

TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage (Note 4) LTC6241 S8

0°C to 70°C

–40°C to 85°C

40 125

250

300

µV

LTC6242 GN

0°C to 70°C

–40°C to 85°C

50 150

275

300

µV

LTC6240

0°C to 70°C

–40°C to 85°C

50 175

300

350

µV

LTC6241 DD, LTC6242 DHC

0°C to 70°C

–40°C to 85°C

100 550

650

725

µV

VOS Match Channel-to-Channel (Note 5) LTC6241 S8

0°C to 70°C

–40°C to 85°C

40 160

300

375

µV

LTC6242 GN

0°C to 70°C

–40°C to 85°C

50 185

325

400

µV

LTC6241 DD, LTC6242 DHC

0°C to 70°C

–40°C to 85°C

150 650

700

750

µV

TC VOS Input Offset Voltage Drift (Note 6) l0.7 2.5 µV/°C

IBInput Bias Current (Notes 4, 7) LTC6241, LTC6242

0.2 75 pA

LTC6240

0.2 1

75 pA

IOS Input Offset Current (Notes 4, 7) LTC6241, LTC6242

0.2 75 pA

LTC6240

0.2 1

75 pA

Input Noise Voltage 0.1Hz to 10Hz 550 nVP-P

enInput Noise Voltage Density f = 1kHz 7 10 nV/√Hz

inInput Noise Current Density (Note 8) 0.56 fA/√Hz

RIN Input Resistance Common Mode 1012 

CIN Input Capacitance

Differential Mode

Common Mode

f = 100kHz 3.5

3pF

VCM Input Voltage Range Guaranteed by CMRR l0 3.5 V

CMRR Common Mode Rejection 0V ≤ VCM ≤ 3.5V l80 105 dB

CMRR Match

Channel-to-Channel (Note 5) l76 95 dB

LTC6240/LTC6241/LTC6242

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AVOL Large Signal Voltage Gain VO = 1V to 4V

RL = 10k to VS/2

0°C to 70°C

–40°C to 85°C

425

300

200

1600 V/mV

V/mV

VO = 1.5V to 3.5V

RL = 1k to VS/2

0°C to 70°C

–40°C to 85°C

215 V/mV

V/mV

VOL Output Voltage Swing Low (Note 9) No Load

ISINK = 1mA

ISINK = 5mA

190

325

VOH Output Voltage Swing High (Note 9) No Load

ISOURCE = 1mA

ISOURCE = 5mA

190

325

PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l80 104 dB

PSRR Match

Channel-to-Channel (Note 5) l74 100 dB

Minimum Supply Voltage (Note 10) l2.8 V

ISC Short-Circuit Current l15 30 mA

ISSupply Current per Ampliﬁ er LTC6241, LTC6242

0°C to 70°C

–40°C to 85°C

1.8 2.2

2.3

2.4

LTC6240

0°C to 70°C

–40°C to 85°C

2 2.4

2.5

2.6

GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k l13 18 MHz

SR Slew Rate (Note 11) AV = –2, RL = 1k l5 10 V/µs

FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1k l0.53 1.06 MHz

tsSettling Time VSTEP = 2V, AV = –1, RL = 1k, 0.1% 1100 ns

ELECTRICAL CHARACTERISTICS

(LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,

LTC6242HVC/I) The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at

TA = 25°C. VS = 5V, 0V, VCM = 2.5V unless otherwise noted.

LTC6240/LTC6241/LTC6242

624012fe

ELECTRICAL CHARACTERISTICS

(LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,

LTC6242HVC/I) The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at

TA = 25°C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage (Note 4) LTC6241 S8

0°C to 70°C

–40°C to 85°C

40 175

275

325

µV

LTC6242 GN

0°C to 70°C

–40°C to 85°C

60 200

275

325

µV

LTC6240

0°C to 70°C

–40°C to 85°C

50 200

325

375

µV

LTC6241 DD, LTC6242 DHC

0°C to 70°C

–40°C to 85°C

100 550

650

725

µV

VOS Match Channel-to-Channel (Note 5) LTC6241 S8

0°C to 70°C

–40°C to 85°C

40 200

325

400

µV

LTC6242 GN

0°C to 70°C

–40°C to 85°C

60 225

325

400

µV

LTC6241 DD, LTC6242 DHC

0°C to 70°C

–40°C to 85°C

150 650

700

750

µV

TC VOS Input Offset Voltage Drift (Note 6) l0.7 2.5 µV/°C

IBInput Bias Current (Notes 4, 7) LTC6241, LTC6242

0.2 75 pA

LTC6240

0.2 1

75 pA

IOS Input Offset Current (Notes 4, 7) LTC6241, LTC6242

0.2 75 pA

LTC6240

0.2 1

75 pA

VCM Input Voltage Range Guaranteed by CMRR l0 1.5 V

CMRR Common Mode Rejection 0V ≤ VCM ≤ 1.5V l78 100 dB

CMRR Match

Channel-to-Channel (Note 5) l76 95 dB

AVOL Large Signal Voltage Gain VO = 1V to 2V

RL = 10k to VS/2

0°C to 70°C

–40°C to 85°C

140

100

600 V/mV

V/mV

VOL Output Voltage Swing Low (Note 9) No Load

ISINK = 1mA

65 30

110 mV

VOH Output Voltage Swing High (Note 9) No Load

ISOURCE = 1mA

70 30

120 mV

PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l80 104 dB

PSRR Match

Channel-to-Channel (Note 5) l74 100 dB

Minimum Supply Voltage (Note 10) l2.8 V

ISC Short-Circuit Current l36 mA

LTC6240/LTC6241/LTC6242

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage (Note 4) LTC6241 S8

0°C to 70°C

–40°C to 85°C

50 175

275

325

µV

LTC6242 GN

0°C to 70°C

–40°C to 85°C

60 200

275

325

µV

LTC6240

0°C to 70°C

–40°C to 85°C

60 250

350

400

µV

LTC6241 DD, LTC6242 DHC

0°C to 70°C

–40°C to 85°C

100 550

650

725

µV

VOS Match Channel-to-Channel (Note 5) LTC6241 S8

0°C to 70°C

–40°C to 85°C

50 200

325

400

µV

LTC6242 GN

0°C to 70°C

–40°C to 85°C

60 225

325

400

µV

LTC6241 DD, LTC6242 DHC

0°C to 70°C

–40°C to 85°C

150 650

700

750

µV

TC VOS Input Offset Voltage Drift (Note 6) l0.7 2.5 µV/°C

IBInput Bias Current (Notes 4, 7) LTC6241, LTC6242

0.5 75 pA

LTC6240

0.5 1

75 pA

IOS Input Offset Current (Notes 4, 7) LTC6241, LTC6242

0.2 75 pA

LTC6240

0.2 1

75 pA

Input Noise Voltage 0.1Hz to 10Hz 550 nVP-P

(LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. VS = ±5V, 0V, VCM = 0V unless otherwise noted.

ELECTRICAL CHARACTERISTICS

(LTC6240C/I, LTC6240HVC/I, LTC6241C/I, LTC6241HVC/I, LTC6242C/I,

LTC6242HVC/I) The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at

TA = 25°C. VS = 3V, 0V, VCM = 1.5V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ISSupply Current per Ampliﬁ er LTC6241, LTC6242

0°C to 70°C

–40°C to 85°C

1.4 1.7

1.8

1.9

LTC6240

0°C to 70°C

–40°C to 85°C

1.5 1.9

2.1

GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k l12 17 MHz

LTC6240/LTC6241/LTC6242

624012fe

ELECTRICAL CHARACTERISTICS

(LTC6240HVC/I, LTC6241HVC/I, LTC6242HVC/I) The l denotes the

speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. VS = ±5V, 0V, VCM = 0V

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

enInput Noise Voltage Density f = 1kHz 7 10 nV/√Hz

inInput Noise Current Density (Note 8) 0.56 fA/√Hz

RIN Input Resistance Common Mode 1012 

CIN Input Capacitance

Differential Mode

Common Mode

f = 100kHz 3.5

3pF

VCM Input Voltage Range Guaranteed by CMRR l–5 3.5 V

CMRR Common Mode Rejection –5V ≤ VCM ≤ 3.5V l83 105 dB

CMRR Match

Channel-to-Channel (Note 5) l76 95 dB

AVOL Large Signal Voltage Gain VO = –3.5V to 3.5V

RL = 10k

0°C to 70°C

–40°C to 85°C

775

600

500

2700 V/mV

V/mV

RL = 1k

0°C to 70°C

–40°C to 85°C

150

360 V/mV

V/mV

VOL Output Voltage Swing Low (Note 9) No Load

ISINK = 1mA

ISINK = 10mA

360

550

VOH Output Voltage Swing High (Note 9) No Load

ISOURCE = 1mA

ISOURCE = 10mA

360

550

PSRR Power Supply Rejection VS = 2.8V to 11V, VCM = 0.2V l85 110 dB

PSRR Match

Channel-to-Channel (Note 5) l82 106 dB

Minimum Supply Voltage (Note 10) l2.8 V

ISC Short-Circuit Current l15 35 mA

ISSupply Current per Ampliﬁ er LTC6241, LTC6242

0°C to 70°C

–40°C to 85°C

2.5 3.2

3.3

3.7

LTC6240

0°C to 70°C

–40°C to 85°C

2.7 3.3

3.4

3.8

GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k l13 18 MHz

SR Slew Rate (Note 11) AV = –2, RL = 1k l5.5 10 V/µs

FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P

, RL = 1k l0.58 1.06 MHz

tsSettling Time VSTEP = 2V, AV = –1, RL = 1k, 0.1% 900 ns

LTC6240/LTC6241/LTC6242

624012fe

(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH)

The l denotes the speciﬁ cations which apply from –40°C to 125°C, otherwise speciﬁ cations are at TA = 25°C. VS = 5V, 0V, VCM = 2.5V

unless otherwise noted.

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage (Note 4) LTC6241 S8

40 125

400 µV

µV

LTC6242 GN

50 150

400 µV

µV

LTC6240

50 175

450 µV

µV

VOS Match Channel-to-Channel (Note 5) LTC6241 S8

40 160

400 µV

µV

LTC6242 GN

50 185

400 µV

µV

TC VOS Input Offset Voltage Drift (Note 6) l0.7 2.5 µV/°C

IBInput Bias Current (Notes 4, 7) LTC6241, LTC6242

0.2 1.5 pA

LTC6240

0.2 1

2.5 pA

IOS Input Offset Current (Notes 4, 7) LTC6241, LTC6242

0.2 150 pA

LTC6240

0.2 1

750 pA

VCM Input Voltage Range Guaranteed by CMRR l0 3.5 V

CMRR Common Mode Rejection 0V ≤ VCM ≤ 3.5V l78 dB

CMRR Match

Channel-to-Channel (Note 5) l74 dB

AVOL Large Signal Voltage Gain VO = 1V to 4V

RL = 10k to VS/2

425

200 1600 V/mV

V/mV

VO = 1.5V to 3.5V

RL = 1k to VS/2

40 215 V/mV

V/mV

VOL Output Voltage Swing Low (Note 9) No Load

ISINK = 1mA

ISINK = 5mA

325

VOH Output Voltage Swing High (Note 9) No Load

ISOURCE = 1mA

ISOURCE = 5mA

325

PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l78 dB

PSRR Match

Channel-to-Channel (Note 5) l74 dB

Minimum Supply Voltage (Note 10) l2.8 V

ISC Short-Circuit Current l15 mA

ISSupply Current per Ampliﬁ er LTC6241, LTC6242

1.8 2.2

2.4 mA

LTC6240

2 2.4

2.8 mA

GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k l12 MHz

SR Slew Rate (Note 11) AV = –2, RL = 1k l4.5 V/µs

FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1k l0.48 MHz

LTC6240/LTC6241/LTC6242

624012fe

ELECTRICAL CHARACTERISTICS

(LTC6240H/LTC6240HVH, LTC6241H/LTC6241HVH, LTC6242H/LTC6242HVH)

The l denotes the speciﬁ cations which apply from –40°C to 125°C, otherwise speciﬁ cations are at TA = 25°C. VS = 3V, 0V, VCM = 1.5V

unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage (Note 4) LTC6241 S8

40 175

400 µV

µV

LTC6242 GN

60 200

400 µV

µV

LTC6240

50 200

450 µV

µV

VOS Match Channel-to-Channel (Note 5) LTC6241 S8

40 200

400 µV

µV

LTC6242 GN

60 225

400 µV

µV

TC VOS Input Offset Voltage Drift (Note 6) l0.7 2.5 µV/°C

IBInput Bias Current (Notes 4, 7) LTC6241, LTC6242

0.2 1.5 pA

LTC6240

0.2 1

2.5 pA

IOS Input Offset Current (Notes 4, 7) LTC6241, LTC6242

0.2 150 pA

LTC6240

0.2 1

750 pA

VCM Input Voltage Range Guaranteed by CMRR l0 1.5 V

CMRR Common Mode Rejection 0V ≤ VCM ≤ 1.5V l75 dB

CMRR Match

Channel-to-Channel (Note 5) l74 dB

AVOL Large Signal Voltage Gain VO = 1V to 2V

RL = 10k to VS/2

140

65 600 V/mV

V/mV

VOL Output Voltage Swing Low (Note 9) No Load

ISINK = 1mA

130 mV

VOH Output Voltage Swing High (Note 9) No Load

ISOURCE = 1mA

130 mV

PSRR Power Supply Rejection VS = 2.8V to 6V, VCM = 0.2V l78 dB

PSRR Match Channel-to-Channel

(Note 5) l74 dB

Minimum Supply Voltage (Note 10) l2.8 V

ISC Short-Circuit Current l2.5 mA

ISSupply Current per Ampliﬁ er LTC6241, LTC6242

1.4 1.7

1.9 mA

LTC6240

1.5 1.9

2.1 mA

GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k l10 MHz

LTC6240/LTC6241/LTC6242

624012fe

(LTC6240HVH/LTC6241HVH/LTC6242HVH) The l denotes the speciﬁ cations

which apply from –40°C to 125°C, otherwise speciﬁ cations are at TA = 25°C. VS = ±5V, VCM = 0V unless otherwise noted.

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOS Input Offset Voltage (Note 4) LTC6241 S8

50 175

400 µV

µV

LTC6242 GN

60 200

400 µV

µV

LTC6240

60 250

450 µV

µV

VOS Match Channel-to-Channel (Note 5) LTC6241 S8

50 200

400 µV

µV

LTC6242 GN

60 225

400 µV

µV

TC VOS Input Offset Voltage Drift (Note 6) l0.7 2.5 µV/°C

IBInput Bias Current (Notes 4, 7) LTC6241, LTC6242

0.5 1.5 pA

LTC6240

0.5 1

2.5 pA

IOS Input Offset Current (Notes 4, 7) LTC6241, LTC6242

0.2 150 pA

LTC6240

0.2 1

750 pA

VCM Input Voltage Range Guaranteed by CMRR l–5 3.5 V

CMRR Common Mode Rejection –5V ≤ VCM ≤ 3.5V l80 dB

CMRR Match

Channel-to-Channel (Note 5) l76 dB

AVOL Large Signal Voltage Gain VO = –3.5V to 3.5V

RL = 10k

775

350 2700 V/mV

V/mV

RL = 1k

150

60 360 V/mV

V/mV

VOL Output Voltage Swing Low (Note 9) No Load

ISINK = 1mA

ISINK = 10mA

600

VOH Output Voltage Swing High (Note 9) No Load

ISOURCE = 1mA

ISOURCE = 10mA

600

PSRR Power Supply Rejection VS = 2.8V to 11V, VCM = 0.2V l83 dB

PSRR Match

Channel-to-Channel (Note 5) l82 dB

Minimum Supply Voltage (Note 10) l2.8 V

ISC Short-Circuit Current l15 mA

ISSupply Current per Ampliﬁ er LTC6241, LTC6242

2.5 3.2

3.7 mA

LTC6240

2.7 3.3

3.8 mA

GBW Gain Bandwidth Product Frequency = 20kHz, RL = 1k l12 MHz

SR Slew Rate (Note 11) AV = –2, RL = 1k l5 V/µs

FPBW Full Power Bandwidth (Note 12) VOUT = 3VP-P, RL = 1k l0.53 MHz

LTC6240/LTC6241/LTC6242

624012fe

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: A heat sink may be required to keep the junction temperature

below the absolute maximum rating when the output is shorted

indeﬁ nitely.

Note 3: The LTC6240C/LTC6240HVC/LTC6241C/LTC6241HVC, LTC6242C/

LTC6242HVC are guaranteed to meet speciﬁ ed performance from 0°C to

70°C. They are designed, characterized and expected to meet speciﬁ ed

performance from –40°C to 85°C, but are not tested or QA sampled at

these temperatures. The LTC6240I/LTC6240HVI, LTC6241I/LTC6241HVI,

LTC6242I/LTC6242HVI are guaranteed to meet speciﬁ ed performance

from –40°C to 85°C. All versions of the LTC6240H/LTC6241H/LTC6242H

are guaranteed to meet speciﬁ ed performance from –40°C to 125°C.

Note 4: ESD (Electrostatic Discharge) sensitive device. ESD protection

devices are used extensively internal to the LTC6240/LTC6241/LTC6242;

however, high electrostatic discharge can damage or degrade the device.

Use proper ESD handling precautions.

Note 5: Matching parameters are the difference between the two ampliﬁ ers

A and D and between B and C of the LTC6242; between the two ampliﬁ ers

of the LTC6241. CMRR and PSRR match are deﬁ ned as follows: CMRR

and PSRR are measured in µV/V on the matched ampliﬁ ers. The difference

is calculated between the matching sides in µV/V. The result is converted

to dB.

Note 6: This parameter is not 100% tested.

Note 7: Bias current at TA = 25°C is 100% tested and guaranteed for the

LTC6240 in the S8 package. The LTC6240S5, LTC6241 and LTC6242 are

expected to achieve the same performance as the LTC6240S8. All parts are

guaranteed to meet speciﬁ cations over temperature.

Note 8: Current noise is calculated from the formula: in = (2qIB)1/2 where

q = 1.6 × 10–19 coulomb. The noise of source resistors up to 50G

dominates the contribution of current noise. See also Typical Performance

Characteristics curve Noise Current vs Frequency.

Note 9: Output voltage swings are measured between the output and

power supply rails.

Note 10: Minimum supply voltage is guaranteed by the power supply

rejection ratio test.

Note 11: Slew rate is measured in a gain of –2 with RF = 1k and RG =

500. On the LTC6240/LTC6241/LTC6242, VS = ±2.5V, VIN is ±1V and

VOUT slew rate is measured between –1V and +1V. On the LTC6240HV/

LTC6241HV/LTC6242HV, VIN is ±2V and VOUT slew rate is measured

between –2V and +2V.

Note 12: Full-power bandwidth is calculated from the slew rate:

FPBW = SR/πVP-P.

ELECTRICAL CHARACTERISTICS

LTC6240/LTC6241/LTC6242

624012fe

Input Bias Current

vs Common Mode Voltage

VOS Distribution LTC6241 VOS Distribution LTC6241

VOS Temperature Coefﬁ cient

Distribution LTC6241

Supply Current vs Supply Voltage

Offset Voltage

vs Input Common Mode Voltage

Input Bias Current

vs Common Mode Voltage

VOS Temperature Coefﬁ cient

Distribution LTC6240VOS Distribution LTC6240

TYPICAL PERFORMANCE CHARACTERISTICS

INPUT OFFSET VOLTAGE (µV)

NUMBER OF UNITS

6241 G01

–70 –50 –30 –10 7030 5010

VS = ±2.5V

SO-8 PACKAGE

INPUT OFFSET VOLTAGE (µV)

NUMBER OF UNITS

120

6241 G02

100

–350 –250 –150 –50 350150 25050

VS = ±2.5V

DD PACKAGE

DISTRIBUTION (µV/°C)

NUMBER OF UNITS

6241 G03

–1.0 –0.6 –0.2 0.2 1.81.0 1.40.6

VS = ±2.5V

2 LOTS

–55°C TO 125°C

INPUT OFFSET VOLTAGE (µV)

PERCENT OF UNITS

6241 G04

–70–90–110 –50 –30 –10 7030 5010

VS = ±2.5V

DISTRIBUTION (µV/°C)

NUMBER OF UNITS

6241 G05

–0.6 –0.2 1.81.41.00.60.2

VS = 5V, 0

VCM = 2.5V

2 LOTS

–40°C TO 125°C

SO-8 AND SOT23

PACKAGES

TOTAL SUPPLY VOLTAGE (V)

2.0

2.5

3.0

610

6241 G06

1.5

1.0

24 812

0.5

SUPPLY CURRENT PER AMP (mA)

3.5

TA = –55°C

TA = 125°C

TA = 25°C

INPUT COMMON MODE VOLTAGE (V)

–0.5

OFFSET VOLTAGE (µV)

300

200

250

150

100

–50

–100

–150

–200

–250

–300 3.0

6241 G07

0 0.5 1.5 2.5 3.5

1.0 2.0 4.54.0

VS = 5V, 0V

TA = –55°C

TA = 125°C

TA = 25°C

COMMON MODE VOLTAGE (V)

0 1.0 2.0 3.0 4.00.5 1.5 2.5 3.5 4.5 5.0

INPUT BIAS CURRENT (pA)

1000

100

0.1

6241 G08

VS = 5V, 0V

TA = 85°C

TA = 125°C

TA = 25°C

COMMON MODE VOLTAGE (V)

–0.8 –0.6 –0.2 0.2 0.6–0.4 0 0.4 0.8 1.0

INPUT BIAS CURRENT (pA)

700

100

200

300

400

500

600

–400

–300

–200

–100

6241 G09

VS = 5V, 0V

TA = 85°C

TA = 125°C

TA = 25°C

LTC6240/LTC6241/LTC6242

624012fe

Output Saturation Voltage

vs Load Current (Output High)

Gain Bandwidth and Phase

Margin vs Temperature Open Loop Gain vs Frequency

Input Bias Current vs Temperature

Output Saturation Voltage

vs Load Current (Output Low)

Gain Bandwidth and Phase

Margin vs Supply Voltage

Slew Rate vs Temperature

Common Mode Rejection Ratio

vs FrequencyOutput Impedance vs Frequency

TYPICAL PERFORMANCE CHARACTERISTICS

TEMPERATURE (°C)

25 45 65 85 10535 55 75 95 115 125

INPUT BIAS CURRENT (pA)

6241 G10

VCM = VS/2

VS = 5V

VS = 10V

1000

100

0.1

LOAD CURRENT (mA)

0.01

OUTPUT LOW SATURATION VOLTAGE (V)

0.1

0.1 10 100

6241 G11

0.001 1

VS = 5V, 0V

TA = 125°C

TA = –55°C

TA = 25°C

LOAD CURRENT (mA)

OUTPUT HIGH SATURATION VOLTAGE (V)

0.1

0.1 10 100

6241 G12

0.01 1

VS = 5V, 0V

TA = 125°C

TA = –55°C

TA = 25°C

TEMPERATURE (°C)

–55 –35 5 45 85–15 25 65 105 125

GAIN BANDWIDTH (MHz)

PHASE MARGIN (DEG)

6241 G13

CL = 5pF

RL = 1k

PHASE MARGIN

GAIN BANDWIDTH

VS = ±1.5V

VS = ±5V

VS = ±1.5V

VS = ±5V

FREQUENCY (Hz)

10k 100k 10M1M 100M

GAIN (dB)

PHASE (DEG)

–20

–10

–80

–40

–60

–20

100

120

6241 G14

CL = 5pF

RL = 1k

VCM = VS/2

PHASE

GAIN

VS = ±1.5V

VS = ±5V

VS = ±1.5V

VS = ±5V

TOTAL SUPPLY VOLTAGE (V)

0482 6 10 12

GAIN BANDWIDTH (MHz)

PHASE MARGIN (DEG)

6241 G15

TA = 25°C

CL = 5pF

RL = 1k

PHASE MARGIN

GAIN BANDWIDTH

TEMPERATURE (°C)

–55 –35 5 45 85–15 25 65 105 125

SLEW RATE (V/µs)

6241 G16

AV = –2

RF = 1k, RG = 500Ω

CONDITIONS: SEE NOTE 12

VS = ±5V RISING

VS = ±5V FALLING

VS = ±2.5V FALLING

VS = ±2.5V RISING

FREQUENCY (Hz)

OUTPUT IMPEDANCE (Ω)

10k 1M 10M

6241 G17

100k

TA = 25°C

VS = ±2.5V

AV = 10

AV = 1

0.01

10k

0.10

100

AV = 2

FREQUENCY (Hz)

10k 100k 10M1M 100M

COMMON MODE REJECTION (dB)

–10

100

6241 G18

TA = 25°C

VS = ±2.5V

LTC6240/LTC6241/LTC6242

624012fe

Input Capacitance vs Frequency

Minimum Supply Voltage Output Short-Circuit Current

vs Power Supply Voltage Open Loop Gain

Open Loop Gain Open Loop Gain

Channel Separation vs Frequency Power Supply Rejection Ratio

vs Frequency

Offset Voltage vs Output Current

TYPICAL PERFORMANCE CHARACTERISTICS

POWER SUPPLY REJECTION RATIO (dB)

01k 100k 1M 100M10k 10M

FREQUENCY (Hz)

6241 G20

TA = 25°C

VS = ±2.5V

POSITIVE SUPPLY

NEGATIVE SUPPLY

FREQUENCY (Hz)

10k 100k 10M1M 100M

VOLTAGE GAIN (dB)

–120

–10

–20

–30

–40

–50

–60

–70

–110

–100

–90

–80

6241 G19

TA = 25°C

VS = ±2.5V

AV = 1

INPUT CAPACITANCE (pF)

01k 100k 1M 100M10k 10M

FREQUENCY (Hz)

6241 G21

VS = ±1.5V

CCM

TOTAL SUPPLY VOLTAGE (V)

02 614 8375910

CHANGE IN OFFSET VOLTAGE (µV)

100

–100

–80

–40

–60

–20

6241 G22

VCM = VS/2

TA = 125°C

TA = –55°C

TA = 25°C

POWER SUPPLY VOLTAGE (±V)

1.5 2.5 4.52.0 3.53.0 4.0 5.0

OUTPUT SHORT-CIRCUIT CURRENT (mA)

–50

–40

–20

–30

–10

6241 G23

SOURCING

SINKING

TA = 125°C

TA = –55°C

TA = 25°C

OUTPUT VOLTAGE (V)

0 0.5 2.51.51.0 2.0 3.0

INPUT VOLTAGE (µV)

120

100

6241 G24

TA = 25°C

VS = 3V, 0V

RL = 100k

RL = 10k

OUTPUT VOLTAGE (V)

012 534

INPUT VOLTAGE (µV)

120

100

–20

6241 G25

TA = 25°C

VS = 5V, 0V

RL = 1k

RL = 10k

OUTPUT VOLTAGE (V)

–5 –4 0–2–3 –1 51234

INPUT VOLTAGE (µV)

100

–60

–40

–20

6241 G26

TA = 25°C

VS = ±5V

RL = 1k

RL = 10k

OUTPUT CURRENT (mA)

–50 –40 –30 –20 –10 10 302004050

OFFSET VOLTAGE (µV)

500

400

100

200

300

–500

–400

–300

–100

–200

6241 G27

TA = 125°C

TA = –55°C

TA = 25°C

VS = ±5V

LTC6240/LTC6241/LTC6242

624012fe

Warm-Up Drift vs Time Noise Voltage vs Frequency

Series Output Resistance and

Overshoot vs Capacitive Load

Series Output Resistance and

Overshoot vs Capacitive Load

0.1Hz to 10Hz Voltage Noise

Noise Current vs Frequency

Minimum Output Series

Resistance vs Capacitive Load

Settling Time vs Output Step

(Inverting)

Settling Time vs Output Step

(Non-Inverting)

TYPICAL PERFORMANCE CHARACTERISTICS

TIME AFTER POWER UP (s)

010 3020540605015 3525 45 55

CHANGE IN OFFSET VOLTAGE (µV)

–5

6241 G28

TA = 25°C

VS = ±1.5V

VS = ±2.5V

VS = ±5V

FREQUENCY (Hz)

NOISE VOLTAGE (nV/√Hz)

1 100 1k 100k

6241 G29

010 10k

TA = 25°C

VS = ±2.5V

VCM = 0V

TIME (1s/DIV)

VOLTAGE NOISE (200nV/DIV)

6241 G30

VS = 5V, 0V

FREQUENCY (Hz)

NOISE CURRENT (fA/√Hz)

100 10k 100k

6241 G31

0.1 1k

1000

100

TA = 25°C

VS = ±2.5V

VCM = 0V

CAPACITIVE LOAD (pF)

OVERSHOOT (%)

0100 1000

6241 G32

RS = 50Ω

RS = 10Ω

VS = ±2.5V

AV = –1

1k 1k

75pF

–

0.01µF 1µF0.1µF1000pF100pF

CAPACITIVE LOAD

OUTPUT SERIES RESISTANCE (Ω)

10pF 10µF

6241 G33

0.1

1000

100

VS = ±2.5V

<30% OVERSHOOT

CAPACITIVE LOAD (pF)

OVERSHOOT (%)

0100 1000

6241 G34

RS = 50Ω

RS = 10Ω

VS = ±2.5V

AV = –2

500Ω 1k

75pF

–

OUTPUT STEP (V)

–4 –2 3–3 10–1 2 4

SETTLING TIME (µs)

3.5

1.5

2.0

2.5

3.0

0.5

1.0

6241 G35

10mV

1mV

10mV

1mV

TA = 25°C

VS = ±5V

AV = 1

OUT

–

3.0

1.5

2.0

2.5

0.5

1.0

OUTPUT STEP (V)

–4 –2 3–3 10–1 2 4

SETTLING TIME (µs)

6241 G36

10mV

1mV

10mV

1mV

TA = 25°C

VS = ±5V

AV = –1

OUT

–

1k 1k

LTC6240/LTC6241/LTC6242

624012fe

Distortion vs Frequency Distortion vs Frequency

Maximum Undistorted Output

Signal vs Frequency

Distortion vs Frequency

Large Signal Response Large Signal Response Output Overdrive Recovery

Small Signal ResponseDistortion vs Frequency

TYPICAL PERFORMANCE CHARACTERISTICS

FREQUENCY (Hz)

10k 100k 1M 10M

OUTPUT VOLTAGE SWINGING (VP-P)

6241 G37

TA = 25°C

VS = ±5V

HD2, HD3 < –40dBc

AV = +2

AV = –1

FREQUENCY (Hz)

10k 100k 1M 10M

DISTORTION (dBc)

–30

–60

–90

–100

–50

–80

–40

–70

6241 G38

VS = ±2.5V

AV = 1

VOUT = 2VP-P

RL = 1k, 2ND

RL = 1k, 3RD

FREQUENCY (Hz)

10k 100k 1M 10M

DISTORTION (dBc)

–30

–60

–90

–100

–50

–80

–40

–70

6241 G39

VS = ±5V

AV = 1

VOUT = 2VP-P

RL = 1k, 2ND

RL = 1k, 3RD

FREQUENCY (Hz)

10k 100k 1M 10M

DISTORTION (dBc)

–30

–60

–90

–100

–50

–80

–40

–70

6241 G40

VS = ±2.5V

AV = 2

VOUT = 2VP-P

RL = 1k, 2ND

RL = 1k, 3RD

FREQUENCY (Hz)

10k 100k 1M 10M

DISTORTION (dBc)

–30

–60

–90

–100

–50

–80

–40

–70

6241 G41

VS = ±5V

AV = 2

VOUT = 2VP-P

RL = 1k, 2ND

RL = 1k, 3RD

VS = ±2.5V

AV = 1

RL = ∞

6241 G42

VS = ±5V

AV = 1

RL = ∞

6241 G43

VS = ±2.5V

AV = –1

RL = 1k

6241 G44

VS = ±2.5V

AV = 3

RL = ∞

500ns/DIV 6241 G45

VIN

(1V/DIV)

VOUT

(2V/DIV)

LTC6240/LTC6241/LTC6242

624012fe

Ampliﬁ er Characteristics

Figure 1 is a simpliﬁ ed schematic of the ampliﬁ er, which

has a pair of low noise input transistors M1 and M2. A

simple folded cascode Q1, Q2 and R1, R2 allow the input

stage to swing to the negative rail, while performing level

shift to the differential drive generator. Low offset voltage

is accomplished by laser trimming the input stage.

Capacitor C1 reduces the unity cross frequency and im-

proves the frequency stability without degrading the gain

bandwidth of the ampliﬁ er. Capacitor CM sets the overall

ampliﬁ er gain bandwidth. The differential drive generator

supplies signals to transistors M3 and M4 that swing the

output from rail-to-rail.

The photo of Figure 2 shows the output response to an

input overdrive with the ampliﬁ er connected as a voltage

follower. If the negative going input signal is less than

a diode drop below V–, no phase inversion occurs. For

input signals greater than a diode drop below V–, limit the

current to 3mA with a series resistor RS to avoid phase

inversion.

ESD

The LTC6240/LTC6241/LTC6242 have reverse-biased ESD

protection diodes on all input and outputs as shown in

Figure 1. If these pins are forced beyond either supply,

unlimited current will ﬂ ow through these diodes. If the

current is transient and limited to one hundred milliamps

or less, no damage to the device will occur.

The ampliﬁ er input bias current is the leakage current of

these ESD diodes. This leakage is a function of the tempera-

ture and common mode voltage of the ampliﬁ er, as shown

in the Typical Performance Characteristics curves.

Noise

The LTC6240/LTC6241/LTC6242 exhibit exceptionally

low 1/f noise in the 0.1Hz to 10Hz region. This 550nVP-P

noise allows these op amps to be used in a wide variety

of high impedance low frequency applications, where

zero-drift ampliﬁ ers might be inappropriate due to their

charge injection.

In the frequency region above 1kHz the LTC6240/LTC6241/

LTC6242 also show good noise voltage performance. In

this frequency region, noise can easily be dominated by

the total source resistance of the particular application.

Speciﬁ cally, these ampliﬁ ers exhibit the noise of a 3.1k

resistor, meaning it is desirable to keep the source and

feedback resistance at or below this value, i.e. RS + RG||RFB

≤ 3.1k. Above this total source impedance, the noise

voltage is not dominated by the ampliﬁ er.

Noise current can be estimated from the expression in =

√2qIB, where q = 1.6 • 10–19 coulombs. Equating √4kTRΔf

and R√2qIBΔf shows that for source resistors below 50G

the ampliﬁ er noise is dominated by the source resistance.

See the Typical Performance Characteristics curve Noise

Current vs Frequency.

Figure 1. Simpliﬁ ed Schematic Figure 2. Unity Gain Follower Test Circuit

APPLICATIONS INFORMATION

6241 F01

VIN+

ITAIL

VIN–

V+

V–

DESD5

DIFFERENTIAL

DRIVE

GENERATOR

BIAS

DESD6

V+

DESD2

V+

DESD4

V–

DESD1

V–

DESD3

M2M1

CLAMP

+2.5V

–2.5V

6241 F02

–

LTC6240

VIN VOUT

VOUT AND VIN OF FOLLOWER WITH LARGE INPUT OVERDRIVE

VDD =

+2.5V

VSS =

–2.5V

LTC6240/LTC6241/LTC6242

624012fe

Proprietary design techniques are used to obtain simulta-

neous low 1/f noise and low input capacitance. Low input

capacitance is important when the ampliﬁ er is used with

high value source and feedback resistors. High frequency

noise from the ampliﬁ er tail current source, ITAIL in Fig-

ure 1, couples through the input capacitance and appears

across these large source and feedback resistors. As an

example, the photodiode ampliﬁ er of Figure 15 on the last

page of this data sheet shows the noise results from the

LTC6241 and the results of a competitive CMOS ampliﬁ er.

The LTC6241 output is the ideal noise of a 1M resistor

at room temperature, 130nV√Hz.

Half the Noise

The circuit shown in Figure 3 can be used to achieve even

lower noise voltage. By paralleling 4 ampliﬁ ers the noise

voltage can be lowered by √4, or half as much noise. The

√– comes about from an RMS summing of uncorrelated

noise sources. This circuit maintains extremely high input

resistance, and has a 250 output resistance. For lower

output resistance, a buffer ampliﬁ er can be added without

inﬂ uencing the noise.

Stability

The good noise performance of these op amps can be at-

tributed to large input devices in the differential pair. Above

several hundred kilohertz, the input capacitance rises and

can cause ampliﬁ er stability problems if left unchecked.

When the feedback around the op amp is resistive (RF), a

pole will be created with RF, the source resistance, source

capacitance (RS, CS), and the ampliﬁ er input capacitance.

In low gain conﬁ gurations and with RF and RS in even

the kilohm range (Figure 4), this pole can create excess

phase shift and possibly oscillation. A small capacitor CF

in parallel with RF eliminates this problem.

Low Noise Single-Ended Input to Differential Output

Ampliﬁ er

The circuit on the ﬁ rst page of the data sheet is a low noise

single-ended input to differential output ampliﬁ er, with a

200k input impedance. The very low input bias current

of the LTC6241 allows for these large input and feedback

resistors. The 200k resistors, R1 and R2, along with C1 and

C2 set the –3dB bandwidth to 80kHz. Capacitor C3 is used

to cancel effects of input capacitance, while C4 adds phase

lead to compensate the phase lag of the second ampliﬁ er.

Figure 3. Parallel Ampliﬁ er Lowers Noise by 2x Figure 4. Compensating Input Capacitance

APPLICATIONS INFORMATION

10Ω

6241 F03

–

+1/4

LTC6242

10Ω

–

+1/4

LTC6242

10Ω

–

+1/4

LTC6242

10Ω

–

+1/4

LTC6242

+2.5

–2.5

VIN VO

–

CIN

6241 F04

OUTPUT

LTC6240/LTC6241/LTC6242

624012fe

The op amp’s good input offset voltage match and low

input bias current means that the typical differential output

offset voltage is less than 40µV. A noise spectrum plot of

the differential output is shown in Figure 5.

The guard ring should extend as far as necessary to shield

the high impedance signal from any and all leakage paths.

Figure 6 shows the use of a guard ring on the LTC6241 in

a unity gain conﬁ guration. In this case the guard ring is

connected to the output and is shielding the high impedance

noninverting input from V–. Figure 7 shows the inverting

gain conﬁ guration.

A Digitally Programmable AC Difference Ampliﬁ er

The LTC6241 conﬁ gured as a difference ampliﬁ er, can be

combined with a programmable gain ampliﬁ er (PGA) to

obtain a low noise high speed programmable difference

ampliﬁ er. Figure 8 shows the LTC6241 based as a single-

supply AC ampliﬁ er. One LTC6241 op amp is used at the

circuit’s input as a standard four resistor difference ampliﬁ er.

Figure 5. Differential Output Noise

Achieving Low Input Bias Current

The DD package is leadless and makes contact to the PCB

beneath the package. Solder ﬂ ux used during the attach-

ment of the part to the PCB can create leakage current

paths and can degrade the input bias current performance

of the part. All inputs are susceptible because the backside

paddle is connected to V– internally. As the input voltage

changes or if V– changes, a leakage path can be formed

and alter the observed input bias current. For lowest bias

current, use the LTC6240/LTC6241 in the SO-8 and provide

a guard ring around the inputs that are tied to a potential

near the input voltage.

Layout Considerations and a PCB Guard Ring

In high source impedance applications such as pH probes,

photodiodes, strain gauges, et cetera, the low input bias

current of these parts requires a clean board layout to

minimize additional leakage current into a high impedance

signal node. A mere 100G of PC board resistance

between a 5V supply trace and an input trace adds 50pA

of leakage current, far greater then the input bias current

of the operational ampliﬁ er. A guard ring around the high

impedance input traces driven by a low impedance source

equal to the input voltage prevents such leakage problems.

Figure 6. Sample Layout. Unity Gain Conﬁ guration, Using Guard

Ring to Shield High Impedance Input from Board Leakage

Figure 7. Sample Layout. Inverting Gain Conﬁ guration, Using

Guard Ring to Shield High Impedance Input from Board Leakage

APPLICATIONS INFORMATION

FREQUENCY (kHz)

020 6010 40 8030 7050 90 100

DIFFERENTIAL OUTPUT VOLTAGE DENSITY (nV/√Hz)

140

100

120

6241 F05

VS = ±2.5V

TA = 25°C

–3dB BW = 80kHz

LTC6241 S8

OUT+

IN–

IN+

V–

LEAKAGE

CURRENT

NO LEAKAGE

CURRENT

GUARD

RING

NO SOLDER MASK

OVER THE GUARD RING

LTC6241 F06

LTC6241 S8

LTC6241 F07

OUT+

IN–

IN+

V–

VIN

GND

LTC6240/LTC6241/LTC6242

624012fe

Figure 8. Wideband Difference Ampliﬁ er with High

Input Impedance and Digitally Programmable Gain

The low bias current and current noise of the LTC6241

allow the use of high valued input resistors, 100k or

greater. Resistors R1, R2, R3 and R4 are equal and the

gain of the difference ampliﬁ er is one. An LTC6910-2 PGA

ampliﬁ es the difference ampliﬁ er output with inverting

gains of –1, –2, –4, –8, –16, –32 and –64. The second

LTC6241 op amp is used as an integrator to set the DC

output voltage equal to the LT6650 reference voltage VREF.

The integrator drives the PGA analog ground to provide

a feedback loop, in addition to blocking any DC voltage

through the PGA. The reference voltage of the LT6650

can be set to a voltage from 400mV to V+ – 350mV with

resistors R5 and R6. If R6 is 20k or less, the error due

to the LT6650 op amp bias current is negligible. The low

voltage offset and drift of the LTC6241 integrator will not

contribute any signiﬁ cant error to the LT6650 reference

voltage. The LT6650 VREF voltage has a maximum error

of ±2% with 1% resistors. The upper –3dB frequency of

the ampliﬁ er is set by resistor R3 and capacitor C1 and

is limited by the bandwidth of the PGA when operated at

a gain of 64. Capacitor C2 is equal to C1 and is added to

maintain good common mode rejection at high frequency.

The lower –3dB frequency is set by the integrator resistor

R7, capacitor C3, and the gain setting of the LTC6910-2

PGA. This lower –3dB zero frequency is multiplied by the

PGA gain. The rail-to-rail output of the LTC6910-2 PGA

allows for a maximum output peak-to-peak voltage equal

to twice the VREF voltage. At the maximum gain setting of

64, the maximum peak-to-peak difference between inputs

V1 and V2 is equal to twice VREF divided by 64.

Example Design: Design a programmable gain AC differ-

ence ampliﬁ er, with a bandwidth of at least 10Hz to 100kHz,

an input impedance equal to or greater than 100k, and

an output DC reference equal to 1V.

a. Select input resistors R1, R2, R3 and R4 equal to

100k.

b. If the upper –3dB frequency is 100kHz then C1 = 1/(2π

• R2 • f3dB) = 1/(6.28 • 100k • 100kHz) = 15pF (to

the nearest 5% value) and C2 = C1 = 15pF.

c. Select R7 equal to one 1M and set the lower –3dB

frequency to 10Hz at the highest PGA gain of 64, then

C3 = Gain/(2π • R7 • f3dB) = 64/(6.28 • 100k • 10Hz)

= 1µF. Lower gains settings will give a lower f3dB.

d. Calculate the value of R5 to set the LT6650 reference

equal to 1V;

REF = 0.4(R5/R6 + 1), so R5 = R6(2.5VREF – 1). For

R6 = 20k, R5 = 30k

With VREF = 1V the maximum input difference voltage

is equal to 2V/64 = 31.2mV.

40nVpp Noise, 0.05μV/°C Drift, Chopped FET

Ampliﬁ er

Figure 9’s circuit combines the ±5V rail-to-rail performance

of the LTC6241HV with a pair of extremely low noise JFETs

conﬁ gured in a chopper based carrier modulation scheme

APPLICATIONS INFORMATION

6241 F08

–

+1/2

LTC6241

1µF

0.1µF8 765

G2 G1 G0

234

AGNDOUT IN V–

V+

0.1µF

V+

R1 = R2 = R3 = R4

1000pF

3 4

20k

LTC6910-2

LT6650

VOUT

VREF

–

1/2

LTC6241

C3 R7

100Ω

1µF

DIGITAL INPUTS

G1G2 GO

GAIN

–1

–2

–4

–8

–16

–32

–64

VOUT = (V1 – V2) GAIN + VREF



RkV

REF

¦´



04 5

510 5 2 R620

.•

•• – k

d BANDWIDTH f f

fRC

HIGH LOW

HIGH

––

•• •

=P1273

fGAIN

LOW =•• •P

LTC6240/LTC6241/LTC6242

624012fe

Figure 9. Ultralow Noise Chopper Ampliﬁ er

to achieve an extraordinarily low noise and low DC drift.

The performance of this circuit is suited for the demand-

ing transducer signal conditioning situations such as high

resolution scales and magnetic search coils.

The LTC1799’s output is divided down to form a 2-phase

925Hz square wave clock. This frequency, harmonically

unrelated to 60Hz, provides excellent immunity to harmonic

beating or mixing effects which could cause instabilities.

S1 and S2 receive complementary drive, causing A1 to

see a chopped version of the input voltage. A1’s square

wave output is synchronously demodulated by S3 and

S4. Because these switches are synchronously driven

with the input chopper, proper amplitude and polarity

information is presented to A2, the DC output ampliﬁ er.

This stage integrates the square wave into a DC voltage,

providing the output. The output is divided down (R2 and

R1) and fed back to the input chopper where it serves as

a zero signal reference. Gain, in this case 1000, is set by

the R1-R2 ratio. Because A1 is AC coupled, its DC offset

and drift do not affect the overall circuit offset, resulting

in the extremely low offset and drift noted. The JFETs

have an input RC damper that minimizes offset voltage

contribution due to parasitic switch behavior, resulting in

the 1µV offset speciﬁ cation.

APPLICATIONS INFORMATION

–

BIAS

10M

1µF

S3 240k

1µF

OUTPUT

LTC6241HV

1µF

INPUT

10k

10Ω

NOISE

OFFSET

DRIFT

OPEN-LOOP GAIN

= 40nVP-P 0.1Hz TO 10Hz

= 1µV

= 0.05µV/°C

= 10

= 500pA

GAIN =

0.01µF

Ø1

Ø2

6241 F09

= 0.1% METAL FILM RESISTOR

= 1% METAL FILM RESISTOR

= LTC201 QUAD

= LSK389

= LINEAR INTEGRATED SYSTEMS

FREMONT, CA

1µF

DIV

RSET

LTC1799

V+

74C90 ÷ 10

18.5kHz

OUT 74C74 ÷ 2

Ø1

POINTS

Ø2

POINTS

54.2k*

TO LTC201 V+ PIN

5V –5V

5V 5V

925Hz

TO LTC201 V– PIN

1µF

898Ω**

–5V

898Ω**

LSK389

30.1Ω

499Ω**

LTC6240/LTC6241/LTC6242

624012fe

by the sensor is forced across the feedback capacitor

by the op amp action. Because the feedback capacitor

is 100 times smaller than the sensor, it will be forced to

100 times what would have been the sensor’s open circuit

voltage. So the circuit gain is 100. The beneﬁ t of this ap-

proach is that the signal gain of the circuit is independent

of any cable capacitance introduced between the sensor

and the ampliﬁ er. Hence this circuit is favored for remote

accelerometers where the cable length may vary. Difﬁ culties

with the circuit are inaccuracy of the gain setting with the

small capacitor, and low frequency cutoff due to the bias

resistor working into the small feedback capacitor.

Figure 12 shows a noninverting ampliﬁ er approach. This

approach has many advantages. First of all, the gain is set

accurately with resistors rather than with a small capaci-

tor. Second, the low frequency cutoff is dictated by the

bias resistor working into the large 770pF sensor, rather

than into a small feedback capacitor, for lower frequency

response. Third, the noninverting topology can be paral-

leled and summed (as shown) for scalable reductions in

voltage noise. The only drawback to this circuit is that the

parasitic capacitance at the input reduces the gain slightly.

This circuit is favored in cases where parasitic input

capacitances such as traces and cables will be relatively

small and invariant.

The noise measured over a 50 second interval, in Figure 10,

is 40nV in a 0.1Hz to 10Hz bandwidth.This low noise is at-

tributed to the input JFET’s die size and current density.

Figure 11. Classical Inverting Charge Ampliﬁ er Figure 12. Low Noise Noninverting Shock Sensor Ampliﬁ er

Figure 10. Noise in a 0.1Hz to 10Hz Bandwidth

Low Noise Shock Sensor Ampliﬁ ers

Figures 11 and 12 show the ampliﬁ ers realizing two dif-

ferent approaches to amplifying signals from a capacitive

sensor. The sensor in both cases is a 770pF piezoelectric

shock sensor accelerometer, which generates charge under

physical acceleration.

Figure 11 shows the classical “charge ampliﬁ er” approach.

The LTC6240 is in the inverting conﬁ guration so the sensor

looks into a virtual ground. All of the charge generated

APPLICATIONS INFORMATION

5s/DIV 6241 F10

20nV/DIV

BIAS RESISTOR

VISHAY-TECHNO

CRHV2512AF1007G

(OR EQUIVALENT)

MAIN

GAIN-SETTING

ELEMENT IS A

CAPACITOR

SHOCK SENSOR

MURATA-ERIE

PKGS-00LD

770pF

CABLE HAS

UNKNOWN C

6241 F11

VOUT = 110mV/g

–

LTC6240

7.7pF

BIAS RESISTOR

VISHAY-TECHNO

CRHV2512AF1007G

(OR EQUIVALENT)

VS+

6241 F12

10k

100Ω

VOUT = 110mV/g

VS = ±1.4V to ±5.5V

BW = 0.2Hz to 10kHz

VOUT

–

+1/2

LTC6241HV

VS–

10k100Ω

–

+1/2

LTC6241HV

SHOCK SENSOR

MURATA-ERIE

PKGS-00LD

770pF

LTC6240/LTC6241/LTC6242

624012fe

1M Transimpedance Ampliﬁ er with 43nV/√Hz

Output Noise

In a normal 1M transimpedance ampliﬁ er, like that shown

on the back page of this data sheet, the output noise density

must be at least 130nV/√Hz at room temperature. This is

true even should the op amp be perfectly noiseless, because

the 1M resistor provides 130nV/√Hz of voltage noise at

room temperature independently of the op amp.

The circuit of Figure 13 provides an overall transimpedance

gain of 1M, but it has an output noise density of only

43nV/√Hz, about 1/3 of the normal transimpedance ampli-

ﬁ er. It does this by taking a higher initial transimpedance

gain of 10M and then attenuating by a factor of 10. The

transistor section provides voltage gain and works on a

54V supply voltage to guarantee adequate output swing.

By achieving an output swing of 50V before attenuation,

the circuit provides an output swing to 5V after attenu-

ation. The 10M resistor sets the gain of the TIA stage

and has a noise density of 400nV/√Hz. After attenuation,

the effective TIA gain drops to 1M while the noise ﬂ oor

drops to 40nV/√Hz, which clearly dominates the observed

43nV/√Hz. Note the additional beneﬁ t that the offset voltage

of the op amp is divided by 10. Worst-case output offset

for this circuit is 150µV over temperature.

Reference Buffer

Figure 14 shows the LTC6240 being utilized as a buffer

in conjunction with the LT1019 reference. The passive

R-C ﬁ lter attenuates the reference noise and the LTC6240

provides a low noise buffer, resulting in an output noise

of 8nV/√Hz.

Figure 13. 1M Transimpedance Ampliﬁ er with 43nV/√Hz Output Noise

Figure 14. Low Noise Reference Buffer

APPLICATIONS INFORMATION

54V

–5V

–1.5V

3pF

PHOTODIODE

6241 F13

–5V

10k

–

LTC6240HV

100pF

10M

0.3pF

10k 2.4k

33k

MPSA06

43k

9.09k

1/4W

VOUT

1M GAIN

(1V/µA)

10M GAIN

(10V/µA)

MPSA06

–5V

6241 F14

0.2Ω

–

LTC6240HV

10µF

CERAMIC

OR FILM

8nV/√Hz VOUT

1µF

LT1019-2.5 180nV/√Hz

LTC6240/LTC6241/LTC6242

624012fe

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698)

PACKAGE DESCRIPTION

3.00 p0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

0.40 p 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 p 0.10

(2 SIDES)

0.75 p0.05

R = 0.125

TYP

2.38 p0.10

PIN 1

TOP MARK

(NOTE 6)

0.200 REF

0.00 – 0.05

(DD8) DFN 0509 REV C

0.25 p 0.05

2.38 p0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

1.65 p0.05

(2 SIDES)

2.10 p0.05

0.50

BSC

0.70 p0.05

3.5 p0.05

PACKAGE

OUTLINE

0.25 p 0.05

0.50 BSC

LTC6240/LTC6241/LTC6242

624012fe

DHC Package

16-Lead Plastic DFN (5mm × 3mm)

(Reference LTC DWG # 05-08-1706)

PACKAGE DESCRIPTION

3.00 ±0.10

(2 SIDES)

5.00 ±0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ± 0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

R = 0.20

TYP

4.40 ±0.10

(2 SIDES)

169

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DHC16) DFN 1103

0.25 ± 0.05

PIN 1

NOTCH

0.50 BSC

4.40 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)2.20 ±0.05

0.50 BSC

0.65 ±0.05

3.50 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

LTC6240/LTC6241/LTC6242

624012fe

PACKAGE DESCRIPTION

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

GN16 (SSOP) 0204

345678

.229 – .244

(5.817 – 6.198)

.150 – .157**

(3.810 – 3.988)

16 15 14 13

.189 – .196*

(4.801 – 4.978)

12 11 10 9

.016 – .050

(0.406 – 1.270)

.015 ± .004

(0.38 ± 0.10) × 45°

0° – 8° TYP

.007 – .0098

(0.178 – 0.249)

.0532 – .0688

(1.35 – 1.75)

.008 – .012

(0.203 – 0.305)

TYP

.004 – .0098

(0.102 – 0.249)

.0250

(0.635)

BSC

.009

(0.229)

REF

.254 MIN

RECOMMENDED SOLDER PAD LAYOUT

.150 – .165

.0250 BSC.0165 ±.0015

.045 ±.005

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

INCHES

(MILLIMETERS)

NOTE:

1. CONTROLLING DIMENSION: INCHES

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

LTC6240/LTC6241/LTC6242

624012fe

S5 Package

5-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1635 Rev B)

1.50 – 1.75

(NOTE 4)

2.80 BSC

0.30 – 0.45 TYP

5 PLCS (NOTE 3)

DATUM ‘A’

0.09 – 0.20

(NOTE 3) S5 TSOT-23 0302 REV B

PIN ONE

2.90 BSC

(NOTE 4)

0.95 BSC

1.90 BSC

0.80 – 0.90

1.00 MAX

0.01 – 0.10

0.20 BSC

0.30 – 0.50 REF

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

3.85 MAX

0.62

MAX

0.95

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.4 MIN

2.62 REF

1.22 REF

PACKAGE DESCRIPTION

LTC6240/LTC6241/LTC6242

624012fe

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

PACKAGE DESCRIPTION

.016 – .050

(0.406 – 1.270)

.010 – .020

(0.254 – 0.508)× 45°

0°– 8° TYP

.008 – .010

(0.203 – 0.254)

SO8 0303

.053 – .069

(1.346 – 1.752)

.014 – .019

(0.355 – 0.483)

TYP

.004 – .010

(0.101 – 0.254)

.050

(1.270)

BSC

1234

.150 – .157

(3.810 – 3.988)

NOTE 3

8765

.189 – .197

(4.801 – 5.004)

NOTE 3

.228 – .244

(5.791 – 6.197)

.245

MIN .160 ±.005

RECOMMENDED SOLDER PAD LAYOUT

.045 ±.005

.050 BSC

.030 ±.005

TYP

INCHES

(MILLIMETERS)

NOTE:

1. DIMENSIONS IN

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

LTC6240/LTC6241/LTC6242

624012fe

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

E 07/10 Update to Simpliﬁ ed Schematic (Figure 1) 19

(Revision history begins at Rev E)

LTC6240/LTC6241/LTC6242

624012fe

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0710 REV E • PRINTED IN USA

PART NUMBER DESCRIPTION COMMENTS

LTC1151 ±15V Zero-Drift Op Amp Dual High Voltage Operation ±18V

LT1792 Low Noise Precision JFET Op Amp 6nV/√Hz Noise, ±15V Operation

LTC2050 Zero-Drift Op Amp 2.7 Volt Operation, SOT-23

LTC2051/LTC2052 Dual/Quad Zero-Drift Op Amp Dual/Quad Version of LTC2050 in MS8/GN16 Packages

LTC2054/LTC2055 Single/Dual Zero-Drift Op Amp Micropower Version of the LTC2050/LTC2051 in SOT-23 and DD Packages

LTC6244 Dual 50MHz Rail-to-Rail Op Amp 100µV VOS(MAX), 1pA IBIAS, 40V/µV, Slew Rate

Figure 15. Ultralow Noise 1MΩ 150kHz Photodiode Ampliﬁ er

LTC6241 Output Noise Spectrum. 1MΩ Resistor Noise

Dominates; Ideal Performance Competition Output Noise Spectrum. Op Amp Noise Dominates;

Performance Compromised

RELATED PARTS

TYPICAL APPLICATION

1.69k

180pF

1500pF

+1.5V

–1.5V

SFH213FA

OR EQUIVALENT

(≤4pF) 6241 TA02a

866Ω

–

+1/2

LTC6241

–

+1/2

LTC6241

1500pF

1pF

1MΩ TIA 150kHz 3RD ORDER BUTTERWORTH FILTER

1kHz 101kHz10kHz/DIV

6241 TA02b

30nV/√Hz PER DIV

1kHz 101kHz

6241 TA02c

10kHz/DIV

30nV/√Hz PER DIV