ADP5040CP-1-EVALZ - Analog Devices

Micro PMU with 1.2 A Buck Regulator

and Two 300 mA LDOs

Data Sheet

ADP5040

Rev. A Document Feedback

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FEATURES

Input voltage range: 2.3 V to 5.5 V

One 1.2 A buck regulator

Two 300 mA LDOs

20-lead, 4 mm × 4 mm LFCSP package

Overcurrent and thermal protection

Soft start

Undervoltage lockout

Buck key specifications

Output voltage range: 0.8 V to 3.8 V

Current mode topology for excellent transient response

3 MHz operating frequency

Peak efficiency up to 96%

Uses tiny multilayer inductors and capacitors

Mode pin selects forced PWM or auto PWM/PSM modes

100% duty cycle low dropout mode

LDOs key specifications

Output voltage range: 0.8 V to 5.2 V

Low VIN from 1.7 V to 5.5 V

Stable with 2.2 µF ceramic output capacitors

High PSRR

Low output noise

Low dropout voltage

−40°C to +125°C junction temperature range

GENERAL DESCRIPTION

The ADP5040 combines one high performance buck regulator

and two low dropout regulators (LDO) in a small 20-lead

LFCSP to meet demanding performance and board space

requirements.

The high switching frequency of the buck regulator enables the use

of tiny multilayer external components and minimizes board space.

When the MODE pin is set to logic high, the buck regulator

operates in forced pulse width modulation (PWM) mode. When

the MODE pin is set to logic low, the buck regulator operates in

PWM mode when the load is around the nominal value. When

the load current falls below a predefined threshold the regulator

operates in power save mode (PSM) improving the light-load

efficiency. The low quiescent current, low dropout voltage, and

wide input voltage range of the ADP5040 LDOs extend the

battery life of portable devices. The ADP5040 LDOs maintain

a power supply rejection greater than 60 dB for frequencies as

high as 10 kHz while operating with a low headroom voltage.

Each regulator in the ADP5040 is activated by a high level on

the respective enable pin. The output voltages of the regulators

are programmed though external resistor dividers to address a

variety of applications.

FUNCTIONAL BLOCK DIAGRAM

1µF

09665-001

FB2

R2 R1

FB3

R3 R7

2.2µF

VOUT2

VOUT1

FB1

VIN1 = 2. 3V TO

5.5V VIN1

EN1

VIN2

EN2

EN3

VIN3

VIN3 = 1. 7V

TO 5.5V

EN_LDO2

LDO2

(ANALOG)

BUCK

PGND

MODE

VOUT3

LDO1

(DIGITAL)

EN_LDO1

AVIN

4.7µF

VIN2 = 1. 7V

TO 5.5V

VOUT1 AT

1.2A

VOUT2 AT

300mA

VOUT3 AT

300mA

10µF

1µH

1µF ON

OFF

AGND

EN_BK

PSM/PWM

FPWM

Figure 1.

ADP5040 Data Sheet

Rev. A | Page 2 of 40

TABLE OF CONTENTS

Features .............................................................................................. 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

General Specifications ................................................................. 3

Buck Specifications ....................................................................... 3

LDO1, LDO2 Specifications ....................................................... 4

Input and Output Capacitor, Recommended Specifications .. 5

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 25

Power Management Unit ........................................................... 25

Buck Section ................................................................................ 26

LDO Section ............................................................................... 27

Applications Information .............................................................. 29

Buck External Component Selection ....................................... 29

LDO External Component Selection ...................................... 30

Power Dissipation/Thermal Considerations ............................. 31

Application Diagram ................................................................. 33

PCB Layout Guidelines .................................................................. 34

Suggested Layout ........................................................................ 34

Bill of Materials ........................................................................... 35

Factory Programmable Options ................................................... 36

Outline Dimensions ....................................................................... 37

Ordering Guide .......................................................................... 37

REVISION HISTORY

1/14—Rev. 0 to Re v. A

Change to Figure 1 ........................................................................... 1

Change to Figure 106 ..................................................................... 30

Change to Figure 108 ..................................................................... 33

Change to Figure 109 ..................................................................... 34

12/11—Revision 0: Initial Version

Data Sheet ADP5040

Rev. A | Page 3 of 40

SPECIFICATIONS

GENERAL SPECIFICATIONS

AVIN, VIN1 = 2.3 V to 5.5 V; AVIN, VIN1 ≥VIN2, VIN3; VIN2, VIN3 = 1.7 V to 5.5 V, T J = −40°C to +125°C for minimum/maximum

specifications, and TA = 25°C for typical specifications, unless otherwise noted.

Table 1.

Parameter Symbol Description Min Typ Max Unit

AVIN UNDERVOLTAGE LOCKOUT UVLOAVIN

Input Voltage Rising UVLOAVINRISE

Option 0 2.275 V

Option 1 3.9 V

Input Voltage Falling UVLOAVINFALL

Option 0 1.95 V

Option 1 3.1 V

SHUTDOWN CURRENT IGND-SD ENx = GND 0.1 2 µA

Thermal Shutdown Threshold TSSD TJ rising 150 °C

Thermal Shutdown Hysteresis TSSD-HYS 20 °C

START-UP TIME1

BUCK tSTART1 250 µs

LDO1, LDO2 tSTART2 VOUT2, VOUT3 = 3.3 V 85 µs

Enx, MODE, INPUTS

Input Logic High VIH 2.5 V ≤ AVIN ≤ 5.5 V 1.2 V

Input Logic Low VIL 2.5 V ≤ AVIN ≤ 5.5 V 0.4 V

Input Leakage Current

I-LEAKAGE

ENx = AVIN or GND

0.05

µA

1 Start-up time is defined as the time from the moment EN1 = EN2 = EN3 transfers from 0 V to VAVIN to the moment VOUT1, VOUT2, and VOUT3 reach 90% of their

nominal level. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more

information.

BUCK SPECIFICATIONS

AVIN, VIN1 = 2.3 V to 5.5 V; VOUT1 = 1.8 V; L = 1 µH; CIN = 10 µF; COUT = 10 µF; TJ= −40°C to +125°C for minimum/maximum

specifications, and TA = 25°C for typical specifications, unless otherwise noted.1

Table 2.

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

INPUT CHARACTERISTICS

Input Voltage Range VIN1 2.3 5.5 V

OUTPUT CHARACTERISTICS

Output Voltage Accuracy VOUT1 PWM mode,

ILOAD = 0 mA to 1200 mA

−3 +3 %

Line Regulation (ΔVOUT1/VOUT1)/ΔVIN1 PWM mode −0.05 %/V

Load Regulation (ΔVOUT1/VOUT1)/ΔIOUT1 ILOAD = mA to 1200 mA, PWM mode −0.1 %/A

VOLTAGE FEEDBACK VFB1 0.485 0.5 0.515 V

PWM TO POWER SAVE MODE

CURRENT THRESHOLD

IPSM_L 100 mA

INPUT CURRENT CHARACTERISTICS MODE = ground

DC Operating Current INOLOAD ILOAD = 0 mA, device not switching, all other

channels disabled

21 35 μA

Shutdown Current ISHTD EN1 = 0 V, TA = TJ = −40°C to +125°C 0.2 1.0 μA

ADP5040 Data Sheet

Rev. A | Page 4 of 40

Parameter Symbol Test Conditions/Comments Min Typ Max Unit

SW CHARACTERISTICS

SW On Resistance RPFET PFET, AVIN = VIN1 = 3.6 V 180 240 mΩ

PFET, AVIN = VIN1 = 5 V 140 190 mΩ

RNFET NFET, AVIN = VIN1 = 3.6 V 170 235 mΩ

NFET, AVIN = VIN1 = 5 V

150

210

mΩ

Current Limit ILIMIT PFET switch peak current limit 1600 1950 2300 mA

ACTIVE PULL-DOWN EN1 = 0 V 85 Ω

OSCILLATOR FREQUENCY FOSC 2.5 3.0 3.5 MHz

1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

LDO1, LDO2 SPECIFICATIONS

VIN2, VIN3 = (VOUT2,VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; AVIN, VIN1 ≥ VIN2, VIN3; CIN = 1 µF, COUT = 2.2 µF;

TJ= −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted. 1

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

INPUT VOLTAGE RANGE VIN2, VIN3 TJ = −40°C to +125°C 1.7 5.5 V

OPERATING SUPPLY CURRENT

Bias Current per LDO2 IVIN2BIAS /IVIN3BIAS IOUT3 = IOUT4 = 0 µA 10 30 µA

IOUT2 = IOUT3 = 10 mA 60 100 µA

IOUT2 = IOUT3 = 300 mA

165

245

µA

Total System Input Current IIN Includes all current into AVIN, VIN1, VIN2 and VIN3

LDO1 or LDO2 Only IOUT2 = IOUT3 = 0 µA, all other channels disabled 53 µA

LDO1 and LDO2 Only IOUT2 = IOUT3 = 0 µA, buck disabled 74 µA

OUTPUT VOLTAGE ACCURACY VOUT2, VOUT3

100 µA < IOUT2 < 300 mA, 100 µA < IOUT3 < 300 mA

VIN2 = (VOUT2 + 0.5 V) to 5.5 V,

VIN3 = (VOUT3 + 0.5 V) to 5.5 V

−3 +3 %

REFERENCE VOLTAGE VFB2, VFB3 0.485 0.500 0.515 V

REGULATION

Line Regulation (ΔVOUT2/VOUT2)/ΔVIN2

(ΔVOUT3/VOUT3)/ΔVIN3

VIN2 = (VOUT2 + 0.5 V) to 5.5 V

VIN3 = (VOUT3 + 0.5 V) to 5.5 V

−0.03 +0.03 %/ V

IOUT2 = IOUT3 = 1 mA

Load Regulation3 (ΔVOUT2/VOUT2)/ΔIOUT2

(ΔVOUT3/VOUT3)/ΔIOUT3

IOUT2 = IOUT3 = 1 mA to 300 mA 0.002 0.0075 %/mA

DROPOUT VOLTAGE4 VDROPOUT

VOUT2 = VOUT3 = 5.0 V, IOUT2 = IOUT3 = 300 mA 72 mV

VOUT2 = VOUT3 = 3.3 V, IOUT2 = IOUT3 = 300 mA 86 140 mV

VOUT2 = VOUT3 = 2.5 V, IOUT2 = IOUT3 = 300 mA 107 mV

VOUT2 = VOUT3 = 1.8 V, IOUT2 = IOUT3 = 300 mA 180 mV

ACTIVE PULL-DOWN RPDLDO EN2/EN3 = 0 V 600 Ω

CURRENT-LIMIT THRESHOLD5 ILIMIT TJ = −40°C to +125°C 335 470 mA

OUTPUT NOISE OUTLDO2NOISE 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V 123 µV rms

10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 110 µV rms

10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V 59 µV rms

OUTLDO1NOISE 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V 140 µV rms

10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V 129 µV rms

10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V 66

µV rms

Data Sheet ADP5040

Rev. A | Page 5 of 40

Parameter Symbol Conditions Min Typ Max Unit

POWER SUPPLY REJECTION

RATIO

PSRR 1 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,

IOUT = 100 mA

66 dB

100 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,

IOUT = 100 mA

57 dB

1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,

IOUT = 100 mA

60 dB

1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).

2 This is the input current into VIN2 and VIN3, which is not delivered to the output load.

3 Based on an end-point calculation using 1 mA and 300 mA loads.

4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output

voltages above 1.7 V.

5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V

output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 4.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CAPACITANCE (BUCK)1 CMIN1 TJ = −40°C to +125°C 4.7 40 µF

OUTPUT CAPACITANCE (BUCK)

MIN2

= −40°C to +125°C

µF

INPUT AND OUTPUT CAPACITANCE3 (LDO1, LDO2) CMIN34 TJ = −40°C to +125°C 0.70 µF

CAPACITOR ESR RESR TJ = −40°C to +125°C 0.001 1 Ω

1 The minimum input capacitance should be greater than 4.7 µF over the full range of operating conditions. The full range of operating conditions in the application

must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas

Y5V and Z5U capacitors are not recommended for use with the buck.

2 The minimum output capacitance should be greater than 7 µF over the full range of operating conditions. The full range of operating conditions in the application

must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas

Y5V and Z5U capacitors are not recommended for use with the buck.

3 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the

application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,

whereas Y5V and Z5U capacitors are not recommended for use with LDOs.

ADP5040 Data Sheet

Rev. A | Page 6 of 40

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

AVIN to AGND −0.3 V to +6 V

VIN1 to AVIN −0.3 V to +0.3 V

PGND to AGND −0.3 V to +0.3 V

VIN2, VIN3, VOUTx, ENx, MODE, FBx,

SW to AGND

−0.3 V to (AVIN + 0.3 V)

SW to PGND −0.3 V to (VIN1 + 0.3 V)

Storage Temperature Range −65°C to +150°C

Operating Junction Temperature Range −40°C to +125°C

Soldering Conditions JEDEC J-STD-020

ESD Human Body Model 3000 V

ESD Charged Device Model 1500 V

ESD Machine Model 200 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θ

JC Unit

20-Lead, 0.5 mm pitch LFCSP 38 4.2 °C/W

ESD CAUTION

Data Sheet ADP5040

Rev. A | Page 7 of 40

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VOUT2

15 FB2

VIN2

FB1

11 VOUT1

FB3

VIN3 2

VOUT3

EN3 5

VIN1 6

AVIN

SW 9

PGND 10

EN1

19 NC

20 NC

18 NC

17 MODE

16 EN2

DP5040

TOP VIEW

(No t to Scale)

NOTES

1. EXPOSED PAD MUST BE CONNECT ED TO

SYSTEM GROUND PLANE.

09665-002

Figure 2. Pin Configuration—View from Top of the Die

Table 7. Preliminary Pin Function Descriptions

Pin No. Mnemonic Description

1 FB3 LDO2 Feedback Input.

2 VOUT3 LDO2 Output Voltage.

3 VIN3 LDO2 Input Supply (1.7 V to 5.5 V).

4 EN3 Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2.

6 AVIN Housekeeping Input Supply (2.3 V to 5.5 V).

7 VIN1 Buck Input Supply (2.3 V to 5.5 V).

8 SW Buck Switching Node.

9 PGND Dedicated Power Ground for Buck Regulator.

10 EN1 Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck.

11 VOUT1 Buck Output Sensing Node.

12 FB1 Buck Feedback Input.

13 VIN2 LDO1 Input Supply (1.7 V to 5.5 V).

14 VOUT2 LDO1 Output Voltage.

15 FB2 LDO1 Feedback Input.

16 EN2 Enable LDO1. EN2 = high: turn on LDO1; EN2 = low: turn off LDO1.

17 MODE

Buck Mode. Mode = high: buck regulator operates in fixed PWM mode; mode = low: buck regulator operates in

power save mode (PSM) at light load and in constant PWM at higher load.

5, 18, 19, 20 NC Not Connected.

0 EPAD Exposed Pad. (AGND = Analog Ground). The exposed pad must be connected to the system ground plane.

ADP5040 Data Sheet

Rev. A | Page 8 of 40

TYPICAL PERFORMANCE CHARACTERISTICS

VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25°C, unless otherwise noted.

CH4 2.0V/DIV 1MΩ

500M

CH2 2.0V/DIV 1MΩ

20.0M

CH3 2.0V/DIV 1MΩ

500M

A CH2 1.88V 200µs/DIV

1.0MS/s

1.0µs/pt

OUT1

OUT2

OUT3

09665-003

Figure 3. 3-Channel Start-Up Waveforms

CH1

CH2

CH3

CH4

A CH1 1.08V 200µs/DIV

5.0MS/s

200ns/pt

OUT3

OUT2

OUT1

2.0V/DIV 1MΩ

20.0M

2.0V/DIV 1MΩ

20.0M

300mA/DIV 1MΩ

20.0M

2.0V/DIV 1MΩ

20.0M

09665-004

Figure 4. Total Inrush Current, All Channels Started Simultaneously

1.0

2.4 2.9 3.4 3.9 4.4 4.9 5.4

(mA)

(V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

09665-005

Figure 5. System Quiescent Current (Sum of All the Input Currents) vs.

Input Voltage

VOUT1 = 1.8 V, VOUT2 = VOUT3 = 3.3 V (UVLO = 3.3 V)

CH1

CH2

CH3

CH4

A CH1 2.32V 50µs/DIV

2.0MS/s

500ns/pt

OUT1

4.0V/DIV 1MΩ

20.0M

3.0V/DIV 1MΩ

500M

200mA/DIV 1MΩ

20.0M

5.0V/DIV 1MΩ

500M

09665-006

Figure 6. Buck Startup, VOUT1 = 3.3 V, IOUT2 = 20 mA

CH1

CH2

CH3

CH4

A CH1 1.12V 50µs/DIV

2.0MS/s

500ns/pt

OUT1

8.0V/DIV 1MΩ

20.0M

2.0V/DIV 1MΩ

500.0M

200mA/DIV 1MΩ

20.0M

5.0V/DIV 1MΩ

500.0M

09665-007

Figure 7. Buck Startup, VOUT1 = 1.8 V, IOUT = 20 mA

CH1

CH2

CH3

CH4

A CH1 640mV 50µs/DIV

2.0MS/s

500ns/pt

OUT1

8.0V/DIV 1MΩ

20.0M

2.0V/DIV 1MΩ

500.0M

200mA/DIV 1MΩ

20.0M

5.0V/DIV 1MΩ

500.0M

09665-008

Figure 8. Buck Startup, VOUT1 = 1.2 V, IOUT = 20 mA

Data Sheet ADP5040

Rev. A | Page 9 of 40

3.90

3.70

0.01 0.1 1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

3.72

3.74

3.76

3.78

3.80

3.82

3.84

3.86

3.88

–40°C

+25°C

+85°C

09665-009

Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 3.8 V,

Auto Mode

3.39

3.37

3.35

3.33

3.31

3.29

3.25

3.27

0.01 0.1 1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-010

Figure 10. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V,

Auto Mode

1.820

1.815

1.810

1.800

1.805

1.795

1.790

1.780

1.785

0.01 0.1 1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-011

Figure 11. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V,

Auto Mode

1.24

1.23

1.22

1.21

1.20

1.19

1.18

0.01 0.1 1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-012

Figure 12. Buck Load Regulation Across Temperature, VOUT1 = 1.2 V,

Auto Mode

3.90

3.88

3.86

3.70

3.72

3.74

3.76

3.78

3.80

3.82

3.84

0.01 0.1 1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-013

Figure 13. Buck Load Regulation Across Temperature, VOUT1 = 3.8 V,

PWM Mode

3.32

3.31

3.30

3.25

3.26

3.27

3.28

3.29

0.01 0.1 1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-014

Figure 14. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V,

PWM Mode

ADP5040 Data Sheet

Rev. A | Page 10 of 40

1.820

1.815

1.810

1.800

1.805

1.795

1.790

1.780

1.785

0.01 0.1 1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-015

Figure 15. Buck Load Regulation Across Temperature,

VOUT1 = 1.8 V, PWM Mode

1.205

1.200

1.195

1.185

1.190

1.180

0.01 0.1 1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-016

Figure 16. Buck Load Regulation Across Temperature,

VOUT1 = 1.2 V, PWM Mode

100

0.0001 0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

VIN = 5.5V

VIN = 4.5V

09665-017

Figure 17. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 3.8 V, Auto Mode

100

0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

VIN = 5.5V

VIN = 4.5V

09665-018

Figure 18. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 3.8 V, PWM Mode

100

0.0001 0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

VIN = 5.5V

VIN = 4.5V

VIN = 3.6V

09665-019

Figure 19. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 3.3 V, Auto Mode

100

0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

VIN = 5.5

VIN = 3.6

VIN = 4.5

09665-020

Figure 20. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 3.3 V, PWM Mode

Data Sheet ADP5040

Rev. A | Page 11 of 40

100

0.0001 0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

VIN = 2.4V

VIN = 3.6V

VIN = 4.5V

VIN = 5.5V

09665-021

Figure 21. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 1.8 V, Auto Mode

100

0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

VIN = 2.4V

VIN = 3.6V

VIN = 4.5V

VIN = 5.5V

09665-022

Figure 22. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 1.8 V, PWM Mode

100

0.0001 0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

VIN = 2.4V

VIN = 3.6V

VIN = 4.5V

VIN = 5.5V

09665-023

Figure 23. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 1.2 V, Auto Mode

100

0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

VIN = 2.4V

VIN = 3.6V

VIN = 4.5V

VIN = 5.5V

09665-024

Figure 24. Buck Efficiency vs. Load Current, Across Input Voltage,

VOUT1 = 1.2 V, PWM Mode

100

0.0001 0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-025

Figure 25. Buck Efficiency vs. Load Current, Across Temperature,

VIN = 5.0 V, VOUT1 = 3.3 V, Auto Mode

100

0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-026

Figure 26. Buck Efficiency vs. Load Current, Across Temperature,

VIN = 5.0 V, VOUT1 = 3.3 V, PWM Mode

ADP5040 Data Sheet

Rev. A | Page 12 of 40

100

0.0001 0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-027

Figure 27. Buck Efficiency vs. Load Current, Across Temperature,

VIN = 5.0 V, VOUT1 = 1.8 V, Auto Mode

100

0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-028

Figure 28. Buck Efficiency vs. Load Current, Across Temperature,

VIN = 5.0 V, VOUT1 = 1.8 V, PWM Mode

100

0.0001 0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-029

Figure 29. Buck Efficiency vs. Load Current, Across Temperature,

VIN = 5.0 V, VOUT1 = 1.2 V, Auto Mode

100

0.001 0.01 0.1 1

EF FICIENCY ( %)

OUTPUT CURRE NT (A)

–40°C

+25°C

+85°C

09665-030

Figure 30. Buck Efficiency vs. Load Current, Across Temperature,

VIN = 5.0 V, VOUT1 = 1.2 V, PWM Mode

2.5

2.0

0.5

1.0

1.5

3.4 3.9 4.4 4.9 5.4

OUTPUT CURRE NT (A)

VIN (V)

VOUT = 3. 3V

09665-031

Figure 31. Buck DC Current Capability vs. Input Voltage

2.0

1.8

0.2

0.4

0.6

0.8

1.6

1.4

1.2

1.0

2.4 3.93.42.9 4.4 4.9 5.4

OUTPUT CURRE NT (A)

(V)

OUT

= 1.8V

09665-032

Figure 32. Buck DC Current Capability vs. Input Voltage

Data Sheet ADP5040

Rev. A | Page 13 of 40

2.0

1.8

0.2

0.4

0.6

0.8

1.6

1.4

1.2

1.0

2.4 3.93.42.9 4.4 4.9 5.4

OUTPUT CURRENT (A)

(V)

OUT

= 1.2V

09665-033

Figure 33. Buck DC Current Capability vs. Input Voltage

2.80

2.82

2.84

2.86

2.88

2.90

2.92

2.94

01.21.00.2 0.4 0.6 0.8

FREQUENCY (MHz)

OUTPUT CURRENT (A)

–40°C

+25°C

+85°C

09665-034

Figure 34. Buck Switching Frequency vs. Output Current,

Across Temperature, VOUT1 = 1.8 V, PWM Mode

CH2

CH3

CH4

A CH1 640mV 5µs/DIV

500MS/s

2.0ns/pt

VOUT

ISW

200mA/DIV 1MΩBW 20.0M

3.0V/DIV 1MΩBW 20.0M

40.0mV/DIV 20.0M

09665-035

Figure 35. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode

CH2

CH3

CH4

A CH1 640mV 5µs/DIV

500MS/s

2.0ns/pt

VOUT

ISW

200mA/DIV 1MΩBW 20.0M

3.0V/DIV 1MΩBW 20.0M

40.0mV/DIV 20.0M

09665-036

Figure 36. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, Auto Mode

CH2

CH3

CH4

A CH3 1.14V 5µs/DIV

500MS/s

2.0ns/pt

VOUT

ISW

200mA/DIV 1MΩBW 20.0M

3.0V/DIV 1MΩBW 20.0M

40.0mV/DIV 20.0M

09665-037

Figure 37. Typical Waveforms, VOUT1 = 1.2 V, IOUT1 = 30 mA, Auto Mode

CH2

CH3

CH4

A CH1 640mV 200ns/DIV

500MS/s

2.0ns/pt

OUT

200mA/DIV 1MΩ

20.0M

3.0V/DIV 1MΩ

20.0M

10.0mV/DIV 20.0M

09665-038

Figure 38. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode

ADP5040 Data Sheet

Rev. A | Page 14 of 40

CH2

CH3

CH4

A CH1 640mV 200ns/DIV

500MS/s

2.0ns/pt

VOUT

ISW

200mA/DIV 1MΩ BW 20. 0M

3.0V/DIV 1MΩ BW 20. 0M

20.0mV/DIV 20.0M

09665-039

Figure 39. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode

CH2

CH3

CH4

A CH3 1.14V 200ns/DIV

500MS/s

2.0ns/pt

VOUT

ISW

200mA/DIV 1MΩ BW 20. 0M

3.0V/DIV 1MΩ BW 20. 0M

40.0mV/DIV 20.0M

09665-040

Figure 40. Typical Waveforms, VOUT1 = 1.2 V, IOUT1 = 30 mA, PWM Mode

CH1

CH2

CH3

A CH3 4.48V

OUT

3.0V/DIV

50.0mV/DIV 1MΩ

20.0M

1.0V/DIV

400M

20.0M

200µs/DIV

1.0MS/s

1.0µs/pt

09665-041

Figure 41. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, VOUT1 = 3.3 V, IOUT1 = 5 mA, Auto Mode

CH1

CH2

CH3

A CH3 4.48V

OUT

3.0V/DIV

30.0mV/DIV 1MΩ

20.0M

1.0V/DIV

400M

20.0M 200µs/DIV

1.0MS/s

1.0µs/pt

09665-042

Figure 42. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, VOUT1 = 1.8 V, IOUT1 = 5 mA, Auto Mode

CH1

CH2

CH3

A CH3 4.48V

VOUT

VIN

3.0V/DIV

50.0mV/DIV 1MΩ BW 20. 0M

1.0V/DIV

BW 400M

BW 20.0M 200µs/DIV

1.0MS/s

1.0µs/pt

09665-043

Figure 43. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, VOUT1 = 1.2 V, IOUT1 = 5 mA, Auto Mode

CH1

CH2

CH3

A CH3 4.48V

VOUT

VIN

3.0V/DIV

50.0mV/DIV 1MΩ BW 20. 0M

1.0V/DIV

BW 400M

BW 20.0M 200µs/DIV

1.0MS/s

1.0µs/pt

09665-044

Figure 44. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, VOUT1 = 3.3 V, PWM Mode

Data Sheet ADP5040

Rev. A | Page 15 of 40

CH1

CH2

CH3

A CH3 4.48V

OUT

3.0V/DIV

20.0mV/DIV 1MΩ

20.0M

1.0V/DIV

400M

20.0M 200µs/DIV

1.0MS/s

1.0µs/pt

09665-045

Figure 45. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, VOUT1 = 1.8 V, PWM Mode

CH1

CH2

CH3

A CH3 4.48V

VOUT

VIN

3.0V/DIV

50.0mV/DIV 1MΩ BW 20. 0M

1.0V/DIV

BW 20.0M

BW 20.0M 200µs/DIV

1.0MS/s

1.0µs/pt

09665-046

Figure 46. Buck Response to Line Transient, Input Voltage from 4.5 V to

5.0 V, VOUT1 = 1.2 V, PWM Mode

CH1

CH2

CH3

A CH3 150mA

VOUT

4.0V/DIV

100mV/DIV 1MΩ BW 20.0M

1MΩ BW 20. 0M

300mA/DIV

BW 20.0M 500µs/DIV

20.0MS/s

50.0ns/pt

IOUT

09665-047

Figure 47. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA,

VOUT1 = 3.3 V, Auto Mode

CH1

CH2

CH3

A CH3 150mA

OUT

4.0V/DIV

100mV/DIV 1MΩ

20.0M

1MΩ

20.0M

300mA/DIV

20.0M 500µs/DIV

20.0MS/s

50.0ns/pt

OUT

09665-048

Figure 48. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA,

VOUT1 = 3.3 V, Auto Mode

CH1

CH2

CH3

A CH3 150mA

VOUT

4.0V/DIV

100mV/DIV 1MΩ BW 20.0M

1MΩ BW 20.0M

300mA/DIV

BW 20.0M 500µs/DIV

20.0MS/s

50.0ns/pt

IOUT

09665-049

Figure 49. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA,

VOUT1 = 1.8 V, Auto Mode

CH1

CH2

CH3

A CH3 150mA

VOUT

4.0V/DIV

100mV/DIV 1MΩ BW 20.0M

1MΩ BW 20.0M

300mA/DIV

BW 20.0M 500µs/DIV

20.0MS/s

50.0ns/pt

IOUT

09665-050

Figure 50. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA,

VOUT1 = 1.8 V, Auto Mode

ADP5040 Data Sheet

Rev. A | Page 16 of 40

CH1

CH2

CH3

A CH3 94.0mA

OUT

4.0V/DIV

50.0mV/DIV 1MΩ

120M

1MΩ

20.0M

100mA/DIV

20.0M 200µs/DIV

500kS/s

2.0µs/pt

OUT

09665-051

Figure 51. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA,

VOUT1 = 1.2 V, Auto Mode

CH1

CH2

CH3

A CH3 92.0mA

VOUT

4.0V/DIV

50.0mV/DIV 1MΩ BW 120M

BW 20.0M

200mA/DIV

BW 20.0M 200µs/DIV

500kS/s

2.0µs/pt

IOUT

09665-052

Figure 52. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA,

VOUT1 = 1.2 V, Auto Mode

CH1

CH2

CH3

A CH3 150mA

VOUT

4.0V/DIV

50.0mV/DIV 1MΩ BW 20. 0M

1MΩ BW 20. 0M

300mA/DIV

BW 20.0M 500µs/DIV

20.0MS/s

50.0ns/pt

IOUT

09665-053

Figure 53. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA,

VOUT1 = 3.3 V, PWM Mode

CH1

CH2

CH3

A CH3 150mA

OUT

4.0V/DIV

50.0mV/DIV 1MΩ

20.0M

1MΩ

20.0M

300mA/DIV

20.0M 500µs/DIV

20.0MS/s

50.0ns/pt

OUT

09665-054

Figure 54. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA,

VOUT1 = 3.3 V, PWM Mode

CH1

CH2

CH3

A CH3 150mA

VOUT

4.0V/DIV

50.0mV/DIV 1MΩ BW 20. 0M

1MΩ BW 20.0M

300mA/DIV

BW 20.0M 500µs/DIV

20.0MS/s

50.0ns/pt

IOUT

09665-055

Figure 55. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA,

VOUT1 = 1.8 V, PWM Mode

CH1

CH2

CH3

A CH3 150mA

VOUT

4.0V/DIV

100mV/DIV 1MΩ BW 20.0M

1MΩ BW 20.0M

300mA/DIV

BW 20.0M 500µs/DIV

20.0MS/s

50.0ns/pt

IOUT

09665-056

Figure 56. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA,

VOUT1 = 1.8 V, PWM Mode

Data Sheet ADP5040

Rev. A | Page 17 of 40

CH1

CH2

CH3

A CH3 94.0mA

OUT

4.0V/DIV

50.0mV/DIV

1MΩ

120.0M

20.0M

100mA/DIV

20.0M

200µs/DIV

500kS/s

2.0ns/pt

OUT

09665-057

Figure 57. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA,

VOUT1 = 1.2 V, PWM Mode

CH1

CH2

CH3

A CH3 92.0mA

VOUT

4.0V/DIV

50.0mV/DIV

1MΩBW 20.0M

20.0M

200mA/DIV

20.0M

200µs/DIV

500kS/s

2.0ns/pt

IOUT

09665-058

Figure 58. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA,

VOUT1 = 1.2 V, PWM Mode

CH1

CH2

CH3

A CH1 1.72V

OUT

2.0V/DIV

20.0M

1MΩ

20.0M

200mA/DIV

1MΩ

20.0M

50.0µs/DIV

200MS/s

5.0ns/pt

09665-059

Figure 59. LDO1, LDO2 Startup, VOUT = 4.7 V, IOUT = 5 mA

CH1

CH2

CH3

A CH1 1.72V

OUT

2.0V/DIV

20.0M

1MΩ

20.0M

200mA/DIV

1MΩ

20.0M

50.0µs/DIV

200MS/s

5.0ns/pt

09665-060

Figure 60. LDO1, LDO2 Startup, VOUT = 3.3 V, IOUT = 5 mA

CH1

CH2

CH3

A CH1 760mV

OUT

2.0V/DIV

1.0V/DIV

20.0M

1MΩ

20.0M

200mA/DIV

1MΩ

20.0M

50.0µs/DIV

200MS/s

5.0ns/pt

09665-061

Figure 61. LDO1, LDO2 Startup, VOUT = 1.8 V, IOUT = 5 mA

CH1

CH2

CH3

A CH1 1.72V

VOUT

2.0V/DIV

1.0V/DIV

BW 20.0M

1MΩBW 20.0M

200mA/DIV

1MΩBW 20.0M

50.0µs/DIV

200MS/s

5.0ns/pt

IIN

09665-062

Figure 62. LDO1, LDO2 Startup, VOUT = 1.2 V, IOUT = 5 mA

ADP5040 Data Sheet

Rev. A | Page 18 of 40

4.758

4.708

4.658

4.608

0.001 0.01 0.1

OUT P UT VO LTAGE (V)

OUT P UT CURRENT ( A)

5.5V

5.0V

09665-063

Figure 63. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 4.7 V

3.40

3.20

0.001 0.01 0.1

OUTPUT VOLTAGE (V)

OUT PUT CURRENT (A)

5.5V

3.6V

4.5V

3.22

3.24

3.26

3.28

3.30

3.32

3.34

3.36

3.38

09665-064

Figure 64. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 3.3 V

1.800

1.770

0.001 0.01 0.1

OUTPUT VOLTAGE (V)

OUT PUT CURRENT (A)

1.775

1.780

1.785

1.790

1.795

3.6V

4.5V

5.5V

2.8V

09665-065

Figure 65. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 1.8 V

1.220

1.180

0.001 0.01 0.1

OUTPUT VOLTAGE (V)

OUT PUT CURRENT (A)

3.6V

4.5V

5.5V

2.8V

1.185

1.190

1.195

1.200

1.205

1.210

1.215

09665-066

Figure 66. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 1.2 V

3.40

3.20

0.001 0.01 0.1

OUTPUT VOLTAGE (V)

OUT PUT CURRENT (A)

3.22

3.24

3.26

3.28

3.30

3.32

3.34

3.36

3.38 –40°C

+25°C

+85°C

09665-067

Figure 67. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V,

VOUT = 3.3 V

1.800

1.770

0.001 0.01 0.1

OUTPUT VOLTAGE (V)

OUT PUT CURRENT (A)

–40°C

+25°C

+85°C

1.775

1.780

1.785

1.790

1.795

09665-068

Figure 68. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V,

VOUT = 1.8 V

Data Sheet ADP5040

Rev. A | Page 19 of 40

1.220

1.180

0.001 0.01 0.1

OUTPUT VOLTAGE (V)

OUTPUT CURRE NT (A)

1.185

1.190

1.195

1.200

1.205

1.210

1.215

–40°C

+25°C

+85°C

09665-069

Figure 69. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V,

VOUT = 1.2 V

4.75

4.73

4.65

4.67

4.69

4.71

5.0 5.1 5.55.45.35.2

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

100µA

1mA

10mA

100mA

200mA

09665-070

Figure 70. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 4.7 V

3.310

3.2803.6 3.9 4.2 4.5 5.14.8 5.4

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

3.285

3.290

3.295

3.300

3.305

100µA

1mA

10mA

100mA

200mA

09665-071

Figure 71. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 3.3 V

1.820

1.7902.5 3.0 3.5 4.0 5.04.5 5.5

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

100µA

1mA

10mA

100mA

200mA

1.795

1.800

1.805

1.810

1.815

09665-072

Figure 72. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 1.8 V

1.201

1.1922.5 5.5

OUTPUT VOLTAGE (V)

INPUT VOLTAGE (V)

1.193

1.194

1.195

1.196

1.197

1.198

1.199

1.200

3.0 3.5 4.0 4.5 5.0

100µA

1mA

10mA

100mA

200mA

09665-073

Figure 73. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 1.2 V

200

000.05 0.10 0.15 0.20 0.25 0.30

GROUND CURRENT ( µA)

OUTPUT CURRE NT (A)

100

120

140

160

180

09665-074

Figure 74. LDO1, LDO2 Ground Current vs. Output Current, VOUT = 3.3 V

ADP5040 Data Sheet

Rev. A | Page 20 of 40

200

3.8 4.3 4.8 5.3

GROUND CURRENT ( µA)

INPUT VOLTAGE (V)

100

120

140

160

180

0.000001A

0.0001A

0.001A

0.01A

0.1A

0.15A

0.3A

09665-075

Figure 75. LDO1, LDO2 Ground Current vs. Input Voltage, Across Output

Load (A), VOUT = 3.3 V

CH2

CH3 A CH3 27.2mA

OUT

30.0mV/DIV

80.0mA/DIV

20.0M

1MΩ

20.0M 200µs/DIV

5.0MS/s

200ns/pt

OUT

09665-076

Figure 76. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to

80 mA, VOUT = 4.7 V

CH2

CH3 A CH3 27.2mA

2VOUT

30.0mV/DIV

80.0mA/DIV

BW 20.0M

1MΩ BW 20. 0M 200µs/DIV

5.0MS/s

200ns/pt

IOUT

09665-077

Figure 77. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to

200 mA, VOUT = 4.7 V

CH2

CH3 A CH3 42.0mA

VOUT

30.0mV/DIV

50.0mA/DIV

BW 20.0M

1MΩ BW 120M 200µs/DIV

500kS/s

2.0µs/pt

IOUT

09665-078

Figure 78. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to

80 mA, VOUT = 3.3 V

CH2

CH3 A CH3 89.6mA

OUT

50.0mV/DIV

80.0mA/DIV

20.0M

1MΩ

120M 200µs/DIV

500kS/s

2.0µs/pt

OUT

09665-079

Figure 79. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to

200 mA, VOUT = 3.3 V

CH2

CH3 A CH3 89.6mA

2VOUT

30.0mV/DIV

80.0mA/DIV

BW 20.0M

1MΩ BW 120M 200µs/DIV

500kS/s

2.0µs/pt

IOUT

09665-080

Figure 80. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to

80 mA, VOUT = 1.8 V

Data Sheet ADP5040

Rev. A | Page 21 of 40

CH2

CH3 A CH3 89.6mA

2VOUT

50.0mV/DIV

80.0mA/DIV

BW 20.0M

1MΩ BW 120M 200µs/DIV

500kS/s

2.0µs/pt

IOUT

09665-081

Figure 81. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to

200 mA, VOUT = 1.8 V

CH2

CH3 A CH3 27.2mA

OUT

30.0mV/DIV

80.0mA/DIV

20.0M

1MΩ

20.0M 200µs/DIV

5.0MS/s

200ns/pt

OUT

09665-082

Figure 82. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to

80 mA, VOUT = 1.2 V

CH2

CH3 A CH3 27.2mA

2VOUT

30.0mV/DIV

80.0mA/DIV

BW 20.0M

1MΩ BW 20. 0M 200µs/DIV

5.0MS/s

200ns/pt

IOUT

09665-083

Figure 83. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to

200 mA, VOUT = 1.2 V

CH2

CH3 A CH3 4.84V

VOUT

20.0mV/DIV

1.0V/DIV

BW 20.0M

1MΩ BW 20. 0M 200µs/DIV

1.0MS/s

1.0µs/pt

VIN

09665-084

Figure 84. LDO1, LDO2 Response to Line Transient, Input Voltage from

4.5 V to 5.5 V, VOUT = 3.3 V

CH2

CH3 A CH3 4.86V

OUT

20.0mV/DIV

1.0V/DIV

20.0M

1MΩ

20.0M 500µs/DIV

1.0MS/s

1.0µs/pt

09665-085

Figure 85. LDO1, LDO2 Response to Line Transient, Input Voltage from

4.5 V to 5.5 V, VOUT = 1.8 V

CH2

CH3 A CH3 4.48V

2VOUT

20.0mV/DIV

1.0V/DIV

BW 20.0M

1MΩ BW 20. 0M 200µs/DIV

1.0MS/s

1.0µs/pt

VIN

09665-086

Figure 86. LDO1, LDO2 Response to Line Transient, Input Voltage from

4.5 V to 5.5 V, VOUT = 1.2 V

ADP5040 Data Sheet

Rev. A | Page 22 of 40

CH2

CH3

A CH3 4.02V

OUT

20.0mV/DIV

1.0V/DIV

20.0M

1MΩ

20.0M

200µs/DIV

1.0MS/s

1.0µs/pt

09665-087

Figure 87. LDO1, LDO2 Response to Line Transient, Input Voltage from

3.3 V to 3.8 V, VOUT = 1.8 V

CH2

CH3

A CH3 4.84V

OUT

20.0mV/DIV

1.0V/DIV

20.0M

1MΩ

20.0M

200µs/DIV

1.0MS/s

1.0µs/pt

09665-088

Figure 88. LDO1, LDO2 Response to Line Transient, Input Voltage from

3.3 V to 3.8 V, VOUT = 1.2 V

0.7

0.6

0.5

0.4

0.3

0.2

0.1

3.6 4.1 4.6 5.1 5.6

OUTPUT CURRENT (A)

(V)

OUT

= 3.3V

09665-089

Figure 89. LDO1, LDO2 Output Current Capability vs. Input Voltage

LOAD (mA)

RMS NOISE (µV)

100

0.0001 0.001 0.01 0.1 1 10 100 1k

CH2; V

OUT

= 3.3V; V

= 5V

CH2; V

OUT

= 3.3V; V

= 3.6V

CH2; V

OUT

= 2.8V; V

= 3.1V

CH2; V

OUT

= 1.5V; V

= 5V

CH2; V

OUT

= 1.5V; V

= 1.8V

09665-104

Figure 90. LDO1 Output Noise vs. Load Current, Across Input and

Output Voltage

LOAD (mA)

RMS NOISE (µV)

100

CH3; V

OUT

= 3.3V; V

= 5V

CH3; V

OUT

= 3.3V; V

= 3.6V

CH3; V

OUT

= 2.8V; V

= 3.1V

CH3; V

OUT

= 1.5V; V

= 5V

CH3; V

OUT

= 1.5V; V

= 1.8V

0.0001 0.001 0.01 0.1 1 10 100 1k

09665-105

Figure 91. LDO2 Output Noise vs. Load Current, Across Input and Output

Voltage

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

NOISE (µV/

√

Hz)

100

1.0

0.1

0.01

OUT2

= 3.3V, V

IN2

= 3.6V, I

LOAD

= 300mA

OUT2

= 1.5V, V

IN2

= 1.8V, I

LOAD

= 300mA

OUT2

= 2.8V, V

IN2

= 3.1V, I

LOAD

= 300mA

09665-106

Figure 92. LDO1 Noise Spectrum Across Output Voltage,

VIN = VOUT + 0.3 V

Data Sheet ADP5040

Rev. A | Page 23 of 40

NOISE (µV/√Hz)

100

0.1

0.01 110 100 1k

FREQUENCY (Hz)10k 100k 1M

VOUT3 = 3.3V, VIN3 = 3.6V, ILOAD = 300mA

VOUT3 = 1.5V, VIN3 = 1.8V, ILOAD = 300mA

VOUT3 = 2.8V, VIN3 = 3.1V, ILOAD = 300mA

09665-115

Figure 93. LDO2 Noise Spectrum Across Output Voltage,

VIN = VOUT + 0.3 V

100

1.0

0.1

0.0110 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

NOISE (µV/

√Hz

)

OUT2

= 3.3V , V

IN2

= 3.6V , I

LOAD

= 300mA

OUT3

= 3.3V , V

IN3

= 3.6V , I

LOAD

= 300mA

OUT2

= 1.5V , V

IN2

= 1.8V , I

LOAD

= 300mA

OUT3

= 1.5V, V

IN3

= 1.8V, I

LOAD

= 300m A

OUT2

= 2.8V, V

IN2

= 3.1V, I

LOAD

= 300m A

OUT3

= 2.8V, V

IN3

= 3.1V, I

LOAD

= 300m A

09665-108

Figure 94. LDO1 vs. LDO2 Noise Spectrum

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10010 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

PSRR ( dB)

1mA

10mA

100mA

200mA

300mA

09665-109

Figure 95. LDO2 PSRR Across Output Load,

VIN3 = 3.3 V, VOUT3 = 2.8 V

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10010 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

PSRR ( dB)

1mA

10mA

100mA

200mA

300mA

09665-110

Figure 96. LDO2 PSRR Across Output Load,

VIN3 = 3.1 V, VOUT3 = 2.8 V

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10010 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

PSRR ( dB)

1mA

10mA

100mA

200mA

09665-111

Figure 97. LDO2 PSRR Across Output Load,

VIN3 = 5.0 V, VOUT3 = 3.3 V

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10010 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

PSRR ( dB)

1mA

10mA

100mA

200mA

300mA

09665-112

Figure 98. LDO2 PSRR Across Output Load,

VIN3 = 3.6 V, VOUT3 = 3.3 V

ADP5040 Data Sheet

Rev. A | Page 24 of 40

–

–20

–30

–40

–50

–60

–70

–80

–90

–10010 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

PSRR (d B)

1mA

10mA

100mA

200mA

300mA

09665-113

Figure 99. LDO1 PSRR Across Output Load,

VIN2 = 5.0 V, VOUT2 = 1.5 V

–

–20

–30

–40

–50

–60

–70

–80

–90

–10010 100 1k 10k 100k 1M 10M

FRE QUENC Y ( Hz )

PSRR (dB)

1mA

10mA

100mA

200mA

300mA

09665-114

Figure 100. LDO1 PSRR Across Output Load,

VIN2 = 1.8 V, VOUT2 = 1.5 V

Data Sheet ADP5040

Rev. A | Page 25 of 40

THEORY OF OPERATION

PWM/

PSM

CONTROL

BUCK1

DRIVER

AND

ANTISHOOT

THROUGH

PSM

COMP

ADP5040

VOUT1 FB1

VIN1

AVIN

PGND

AGND

VIN2 FB2 VOUT2 VIN3

ENLDO1

600Ω

ENBK

ENLDO2

600Ω

VOUT3FB3

09665-090

OSCILLATOR

THERMAL

SHUTDOWN

VDDA

PWM

COMP

GM E RROR

AMP

85Ω

SOFT START

SYSTEM

UNDERVOLTAGE

LOCK OUT

LDO1

CONTROL LDO2

CONTROL

VDDA

ENABLE

& MO DE

CONTROL

ENLDO1

ENBK

ENLDO2

MODE

SEL

MODE

EN1

EN2

EN3

OPMODE_FUSES

VDDA

ILIMIT

LOW

CURRENT

Figure 101. Functional Block Diagram

POWER MANAGEMENT UNIT

The ADP5040 is a micro power management unit (micro PMU)

combing one step-down (buck) dc-to-dc regulator and two low

dropout linear regulators (LDOs). The high switching frequency

and tiny 20-pin LFCSP package allow for a small power

management solution.

The regulators are activated by a logic level high applied to the

respective EN pin. The EN1 pin controls the buck regulator, the

EN2 pin controls LDO1, and the EN3 pin controls LDO2. The

MODE pin controls the buck switching operation.

The regulator output voltages are set through external resistor

dividers.

When a regulator is turned on, the output voltage ramp is

controlled through a soft start circuit to avoid a large inrush

current due to the discharged output capacitors.

The buck regulator can operate in forced PWM mode if the

MODE pin is at a logic high level. In forced PWM mode, the

switching frequency of the buck is always constant and does not

change with the load current. If the MODE pin is at a logic low

level, the switching regulator operates in auto PWM/PSM mode.

In this mode, the regulator operates at fixed PWM frequency

when the load current is above the power saving current threshold.

When the load current falls below the power save current

threshold, the regulator enters power saving mode, where the

switching occurs in bursts. The burst repetition rate is a

function of the current load and the output capacitor value.

This operating mode reduces the switching and quiescent

current losses.

ADP5040 Data Sheet

Rev. A | Page 26 of 40

Thermal Protection

In the event that the junction temperature rises above 150°C,

the thermal shutdown circuit turns off the buck and the LDOs.

Extreme junction temperatures can be the result of high current

operation, poor circuit board design, or high ambient temperature.

A 20°C hysteresis is included in the thermal shutdown circuit so

that when thermal shutdown occurs, the buck and the LDOs do

not return to normal operation until the on-chip temperature

drops below 130°C. When coming out of thermal shutdown, all

regulators start with soft start control.

Undervoltage Lockout

To protect against battery discharge, undervoltage lockout

(UVLO) circuitry is integrated in the ADP5040. If the input

voltage on AVIN drops below a typical 2.15 V UVLO threshold,

all channels shut down. In the buck channel, both the power

switch and the synchronous rectifier turn off. When the voltage

on AVIN rises above the UVLO threshold, the part is enabled

once more.

Alternatively, the user can select device models with a UVLO

set at a higher level, suitable for 5 V applications. For these

models, the device reaches the turn-off threshold when the

input supply drops to 3.65 V typical.

Enable/Shutdown

The ADP5040 has individual control pins for each regulator.

A logic level high applied to the ENx pin activates a regulator,

whereas a logic level low turns off a regulator.

Active Pull-Down

The ADP5040 can be purchased with the active pull-down

option enabled. The pull-down resistors are connected between

each regulator output and AGND. The pull-downs are enabled,

when the regulators are turned off. The typical value of the pull-

down resistor is 600 Ω for the LDOs and 85 Ω for the buck.

BUCK SECTION

The buck uses a fixed frequency and high speed current mode

architecture. The buck operates with an input voltage of 2.3 V

to 5.5 V.

The buck output voltage is set though external resistor dividers,

as shown in Figure 102. VOUT1 must be connected to the

output capacitor. VFB1 is internally set to 0.5 V. The output

voltage can be set from 0.8 V to 3.8 V.

BUCK

VOUT1

IN1

FB1

AGND

10µF

L1 – 1µH

09665-091

Figure 102. Buck External Output Voltage Setting

Control Scheme

The buck operates with a fixed frequency, current mode PWM

control architecture at medium to high loads for high efficiency,

but operation shifts to a power save mode (PSM) control scheme

at light loads to lower the regulation power losses. When operating

in fixed frequency PWM mode, the duty cycle of the integrated

switches is adjusted and regulates the output voltage. When

operating in PSM at light loads, the output voltage is controlled

in a hysteretic manner, with higher output voltage ripple. During

part of this time, the converter is able to stop switching and

enters an idle mode, which improves conversion efficiency.

PWM Mode

In PWM mode, the buck operates at a fixed frequency of 3 MHz,

set by an internal oscillator. At the start of each oscillator cycle,

the PFET switch is turned on, sending a positive voltage across

the inductor. Current in the inductor increases until the current

sense signal crosses the peak inductor current threshold that

turns off the PFET switch and turns on the NFET synchronous

rectifier. This sends a negative voltage across the inductor,

causing the inductor current to decrease. The synchronous

rectifier stays on for the rest of the cycle. The buck regulates the

output voltage by adjusting the peak inductor current threshold.

Power Save Mode (PSM)

The buck smoothly transitions to PSM operation when the load

current decreases below the PSM current threshold. When the

buck enters power save mode, an offset is introduced in the

PWM regulation level, which makes the output voltage rise.

When the output voltage reaches a level that is approximately

1.5% above the PWM regulation level, PWM operation is

turned off. At this point, both power switches are off, and the

buck enters an idle mode. The output capacitor discharges until

the output voltage falls to the PWM regulation voltage, at which

point the device drives the inductor to make the output voltage

rise again to the upper threshold. This process is repeated while

the load current is below the PSM current threshold.

Data Sheet ADP5040

Rev. A | Page 27 of 40

The ADP5040 has a dedicated MODE pin controlling the PSM

and PWM operation. A high logic level applied to the MODE

pin forces the buck to operate in PWM mode. A logic level low

sets the buck to operate in auto PSM/PWM.

PSM Current Threshold

The PSM current threshold is set to 100 mA. The buck employs

a scheme that enables this current to remain accurately con-

trolled, independent of input and output voltage levels. This

scheme also ensures that there is very little hysteresis between

the PSM current threshold for entry to, and exit from, the PSM

mode. The PSM current threshold is optimized for excellent

efficiency over all load currents.

Short-Circuit Protection

The buck includes frequency foldback to prevent current

runaway on a hard short at the output. When the voltage at the

feedback pin falls below half the internal reference voltage,

indicating the possibility of a hard short at the output, the

switching frequency is reduced to half the internal oscillator

frequency. The reduction in the switching frequency allows

more time for the inductor to discharge, preventing a runaway

of output current.

Soft Start

The buck has an internal soft start function that ramps the

output voltage in a controlled manner upon startup, thereby

limiting the inrush current. This prevents possible input voltage

drops when a battery or a high impedance power source is

connected to the input of the converter.

Current Limit

The buck has protection circuitry to limit the amount of

positive current flowing through the PFET switch and the

amount of negative current flowing through the synchronous

rectifier. The positive current limit on the power switch limits

the amount of current that can flow from the input to the

output. The negative current limit prevents the inductor

current from reversing direction and flowing out of the load.

100% Duty Operation

With a dropping input voltage or with an increase in load

current, the buck may reach a limit where, even with the PFET

switch on 100% of the time, the output voltage drops below the

desired output voltage. At this limit, the buck transitions to a

mode where the PFET switch stays on 100% of the time. When

the input conditions change again and the required duty cycle

falls, the buck immediately restarts PWM regulation without

allowing overshoot on the output voltage.

LDO SECTION

The ADP5040 contains two LDOs with low quiescent current

that provide output currents up to 300 mA. The low 10 μA

typical quiescent current at no load makes the LDO ideal for

battery-operated portable equipment.

The LDOs operate with an input voltage range of 1.7 V to 5.5 V.

The wide operating range makes these LDOs suitable for

cascade configurations where the LDO supply voltage is

provided from the buck regulator.

Each LDO output voltage is set though external resistor dividers

as shown in Figure 103. VFB2 and VFB3 are internally set to 0.5 V.

The output voltage can be set from 0.8 V to 5.2 V.

LD01, LD02

VI N2, VI N3 VOUT2, VOUT3 VOUT2,

VOUT3

FB2, FB3

2.2µF

09665-092

Figure 103. LDOs External Output Voltage Setting

The LDOs also provide high power supply rejection ratio (PSRR),

low output noise, and excellent line and load transient response

with small 1 µF ceramic input and output capacitors.

LDO2 is optimized to supply analog circuits because it offers

better noise performance compared to LDO1. LDO1 should be

used in applications where noise performance is not critical.

ADP5040 Data Sheet

Rev. A | Page 28 of 40

POR

STANDBY

AVIN < VUVLO

ALL ENx = LOW

ALL RE GULA TO R S ACTIV ATED

AVIN < VUVLO

INTERNAL CIRCUIT BIASED

REGULATORS NOT ACTIVATED

NO POWER A PPLIE D TO A V IN.

ALL REGUL ATORS TURNED OF F

TRANSITION

STATE

09665-096

END O F POR

AVIN > VUVLO

ENx = HIGH

NO P OWER

ACTIVE

Figure 104. ADP5040 State Flow

Data Sheet ADP5040

Rev. A | Page 29 of 40

APPLICATIONS INFORMATION

BUCK EXTERNAL COMPONENT SELECTION

Trade-offs between performance parameters such as efficiency

and transient response are made by varying the choice of

external components in the applications circuit, as shown in

Figure 1.

Feedback Resistors

Referring to Figure 102, the total combined resistance for R1

and R2 is not to exceed 400 kΩ.

Inductor

The high switching frequency of the ADP5040 buck allows for

the selection of small chip inductors. For best performance, use

inductor values between 0.7 μH and 3.0 μH. Suggested inductors

are shown in Table 8.

The peak-to-peak inductor current ripple is calculated using

the following equation:

LfV

VVV

OUT

RIPPLE

××

−×

=)(

where:

fSW is the switching frequency.

L is the inductor value.

The minimum dc current rating of the inductor must be greater

than the inductor peak current. The inductor peak current is

calculated using the following equation:

)(

RIPPLE

MAXLOAD

PEAK

II +

Table 8. Suggested 1.0 μH Inductors

Vendor Model

Dimensions

(mm)

ISAT

(mA)

DCR

(mΩ)

Murata LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9 1400 85

Murata LQM18FN1R0M00B 3.2 × 2.5 × 1.5 2300 54

Tayo Yuden CBC322ST1R0MR 3.2 × 2.5 × 2.5 2000 71

Coilcraft XFL4020-102ME 4.0 × 4.0 × 2.1 5400 11

Coilcraft XPL2010-102ML 1.9 × 2.0 × 1.0 1800 89

Toko MDT2520-CN 2.5 × 2.0 × 1.2 1350 85

Inductor conduction losses are caused by the flow of current

through the inductor, which has an associated internal dc

resistance (DCR). Larger sized inductors have smaller DCR,

which may decrease inductor conduction losses. Inductor core

losses are related to the magnetic permeability of the core material.

Because the buck is high switching frequency dc-to-dc converter,

shielded ferrite core material is recommended for its low core

losses and low EMI.

Output Capacitor

Higher output capacitor values reduce the output voltage ripple

and improve load transient response. When choosing the

capacitor value, it is also important to account for the loss of

capacitance due to output voltage dc bias.

Ceramic capacitors are manufactured with a variety of dielec-

trics, each with a different behavior over temperature and

applied voltage. Capacitors must have a dielectric adequate

to ensure the minimum capacitance over the necessary

temperature range and dc bias conditions. X5R or X7R

dielectrics with a voltage rating of 6.3 V or 10 V are highly

recommended for best performance. Y5V and Z5U dielectrics

are not recommended for use with any dc-to-dc converter

because of their poor temperature and dc bias characteristics.

The worst-case capacitance accounting for capacitor variation

over temperature, component tolerance, and voltage is calcu-

lated using the following equation:

CEFF = COUT × (1 − TEMPCO) × (1 − TOL)

where:

CEFF is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

COUT is 9.2481 μF at 1.8 V, as shown in Figure 105.

Substituting these values in the equation yields

CEFF = 9.24 μF × (1 − 0.15) × (1 − 0.1) = 7.07 μF

To guarantee the performance of the buck, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

0123456

DC BIAS VOLTAGE (V)

CAPACI TANCE (µF)

09665-097

Figure 105. Typical Capacitor Performance

The peak-to-peak output voltage ripple for the selected output

capacitor and inductor values is calculated using the following

equation:

( )

OUTSW

RIPPLE

RIPPLE CLf

CfI

V×××

××

≈

ADP5040 Data Sheet

Rev. A | Page 30 of 40

Capacitors with lower equivalent series resistance (ESR) are

preferred to guarantee low output voltage ripple, as shown in

the following equation:

RIPPLE

COUT I

ESR ≤

The effective capacitance needed for stability, which includes

temperature and dc bias effects, is a minimum of 7 µF and a

maximum of 40 µF.

Table 9. Suggested 10 μF Capacitors

Vendor Type Model

Case

Size

Voltage

Rating

(V)

Murata X5R GRM188R60J106 0603 6.3

Taiyo Yuden X5R JMK107BJ106MA-T 0603 6.3

TDK X5R C1608JB0J106K 0603 6.3

Panasonic X5R ECJ1VB0J106M 0603 6.3

The buck regulator requires 10 µF output capacitors to guaran-

tee stability and response to rapid load variations and to transition

in and out the PWM/PSM modes. In certain applications, where

the buck regulator powers a processor, the operating state is

known because it is controlled by software. In this condition,

the processor can drive the MODE pin according to the operating

state; consequently, it is possible to reduce the output capacitor

from 10 µF to 4.7 µF because the regulator does not expect a

large load variation when working in PSM mode (see Figure 106).

VIN1

VIN2

VIN3

VOUT1

VOUT2

PGND

VOUT3

10µF

1µF

PROCESSOR

VCORE

VDDIO

MODE GPIO1

ENx GPIO[x:y]

FB3

VANALOG

FB1

FB2 C5

2.2µF

4.7µF

2.2µF

09665-098

ADP5040

MICRO PMU

2.3V TO 5.5V

1µH

AVIN

ANALOG

SUBSYSTEM

Figure 106. Processor System Power Management with PSM/PWM Control

Input Capacitor

A higher value input capacitor helps to reduce the input voltage

ripple and improve transient response. Maximum input

capacitor current is calculated using the following equation:

OUT

MAXLOAD

CIN V

VVV

II )(

)(

−

≥

To minimize supply noise, place the input capacitor as close

to the VIN pin of the buck as possible. As with the output

capacitor, a low ESR capacitor is recommended.

The effective capacitance needed for stability, which includes

temperature and dc bias effects, is a minimum of 3 µF and a

maximum of 10 µF. A list of suggested capacitors is shown in

Table 10.

Table 10. Suggested 4.7 μF Capacitors

Vendor Type Model

Case

Size

Voltage

Rating

(V)

Murata X5R GRM188R60J475ME19D 0603 6.3

Taiyo Yuden X5R JMK107BJ475 0603 6.3

Panasonic X5R ECJ-0EB0J475M 0402 6.3

LDO EXTERNAL COMPONENT SELECTION

Feedback Resistors

Referring to Figure 103 the maximum value of Rb is not to

exceed 200 kΩ.

Output Capacitor

The ADP5040 LDOs are designed for operation with small,

space-saving ceramic capacitors, but they function with most

commonly used capacitors as long as care is taken with the ESR

value. The ESR of the output capacitor affects stability of the

LDO control loop. A minimum of 0.70 µF capacitance with an

ESR of 1 Ω or less is recommended to ensure stability of the

LDO. Transient response to changes in load current is also

affected by output capacitance. Using a larger value of output

capacitance improves the transient response of the LDO to large

changes in load current.

When operating at output currents higher than 200 mA a

minimum of 2.2 µF capacitance with an ESR of 1 Ω or less is

recommended to ensure stability of the LDO.

Table 11. Suggested 2.2 μF Capacitors

Vendor Type Model

Case

Size

Voltage

Rating

(V)

Murata X5R GRM188B31A225K 0402 10.0

TDK X5R C1608JB0J225KT 0402 6.3

Panasonic X5R ECJ1VB0J225K 0402 6.3

Taiyo Yuden X5R JMK107BJ225KK-T 0402 6.3

Input Bypass Capacitor

Connecting 1 µF capacitors from VIN2 and VIN3 to ground

reduces the circuit sensitivity to printed circuit board (PCB)

layout, especially when long input traces or high source impedance

is encountered. If greater than 1 µF of output capacitance is

required, increase the input capacitor to match it.

Data Sheet ADP5040

Rev. A | Page 31 of 40

Table 12. Suggested 1.0 μF Capacitors

Vendor Type Model

Case

Size

Voltage

Rating

(V)

Murata X5R GRM155R61A105ME15 0402 10.0

TDK X5R C1005JB0J105KT 0402 6.3

Panasonic X5R ECJ0EB0J105K 0402 6.3

Taiyo Yuden X5R LMK105BJ105MV-F 0402 10.0

Input and Output Capacitor Properties

Use any good quality ceramic capacitor with the ADP5040 as

long as it meets the minimum capacitance and maximum ESR

requirements. Ceramic capacitors are manufactured with a variety

of dielectrics, each with a different behavior over temperature

and applied voltage. Capacitors must have a dielectric adequate

to ensure the minimum capacitance over the necessary tempe-

rature range and dc bias conditions. X5R or X7R dielectrics

with a voltage rating of 6.3 V or 10 V are recommended for best

performance. Y5V and Z5U dielectrics are not recommended

for use with any LDO because of their poor temperature and dc

bias characteristics.

Figure 107 depicts the capacitance vs. voltage bias characteristic

of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or higher voltage

rating exhibits better stability. The temperature variation of the

X5R dielectric is about ±15% over the −40°C to +85°C tempera-

ture range and is not a function of package or voltage rating.

1.2

1.0

0.8

0.6

0.4

0.2

00 1 2 3 4 5 6

DC BIAS VOLTAGE (V)

CAPACI TANCE (µF)

09665-099

Figure 107. Capacitance vs. Voltage Characteristic

Use the following equation to determine the worst-case capa-

citance accounting for capacitor variation over temperature,

component tolerance, and voltage.

CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)

where:

CBIAS is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient

(TEMPCO) over −40°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

to be 10%, and CBIAS is 0.94 μF at 1.8 V as shown in Figure 107.

Substituting these values into the following equation yields:

CEFF = 0.94 μF × (1 – 0.15) × (1 – 0.1) = 0.72 μF

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over

temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADP5040, it is imperative

that the effects of dc bias, temperature, and tolerances on the

behavior of the capacitors be evaluated for each application.

POWER DISSIPATION/THERMAL CONSIDERATIONS

The ADP5040 is a highly efficient micropower management

unit (micro PMU), and in most cases the power dissipated in

the device is not a concern. However, if the device operates at

high ambient temperatures and with maximum loading

conditions, the junction temperature can reach the maximum

allowable operating limit (125°C).

When the junction temperature exceeds 150°C, the ADP5040

turns off all the regulators, allowing the device to cool down.

Once the die temperature falls below 135°C, the ADP5040

resumes normal operation.

This section provides guidelines to calculate the power dissi-

pated in the device and to make sure the ADP5040 operates

below the maximum allowable junction temperature.

The efficiency for each regulator on the ADP5040 is given by

100%×=η

OUT

(1)

where:

η is efficiency.

PIN is the input power.

POUT is the output power.

Power loss is given by

PLOSS = PIN − POUT (2a)

PLOSS = POUT × (1 − η)/η (2b)

Power dissipation can be calculated in several ways. The most

intuitive and practical way is to measure the power dissipated at

the input and all the outputs. The measurements should be

performed at the worst-case conditions (voltages, currents,

and temperature). The difference between input and output

power is dissipated in the device and the inductor. Use

Equation 4 to derive the power lost in the inductor, and from

this use Equation 3 to calculate the power dissipation in the

ADP5040 buck regulator.

A second method to estimate the power dissipation uses the

efficiency curves provided for the buck regulator, whereas the

power lost on a LDO is calculated using Equation 12. When the

buck efficiency is known, use Equation 2b to derive the total

power lost in the buck regulator and inductor. Use Equation 4

ADP5040 Data Sheet

Rev. A | Page 32 of 40

to derive the power lost in the inductor, and then calculate the

power dissipation in the buck converter using Equation 3. Add

the power dissipated in the buck and in the LDOs to find the

total dissipated power.

Note that the buck efficiency curves are typical values and may

not be provided for all possible combinations of VIN, VOUT, and

IOUT. To account for these variations, it is necessary to include a

safety margin when calculating the power dissipated in the buck.

A third way to estimate the power dissipation is analytical and

involves modeling the losses in the buck circuit provided by

Equation 8 to Equation 11 and the losses in the LDOs provided

by Equation 12.

Buck Regulator Power Dissipation

The power loss of the buck regulator is approximated by

PLOSS = PDBUCK + PL (3)

where:

PDBUCK is the power dissipation on the ADP5040 buck regulator.

PL is the inductor power losses.

The inductor losses are external to the device and they do not

have any effect on the die temperature.

The inductor losses are estimated (without core losses) by

RMS

OUT1

LDCRI

P×≅ 2

)(

(4)

where:

DCRL is the inductor series resistance.

IOUT1(RMS) is the rms load current of the buck regulator.

/12+

)( rII OUT1

RMS

OUT1 ×=

(5)

where r is the normalized inductor ripple current.

R ≈ VOUT1 × (1 − D)/(IOUT1 × L × fSW) (6)

where:

L is inductance.

FSW is switching frequency.

D is duty cycle.

D = VOUT1/VIN1 (7)

The ADP5040 buck regulator power dissipation, PDBUCK,

includes the power switch conductive losses, the switch losses,

and the transition losses of each channel. There are other

sources of loss, but these are generally less significant at high

output load currents, where the thermal limit of the application

is. Equation 8 shows the calculation made to estimate the power

dissipation in the buck regulator.

PDBUCK = PCOND + PSW + PTRAN (8)

The power switch conductive losses are due to the output current,

IOUT1, flowing through the PMOSFET and the NMOSFET power

switches that have internal resistance, RDSON-P and RDSON-N. The

amount of conductive power loss is found by:

PCOND = [RDSON-P × D + RDSON-N × (1 – D)] × IOUT12 (9)

For the ADP5040, at 125°C junction temperature and VIN1 =

3.6 V, R DSON-P is approximately 0.2 Ω, and RDSON-N is approximately

0.16 Ω. At VIN1 = 2.3 V, these values change to 0.31 Ω and 0.21 Ω,

respectively, and at VIN1 = 5.5 V, the values are 0.16 Ω and

0.14 Ω, respectively.

Switching losses are associated with the current drawn by the

driver to turn on and turn off the power devices at the switching

frequency. The amount of switching power loss is given by:

PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10)

where:

CGATE-P is the PMOSFET gate capacitance.

CGATE-N is the NMOSFET gate capacitance.

For the ADP5040, the total of (CGATE-P + CGAT E-N) is approximately

150 pF.

The transition losses occur because the PMOSFET cannot be

turned on or off instantaneously, and the SW node takes some

time to slew from near ground to near VOUT1 (and from VOUT1 to

ground). The amount of transition loss is calculated by:

PTRAN = VIN1 × IOUT1 × (tRISE + tFALL) × fSW (11)

where tRISE and tFALL are the rise time and the fall time of the

switching n o d e , S W. For the ADP5040, the rise and fall times of

SW are in the order of 5 ns.

If the preceding equations and parameters are used for

estimating the converter efficiency, note that the equations do

not describe all of the converter losses, and the parameter

values given are typical numbers. The converter performance

also depends on the choice of passive components and board

layout; therefore, a sufficient safety margin should be included

in the estimate.

LDO Regulator Power Dissipation

The power loss of a LDO regulator is given by:

PDLDO = [(VIN – VOUT) × ILOAD] + (VIN × IGND) (12)

where:

ILOAD is the load current of the LDO regulator.

VIN and VOUT are input and output voltages of the LDO,

respectively.

IGND is the ground current of the LDO regulator.

Power dissipation due to the ground current is small and it

can be ignored.

The total power dissipation in the ADP5040 simplifies to:

PD = {[PDBUCK + PDLDO1 + PDLDO2]} (13)

Data Sheet ADP5040

Rev. A | Page 33 of 40

Junction Temperature

In cases where the board temperature, TA, is known, the

thermal resistance parameter, θJA, can be used to estimate the

junction temperature rise. TJ is calculated from TA and PD using

the formula

TJ = TA + (PD × θJA) (14)

The typical θJA value for the 20-lead, 4 mm × 4 mm LFCSP is

38°C/W (see Table 6). A very important factor to consider is

that θJA is based on a 4-layer, 4 inch × 3 inch, 2.5 oz copper, as

per JEDEC standard, and real applications may use different

sizes and layers. To remove heat from the device, it is important

to maximize the use of copper. Copper exposed to air dissipates

heat better than copper used in the inner layers. The exposed

pad (EP) should be connected to the ground plane with several

vias as shown in Figure 109.

If the case temperature can be measured, the junction temperature

is calculated by

TJ = TC + (PD × θJC) (15)

where:

TC is the case temperature.

θJC is the junction-to-case thermal resistance provided in Table 6.

When designing an application for a particular ambient

temperature range, calculate the expected ADP5040 power

dissipation (PD) due to the losses of all channels by using

Equation 8 to Equation 13. From this power calculation, the

junction temperature, TJ, can be estimated using Equation 14.

The reliable operation of the buck regulator and the LDO

regulator can be achieved only if the estimated die junction

temperature of the ADP5040 (Equation 14) is less than 125°C.

Reliability and mean time between failures (MTBF) is highly

affected by increasing the junction temperature. Additional

information about product reliability can be found in the

Analog Devices, Inc., Reliability Handbook, which is available

at http://www.analog.com/reliability_handbook.

APPLICATION DIAGRAM

OFF

FPWM

PWM/PSM

PGND

MODE

10µF

1µH

VIN1

EN3

EN1

VIN2

VIN3

EN2

AGND

VOUT2

VOUT1

FB3

VOUT3

4.7µF

1µF

EN_BK

BUCK

EN_LDO1

LDO1

(DIGITAL)

EN_LDO2

LDO2

(ANALOG)

OFF

FB2

FB1

2.2µF

OUT1

1.2A

2.2µF

IN1

= 2.3V

TO 5.5V

IN2

= 1.7V

TO 5.5V

IN3

= 1.7V

TO 5.5V

OUT2

300mA

OUT3

300mA

09665-103

AVIN

Figure 108. Application Diagram

ADP5040 Data Sheet

Rev. A | Page 34 of 40

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5040 performance, causing electro-

magnetic interference (EMI) and electromagnetic compatibility

(EMC) problems, ground bounce, and voltage losses. Poor

layout can also affect regulation and stability. A good layout is

implemented using the following guidelines:

• Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies, and large tracks act as antennas.

• Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

• Maximize the size of ground metal on the component side

to help with thermal dissipation.

• Use a ground plane with several vias connecting to the

component side ground to further reduce noise interference

on sensitive circuit nodes.

SUGGESTED LAYOUT

See Figure 109 for an example layout.

GPL

AGND

GPL

VOUT3

VOUT1

VOUT2

PPL PPL

PPL

Pin1

GPL GPL

GPL

PPL

TOP L AYER

09665-102

VIAS LEGEND:

PPL = POWER PLANE (+4V)

GP L = G ROUND PLANE

2ND LAY E R

MODE

L1 – 1µH

0603

C5 – 4.7µF

10V/XR5 0603

C6 – 10µF

6.3V/XR5

0603

1.0

2.0

3.0

4.0

5.0

6.0

6.5

6.5 7.0

0.5

1.5

2.5

3.5

4.5

5.5

C3 – 1µF

10V/XR5

0402

C4– 2.2µ F

6.3V/XR5

0402

EN3

VIN3

VOUT3

FB3

VOUT1

FB1

VIN2

VOUT2

FB2

C2 – 1µF

10V/XR5

0402

C5 – 2.2µF

6.3V/XR5

0402

AVIN

VIN

PGND

EN1

ADP5040

Figure 109. Evaluation Board Layout

Data Sheet ADP5040

Rev. A | Page 35 of 40

BILL OF MATERIALS

Table 13.

Reference Value Part Number Vendor Package

4.7 µF, X5R, 6.3 V

JMK107BJ475

Taiyo-Yuden

0603

C2, C3 1 µF, X5R, 6.3 V LMK105BJ105MV-F Taiyo-Yuden 0402

C4 10 µF, X5R, 6.3 V JMK107BJ106MA-T Taiyo-Yuden 0603

C5, C6 2.2 µF, X5R, 6.3 V JMK105BJ225MV-F Taiyo-Yuden 0402

L1 1 µH, 85 mΩ, 1400 mA LQM2MPN1R0NG0B Murata 2.0 × 1.6 × 0.9 (mm)

1 µH, 85 mΩ, 1350 mA MDT2520-CN Toko 2.5 × 2.0 × 1.2 (mm)

1 µH, 89 mΩ, 1800 mA XPL2010-1102ML Coilcraft 1.9 × 2.0 × 1.0 (mm)

IC1 3-regulator micro PMU ADP5040 Analog Devices 20-Lead LFCSP

ADP5040 Data Sheet

Rev. A | Page 36 of 40

FACTORY PROGRAMMABLE OPTIONS

Table 14. Regulator Output Discharge Resistor Options

Selection

0 All discharge resistors disabled

1 All discharge resistors enabled

Table 15. Under Voltage Lockout options

Selection Min Typ Max Unit

1.95

2.15

2.275

1 3.10 3.65 3.90 V

Data Sheet ADP5040

Rev. A | Page 37 of 40

OUTLINE DIMENSIONS

0.50

BSC

0.50

0.40

0.30

0.25

0.20

COMPLIANT

JEDEC STANDARDS MO-220-WGGD.

061609-B

BOTTOM VIEWTOP VIEW

EXPOSED

PAD

PIN1

INDICATOR

4.10

4.00 SQ

3.90

SEATING

PLANE

0.80

0.75

0.70 0.05 MAX

0.02 NOM

0.20 REF

0.25 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

2.65

2.50 SQ

2.35

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

1516

Figure 110. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 UVLO Active Pull-Down Temperature Range Package Description

Package

Option

ADP5040ACPZ-1-R7 2.15 V Enabled on all channels TJ = −40°C to +125°C 20-Lead LFCSP_WQ CP-20-10

ADP5040CP-1-EVALZ Evaluation Board

1 Z = RoHS Compliant Part.

ADP5040 Data Sheet

Rev. A | Page 38 of 40

NOTES

Data Sheet ADP5040

Rev. A | Page 39 of 40

NOTES

ADP5040 Data Sheet

Rev. A | Page 40 of 40

NOTES

registered trademarks are the property of their respective owners.

D09665-0-1/14(A)

Mouser Electronics

Authorized Distributor

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