Micro PMU with 1.2 A Buck Regulator and Two 300 mA LDOs ADP5040 Data Sheet FEATURES GENERAL DESCRIPTION Input voltage range: 2.3 V to 5.5 V One 1.2 A buck regulator Two 300 mA LDOs 20-lead, 4 mm x 4 mm LFCSP package Overcurrent and thermal protection Soft start Undervoltage lockout Buck key specifications Output voltage range: 0.8 V to 3.8 V Current mode topology for excellent transient response 3 MHz operating frequency Peak efficiency up to 96% Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PWM/PSM modes 100% duty cycle low dropout mode LDOs key specifications Output voltage range: 0.8 V to 5.2 V Low VIN from 1.7 V to 5.5 V Stable with 2.2 F ceramic output capacitors High PSRR Low output noise Low dropout voltage -40C to +125C junction temperature range The ADP5040 combines one high performance buck regulator and two low dropout regulators (LDO) in a small 20-lead LFCSP to meet demanding performance and board space requirements. The high switching frequency of the buck regulator enables the use of tiny multilayer external components and minimizes board space. When the MODE pin is set to logic high, the buck regulator operates in forced pulse width modulation (PWM) mode. When the MODE pin is set to logic low, the buck regulator operates in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold the regulator operates in power save mode (PSM) improving the light-load efficiency. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5040 LDOs extend the battery life of portable devices. The ADP5040 LDOs maintain a power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Each regulator in the ADP5040 is activated by a high level on the respective enable pin. The output voltages of the regulators are programmed though external resistor dividers to address a variety of applications. FUNCTIONAL BLOCK DIAGRAM VOUT1 L1 1H AVIN SW AVIN C6 10F EN_BK ON MODE EN1 FPWM PSM/PWM C1 1F VOUT2 LDO1 (DIGITAL) VIN2 VOUT2 AT 300mA FB2 EN_LDO1 R4 ON R3 C2 2.2F EN2 OFF ON OFF VIN3 = 1.7V TO 5.5V R1 PGND C5 4.7F OFF VIN2 = 1.7V TO 5.5V R2 VIN1 EN3 VIN3 C3 1F EN_LDO2 VOUT3 LDO2 (ANALOG) FB3 R3 AGND VOUT3 AT 300mA R7 C4 2.2F 09665-001 VIN1 = 2.3V TO 5.5V VOUT1 AT 1.2A FB1 BUCK Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com ADP5040 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Management Unit........................................................... 25 General Description ......................................................................... 1 Buck Section................................................................................ 26 Functional Block Diagram .............................................................. 1 LDO Section ............................................................................... 27 Revision History ............................................................................... 2 Applications Information .............................................................. 29 Specifications..................................................................................... 3 Buck External Component Selection....................................... 29 General Specifications ................................................................. 3 LDO External Component Selection ...................................... 30 Buck Specifications....................................................................... 3 Power Dissipation/Thermal Considerations ............................. 31 LDO1, LDO2 Specifications ....................................................... 4 Application Diagram ................................................................. 33 Input and Output Capacitor, Recommended Specifications .. 5 PCB Layout Guidelines .................................................................. 34 Absolute Maximum Ratings............................................................ 6 Suggested Layout ........................................................................ 34 Thermal Resistance ...................................................................... 6 Bill of Materials ........................................................................... 35 ESD Caution .................................................................................. 6 Factory Programmable Options ................................................... 36 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 37 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 37 Theory of Operation ...................................................................... 25 REVISION HISTORY 1/14--Rev. 0 to Rev. A Change to Figure 1 ........................................................................... 1 Change to Figure 106 ..................................................................... 30 Change to Figure 108 ..................................................................... 33 Change to Figure 109 ..................................................................... 34 12/11--Revision 0: Initial Version Rev. A | Page 2 of 40 Data Sheet ADP5040 SPECIFICATIONS GENERAL SPECIFICATIONS AVIN, VIN1 = 2.3 V to 5.5 V; AVIN, VIN1 VIN2, VIN3; VIN2, VIN3 = 1.7 V to 5.5 V, TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 1. Parameter AVIN UNDERVOLTAGE LOCKOUT Input Voltage Rising Option 0 Option 1 Input Voltage Falling Option 0 Option 1 SHUTDOWN CURRENT Thermal Shutdown Threshold Thermal Shutdown Hysteresis START-UP TIME 1 BUCK LDO1, LDO2 Enx, MODE, INPUTS Input Logic High Input Logic Low Input Leakage Current 1 Symbol UVLOAVIN UVLOAVINRISE Description Min Typ Max Unit 2.275 3.9 V V 2 V V A C C UVLOAVINFALL 1.95 3.1 IGND-SD TSSD TSSD-HYS ENx = GND TJ rising tSTART1 tSTART2 VOUT2, VOUT3 = 3.3 V VIH VIL VI-LEAKAGE 2.5 V AVIN 5.5 V 2.5 V AVIN 5.5 V ENx = AVIN or GND 0.1 150 20 250 85 s s 1.2 0.05 0.4 1 V V A Start-up time is defined as the time from the moment EN1 = EN2 = EN3 transfers from 0 V to VAVIN to the moment VOUT1, VOUT2, and VOUT3 reach 90% of their nominal level. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information. BUCK SPECIFICATIONS AVIN, VIN1 = 2.3 V to 5.5 V; VOUT1 = 1.8 V; L = 1 H; CIN = 10 F; COUT = 10 F; TJ= -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. 1 Table 2. Parameter INPUT CHARACTERISTICS Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Accuracy Line Regulation Load Regulation VOLTAGE FEEDBACK PWM TO POWER SAVE MODE CURRENT THRESHOLD INPUT CURRENT CHARACTERISTICS DC Operating Current Shutdown Current Symbol Test Conditions/Comments VIN1 VOUT1 (VOUT1/VOUT1)/VIN1 (VOUT1/VOUT1)/IOUT1 VFB1 IPSM_L INOLOAD ISHTD PWM mode, ILOAD = 0 mA to 1200 mA PWM mode ILOAD = mA to 1200 mA, PWM mode Min Max Unit 2.3 5.5 V -3 +3 % 0.485 MODE = ground ILOAD = 0 mA, device not switching, all other channels disabled EN1 = 0 V, TA = TJ = -40C to +125C Rev. A | Page 3 of 40 Typ -0.05 -0.1 0.5 100 0.515 %/V %/A V mA 21 35 A 0.2 1.0 A ADP5040 Data Sheet Parameter SW CHARACTERISTICS SW On Resistance Symbol Test Conditions/Comments RPFET PFET, AVIN = VIN1 = 3.6 V PFET, AVIN = VIN1 = 5 V NFET, AVIN = VIN1 = 3.6 V NFET, AVIN = VIN1 = 5 V PFET switch peak current limit EN1 = 0 V RNFET Current Limit ACTIVE PULL-DOWN OSCILLATOR FREQUENCY 1 ILIMIT FOSC Min 1600 2.5 Typ Max Unit 180 140 170 150 1950 85 3.0 240 190 235 210 2300 m m m m mA MHz 3.5 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). LDO1, LDO2 SPECIFICATIONS VIN2, VIN3 = (VOUT2,VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; AVIN, VIN1 VIN2, VIN3; CIN = 1 F, COUT = 2.2 F; TJ= -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. 1 Table 3. Parameter Symbol Conditions Min INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT Bias Current per LDO 2 VIN2, VIN3 TJ = -40C to +125C 1.7 IVIN2BIAS /IVIN3BIAS IOUT3 = IOUT4 = 0 A Total System Input Current LDO1 or LDO2 Only LDO1 and LDO2 Only OUTPUT VOLTAGE ACCURACY IIN Max Unit 5.5 V IOUT2 = IOUT3 = 10 mA 10 60 30 100 A A IOUT2 = IOUT3 = 300 mA 165 245 A Includes all current into AVIN, VIN1, VIN2 and VIN3 IOUT2 = IOUT3 = 0 A, all other channels disabled IOUT2 = IOUT3 = 0 A, buck disabled 53 74 Load Regulation 3 DROPOUT VOLTAGE 4 ACTIVE PULL-DOWN CURRENT-LIMIT THRESHOLD 5 OUTPUT NOISE A A VOUT2, VOUT3 100 A < IOUT2 < 300 mA, 100 A < IOUT3 < 300 mA VIN2 = (VOUT2 + 0.5 V) to 5.5 V, VIN3 = (VOUT3 + 0.5 V) to 5.5 V REFERENCE VOLTAGE REGULATION Line Regulation Typ VFB2, VFB3 (VOUT2/VOUT2)/VIN2 (VOUT3/VOUT3)/VIN3 (VOUT2/VOUT2)/IOUT2 (VOUT3/VOUT3)/IOUT3 VDROPOUT RPDLDO ILIMIT OUTLDO2NOISE OUTLDO1NOISE -3 0.485 VIN2 = (VOUT2 + 0.5 V) to 5.5 V VIN3 = (VOUT3 + 0.5 V) to 5.5 V IOUT2 = IOUT3 = 1 mA IOUT2 = IOUT3 = 1 mA to 300 mA VOUT2 = VOUT3 = 5.0 V, IOUT2 = IOUT3 = 300 mA VOUT2 = VOUT3 = 3.3 V, IOUT2 = IOUT3 = 300 mA VOUT2 = VOUT3 = 2.5 V, IOUT2 = IOUT3 = 300 mA VOUT2 = VOUT3 = 1.8 V, IOUT2 = IOUT3 = 300 mA EN2/EN3 = 0 V TJ = -40C to +125C 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V Rev. A | Page 4 of 40 0.500 -0.03 0.002 335 72 86 107 180 600 470 123 110 59 140 129 66 +3 % 0.515 V +0.03 %/ V 0.0075 %/mA 140 mV mV mV mV mA V rms V rms V rms V rms V rms V rms Data Sheet ADP5040 Parameter Symbol Conditions POWER SUPPLY REJECTION RATIO PSRR 1 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 100 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA Min Typ Max Unit 66 dB 57 dB 60 dB All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). This is the input current into VIN2 and VIN3, which is not delivered to the output load. 3 Based on an end-point calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V. 1 2 INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS Table 4. Parameter INPUT CAPACITANCE (BUCK) 1 OUTPUT CAPACITANCE (BUCK) 2 INPUT AND OUTPUT CAPACITANCE 3 (LDO1, LDO2) CAPACITOR ESR Symbol CMIN1 CMIN2 CMIN34 RESR Conditions TJ = -40C to +125C TJ = -40C to +125C TJ = -40C to +125C TJ = -40C to +125C Min 4.7 7 0.70 0.001 Typ Max 40 40 1 Unit F F F The minimum input capacitance should be greater than 4.7 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas Y5V and Z5U capacitors are not recommended for use with the buck. 2 The minimum output capacitance should be greater than 7 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas Y5V and Z5U capacitors are not recommended for use with the buck. 3 The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, whereas Y5V and Z5U capacitors are not recommended for use with LDOs. 1 Rev. A | Page 5 of 40 ADP5040 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter AVIN to AGND VIN1 to AVIN PGND to AGND VIN2, VIN3, VOUTx, ENx, MODE, FBx, SW to AGND SW to PGND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions ESD Human Body Model ESD Charged Device Model ESD Machine Model Rating -0.3 V to +6 V -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to (AVIN + 0.3 V) -0.3 V to (VIN1 + 0.3 V) -65C to +150C -40C to +125C JEDEC J-STD-020 3000 V 1500 V 200 V JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type 20-Lead, 0.5 mm pitch LFCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 6 of 40 JA 38 JC 4.2 Unit C/W Data Sheet ADP5040 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP5040 20 19 18 17 16 NC NC NC MODE EN2 TOP VIEW (Not to Scale) 15 14 13 12 11 1 2 3 4 5 FB2 VOUT2 VIN2 FB1 VOUT1 NOTES 1. EXPOSED PAD MUST BE CONNECTED TO SYSTEM GROUND PLANE. 09665-002 AVIN 6 VIN1 7 SW 8 PGND 9 EN1 10 FB3 VOUT3 VIN3 EN3 NC Figure 2. Pin Configuration--View from Top of the Die Table 7. Preliminary Pin Function Descriptions Pin No. 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 17 Mnemonic FB3 VOUT3 VIN3 EN3 AVIN VIN1 SW PGND EN1 VOUT1 FB1 VIN2 VOUT2 FB2 EN2 MODE 5, 18, 19, 20 0 NC EPAD Description LDO2 Feedback Input. LDO2 Output Voltage. LDO2 Input Supply (1.7 V to 5.5 V). Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2. Housekeeping Input Supply (2.3 V to 5.5 V). Buck Input Supply (2.3 V to 5.5 V). Buck Switching Node. Dedicated Power Ground for Buck Regulator. Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck. Buck Output Sensing Node. Buck Feedback Input. LDO1 Input Supply (1.7 V to 5.5 V). LDO1 Output Voltage. LDO1 Feedback Input. Enable LDO1. EN2 = high: turn on LDO1; EN2 = low: turn off LDO1. Buck Mode. Mode = high: buck regulator operates in fixed PWM mode; mode = low: buck regulator operates in power save mode (PSM) at light load and in constant PWM at higher load. Not Connected. Exposed Pad. (AGND = Analog Ground). The exposed pad must be connected to the system ground plane. Rev. A | Page 7 of 40 ADP5040 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25C, unless otherwise noted. 4 SW VOUT1 2 VOUT1 2 VOUT2 3 EN VOUT3 1 3 A CH2 1.88V 200s/DIV 1.0MS/s 1.0s/pt CH1 CH2 CH3 CH4 09665-003 CH4 2.0V/DIV 1M BW 500M CH2 2.0V/DIV 1M BW 20.0M CH3 2.0V/DIV 1M BW 500M IIN Figure 3. 3-Channel Start-Up Waveforms 1M BW 20.0M 1M BW 500M 1M BW 20.0M 1M BW 500M A CH1 2.32V 50s/DIV 2.0MS/s 500ns/pt Figure 6. Buck Startup, VOUT1 = 3.3 V, IOUT2 = 20 mA VOUT3 4 4.0V/DIV 3.0V/DIV 200mA/DIV 5.0V/DIV 09665-006 4 SW 4 VOUT2 2 2 VOUT1 VOUT1 1 EN 1 2.0V/DIV 2.0V/DIV 300mA/DIV 2.0V/DIV 1M BW 20.0M 1M BW 20.0M 1M BW 20.0M 1M BW 20.0M A CH1 1.08V 200s/DIV 5.0MS/s 200ns/pt IIN CH1 CH2 CH3 CH4 09665-004 CH1 CH2 CH3 CH4 3 Figure 4. Total Inrush Current, All Channels Started Simultaneously 8.0V/DIV 2.0V/DIV 200mA/DIV 5.0V/DIV 1M BW 20.0M A CH1 1M BW 500.0M 1M BW 20.0M 1M BW 500.0M 1.12V 50s/DIV 2.0MS/s 500ns/pt 09665-007 IIN 3 Figure 7. Buck Startup, VOUT1 = 1.8 V, IOUT = 20 mA 1.0 0.9 SW 0.8 4 0.7 IIN (mA) 0.6 VOUT1 0.5 2 0.4 EN 0.3 1 0.2 2.9 3.4 3.9 VIN (V) 4.4 4.9 5.4 09665-005 0 2.4 3 IIN CH1 CH2 CH3 CH4 8.0V/DIV 2.0V/DIV 200mA/DIV 5.0V/DIV 1M BW 20.0M A CH1 1M BW 500.0M 1M BW 20.0M 1M BW 500.0M 640mV 50s/DIV 2.0MS/s 500ns/pt Figure 8. Buck Startup, VOUT1 = 1.2 V, IOUT = 20 mA Figure 5. System Quiescent Current (Sum of All the Input Currents) vs. Input Voltage VOUT1 = 1.8 V, VOUT2 = VOUT3 = 3.3 V (UVLO = 3.3 V) Rev. A | Page 8 of 40 09665-008 0.1 Data Sheet ADP5040 1.24 3.90 -40C +25C +85C 3.88 1.23 OUTPUT VOLTAGE (V) 3.84 3.82 3.80 3.78 3.76 3.74 0.1 1 OUTPUT CURRENT (A) 1.20 1.18 0.01 09665-009 3.70 0.01 1.21 1.19 -40C +25C +85C 3.72 1.22 0.1 1 OUTPUT CURRENT (A) 09665-012 OUTPUT VOLTAGE (V) 3.86 Figure 12. Buck Load Regulation Across Temperature, VOUT1 = 1.2 V, Auto Mode Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 3.8 V, Auto Mode 3.90 3.39 -40C +25C +85C 3.37 -40C +25C +85C 3.88 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 3.86 3.35 3.33 3.31 3.29 3.84 3.82 3.80 3.78 3.76 3.74 3.27 0.1 1 OUTPUT CURRENT (A) 3.70 0.01 09665-010 3.25 0.01 1 Figure 13. Buck Load Regulation Across Temperature, VOUT1 = 3.8 V, PWM Mode Figure 10. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode 3.32 1.820 -40C +25C +85C 1.815 -40C +25C +85C 3.31 OUTPUT VOLTAGE (V) 1.810 OUTPUT VOLTAGE (V) 0.1 OUTPUT CURRENT (A) 09665-013 3.72 1.805 1.800 1.795 3.30 3.29 3.28 3.27 1.790 0.1 1 OUTPUT CURRENT (A) Figure 11. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, Auto Mode 3.25 0.01 09665-011 1.780 0.01 0.1 1 OUTPUT CURRENT (A) Figure 14. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, PWM Mode Rev. A | Page 9 of 40 09665-014 3.26 1.785 ADP5040 Data Sheet 1.820 100 -40C +25C +85C 1.815 90 VIN = 4.5V 80 VIN = 5.5V 70 EFFICIENCY (%) OUTPUT VOLTAGE (V) 1.810 1.805 1.800 1.795 60 50 40 30 1.790 20 1.785 0.1 0 0.001 09665-015 1.780 0.01 1 OUTPUT CURRENT (A) 0.1 1 OUTPUT CURRENT (A) Figure 15. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode Figure 18. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.8 V, PWM Mode 1.205 100 -40C +25C +85C 90 80 1.200 VIN = 3.6V VIN = 4.5V VIN = 5.5V 70 EFFICIENCY (%) OUTPUT VOLTAGE (V) 0.01 09665-018 10 1.195 1.190 60 50 40 30 1.185 20 0 0.0001 09665-016 0.1 1 OUTPUT CURRENT (A) 1 100 90 90 VIN = 3.6 VIN = 4.5 VIN = 4.5V 80 VIN = 5.5V VIN = 5.5 70 EFFICIENCY (%) 70 50 40 60 50 40 30 30 20 20 10 10 0.001 0.01 0.1 1 OUTPUT CURRENT (A) Figure 17. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.8 V, Auto Mode 0 0.001 0.01 0.1 1 OUTPUT CURRENT (A) Figure 20. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, PWM Mode Rev. A | Page 10 of 40 09665-020 60 09665-017 EFFICIENCY (%) 0.1 Figure 19. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, Auto Mode 100 0 0.0001 0.01 OUTPUT CURRENT (A) Figure 16. Buck Load Regulation Across Temperature, VOUT1 = 1.2 V, PWM Mode 80 0.001 09665-019 10 1.180 0.01 ADP5040 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 60 50 40 30 30 10 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 10 0 0.001 100 100 90 90 80 80 70 70 EFFICIENCY (%) EFFICIENCY (%) 1 Figure 24. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.2 V, PWM Mode 60 50 40 60 50 40 30 30 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 10 0 0.001 0.01 0.1 20 1 OUTPUT CURRENT (A) -40C +25C +85C 10 0 0.0001 09665-022 20 0.001 0.01 0.1 1 OUTPUT CURRENT (A) Figure 22. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.8 V, PWM Mode Figure 25. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 3.3 V, Auto Mode 100 90 90 80 80 70 70 EFFICIENCY (%) 100 60 50 40 60 50 40 30 30 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 20 10 0.001 0.01 0.1 1 OUTPUT CURRENT (A) Figure 23. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.2 V, Auto Mode 20 -40C +25C +85C 10 0 0.001 09665-023 EFFICIENCY (%) 0.1 OUTPUT CURRENT (A) Figure 21. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.8 V, Auto Mode 0 0.0001 0.01 09665-025 0 0.0001 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 20 09665-021 20 09665-024 VIN = 2.4V VIN = 3.6V VIN = 4.5V VIN = 5.5V 0.01 0.1 1 OUTPUT CURRENT (A) Figure 26. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 3.3 V, PWM Mode Rev. A | Page 11 of 40 09665-026 EFFICIENCY (%) Data Sheet Data Sheet 100 100 90 90 80 80 70 70 EFFICIENCY (%) 60 50 40 60 50 40 30 30 20 20 -40C +25C +85C 0 0.0001 0.001 0.01 0.1 1 OUTPUT CURRENT (A) -40C +25C +85C 10 0 0.001 09665-027 10 0.01 0.1 09665-030 EFFICIENCY (%) ADP5040 1 OUTPUT CURRENT (A) Figure 27. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.8 V, Auto Mode Figure 30. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.2 V, PWM Mode 100 2.5 90 OUTPUT CURRENT (A) 60 50 40 30 1.0 0.5 20 0.01 0.1 0 3.4 09665-028 0 0.001 1 OUTPUT CURRENT (A) 3.9 4.4 4.9 5.4 VIN (V) Figure 28. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.8 V, PWM Mode 09665-031 -40C +25C +85C 10 Figure 31. Buck DC Current Capability vs. Input Voltage 2.0 90 1.8 80 1.6 OUTPUT CURRENT (A) 100 70 60 50 40 30 VOUT = 1.8V 1.4 1.2 1.0 0.8 0.6 0.4 20 -40C +25C +85C 10 0.001 0.01 0.1 1 OUTPUT CURRENT (A) 0.2 0 2.4 09665-029 EFFICIENCY (%) 1.5 2.9 3.4 3.9 4.4 4.9 VIN (V) Figure 29. Buck Efficiency vs. Load Current, Across Temperature, VIN = 5.0 V, VOUT1 = 1.2 V, Auto Mode Figure 32. Buck DC Current Capability vs. Input Voltage Rev. A | Page 12 of 40 5.4 09665-032 EFFICIENCY (%) 70 0 0.0001 VOUT = 3.3V 2.0 80 Data Sheet ADP5040 2.0 VOUT VOUT = 1.2V 1.8 1.6 4 OUTPUT CURRENT (A) 1.4 1.2 ISW 2 1.0 0.8 0.6 SW 0.4 0.2 3.4 3.9 4.4 4.9 CH2 200mA/DIV 1M BW 20.0M CH3 3.0V/DIV 1M BW 20.0M 20.0M CH4 40.0mV/DIV 09665-033 2.9 5.4 VIN (V) Figure 33. Buck DC Current Capability vs. Input Voltage A CH1 640mV 5s/DIV 500MS/s 2.0ns/pt 09665-036 3 0 2.4 Figure 36. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, Auto Mode 2.94 VOUT 2.92 ISW 2.88 2 2.86 2.84 SW -40C +25C +85C 2.80 0 0.2 0.4 0.6 0.8 1.0 3 1.2 OUTPUT CURRENT (A) 09665-034 2.82 Figure 34. Buck Switching Frequency vs. Output Current, Across Temperature, VOUT1 = 1.8 V, PWM Mode 4 CH2 200mA/DIV 1M BW 20.0M CH3 3.0V/DIV 1M BW 20.0M 20.0M CH4 40.0mV/DIV A CH3 1.14V 5s/DIV 500MS/s 2.0ns/pt 09665-037 FREQUENCY (MHz) 4 2.90 Figure 37. Typical Waveforms, VOUT1 = 1.2 V, IOUT1 = 30 mA, Auto Mode VOUT VOUT 4 ISW ISW 2 2 SW SW 3 A CH1 640mV 5s/DIV 500MS/s 2.0ns/pt CH2 200mA/DIV 1M BW 20.0M CH3 3.0V/DIV 1M BW 20.0M 20.0M CH4 10.0mV/DIV 09665-035 CH2 200mA/DIV 1M BW 20.0M CH3 3.0V/DIV 1M BW 20.0M 20.0M CH4 40.0mV/DIV Figure 35. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode A CH1 640mV 200ns/DIV 500MS/s 2.0ns/pt 09665-038 3 Figure 38. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode Rev. A | Page 13 of 40 ADP5040 Data Sheet VOUT 4 VIN VOUT ISW 2 2 3 SW SW 1 A CH1 640mV 200ns/DIV 500MS/s 2.0ns/pt B 400M CH1 3.0V/DIV W B 20.0M CH2 30.0mV/DIV W B 1M W 20.0M CH3 1.0V/DIV 09665-039 CH2 200mA/DIV 1M BW 20.0M CH3 3.0V/DIV 1M BW 20.0M 20.0M CH4 20.0mV/DIV Figure 39. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode A CH3 4.48V 200s/DIV 1.0MS/s 1.0s/pt 09665-042 3 Figure 42. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.8 V, IOUT1 = 5 mA, Auto Mode VOUT VIN 4 VOUT ISW 2 2 SW 3 SW 1 A CH3 1.14V 200ns/DIV 500MS/s 2.0ns/pt B 400M CH1 3.0V/DIV W B 20.0M CH2 50.0mV/DIV W 1M BW 20.0M CH3 1.0V/DIV 09665-040 CH2 200mA/DIV 1M BW 20.0M CH3 3.0V/DIV 1M BW 20.0M 20.0M CH4 40.0mV/DIV Figure 40. Typical Waveforms, VOUT1 = 1.2 V, IOUT1 = 30 mA, PWM Mode A CH3 4.48V 200s/DIV 1.0MS/s 1.0s/pt 09665-043 3 Figure 43. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.2 V, IOUT1 = 5 mA, Auto Mode VIN VIN VOUT VOUT 2 2 3 3 SW SW 1 A CH3 4.48V 200s/DIV 1.0MS/s 1.0s/pt 09665-041 B 400M CH1 3.0V/DIV W B 20.0M CH2 50.0mV/DIV W B 1M W 20.0M CH3 1.0V/DIV B 400M CH1 3.0V/DIV W B 20.0M CH2 50.0mV/DIV W 1M BW 20.0M CH3 1.0V/DIV Figure 41. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 3.3 V, IOUT1 = 5 mA, Auto Mode A CH3 4.48V 200s/DIV 1.0MS/s 1.0s/pt 09665-044 1 Figure 44. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 3.3 V, PWM Mode Rev. A | Page 14 of 40 Data Sheet ADP5040 SW VIN 1 VOUT VOUT 2 3 2 SW IOUT 1 A CH3 4.48V 200s/DIV 1.0MS/s 1.0s/pt 1M BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1M BW 20.0M 09665-045 B 400M CH1 3.0V/DIV W B 20.0M CH2 20.0mV/DIV W B 1M W 20.0M CH3 1.0V/DIV Figure 45. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.8 V, PWM Mode A CH3 150mA 500s/DIV 20.0MS/s 50.0ns/pt 09665-048 3 Figure 48. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 3.3 V, Auto Mode SW VIN 1 VOUT VOUT 2 3 2 SW 1 IOUT A CH3 4.48V 200s/DIV 1.0MS/s 1.0s/pt 1M BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1M BW 20.0M 09665-046 B 20.0M CH1 3.0V/DIV W B 20.0M CH2 50.0mV/DIV W B 1M W 20.0M CH3 1.0V/DIV Figure 46. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 1.2 V, PWM Mode A CH3 150mA 500s/DIV 20.0MS/s 50.0ns/pt 09665-049 3 Figure 49. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.8 V, Auto Mode SW SW 1 1 VOUT VOUT 2 2 IOUT IOUT 3 A CH3 150mA 500s/DIV 20.0MS/s 50.0ns/pt 1M BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1M BW 20.0M 09665-047 1M BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1M BW 20.0M Figure 47. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 3.3 V, Auto Mode A CH3 150mA 500s/DIV 20.0MS/s 50.0ns/pt 09665-050 3 Figure 50. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 1.8 V, Auto Mode Rev. A | Page 15 of 40 ADP5040 Data Sheet SW SW 1 1 VOUT VOUT 2 2 IOUT IOUT A CH3 94.0mA 200s/DIV 500kS/s 2.0s/pt 1M BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 300mA/DIV 1M BW 20.0M 09665-051 1M BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 100mA/DIV 1M BW 120M Figure 51. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.2 V, Auto Mode A CH3 150mA 500s/DIV 20.0MS/s 50.0ns/pt 09665-054 3 3 Figure 54. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 3.3 V, PWM Mode SW SW 1 1 VOUT VOUT 2 2 IOUT IOUT 3 A CH3 92.0mA 200s/DIV 500kS/s 2.0s/pt 1M BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 300mA/DIV 1M BW 20.0M 09665-052 B 20.0M CH1 4.0V/DIV W B 20.0M CH2 50.0mV/DIV W B CH3 200mA/DIV 1M W 120M Figure 52. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 1.2 V, Auto Mode A CH3 150mA 500s/DIV 20.0MS/s 50.0ns/pt 09665-055 3 Figure 55. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.8 V, PWM Mode SW SW 1 1 VOUT VOUT 2 2 IOUT IOUT A CH3 150mA 500s/DIV 20.0MS/s 50.0ns/pt 1M BW 20.0M CH1 4.0V/DIV B 20.0M CH2 100mV/DIV W CH3 300mA/DIV 1M BW 20.0M 09665-053 1M BW 20.0M CH1 4.0V/DIV B 20.0M CH2 50.0mV/DIV W CH3 300mA/DIV 1M BW 20.0M Figure 53. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 3.3 V, PWM Mode A CH3 150mA 500s/DIV 20.0MS/s 50.0ns/pt 09665-056 3 3 Figure 56. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 1.8 V, PWM Mode Rev. A | Page 16 of 40 Data Sheet ADP5040 1 SW IIN VOUT 2 VOUT IOUT 94.0mA 200s/DIV 500kS/s 2.0ns/pt CH1 2.0V/DIV CH2 2.0V/DIV CH3 200mA/DIV 09665-057 B 20.0M A CH3 CH1 4.0V/DIV W B 20.0M CH2 50.0mV/DIV W B CH3 100mA/DIV 1M W 120.0M Figure 57. Buck Response to Load Transient, IOUT1 = 20 mA to 200 mA, VOUT1 = 1.2 V, PWM Mode 1 1.72V 50.0s/DIV 200MS/s 5.0ns/pt Figure 60. LDO1, LDO2 Startup, VOUT = 3.3 V, IOUT = 5 mA 3 SW 1M BW 20.0M A CH1 1M BW 20.0M B 20.0M W 09665-060 EN 3 IIN VOUT 2 2 VOUT EN IOUT 1 92.0mA 200s/DIV 500kS/s 2.0ns/pt CH1 2.0V/DIV CH2 1.0V/DIV CH3 200mA/DIV 09665-058 20.0M A CH3 CH1 4.0V/DIV CH2 50.0mV/DIV 20.0M CH3 200mA/DIV 1M BW 20.0M Figure 58. Buck Response to Load Transient, IOUT1 = 50 mA to 500 mA, VOUT1 = 1.2 V, PWM Mode 50.0s/DIV 200MS/s 5.0ns/pt IIN VOUT VOUT 2 2 EN EN 1 CH1 2.0V/DIV CH2 2.0V/DIV CH3 200mA/DIV 1M BW 20.0M A CH1 1M BW 20.0M B 20.0M W 1.72V 50.0s/DIV 200MS/s 5.0ns/pt CH1 2.0V/DIV CH2 1.0V/DIV CH3 200mA/DIV 09665-059 1 Figure 59. LDO1, LDO2 Startup, VOUT = 4.7 V, IOUT = 5 mA 1M BW 20.0M A CH1 1M BW 20.0M B 20.0M W 1.72V 50.0s/DIV 200MS/s 5.0ns/pt Figure 62. LDO1, LDO2 Startup, VOUT = 1.2 V, IOUT = 5 mA Rev. A | Page 17 of 40 09665-062 3 760mV Figure 61. LDO1, LDO2 Startup, VOUT = 1.8 V, IOUT = 5 mA 3 IIN 1M BW 20.0M A CH1 1M BW 20.0M B 20.0M W 09665-061 3 ADP5040 Data Sheet 1.220 3.6V 4.5V 5.5V 2.8V 1.215 1.210 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 4.758 5.5V 4.708 4.658 1.205 1.200 1.195 1.190 5.0V 1.180 0.001 3.38 3.38 3.36 3.36 OUTPUT VOLTAGE (V) 3.40 3.34 5.5V 3.30 3.28 4.5V 3.6V 3.30 3.28 3.26 3.24 3.22 3.22 0.01 0.1 OUTPUT CURRENT (A) 3.20 0.001 0.1 Figure 67. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V, VOUT = 3.3 V 1.800 1.800 3.6V 4.5V 5.5V 2.8V -40C +25C +85C 1.795 OUTPUT VOLTAGE (V) 1.795 1.790 1.785 1.780 1.775 1.790 1.785 1.780 1.775 0.01 OUTPUT CURRENT (A) 0.1 1.770 0.001 09665-065 1.770 0.001 0.01 OUTPUT CURRENT (A) Figure 64. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 3.3 V OUTPUT VOLTAGE (V) 3.32 3.24 3.20 0.001 -40C +25C +85C 3.34 09665-064 OUTPUT VOLTAGE (V) Figure 66. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 1.2 V 3.40 3.26 0.1 OUTPUT CURRENT (A) Figure 63. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 4.7 V 3.32 0.01 09665-066 0.1 09665-067 0.01 OUTPUT CURRENT (A) 0.01 OUTPUT CURRENT (A) Figure 65. LDO1, LDO2 Load Regulation Across Input Voltage, VOUT = 1.8 V 0.1 09665-068 4.608 0.001 09665-063 1.185 Figure 68. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V, VOUT = 1.8 V Rev. A | Page 18 of 40 Data Sheet ADP5040 1.820 1.220 -40C +25C +85C 1.215 1.815 OUTPUT VOLTAGE (V) 1.210 OUTPUT VOLTAGE (V) 100A 1mA 10mA 100mA 200mA 1.205 1.200 1.195 1.810 1.805 1.800 1.190 1.795 0.01 1.790 2.5 09665-069 1.180 0.001 0.1 OUTPUT CURRENT (A) 4.0 4.5 5.0 5.5 Figure 72. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 1.8 V 1.201 4.75 100A 1mA 10mA 100mA 200mA 100A 1mA 10mA 100mA 200mA 1.200 1.199 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 3.5 INPUT VOLTAGE (V) Figure 69. LDO1, LDO2 Load Regulation Across Temperature, VIN = 3.6 V, VOUT = 1.2 V 4.73 3.0 09665-072 1.185 4.71 4.69 1.198 1.197 1.196 1.195 1.194 4.67 5.1 5.2 5.3 5.4 5.5 INPUT VOLTAGE (V) 1.192 2.5 09665-070 4.65 5.0 4.0 4.5 5.0 5.5 Figure 73. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 1.2 V 3.310 200 100A 1mA 10mA 100mA 200mA 180 160 GROUND CURRENT (A) OUTPUT VOLTAGE (V) 3.5 INPUT VOLTAGE (V) Figure 70. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 4.7 V 3.305 3.0 09665-073 1.193 3.300 3.295 3.290 140 120 100 80 60 40 3.285 4.2 4.5 4.8 INPUT VOLTAGE (V) 5.1 5.4 0 0 0.05 0.10 0.15 0.20 OUTPUT CURRENT (A) Figure 71. LDO1, LDO2 Line Regulation Across Input Voltage, VOUT = 3.3 V 0.25 0.30 09665-074 3.9 09665-071 20 3.280 3.6 Figure 74. LDO1, LDO2 Ground Current vs. Output Current, VOUT = 3.3 V Rev. A | Page 19 of 40 ADP5040 Data Sheet 200 180 VOUT GROUND CURRENT (A) 160 2 140 120 100 80 20 0 3.8 4.3 4.8 3 09665-075 40 5.3 INPUT VOLTAGE (V) Figure 75. LDO1, LDO2 Ground Current vs. Input Voltage, Across Output Load (A), VOUT = 3.3 V IOUT CH2 30.0mV/DIV CH3 50.0mA/DIV B 20.0M A CH3 W 1M BW 120M 42.0mA 200s/DIV 500kS/s 2.0s/pt 09665-078 0.000001A 0.0001A 0.001A 0.01A 0.1A 0.15A 0.3A 60 Figure 78. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to 80 mA, VOUT = 3.3 V VOUT 2 VOUT 2 IOUT IOUT 27.2mA 200s/DIV 5.0MS/s 200ns/pt CH2 50.0mV/DIV CH3 80.0mA/DIV Figure 76. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to 80 mA, VOUT = 4.7 V B 20.0M A CH3 W 1M BW 120M 89.6mA 200s/DIV 500kS/s 2.0s/pt 09665-079 B 20.0M A CH3 CH2 30.0mV/DIV W CH3 80.0mA/DIV 1M BW 20.0M 3 09665-076 3 Figure 79. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to 200 mA, VOUT = 3.3 V VOUT 2 VOUT 2 3 IOUT IOUT 27.2mA 200s/DIV 5.0MS/s 200ns/pt CH2 30.0mV/DIV CH3 80.0mA/DIV 09665-077 B 20.0M A CH3 CH2 30.0mV/DIV W CH3 80.0mA/DIV 1M BW 20.0M Figure 77. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to 200 mA, VOUT = 4.7 V B 20.0M A CH3 W 1M BW 120M 89.6mA 200s/DIV 500kS/s 2.0s/pt 09665-080 3 Figure 80. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to 80 mA, VOUT = 1.8 V Rev. A | Page 20 of 40 Data Sheet ADP5040 VIN 2 VOUT VOUT 2 3 IOUT B 20.0M A CH3 W 1M BW 120M 89.6mA 200s/DIV 500kS/s 2.0s/pt B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1M BW 20.0M 09665-081 CH2 50.0mV/DIV CH3 80.0mA/DIV Figure 81. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to 200 mA, VOUT = 1.8 V 4.84V 200s/DIV 1.0MS/s 1.0s/pt 09665-084 3 Figure 84. LDO1, LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT = 3.3 V VOUT VIN 2 VOUT 2 3 B 20.0M A CH3 CH2 30.0mV/DIV W CH3 80.0mA/DIV 1M BW 20.0M 27.2mA 200s/DIV 5.0MS/s 200ns/pt B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1M BW 20.0M Figure 82. LDO1, LDO2 Response to Load Transient, IOUT from 1 mA to 80 mA, VOUT = 1.2 V 4.86V 500s/DIV 1.0MS/s 1.0s/pt 09665-085 IOUT 09665-082 3 Figure 85. LDO1, LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT = 1.8 V VOUT 2 VIN 2 VOUT 3 B 20.0M A CH3 CH2 30.0mV/DIV W CH3 80.0mA/DIV 1M BW 20.0M 27.2mA 200s/DIV 5.0MS/s 200ns/pt B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1M BW 20.0M Figure 83. LDO1, LDO2 Response to Load Transient, IOUT from 10 mA to 200 mA, VOUT = 1.2 V 4.48V 200s/DIV 1.0MS/s 1.0s/pt 09665-086 IOUT 09665-083 3 Figure 86. LDO1, LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT = 1.2 V Rev. A | Page 21 of 40 ADP5040 Data Sheet RMS NOISE (V) VIN VOUT 2 100 3 200s/DIV 1.0MS/s 1.0s/pt 10 0.0001 Figure 87. LDO1, LDO2 Response to Line Transient, Input Voltage from 3.3 V to 3.8 V, VOUT = 1.8 V VOUT 2 0.01 0.1 1 LOAD (mA) 10 100 1k Figure 90. LDO1 Output Noise vs. Load Current, Across Input and Output Voltage RMS NOISE (V) VIN 0.001 09665-104 4.02V 09665-087 B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1M BW 20.0M CH2; VOUT = 3.3V; VIN = 5V CH2; VOUT = 3.3V; VIN = 3.6V CH2; VOUT = 2.8V; VIN = 3.1V CH2; VOUT = 1.5V; VIN = 5V CH2; VOUT = 1.5V; VIN = 1.8V 100 4.84V 200s/DIV 1.0MS/s 1.0s/pt 10 0.0001 09665-088 B 20.0M A CH3 CH2 20.0mV/DIV W CH3 1.0V/DIV 1M BW 20.0M Figure 88. LDO1, LDO2 Response to Line Transient, Input Voltage from 3.3 V to 3.8 V, VOUT = 1.2 V 0.001 100 0.6 0.01 0.1 1 LOAD (mA) 10 100 1k Figure 91. LDO2 Output Noise vs. Load Current, Across Input and Output Voltage 0.7 VOUT2 = 3.3V, VIN2 = 3.6V, I LOAD = 300mA VOUT2 = 1.5V, VIN2 = 1.8V, I LOAD = 300mA VOUT2 = 2.8V, VIN2 = 3.1V, I LOAD = 300mA VOUT = 3.3V 10 NOISE (V/Hz) 0.5 0.4 0.3 1.0 0.2 0.1 0 3.6 4.1 4.6 5.1 5.6 VIN (V) 0.01 10 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 92. LDO1 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.3 V Figure 89. LDO1, LDO2 Output Current Capability vs. Input Voltage Rev. A | Page 22 of 40 10M 09665-106 0.1 09665-089 OUTPUT CURRENT (A) CH3; V OUT = 3.3V; VIN = 5V CH3; V OUT = 3.3V; VIN = 3.6V CH3; V OUT = 2.8V; VIN = 3.1V CH3; V OUT = 1.5V; VIN = 5V CH3; V OUT = 1.5V; VIN = 1.8V 09665-105 3 Data Sheet 100 ADP5040 -10 VOUT3 = 3.3V, VIN3 = 3.6V, ILOAD = 300mA VOUT3 = 1.5V, VIN3 = 1.8V, ILOAD = 300mA VOUT3 = 2.8V, VIN3 = 3.1V, ILOAD = 300mA -20 -30 -40 PSRR (dB) NOISE (V/Hz) 10 1mA 10mA 100mA 200mA 300mA 1 -50 -60 -70 0.1 -80 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M -100 10 Figure 93. LDO2 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.3 V -10 ILOAD = 300mA ILOAD = 300mA ILOAD = 300mA -20 10k 100k FREQUENCY (Hz) 1M 10M 1mA 10mA 100mA 200mA -30 10 -40 PSRR (dB) NOISE (V/Hz) 1k Figure 96. LDO2 PSRR Across Output Load, VIN3 = 3.1 V, VOUT3 = 2.8 V 100 VOUT2 = 3.3V, VIN2 = 3.6V, VOUT3 = 3.3V, VIN3 = 3.6V, VOUT2 = 1.5V, VIN2 = 1.8V, 100 09665-110 0.01 09665-115 -90 1.0 -50 -60 -70 0.1 -80 1k 10k 100k FREQUENCY (Hz) 1M 10M -100 10 Figure 94. LDO1 vs. LDO2 Noise Spectrum -20 -30 10M 1mA 10mA 100mA 200mA 300mA PSRR (dB) -40 -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 09665-109 PSRR (dB) 1M -10 1mA 10mA 100mA 200mA 300mA -40 -100 10 10k 100k FREQUENCY (Hz) -100 10 Figure 95. LDO2 PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 98. LDO2 PSRR Across Output Load, VIN3 = 3.6 V, VOUT3 = 3.3 V Rev. A | Page 23 of 40 10M 09665-112 -30 1k Figure 97. LDO2 PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.3 V -10 -20 100 09665-111 100 -90 09665-108 0.01 10 VOUT3 = 1.5V, VIN3 = 1.8V, ILOAD = 300mA VOUT2 = 2.8V, VIN2 = 3.1V, ILOAD = 300mA VOUT3 = 2.8V, VIN3 = 3.1V, ILOAD = 300mA ADP5040 Data Sheet -10 -10 -30 -20 -30 -40 PSRR (dB) -50 -60 -50 -60 -70 -70 -80 -80 -90 -90 100 1k 10k 100k FREQUENCY (Hz) 1M 10M -100 10 09665-113 PSRR (dB) -40 -100 10 1mA 10mA 100mA 200mA 300mA 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 100. LDO1 PSRR Across Output Load, VIN2 = 1.8 V, VOUT2 = 1.5 V Figure 99. LDO1 PSRR Across Output Load, VIN2 = 5.0 V, VOUT2 = 1.5 V Rev. A | Page 24 of 40 10M 09665-114 -20 1mA 10mA 100mA 200mA 300mA Data Sheet ADP5040 THEORY OF OPERATION VOUT1 FB1 85 ENBK AVIN VDDA GM ERROR AMP ENBK MODE ENLDO1 PWM COMP ENLDO2 SOFT START VIN1 EN1 ENABLE & MODE CONTROL EN2 MODE EN3 SEL PSM COMP ILIMIT LOW CURRENT OPMODE_FUSES PWM/ PSM CONTROL BUCK1 SW OSCILLATOR DRIVER AND ANTISHOOT THROUGH SYSTEM UNDERVOLTAGE LOCK OUT PGND 600 ENLDO2 THERMAL SHUTDOWN AGND LDO1 CONTROL VDDA VDDA LDO2 CONTROL 600 VIN2 FB2 VOUT2 VIN3 FB3 VOUT3 09665-090 ENLDO1 ADP5040 Figure 101. Functional Block Diagram POWER MANAGEMENT UNIT The ADP5040 is a micro power management unit (micro PMU) combing one step-down (buck) dc-to-dc regulator and two low dropout linear regulators (LDOs). The high switching frequency and tiny 20-pin LFCSP package allow for a small power management solution. The regulators are activated by a logic level high applied to the respective EN pin. The EN1 pin controls the buck regulator, the EN2 pin controls LDO1, and the EN3 pin controls LDO2. The MODE pin controls the buck switching operation. The regulator output voltages are set through external resistor dividers. The buck regulator can operate in forced PWM mode if the MODE pin is at a logic high level. In forced PWM mode, the switching frequency of the buck is always constant and does not change with the load current. If the MODE pin is at a logic low level, the switching regulator operates in auto PWM/PSM mode. In this mode, the regulator operates at fixed PWM frequency when the load current is above the power saving current threshold. When the load current falls below the power save current threshold, the regulator enters power saving mode, where the switching occurs in bursts. The burst repetition rate is a function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses. When a regulator is turned on, the output voltage ramp is controlled through a soft start circuit to avoid a large inrush current due to the discharged output capacitors. Rev. A | Page 25 of 40 ADP5040 Data Sheet Thermal Protection VOUT1 VIN1 In the event that the junction temperature rises above 150C, the thermal shutdown circuit turns off the buck and the LDOs. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20C hysteresis is included in the thermal shutdown circuit so that when thermal shutdown occurs, the buck and the LDOs do not return to normal operation until the on-chip temperature drops below 130C. When coming out of thermal shutdown, all regulators start with soft start control. L1 - 1H SW VOUT1 BUCK FB1 R2 C5 10F 09665-091 AGND R1 Undervoltage Lockout Figure 102. Buck External Output Voltage Setting To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the ADP5040. If the input voltage on AVIN drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channel, both the power switch and the synchronous rectifier turn off. When the voltage on AVIN rises above the UVLO threshold, the part is enabled once more. Control Scheme Alternatively, the user can select device models with a UVLO set at a higher level, suitable for 5 V applications. For these models, the device reaches the turn-off threshold when the input supply drops to 3.65 V typical. The buck operates with a fixed frequency, current mode PWM control architecture at medium to high loads for high efficiency, but operation shifts to a power save mode (PSM) control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in PSM at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. Enable/Shutdown PWM Mode The ADP5040 has individual control pins for each regulator. A logic level high applied to the ENx pin activates a regulator, whereas a logic level low turns off a regulator. In PWM mode, the buck operates at a fixed frequency of 3 MHz, set by an internal oscillator. At the start of each oscillator cycle, the PFET switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the PFET switch and turns on the NFET synchronous rectifier. This sends a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle. The buck regulates the output voltage by adjusting the peak inductor current threshold. Active Pull-Down The ADP5040 can be purchased with the active pull-down option enabled. The pull-down resistors are connected between each regulator output and AGND. The pull-downs are enabled, when the regulators are turned off. The typical value of the pulldown resistor is 600 for the LDOs and 85 for the buck. BUCK SECTION The buck uses a fixed frequency and high speed current mode architecture. The buck operates with an input voltage of 2.3 V to 5.5 V. The buck output voltage is set though external resistor dividers, as shown in Figure 102. VOUT1 must be connected to the output capacitor. VFB1 is internally set to 0.5 V. The output voltage can be set from 0.8 V to 3.8 V. Power Save Mode (PSM) The buck smoothly transitions to PSM operation when the load current decreases below the PSM current threshold. When the buck enters power save mode, an offset is introduced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level that is approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle mode. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. This process is repeated while the load current is below the PSM current threshold. Rev. A | Page 26 of 40 Data Sheet ADP5040 The ADP5040 has a dedicated MODE pin controlling the PSM and PWM operation. A high logic level applied to the MODE pin forces the buck to operate in PWM mode. A logic level low sets the buck to operate in auto PSM/PWM. PSM Current Threshold The PSM current threshold is set to 100 mA. The buck employs a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to, and exit from, the PSM mode. The PSM current threshold is optimized for excellent efficiency over all load currents. Short-Circuit Protection The buck includes frequency foldback to prevent current runaway on a hard short at the output. When the voltage at the feedback pin falls below half the internal reference voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. switch on 100% of the time, the output voltage drops below the desired output voltage. At this limit, the buck transitions to a mode where the PFET switch stays on 100% of the time. When the input conditions change again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage. LDO SECTION The ADP5040 contains two LDOs with low quiescent current that provide output currents up to 300 mA. The low 10 A typical quiescent current at no load makes the LDO ideal for battery-operated portable equipment. The LDOs operate with an input voltage range of 1.7 V to 5.5 V. The wide operating range makes these LDOs suitable for cascade configurations where the LDO supply voltage is provided from the buck regulator. Each LDO output voltage is set though external resistor dividers as shown in Figure 103. VFB2 and VFB3 are internally set to 0.5 V. The output voltage can be set from 0.8 V to 5.2 V. VOUT2, VOUT3 VIN2, VIN3 LD01, LD02 Soft Start FB2, FB3 The buck has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. RA VOUT2, VOUT3 C7 2.2F 09665-092 RB Figure 103. LDOs External Output Voltage Setting Current Limit The buck has protection circuitry to limit the amount of positive current flowing through the PFET switch and the amount of negative current flowing through the synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load. The LDOs also provide high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with small 1 F ceramic input and output capacitors. LDO2 is optimized to supply analog circuits because it offers better noise performance compared to LDO1. LDO1 should be used in applications where noise performance is not critical. 100% Duty Operation With a dropping input voltage or with an increase in load current, the buck may reach a limit where, even with the PFET Rev. A | Page 27 of 40 ADP5040 Data Sheet NO POWER APPLIED TO AVIN. ALL REGULATORS TURNED OFF NO POWER AVIN > VUVLO AVIN < VUVLO POR INTERNAL CIRCUIT BIASED REGULATORS NOT ACTIVATED END OF POR STANDBY AVIN < VUVLO ALL ENx = LOW ENx = HIGH ACTIVE ALL REGULATORS ACTIVATED Figure 104. ADP5040 State Flow Rev. A | Page 28 of 40 09665-096 TRANSITION STATE Data Sheet ADP5040 APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Trade-offs between performance parameters such as efficiency and transient response are made by varying the choice of external components in the applications circuit, as shown in Figure 1. Feedback Resistors Referring to Figure 102, the total combined resistance for R1 and R2 is not to exceed 400 k. Inductor The high switching frequency of the ADP5040 buck allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 H and 3.0 H. Suggested inductors are shown in Table 8. The peak-to-peak inductor current ripple is calculated using the following equation: I RIPPLE = VOUT x (VIN - VOUT ) VIN x f SW x L The worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: CEFF = COUT x (1 - TEMPCO) x (1 - TOL) where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT is 9.2481 F at 1.8 V, as shown in Figure 105. where: fSW is the switching frequency. L is the inductor value. The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current is calculated using the following equation: I PEAK = I LOAD( MAX ) + Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are highly recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. I RIPPLE 2 Substituting these values in the equation yields CEFF = 9.24 F x (1 - 0.15) x (1 - 0.1) = 7.07 F To guarantee the performance of the buck, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 12 Table 8. Suggested 1.0 H Inductors Dimensions (mm) ISAT (mA) DCR (m) Murata Murata Tayo Yuden Coilcraft Coilcraft Toko LQM2MPN1R0NG0B LQM18FN1R0M00B CBC322ST1R0MR XFL4020-102ME XPL2010-102ML MDT2520-CN 2.0 x 1.6 x 0.9 3.2 x 2.5 x 1.5 3.2 x 2.5 x 2.5 4.0 x 4.0 x 2.1 1.9 x 2.0 x 1.0 2.5 x 2.0 x 1.2 1400 2300 2000 5400 1800 1350 85 54 71 11 89 85 Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the buck is high switching frequency dc-to-dc converter, shielded ferrite core material is recommended for its low core losses and low EMI. Output Capacitor 10 8 6 4 2 0 0 1 2 3 4 5 DC BIAS VOLTAGE (V) 6 09665-097 Model CAPACITANCE (F) Vendor Figure 105. Typical Capacitor Performance The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing the capacitor value, it is also important to account for the loss of capacitance due to output voltage dc bias. Rev. A | Page 29 of 40 V RIPPLE = V IN I RIPPLE 8 x f SW x COUT (2 x f SW )2 x L x COUT ADP5040 Data Sheet To minimize supply noise, place the input capacitor as close to the VIN pin of the buck as possible. As with the output capacitor, a low ESR capacitor is recommended. Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation: ESRCOUT The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 F and a maximum of 10 F. A list of suggested capacitors is shown in Table 10. VRIPPLE I RIPPLE The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 F and a maximum of 40 F. Table 10. Suggested 4.7 F Capacitors Table 9. Suggested 10 F Capacitors Vendor Murata Taiyo Yuden TDK Panasonic Type X5R X5R X5R X5R Case Size 0603 0603 0603 0603 Model GRM188R60J106 JMK107BJ106MA-T C1608JB0J106K ECJ1VB0J106M Voltage Rating (V) 6.3 6.3 6.3 6.3 SW L1 1H PROCESSOR VCORE VIN1 C1 10F FB1 R1 VIN2 VIN3 PGND C3 1F VOUT2 FB2 Table 11. Suggested 2.2 F Capacitors VDDIO C5 2.2F R3 R4 MODE Vendor Murata TDK Panasonic Taiyo Yuden GPIO1 3 ENx GPIO[x:y] VOUT3 FB3 C6 2.2F ANALOG SUBSYSTEM R6 09665-098 VANALOG R5 Figure 106. Processor System Power Management with PSM/PWM Control Input Capacitor A higher value input capacitor helps to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation: I CIN I LOAD ( MAX ) Feedback Resistors When operating at output currents higher than 200 mA a minimum of 2.2 F capacitance with an ESR of 1 or less is recommended to ensure stability of the LDO. C4 4.7F R2 C2 1F LDO EXTERNAL COMPONENT SELECTION The ADP5040 LDOs are designed for operation with small, space-saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure stability of the LDO. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the LDO to large changes in load current. VOUT1 VIN 2.3V TO 5.5V Model GRM188R60J475ME19D JMK107BJ475 ECJ-0EB0J475M Output Capacitor ADP5040 MICRO PMU Type X5R X5R X5R Voltage Rating (V) 6.3 6.3 6.3 Referring to Figure 103 the maximum value of Rb is not to exceed 200 k. The buck regulator requires 10 F output capacitors to guarantee stability and response to rapid load variations and to transition in and out the PWM/PSM modes. In certain applications, where the buck regulator powers a processor, the operating state is known because it is controlled by software. In this condition, the processor can drive the MODE pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 F to 4.7 F because the regulator does not expect a large load variation when working in PSM mode (see Figure 106). AVIN Vendor Murata Taiyo Yuden Panasonic Case Size 0603 0603 0402 Type Model X5R GRM188B31A225K C1608JB0J225KT ECJ1VB0J225K X5R X5R X5R JMK107BJ225KK-T Case Size 0402 0402 0402 0402 Voltage Rating (V) 10.0 6.3 6.3 6.3 Input Bypass Capacitor Connecting 1 F capacitors from VIN2 and VIN3 to ground reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance is encountered. If greater than 1 F of output capacitance is required, increase the input capacitor to match it. VOUT (VIN - VOUT ) VIN Rev. A | Page 30 of 40 Data Sheet ADP5040 Table 12. Suggested 1.0 F Capacitors Vendor Murata TDK Panasonic Taiyo Yuden Type X5R X5R X5R X5R Model GRM155R61A105ME15 C1005JB0J105KT ECJ0EB0J105K LMK105BJ105MV-F Case Size 0402 0402 0402 0402 Voltage Rating (V) 10.0 6.3 6.3 10.0 Input and Output Capacitor Properties Use any good quality ceramic capacitor with the ADP5040 as long as it meets the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 107 depicts the capacitance vs. voltage bias characteristic of a 0402 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40C to +85C temperature range and is not a function of package or voltage rating. X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V as shown in Figure 107. Substituting these values into the following equation yields: CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.72 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage. To guarantee the performance of the ADP5040, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. POWER DISSIPATION/THERMAL CONSIDERATIONS The ADP5040 is a highly efficient micropower management unit (micro PMU), and in most cases the power dissipated in the device is not a concern. However, if the device operates at high ambient temperatures and with maximum loading conditions, the junction temperature can reach the maximum allowable operating limit (125C). When the junction temperature exceeds 150C, the ADP5040 turns off all the regulators, allowing the device to cool down. Once the die temperature falls below 135C, the ADP5040 resumes normal operation. This section provides guidelines to calculate the power dissipated in the device and to make sure the ADP5040 operates below the maximum allowable junction temperature. The efficiency for each regulator on the ADP5040 is given by 1.2 = CAPACITANCE (F) 1.0 POUT x 100% PIN (1) where: is efficiency. PIN is the input power. POUT is the output power. 0.8 0.6 Power loss is given by 0.4 PLOSS = PIN - POUT (2a) or 0.2 0 1 2 3 4 DC BIAS VOLTAGE (V) 5 6 PLOSS = POUT x (1 - )/ 09665-099 0 Figure 107. Capacitance vs. Voltage Characteristic Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an (2b) Power dissipation can be calculated in several ways. The most intuitive and practical way is to measure the power dissipated at the input and all the outputs. The measurements should be performed at the worst-case conditions (voltages, currents, and temperature). The difference between input and output power is dissipated in the device and the inductor. Use Equation 4 to derive the power lost in the inductor, and from this use Equation 3 to calculate the power dissipation in the ADP5040 buck regulator. A second method to estimate the power dissipation uses the efficiency curves provided for the buck regulator, whereas the power lost on a LDO is calculated using Equation 12. When the buck efficiency is known, use Equation 2b to derive the total power lost in the buck regulator and inductor. Use Equation 4 Rev. A | Page 31 of 40 ADP5040 Data Sheet to derive the power lost in the inductor, and then calculate the power dissipation in the buck converter using Equation 3. Add the power dissipated in the buck and in the LDOs to find the total dissipated power. Note that the buck efficiency curves are typical values and may not be provided for all possible combinations of VIN, VOUT, and IOUT. To account for these variations, it is necessary to include a safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and the losses in the LDOs provided by Equation 12. Buck Regulator Power Dissipation The power switch conductive losses are due to the output current, IOUT1, flowing through the PMOSFET and the NMOSFET power switches that have internal resistance, RDSON-P and RDSON-N. The amount of conductive power loss is found by: PCOND = [RDSON-P x D + RDSON-N x (1 - D)] x IOUT12 For the ADP5040, at 125C junction temperature and VIN1 = 3.6 V, RDSON-P is approximately 0.2 , and RDSON-N is approximately 0.16 . At VIN1 = 2.3 V, these values change to 0.31 and 0.21 , respectively, and at VIN1 = 5.5 V, the values are 0.16 and 0.14 , respectively. Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. The amount of switching power loss is given by: The power loss of the buck regulator is approximated by PLOSS = PDBUCK + PL PSW = (CGATE-P + CGATE-N) x VIN12 x fSW (3) where: PDBUCK is the power dissipation on the ADP5040 buck regulator. PL is the inductor power losses. The inductor losses are external to the device and they do not have any effect on the die temperature. The inductor losses are estimated (without core losses) by PL I OUT1( RMS )2 x DCRL (4) I OUT1( RMS ) = I OUT1 x 1 + r/12 For the ADP5040, the total of (CGATE-P + CGATE-N) is approximately 150 pF. The transition losses occur because the PMOSFET cannot be turned on or off instantaneously, and the SW node takes some time to slew from near ground to near VOUT1 (and from VOUT1 to ground). The amount of transition loss is calculated by: PTRAN = VIN1 x IOUT1 x (tRISE + tFALL) x fSW (5) (6) where: L is inductance. FSW is switching frequency. D is duty cycle. D = VOUT1/VIN1 If the preceding equations and parameters are used for estimating the converter efficiency, note that the equations do not describe all of the converter losses, and the parameter values given are typical numbers. The converter performance also depends on the choice of passive components and board layout; therefore, a sufficient safety margin should be included in the estimate. LDO Regulator Power Dissipation The power loss of a LDO regulator is given by: PDLDO = [(VIN - VOUT) x ILOAD] + (VIN x IGND) (7) The ADP5040 buck regulator power dissipation, PDBUCK, includes the power switch conductive losses, the switch losses, and the transition losses of each channel. There are other sources of loss, but these are generally less significant at high output load currents, where the thermal limit of the application is. Equation 8 shows the calculation made to estimate the power dissipation in the buck regulator. PDBUCK = PCOND + PSW + PTRAN (11) where tRISE and tFALL are the rise time and the fall time of the switching node, SW. For the ADP5040, the rise and fall times of SW are in the order of 5 ns. where r is the normalized inductor ripple current. R VOUT1 x (1 - D)/(IOUT1 x L x fSW) (10) where: CGATE-P is the PMOSFET gate capacitance. CGATE-N is the NMOSFET gate capacitance. where: DCRL is the inductor series resistance. IOUT1(RMS) is the rms load current of the buck regulator. (9) (8) (12) where: ILOAD is the load current of the LDO regulator. VIN and VOUT are input and output voltages of the LDO, respectively. IGND is the ground current of the LDO regulator. Power dissipation due to the ground current is small and it can be ignored. The total power dissipation in the ADP5040 simplifies to: PD = {[PDBUCK + PDLDO1 + PDLDO2]} Rev. A | Page 32 of 40 (13) Data Sheet ADP5040 Junction Temperature If the case temperature can be measured, the junction temperature is calculated by In cases where the board temperature, TA, is known, the thermal resistance parameter, JA, can be used to estimate the junction temperature rise. TJ is calculated from TA and PD using the formula TJ = TA + (PD x JA) TJ = TC + (PD x JC) (15) where: TC is the case temperature. JC is the junction-to-case thermal resistance provided in Table 6. (14) The typical JA value for the 20-lead, 4 mm x 4 mm LFCSP is 38C/W (see Table 6). A very important factor to consider is that JA is based on a 4-layer, 4 inch x 3 inch, 2.5 oz copper, as per JEDEC standard, and real applications may use different sizes and layers. To remove heat from the device, it is important to maximize the use of copper. Copper exposed to air dissipates heat better than copper used in the inner layers. The exposed pad (EP) should be connected to the ground plane with several vias as shown in Figure 109. When designing an application for a particular ambient temperature range, calculate the expected ADP5040 power dissipation (PD) due to the losses of all channels by using Equation 8 to Equation 13. From this power calculation, the junction temperature, TJ, can be estimated using Equation 14. The reliable operation of the buck regulator and the LDO regulator can be achieved only if the estimated die junction temperature of the ADP5040 (Equation 14) is less than 125C. Reliability and mean time between failures (MTBF) is highly affected by increasing the junction temperature. Additional information about product reliability can be found in the Analog Devices, Inc., Reliability Handbook, which is available at http://www.analog.com/reliability_handbook. APPLICATION DIAGRAM VOUT1 AVIN 11 L1 1H 6 8 BUCK 12 SW VOUT1 AT 1.2A R1 FB1 C4 10F R2 VIN1 = 2.3V TO 5.5V VIN1 7 9 EN_BK C1 4.7F PGND FPWM OFF VIN2 = 1.7V TO 5.5V EN1 VIN2 17 14 13 ON OFF EN3 R4 16 4 2 VIN3 C3 1F VOUT2 AT 300mA FB2 EN_LDO1 EN2 C5 2.2F R3 EN_LDO2 VIN3 = 1.7V TO 5.5V VOUT2 LDO1 (DIGITAL) 15 ON PWM/PSM 10 C2 1F OFF MODE VOUT3 R7 3 LDO2 (ANALOG) 1 C6 2.2F VOUT3 AT 300mA FB3 R8 EP AGND Figure 108. Application Diagram Rev. A | Page 33 of 40 09665-103 ON ADP5040 Data Sheet PCB LAYOUT GUIDELINES Poor layout can affect ADP5040 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: * * SUGGESTED LAYOUT * Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. 0.5 1.0 2.0 1.5 2.5 3.0 3.5 See Figure 109 for an example layout. 4.0 4.5 5.5 5.0 PPL 0.5 6.0 6.5 7.0 mm VOUT3 GPL C4- 2.2F 6.3V/XR5 0402 FB3 VIN3 EN3 NC Pin 1 1.5 VOUT3 C3 - 1F 10V/XR5 0402 GPL 1.0 2.0 PPL PPL PPL NC AVIN 2.5 NC VIN GPL GPL 3.0 C5 - 4.7F 10V/XR5 0603 3.5 G PL L1 - 1H 0603 4.0 AGND SW NC GPL GPL MODE PGND ADP5040 4.5 EN2 FB2 VOUT2 VIN2 FB1 VOUT1 VIAS LEGEND: PPL = POWER PLANE (+4V) GPL = GROUND PLANE C6 - 10F 6.3V/XR5 0603 5.5 C2 - 1F 10V/XR5 0402 6.0 C5 - 2.2F 6.3V/XR5 0402 VOUT1 6.5 TOP LAYER 2ND LAYER PPL VOUT2 mm Figure 109. Evaluation Board Layout Rev. A | Page 34 of 40 09665-102 5.0 G PL G PL G PL EN1 G PL * Maximize the size of ground metal on the component side to help with thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. Data Sheet ADP5040 BILL OF MATERIALS Table 13. Reference C1 C2, C3 C4 C5, C6 L1 IC1 Value 4.7 F, X5R, 6.3 V 1 F, X5R, 6.3 V 10 F, X5R, 6.3 V 2.2 F, X5R, 6.3 V 1 H, 85 m, 1400 mA 1 H, 85 m, 1350 mA 1 H, 89 m, 1800 mA 3-regulator micro PMU Part Number JMK107BJ475 LMK105BJ105MV-F JMK107BJ106MA-T JMK105BJ225MV-F LQM2MPN1R0NG0B MDT2520-CN XPL2010-1102ML ADP5040 Rev. A | Page 35 of 40 Vendor Taiyo-Yuden Taiyo-Yuden Taiyo-Yuden Taiyo-Yuden Murata Toko Coilcraft Analog Devices Package 0603 0402 0603 0402 2.0 x 1.6 x 0.9 (mm) 2.5 x 2.0 x 1.2 (mm) 1.9 x 2.0 x 1.0 (mm) 20-Lead LFCSP ADP5040 Data Sheet FACTORY PROGRAMMABLE OPTIONS Table 14. Regulator Output Discharge Resistor Options Selection 0 1 All discharge resistors disabled All discharge resistors enabled Table 15. Under Voltage Lockout options Selection 0 1 Min 1.95 3.10 Typ 2.15 3.65 Rev. A | Page 36 of 40 Max 2.275 3.90 Unit V V Data Sheet ADP5040 OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.30 0.25 0.20 0.50 BSC 20 16 15 PIN 1 INDICATOR 1 EXPOSED PAD 2.65 2.50 SQ 2.35 5 11 0.80 0.75 0.70 0.50 0.40 0.30 10 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 6 0.25 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGD. 061609-B TOP VIEW Figure 110. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm x 4 mm Body, Very Very Thin Quad (CP-20-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP5040ACPZ-1-R7 ADP5040CP-1-EVALZ 1 UVLO 2.15 V Active Pull-Down Enabled on all channels Temperature Range TJ = -40C to +125C Z = RoHS Compliant Part. Rev. A | Page 37 of 40 Package Description 20-Lead LFCSP_WQ Evaluation Board Package Option CP-20-10 ADP5040 Data Sheet NOTES Rev. A | Page 38 of 40 Data Sheet ADP5040 NOTES Rev. A | Page 39 of 40 ADP5040 Data Sheet NOTES (c)2011-2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09665-0-1/14(A) Rev. A | Page 40 of 40 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADP5040ACPZ-1-R7 ADP5040CP-1-EVALZ