DT28F016SA-150 - Intel - Product.Network

November 1996 Order Number: 290489-004

User-Selectable 3.3V or 5V VCC

User-Configurable x8 or x16 Operation

70 ns Maximum Access Time

28.6 MB/sec Burst Write Transfer Rate

1 Million Typical Erase Cycles per

Block

56-Lead, 1.2 mm x 14 mm x 20 mm

TSOP Package

56-Lead, 1.8 mm x 16 mm x 23.7 mm

SSOP Package

Revolutionary Architecture



Pipelined Command Execution



Program during Erase



Command Superset of Intel

28F008SA

1 mA Typical ICC in Static Mode

1 µA Typical Deep Power-Down

32 Independently Lockable Blocks

State-of-the-Art 0.6 µm ETOX™ IV Flash

Technology

Intel’s 28F016SA 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for

designing embedded di rect-execut e code and mass s torage data/fi le flash mem ory systems. With innovative

capabilities, low-power, extended temperat ure operation and high read/program performance, the 28F016SA

enables the design of truly mobile, high-performance communications and computing products.

The 28F016SA is the highest density, highest performance nonvolatile read/program solution for solid-state

storage applications. Its symmetrically-blocked architecture (100% compatible with the 28F008SA 8-Mbit

FlashFile memory), extended cycling, extended temperature operation, flexible VCC, fast program and read

performance and selective block locking provide highly flexible memory components suitable for Resident

Flash Arrays, high-density memory cards and PCMCIA-ATA flash drives. The 28F016SA dual read voltage

enables the design of memory c ards which can be interchangeably read/written i n 3.3V and 5.0V systems. Its

x8/x16 architecture all ows optimizati on of the memory-to-proc essor interface. Its high read performance and

flexible block locking enable both storage and execution of operating systems and application software.

Manufactured on Intel’s 0.6 µm ETOX IV process technology, the 28F016SA is the most cost-effective,

highest density monolithic 3.3V FlashFile memory.

28F016SA 16-MBIT

(1 MBIT X 16, 2 MBIT X 8)

FlashFile™ MEMORY

Includes Commercial and Extended Temperature Specifications

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property ri ghts is granted by this document. Except as provided in Intel’s Terms and Conditi ons of

Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to

sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or

infringement of any patent, copyright or other intellectual property ri ght. Intel products are not intended for use in medical, life

saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

The 28F016SA may contain design defects or errors known as errata. Current characterized errata are available upon request.

*Third-party brands and names are the property of their respective owners.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation

P.O. Box 7641

Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

E28F016SA

CONTENTS

PAGE PAGE

1.0 INTRODUCTION.............................................5

1.1 Product Overview ........................................5

2.0 DEVICE PINOUT.............................................6

2.1 Lead Descriptions........................................8

3.0 MEMORY MAPS...........................................12

3.1 Extended Status Register Memory Map.....13

4.0 BUS OPERATIONS, COMMANDS AND

STATUS REGISTER DEFINITIONS.............14

4.1 Bus Operations for Word-Wide Mode

(BYTE# = VIH)...........................................14

4.2 Bus Operations for Byte-Wide Mode

(BYTE# = VIL)...........................................14

4.3 28F008SA–Compatible Mode Command

Bus Definitions..........................................15

4.4 28F016SA–Performance Enhancement

Command Bus Definitions.........................16

4.5 Compatible Status Register .......................18

4.6 Global Status Register...............................19

4.7 Block Status Register ................................20

5.0 ELECTRICAL SPECIFICATIONS.................21

5.1 Absolute Maximum Ratings .......................21

5.2 Capacitance...............................................22

5.3 Timing Nomenclature.................................23

5.4 DC Characteristics (VCC = 3.3V ± 10%).....26

5.5 DC Characteristics

(VCC = 5.0V ± 10%, 5.0V ± 5%)................29

5.6 AC Characteristics–Read Only

Operations.................................................32

5.7 Power-Up and Reset Timings.....................37

5.8 AC Characteristics for WE#–Controlled

Command Write Operations......................38

5.9 AC Characteristics for CE#–Controlled

Command Write Operations......................42

5.10 AC Characteristics for Page Buffer Write

Operations.................................................46

5.11 Erase and Word/Byte Program

Performance, Cycling Performance and

Suspend Latency.......................................49

6.0 DERATING CURVES.....................................50

7.0 MECHANICAL SPECIFICATIONS FOR

TSOP............................................................52

8.0 MECHANICAL SPECIFICATIONS FOR

SSOP............................................................53

APPENDIX A: Device Nomenclature and

Ordering Information ..................................54

APPENDIX B: Additional Information...............55

28F016SA E

REVISION HISTORY

Number Description

-001 Original Version

-002 — Added 56-Lead SSOP Package

— Separated AC Reading Timing Specs tAVEL, tAVGL for Extended Status Register

Reads

— Modified Device Nomenclature

— Added Ordering Information

— Added Page Buffer Typical Program Performance numbers

— Added Typical Erase Suspend Latencies

— For ICCD (Deep Power-Down current) BYTE# must be at CMOS levels

— Added SSOP package mechanical specifications

— Revised document status from “Advanced Information” to “Preliminary”

-003 — Section 5.11: Renamed specification “Erase Suspend Latency Time to Program” as

“Auto Erase Suspend Latency Time to Program”

— Section 5.7: Added specifications tPHEL3, tPHEL5

— TSOP dimension A1 = 0.05 mm (min)

— SSOP dimension B = 0.40 mm (max)

— Minor cosmetic changes

-004 Update:

—Changed Deep Power Down Current

— Changed Standby Current

— Changed Sleep Mode Current

Combined Commercial and Extended Temperature information into single datasheet

E28F016SA

1.0 INTRODUCTION

The documentation of the Intel 28F016SA memory

device includes this datasheet, a detailed user’s

manual, and a number of application notes, all of

which are referenced at the end of this datasheet.

The datasheet i s intended to give an overview of the

chip feature-set and of the operating AC/DC

specifications.

The 16-Mbit Flash Product Family

User’s Manual

provides complete descriptions of

the user modes, system interface examples and

detailed descriptions of al l principles of operat ion. It

also contains the full list of software algorithm

flowcharts, and a brief section on compatibility with

Intel 28F008SA.

1.1 Product Overview

The 28F016SA is a high-performance 16-Mbit

(16,777,216 bit) block erasable nonvolatile random

access memory organized as either 1 Mword x

16 or 2 Mbyte x 8. The 28F016SA includes thirty-

two 64-KB (65,536) blocks or thirty-two 32-KW

(32,768) blocks. A chip memory map is shown in

Figure 4.

The implementation of a new architecture, with

many enhanced features, will improve the device

operating characteristics and results in greater

product reliability and ease-of-use.

Among the significant enhancements on the

28F016SA:

•3.3V Low Power Capability

•Improved Program Performance

•Dedicated Block Program/Erase Protection

A 3/5# input pin reconfigures the device internally

for optimized 3.3V or 5.0V read/program operation.

The 28F016SA will be available in a 56-lead,

1.2 mm thick, 14 mm x 20 mm TSOP type I

package or a 56-lead, 1.8 mm thick, 16 mm x

23.7 mm SSOP package. The TSOP form factor

and pinout allow for very high board layout

densities. SSOP packaging provides relaxed lead

spacing dimensions.

A Command User Interface (CUI) serves as the

system interface between the microprocessor or

microcontroller and the internal memory operation.

Internal algorithm automation allows word/byte

programs and block erase operations to be

executed using a two-write command sequence to

the CUI in the same way as the 28F008SA 8-Mbit

FlashFile memory.

A superset of commands have been added to the

basic 28F008SA command-set to achieve higher

program performance and provide additional

capabilities. These new commands and features

include:

•Page Buffer Writes to Flash

•Command Queueing Capability

•Automatic Data Programs during Erase

•Software Locking of Memory Blocks

•Two-Byte Successive Programs in 8-bit

Systems

•Erase All Unlocked Blocks

Writing of memory data is performed in either byte

or word increments typically within 6 µs, a 33%

improvement over the 28F008SA. A block erase

operation erases one of the 32 blocks in typically

0.6 sec , independent of the ot her blocks, which is a

65% improvement over the 28F008SA.

Each bloc k c an be writ ten and eras ed a m inimum of

100,000 cycles. Systems can achieve typically one-

million block erase cycles by providing wear-leveling

algorithms and graceful block retirement. These

techniques have already been employed in many

flash file systems. Additionally, wear leveling of

block erase cycles can be used to minimize the

program/erase performance differences across

blocks.

The 28F016SA incorporates two Page Buffers of

256 bytes (128 words) each to allow page data

writes. This feature can improve a system write

performance by up to 4.8 times over previous flash

memory devices.

All operations are started by a sequence of

command writes to the device. Three Status

Registers (described in detail later) and a RY/BY#

output pin provide information on the progress of

the requested operation.

While the 28F008SA requires an operation to

complete before the next operation can be

requested, the 28F016SA allows queueing of the

next operation while the memory executes the

current operation. This eliminates system overhead

28F016SA E

when writing several bytes in a row to the array or

erasing several blocks at the same time. The

28F016SA can also perform program operations to

one block of memory while performing erase of

another block.

The 28F016SA provides user-selectable block

locking to protect code or data such as device

drivers, PCMCIA card i nformation, ROM -executable

O/S or application code. Each block has an

assoc iated nonv olat ile loc k -bit whi ch determ ines the

lock status of the block. In addition, the 28F016SA

has a master Write Protect pin (WP#) which

prevents any modifications to memory blocks

whose lock-bits are set.

The 28F016SA contains three types of Status

Registers to accomplish various functions:

•A Compatible Status Register (CSR) which is

100% compatible with the 28F008SA FlashFile

memory’s Status Register. This register, when

used alone, provides a straightforward upgrade

capability to the 28F016SA from a 28F008SA-

based design.

•A Global Status Register (GSR) which informs

the system of Command Queue status, Page

Buffer status, and overall Write State Machine

(WSM) status.

•32 Block Status Registers (BSRs) whic h provide

block-specific status information such as the

block lock-bit status.

The GSR and BSR m emory m aps f or byt e-wide and

word-wide modes are shown in Figures 5

and 6.

The 28F016SA incorporates an open drain RY/BY#

output pin. This feature allows the user to OR-tie

many RY/BY# pins together in a multiple memory

configuration such as a Resident Flash Array.

Other confi gurations of t he RY/BY# pin are enabled

via special CUI commands and are described in

detail in the

16-Mbit Flash Product Family User’s

Manual.

The 28F016SA als o incorporat es a dual c hip-enabl e

functi on with two input pins, CE 0# and CE1#. These

pins have exactly the same functionality as the

regular chip-enable pin CE# on the 28F008SA. For

minimum chip designs, CE1# may be ti ed to ground

to use CE0# as the chip enable input. The

28F016SA uses the logical combination of these

two signals to enable or disable t he entire chip. Both

CE0# and CE1# must be active low to enable the

device and, if either one becomes i nactive, the c hip

will be disabled. This feature, along with the open

drain RY/BY# pin, allows the system designer to

reduce the number of control pins used in a large

array of 16-Mbit devices.

The BYTE# pin allows either x8 or x16

read/programs to the 28F016SA. BYTE# at logic

low selects 8-bit mode with address A0 selecting

between low byte and high by te. On t he other hand,

BYTE# at logic high enables 16-bit operation with

address A1 becoming the lowest order address and

address A0 is not used (don’t care). A device block

diagram is shown in Figure 1.

The 28F016SA is specified for a maximum access

time of 70 ns (tACC) at 5.0V operation (4.75V to

5.25V) over the commercial temperature range

(0°C to +70°C). A corresponding maximum access

time of 120 ns at 3.3V (3.0V to 3.6V and 0°C to

+70°C) is achieved for reduced power consumption

applications.

The 28F016SA incorporates an Automatic Power

Saving (APS) feature which substantially reduces

the active current when the device is in the static

mode of operation (addresses not switching).

In APS mode, the typic al ICC current is 1 mA at 5.0V

(0.8 mA at 3.3V).

A deep power-down mode of operation is invoked

when the RP# (cal led PWD# on the 28F008SA) pi n

transitions low. This mode brings the device power

consumption to less than 1.0 µA, typically, and

provides additional write protection by acting as a

device reset pin during power transitions. A reset

time is required from RP# switching high until

outputs are again valid. In the deep power-down

state, the WSM is reset (any current operation will

abort) and the CSR, GSR and BSR registers are

cleared.

A CMOS standby mode of operation is enabled

when either CE 0# or CE1# transit ions high and RP#

stays high with all input control pins at CMOS

levels. In this mode, the device typically draws an

ICC standby current of 50 µA.

2.0 DEVICE PINOUT

The 28F016SA 56-lead TSOP Type I pinout

configuration is shown in

Figure

2. The 56-lead

SSOP pinout configuration is shown in Figure 3.

E28F016SA

Output

Buffer Output

Buffer Input

Buffer

I/O Logic

CSR

Data

Comparator

Decoder

64-Kbyte

Block 0

64-Kbyte

Block 1

64-Kbyte

Block 30

64-Kbyte

Block 31

Program/Erase

Vo ltag e Sw itc h

Address

Counter

Input

Buffer

Y Gating/Sensing

Output Multiplexer

GND

8-15

0-7

3/5#

BYTE#

CE0

CE1#

OE#

WE#

WP#

RP#

VCC

3/5#

RY/BY#

VPP

A0-20

Address

Queue

Latches

CUI

Data

Queue

Registers

Page

Buffers

WSM

ESRs

0489_01

Figure 1. 28F016SA Block Diagram

Architectural Evolution Includes Page Buffers, Queue Registers and Extended Status Registers

28F016SA E

2.1 Lead Descriptions

Symbol Type Name and Function

A0INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the

device is in x8 mode. This address is latched in x8 data programs. Not

used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is

high).

A1–A15 INPUT WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte block.

A6–15 selects 1 of 1024 rows, and A1–5 selects 16 of 512 columns. These

addresses are latched during data programs.

A16–A20 INPUT BLOCK-SELECT ADDRESSES: Select 1 of 32 erase blocks. These

addresses are latched during data programs, block erase and lock block

operations.

DQ0–DQ7INPUT/OUTPUT LOW-BYTE DATA BUS: Inputs data and commands during CUI write

cycles. Outputs array, buffer, identifier or status data in the appropriate

read mode. Floated when the chip is deselected or the outputs are

disabled.

DQ8–DQ15 INPUT/OUTPUT HIGH-BYTE DATA BUS: Inputs data during x16 data program

operations. Outputs array, buffer or identifier data in the appropriate read

mode; not used for Status Register reads. Floated when the chip is

deselected or the outputs are disabled.

CE0#,CE1# INPUT CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,

decoders and sense amplifiers. With either CE0# or CE1# high, the device

is deselected and power consumption reduces to standby levels upon

completion of any current data program or block erase operations. Both

CE0#, CE1# must be low to select the device.

All timing specifications are the same for both signals. Device selection

occurs with the latter falling edge of CE0# or CE1#. The first rising edge of

CE0# or CE1# disables the device.

RP# INPUT RESET/POWER-DOWN: RP# low places the device in a deep power-

down state. All circuits that burn static power, even those circuits enabled

in standby mode, are turned off. When returning from deep power-down,

a recovery time is required to allow these circuits to power-up.

When RP# goes low, any current or pending WSM operation(s) are

terminated, and the device is reset. All Status Registers return to ready

(with all status flags cleared).

OE# INPUT OUTPUT ENABLE: Gates device data through the output buffers when

low. The outputs float to tri-state off when OE# is high.

NOTE:

CEx# overrides OE#, and OE# overrides WE#.

WE# INPUT WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue

Registers and Address Queue Latches. WE# is active low, and latches

both address and data (command or array) on its rising edge.

Page Buffer addresses are latched on the falling edge of WE#.

E28F016SA

2.1 Lead Descriptions (Continued)

Symbol Type Name and Function

RY/BY# OPEN DRAIN

OUTPUT READY/BUSY: Indicates status of the internal WSM. When low, it

indicates that the WSM is busy performing an operation. RY/BY# high

indicates that the WSM is ready for new operations (or WSM has

completed all pending operations), or block erase is suspended, or the

device is in deep power-down mode. This output is always active (i.e., not

floated to tri-state off when OE# or CE0#,CE1# are high), except if a

RY/BY# Pin Disable command is issued.

WP# INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile

lock-bit for each block. When WP# is low, those locked blocks as

reflected by the Block-Lock Status bits (BSR.6), are protected from

inadvertent data programs or block erases. When WP# is high, all blocks

can be written or erased regardless of the state of the lock-bits. The WP#

input buffer is disabled when RP# transitions low (deep power-down

mode).

BYTE# INPUT BYTE ENABLE: BYTE# low places device in x8 mode. All data is then

input or output on DQ0–7, and DQ8–15 float. Address A0 selects between

the high and low byte. BYTE# high places the device in x16 mode, and

turns off the A0 input buffer. Address A1 then becomes the lowest order

address.

3/5# INPUT 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V

operation. 3/5# low configures internal circuits for 5.0V operation.

NOTES:

Reading the array with 3/5# high in a 5.0V system could damage the

device.

There is a significant delay from 3/5# switching to valid data.

VPP SUPPLY ERASE/PROGRAM POWER SUPPLY: For erasing memory array blocks

or writing words/bytes/pages into the flash array.

VCC SUPPLY DEVICE POWER SUPPLY (3.3V ± 10%, 5.0V ± 10%, 5.0V ± 5%):

Do not leave any power pins floating.

GND SUPPLY GROUND FOR ALL INTERNAL CIRCUITRY:

Do not leave any ground pins floating.

NC NO CONNECT:

Lead may be driven or left floating.

28F016SA E

E28F016SA

56-LEAD TSOP PINOUT

1.2 mm x 14 mm x 20 mm

TOP VIEW

28F032SA 28F016SV 28F032SA28F016SV

3/5#

RP#

GND

CE #

WP#

WE#

OE#

RY/BY#

GND

BYTE#

WP#

WE#

OE#

RY/BY#

GND

BYTE#

WP#

WE#

OE#

RY/BY#

GND

BYTE#

3/5#

RP#

GND

CE #

3/5#

RP#

GND

CE #

NCNC NC

0489_02

NOTE:

56-Lead TSOP Mechanical Diagrams and Dimensions are shown at the end of this specification.

Figure 2. TSOP Pinout Configuration

E28F016SA

DA28F016SA

56-LEAD SSOP

STANDARD PINOUT

1.8 mm x 16 mm x 23.7 mm

TOP VIEW

28F016SV

RP#

GND

BYTE#

GND

RP#

GND

BYTE#

GND

28F016SV

RY/BY#

WE#

WP#

OE#

GND

CE #

RY/BY#

3/5#

WE#

WP#

OE#

GND

CE #

3/5#

0489_17

Figure 3. SSOP Pinout Configuration

28F016SA E

3.0 MEMORY MAPS

64-Kbyte Block

1FFFFF

1F0000

1EFFFF

1E0000

1DFFFF

1D0000

1CFFFF

1C0000

1BFFFF

1B0000

1AFFFF

1A0000

19FFFF

190000

18FFFF

180000

17FFFF

170000

16FFFF

160000

15FFFF

150000

14FFFF

140000

13FFFF

130000

12FFFF

120000

11FFFF

110000

10FFFF

100000

0FFFFF

0F0000

0EFFFF

0E0000

0DFFFF

0D0000

0CFFFF

0C0000

0BFFFF

0B0000

0AFFFF

0A0000

09FFFF

090000

08FFFF

080000

07FFFF

070000

06FFFF

060000

05FFFF

050000

04FFFF

040000

03FFFF

030000

02FFFF

020000

01FFFF

010000

00FFFF

000000

64-Kbyte Block

[20-0]

0489_03

Figure 4. 28F016SA Memory Map (Byte-Wide Mode)

E28F016SA

3.1 Extended Status Register Memory Map

x8 MODE A[20-0]

1F0004H

1F0003H

1F0002H

1F0000H

1F0001H

1F0005H

1F0006H

000004H

000003H

000002H

000000H

000001H

000006H

000005H

010002H

RESERVED

GSR

RESERVED

BSR 0

RESERVED

GSR

RESERVED

BSR 31

RESERVED

0489_04

Figure 5. Extended Status Register Memory

Map (Byte-Wide Mode)

x16 MODE A[20-1]

00002H

00000H

00001H

00003H

08001H

RESERVED

GSR

RESERVED

BSR 0

RESERVED

F8002H

F8000H

F8001H

F8003H

RESERVED

GSR

RESERVED

BSR 31

RESERVED

0489_05

Figure 6. Extended Status Register Memory

Map (Word-Wide Mode)

28F016SA E

4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS

4.1 Bus Operations for Word-Wide Mode (BYTE# = VIH)

Mode Notes RP# CE1#CE

# OE# WE# A1DQ0–15 RY/BY#

Read 1,2,7 VIH VIL VIL VIL VIH XD

OUT X

Output Disable 1,6,7 VIH VIL VIL VIH VIH X High Z X

Standby 1,6,7 VIH VIL

VIH

VIL

VIH

X X X High Z X

Deep Power-Down 1,3 VIL XXXXXHigh Z VOH

Manufacturer ID 4 VIH VIL VIL VIL VIH VIL 0089H VOH

Device ID 4 VIH VIL VIL VIL VIH VIH 66A0H VOH

Write 1,5,6 VIH VIL VIL VIH VIL XD

IN X

4.2 Bus Operations for Byte-Wide Mode (BYTE# = VIL)

Mode Notes RP# CE1#CE

# OE# WE# A0DQ0–7 RY/BY#

Read 1,2,7 VIH VIL VIL VIL VIH XD

OUT X

Output Disable 1,6,7 VIH VIL VIL VIH VIH X High Z X

Standby 1,6,7 VIH VIL

VIH

VIL

VIH

X X X High Z X

Deep Power-Down 1,3 VIL XXXXXHigh Z VOH

Manufacturer ID 4 VIH VIL VIL VIL VIH VIL 89H VOH

Device ID 4 VIH VIL VIL VIL VIH VIH A0H VOH

Write 1,5,6 VIH VIL VIL VIH VIL XD

IN X

NOTES:

1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH.

2. RY/BY# output is open drain. When the WSM is ready, block erase is suspended or the device is in deep power-down

mode. RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM

operation is in progress.

3. RP# at GND ± 0.2V ensures the lowest deep power-down current.

4. A0 and A1 at VIL provide manufacturer ID codes in x8 and x16 modes, respectively. A0 and A1 at VIH provide device ID

codes in x8 and x16 modes, respectively. All other addresses are set to zero.

5. Commands for different block erase operations, data program operations or lock-block operations can only be successfully

completed when VPP = VPPH.

6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes to

VOH when the WSM is not busy or in erase suspend mode.

7. RY/BY# may be at VOL while the WSM is busy performing various operations; for example, a Status Register read during a

data program operation.

E28F016SA

4.3 28F008SA–Compatible Mode Command Bus Definitions

First Bus Cycle Second Bus Cycle

Command Notes Oper Addr Data(4) Oper Addr Data

Read Array Write X xxFFH Read AA AD

Intelligent Identifier 1 Write X xx90H Read IA ID

Read Compatible Status Register 2 Write X xx70H Read X CSRD

Clear Status Register 3 Write X xx50H

Word/Byte Program Write X xx40H Write PA PD

Alternate Word/Byte Program Write X xx10H Write PA PD

Block Erase/Confirm Write X xx20H Write BA xxD0H

Erase Suspend/Resume Write X xxB0H Write X xxD0H

ADDRESS DATA

A = Array Address AD = Array Data

BA = Block Address CSRD = CSR Data

IA = Identifier Address ID = Identifier Data

PA = Program Address PD = Program Data

X = Don’t Care

NOTES:

1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.

2. The CSR is automatically available after device enters data program, block erase, or suspend operations.

3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits.

4. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation of the device.

See Status Register definitions.

28F016SA E

4.4 28F016SA–Performance Enhancement Command Bus Definitions

First Bus Cycle Second Bus Cycle Third Bus Cycle

Command Mode Notes Oper Addr Data(12) Oper Addr Data(12) Oper Addr Data

Read Extended

Status Register 1 Write X xx71H Read RA GSRD

BSRD

Page Buffer Swap 7 Write X xx72H

Read Page Buffer Write X xx75H Read PBA PD

Single Load to Page

Buffer Write X xx74H Write PBA PD

Sequential Load to

Page Buffer x8 4,6,10 Write X xxE0H Write X BCL Write X BCH

x16 4,5,6,10 Write X xxE0H Write X WCL Write X WCH

Page Buffer Write to

Flash x8 3,4,9,10 Write X xx0CH Write A0BC(L,H) Write PA BC(H,L)

x16 4,5,10 Write X xx0CH Write X WCL Write PA WCH

Two-Byte Program x8 3 Write X xxFBH Write A0WD(L,H) Write PA WD(H,L)

Lock Block/Confirm Write X xx77H Write BA xxD0H

Upload Status

Bits/Confirm 2 Write X xx97H Write X xxD0H

Upload Device

Information Write X xx99H Write X xxD0H

Erase All Unlocked

Blocks/Confirm Write X xxA7H Write X xxD0H

RY/BY# Enable to

Level-Mode 8 Write X xx96H Write X xx01H

RY/BY# Pulse-On-

Write 8 Write X xx96H Write X xx02H

RY/BY# Pulse-On-

Erase 8 Write X xx96H Write X xx03H

RY/BY# Disable 8 Write X xx96H Write X xx04H

Sleep 11 Write X xxF0H

Abort Write X xx80H

ADDRESS DATA

BA = Block Address AD = Array Data WC (L,H) = Word Count (Low, High)

PBA = Page Buffer Address PD = Page Buffer Data BC (L,H) = Byte Count (Low, High)

RA = Extended Register Address BSRD = BSR Data WD (L,H) = Write Data (Low, High)

PA = Program Address GSRD = GSR Data

X = Don’t Care

E28F016SA

NOTES:

1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register Memory Maps.

2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the

actual lock-bit status.

3. A0 is automatically complemented to load the second byte of data. BYTE# must be at VIL.

The A0 value determines which WD/BC is supplied first: A0 = 0 looks at the WDL/BCL, A0 = 1 looks at the WDH/BCH.

4. BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the

Page Buffer contents into more than one 256-byte segment within an array block. They are simply shown for future Page

Buffer expandability.

5. In x16 mode, only the lower byte DQ0–7 is used for WCL and WCH. The upper byte DQ8–15 is a don’t care.

6. PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.

7. This command allows the user to swap between available Page Buffers (0 or 1).

8. These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/BY# function.

9. Program address, PA, is the destination address in the flash array which must match the source address in the Page

Buffer. Refer to the

16-Mbit Flash Product Family User’s Manual

10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.

11. To ensure that the 28F016SA’s power consumption during sleep mode reaches the deep power-down current level, the

system also needs to de-select the chip by taking either or both CE0# or CE1# high.

12. The upper byte of the data bus (DQ8–15) during command writes is a “Don’t Care” in x16 operation of the device.

28F016SA E

4.5 Compatible Status Register

WSMS ESS ES DWS VPPS R R R

76543210

NOTES:

CSR.7 = WRITE STATE MACHINE STATUS

1 = Ready

0 = Busy

RY/BY# output or WSMS bit must be checked to

determine completion of an operation (erase

suspend, block erase or data program) before the

appropriate Status bit (ESS, ES or DWS) is

checked for success.

CSR.6 = ERASE-SUSPEND STATUS

1 = Erase Suspended

0 = Erase In Progress/Completed

CSR.5 = ERASE STATUS

1 = Error In Block Erasure

0 = Successful Block Erase

If DWS and ES are set to “1” during a block

erase attempt, an improper command sequence

was entered. Clear the CSR and attempt the

operation again.

CSR.4 = DATA WRITE STATUS

1 = Error in Data Program

0 = Data Program Successful

CSR.3 = VPP STATUS

1 = VPP Low Detect, Operation Abort

0 = VPP OK

The VPPS bit, unlike an A/D converter, does not

provide continuous indication of V

PP level. The

WSM interrogates VPP

’s level only after the Data

Program or Block Erase command sequences

have been entered, and informs the system if

VPP has not been switched on. VPPS is not

guaranteed to report accurate feedback between

VPPL and VPPH.

CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS

These bits are reserved for future use; mask them out when polling the CSR.

E28F016SA

4.6 Global Status Register

WSMS OSS DOS DSS QS PBAS PBS PBSS

76543210

NOTES:

GSR.7 = WRITE STATE MACHINE STATUS

1 = Ready

0 = Busy

[1] RY/BY# output or WSMS bit must be checked

to determine completion of an operation (block

lock, erase suspend, any RY/BY# reconfig-

uration, Upload Status Bits, block erase or data

program) before the appropriate Status bit (OSS

or DOS) is checked for success.

GSR.6 = OPERATION SUSPEND STATUS

1 = Operation Suspended

0 = Operation in Progress/Completed

GSR.5 = DEVICE OPERATION STATUS

1 = Operation Unsuccessful

0 = Operation Successful or Currently

Running

GSR.4 = DEVICE SLEEP STATUS

1 = Device in Sleep

0 = Device Not in Sleep

MATRIX 5/4

0 0 = Operation Successful or Currently

Running

0 1 = Device in Sleep Mode or Pending

Sleep

1 0 = Operation Unsuccessful

1 1 = Operation Unsuccessful or

Aborted

If operation currently running, then GSR.7 = 0.

If device pending sleep, then GSR.7 = 0.

Operation aborted: Unsuccessful due to Abort

command.

GSR.3 = QUEUE STATUS

1 = Queue Full

0 = Queue Available

GSR.2 = PAGE BUFFER AVAILABLE STATUS

1 = One or Two Page Buffers Available

0 = No Page Buffer Available The device contains two Page Buffers.

GSR.1 = PAGE BUFFER STATUS

1 = Selected Page Buffer Ready

0 = Selected Page Buffer Busy Selected Page Buffer is currently busy with WSM

operation.

GSR.0 = PAGE BUFFER SELECT STATUS

1 = Page Buffer 1 Selected

0 = Page Buffer 0 Selected

NOTE:

1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.

GSR.7 provides indication when all queued operations are completed.

28F016SA E

4.7 Block Status Register

BS BLS BOS BOAS QS VPPS R R

76543210

NOTES:

BSR.7 = BLOCK STATUS

1 = Ready

0 = Busy

[1] RY/BY# output or BS bit must be checked to

determine completion of an operation (block lock,

erase suspend, any RY/BY# reconfiguration, Upload

Status Bits, block erase or data program) before the

appropriate Status bits (BOS, BLS) is checked for

success.

BSR.6 = BLOCK-LOCK STATUS

1 = Block Unlocked for Program/Erase

0 = Block Locked for Program/Erase

BSR.5 = BLOCK OPERATION STATUS

1 = Operation Unsuccessful

0 = Operation Successful or Currently

Running

The BOAS bit will not be set until BSR.7 = 1.

BSR.4 = BLOCK OPERATION ABORT STATUS

1 = Operation Aborted

0 = Operation Not Aborted

MATRIX 5/4

0 0 = Operation Successful or

Currently Running

0 1 = Not a Valid Combination

1 0 = Operation Unsuccessful

1 1 = Operation Aborted Operation halted via Abort command.

BSR.3 = QUEUE STATUS

1 = Queue Full

0 = Queue Available

BSR.2 = VPP STATUS

1 = VPP Low Detect, Operation Abort

0 = VPP OK

BSR.1–0 = RESERVED FOR FUTURE ENHANCEMENTS

These bits are reserved for future use; mask them out when polling the BSRs.

NOTE:

1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.

GSR.7 provides indication when all queued operations are completed.

E28F016SA

5.0 ELECTRICAL SPECIFICATIONS

5.1 Absolute Maximum Ratings*

Temperature under Bias.....................0°C to +80°C

Storage Temperature....................–65°C to +125°C

NOTICE: This is a production datasheet. The specifications

are subject to change without notice. Verify with your local

Intel Sales office that you have the latest datasheet before

finalizing a design.

* WARNING: Stressing the device beyond the “Absolute

Maximum Ratings” may cause permanent damage. These

are stress ratings only. Operation beyond the “Operating

Conditions” is not recommended and extended exposure

beyond the "Operating Conditions" may effect device

reliability.

VCC = 3.3V ± 10% Systems

Sym Parameter Notes Min Max Units Test Conditions

TAOperating Temperature, Commercial 1 0 70 °C Ambient Temperature

VCC VCC with Respect to GND 2 –0.2 7.0 V

VPP VPP Supply Voltage with Respect to GND 2,3 –0.2 14.0 V

VVoltage on Any Pin (Except VCC, VPP)

with Respect to GND 2 –0.5 VCC

+0.5 V

I Current into Any Non-Supply Pin 5 ± 30 mA

IOUT Output Short Circuit Current 4 100 mA

VCC = 5.0V ± 10% , VCC = 5.0V ± 5% Systems(6)

Sym Parameter Notes Min Max Units Test Conditions

TAOperating Temperature, Commercial 1 0 70 °C Ambient Temperature

VCC VCC with Respect to GND 2 –0.2 7.0 V

VPP VPP Supply Voltage with Respect to GND 2,3 –0.2 14.0 V

V Voltage on Any Pin (Except VCC, VPP)

with Respect to GND 2 –2.0 7.0 V

I Current into Any Non-Supply Pin 5 ± 30 mA

IOUT Output Short Circuit Current 4 100 mA

NOTES:

1. Operating temperature is for commercial product defined by this specification.

2. Minimum DC voltage is –10% on input/output pins. During transitions, this level may undershoot to –2.0V for periods

<20 ns. Maximum DC voltage on input/output pins is VCC + 10% which, during transitions, may overshoot to VCC + 2.0V for

periods <20 ns.

3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns.

4. Output shorted for no more than one second. No more than one output shorted at a time.

5. This specification also applies to pins marked “NC.”

6. 5% VCC specifications refer to the 28F016SA-070 in its High Speed Test configuration.

28F016SA E

5.2 Capacitance

For a 3.3V System:

Symbol Parameter Notes Typ Max Units Test Conditions

CIN Capacitance Looking into an

Address/Control Pin 1 68pFT

A = +25°C, f = 1.0 MHz

COUT Capacitance Looking into an

Output Pin 1 8 12 pF TA = +25°C, f = 1.0 MHz

CLOAD Load Capacitance Driven by

Outputs for Timing Specifications 1 50 pF For VCC = 3.3V ± 10%

Equivalent Testing Load Circuit 2.5 ns 50Ω Transmission Line

Delay

For a 5.0V System:

Symbol Parameter Notes Typ Max Units Test Conditions

CIN Capacitance Looking into an

Address/Control Pin 1 68pFT

A = +25°C, f = 1.0 MHz

COUT Capacitance Looking into an

Output Pin 1 8 12 pF TA = +25°C, f = 1.0 MHz

CLOAD Load Capacitance Driven by

Outputs for Timing Specifications 1 100 pF For VCC = 5.0V ± 10%

30 pF For VCC = 5.0V ± 5%

Equivalent Testing Load Circuit for

VCC ± 10% 2.5 ns 25Ω Transmission Line

Delay

Equivalent Testing Load Circuit for

VCC ± 5% 2.5 ns 83Ω Transmission Line

Delay

NOTE:

1. Sampled, not 100% tested.

E28F016SA

5.3 Timing Nomenclature

All 3.3V system timings are measured from where signals cross 1.5V.

For 5.0V systems use the standard JEDEC cross point definitions.

Each timing parameter consists of five characters. Some common examples are defined below:

tCE tELQV time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V)

tOE tGLQV time(t) from OE# (G) going low (L) to the outputs (Q) becoming valid (V)

tACC tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)

tAS tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H)

tDH tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)

Pin Characters Pin States

A Address Inputs H High

D Data Inputs L Low

Q Data Outputs V Valid

E CE# (Chip Enable) X Driven, but not necessarily valid

F BYTE# (Byte Enable) Z High Impedance

G OE# (Output Enable)

W WE# (Write Enable)

P RP# (Deep Power-Down Pin)

R RY/BY# (Ready Busy)

V Any Voltage Level

Y 3/5# Pin

5V VCC at 4.5V Minimum

3V VCC at 3.0V Minimum

28F016SA E

TEST POINTS

INPUT OUTPUT

2.0

0.8 0.8

2.0

2.4

0.45

0489_06

AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic “0.” Input timing begins at VIH

(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.

Figure 7. Transient Input/Output Reference Waveform (VCC = 5.0V ± 10%)

for Standard Test Configuration(1)

TEST POINTSINPUT OUTPUT

1.5

3.0

0.0

1.5

0489_07

AC test inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0.” Input timing begins, and output timing ends, at 1.5V.

Input rise and fall times (10% to 90%) <10 ns.

Figure 8. Transient Input/Output Reference Waveform (VCC = 3.3V ± 10%)

High Speed Reference Waveform(2) (VCC = 5.0V ± 5%)

NOTES:

1. Testing characteristics for 28F016SA-080/28F016SA-100.

2. Testing characteristics for 28F016SA-070/28F016SA-120/28F016SA-150.

E28F016SA

From Output

under Test

Test

Point

Total Capacitance = 100 pF

2.5 ns of 25 Transmission Line

Ω

0489_08

Figure 9. Transient Equivalent Testing Load Circuit (VCC = 5.0V ± 10%)

From Output

under Test

Test

Point

Total Capa ci ta nce = 50 pF

2.5 ns of 50

Transmission Line

Ω

0489_09

Figure 10. Transient Equivalent Testing Load Circuit (VCC = 3.3V ± 10%)

From Output

under Test

Test

Point

Total Capa citanc e = 30 pF

2.5 ns of 83

Transmission Line

Ω

0489_10

Figure 11. High Speed Transient Equivalent Testing Load Circuit (VCC = 5.0V ± 5%)

28F016SA E

5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

Vcc = 3.3V ±10%, TA = 0°C to +70°C, –40°C to +85°C

3/5# = Pin Set High for 3.3V Operations

Temp Comm Extended

Sym Parameter Notes Typ Max Typ Max Units Test Conditions

IIL Input Load Current 1 ± 1 ± 1 µA VCC = VCC Max

VIN = VCC or GND

ILO Output Leakage

Current 1 ± 10 ± 10 µA VCC = VCC Max

VIN = VCC or GND

ICCS VCC Standby

Current 1,5,6 50 100 70 250 µA VCC = VCC Max

CE0#, CE1#, RP#, = VCC ±

0.2V

BYTE#, WP#, 3/5# = VCC

± 0.2V or GND ± 0.2V

14110mA

CC = VCC Max

CE0#, CE1#, RP# = VIH

BYTE#, WP#, 3/5# = VIH

or VIL

ICCD VCC Deep Power-

Down Current 115

335µA RP# = GND ± 0.2V

BYTE# = GND ± 0.2V or

VCC ± 0.2V

ICCR1V

CC Read Current 1,4,5 30 35 30 40 mA VCC = VCC Max

CMOS: CE0#, CE1# =

GND ± 0.2V, BYTE# =

GND ± 0.2V or VCC ±

0.2V, Inputs = GND ±

0.2V or VCC ± 0.2V

TTL: CE0#, CE1# = VIL,

BYTE# = VIL or VIH,

Inputs = VIL or VIH

f = 8 MHz, IOUT = 0 mA

ICCR2V

CC Read Current 1,4,5 15 20 15 25 mA VCC = VCC Max

CMOS: CE0#, CE1# =

GND ± 0.2V, BYTE# =

GND ± 0.2V or VCC ±

0.2V, Inputs = GND ±

0.2V or VCC ± 0.2V

TTL: CE0#, CE1# = VIL,

BYTE# = VIL or VIH,

Inputs = VIL or VIH

f = 4 MHz, IOUT = 0 mA

ICCW VCC Program Current

for Word or Byte 1 8 12 8 12 mA Program in Progress

ICCE VCC Block Erase

Current 1 6 12 6 12 mA Block Erase in Progress

ICCES VCC Erase Suspend

Current 1,2 3 6 3 6 mA CE0#, CE1# = VIH

Block Erase Suspended

E28F016SA

5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

(Continued)

Vcc = 3.3V ±10%, TA = 0°C to +70°C, –40°C to +85°C

3/5# = Pin Set High for 3.3V Operations

Temp Comm Extended

Sym Parameter Notes Typ Max Typ Max Units Test Conditions

IPPS VPP Standby/ 1 ± 1 ± 10 ± 1 ± 10 µA VPP ≤ VCC

IPPR Read Current 65 200 65 200 µA VPP > VCC

IPPD VPP Deep Power-

Down Current 1 0.2 5 0.2 5 µA RP# = GND ± 0.2V

28F016SA E

5.4 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

(Continued)

Vcc = 3.3V ± 10%, TA = 0°C to +70°C, –40°C to +85°C

3/5# = Pin Set High for 3.3V Operations

Temp Comm/Extended

Sym Parameter Notes Min Typ Max Units Test Conditions

IPPW VPP Program Current for

Word or Byte 11015mA

PP = VPPH

Program in Progress

IPPE VPP Block Erase

Current 1 4 10 mA VPP = VPPH

Block Erase in Progress

IPPES VPP Erase Suspend

Current 1 65 200 µA VPP = VPPH

Block Erase Suspended

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.0 VCC

0.3

VOL Output Low Voltage 0.4 V VCC = VCC Min

IOL = 4 mA

VOH1 Output High Voltage 2.4 V VCC = VCC Min

IOH = –2.0 mA

VOH2 VCC

–0.2 VVCC = VCC Min

IOH = –100 µA

VPPL VPP during Normal

Operations 3 0.0 6.5 V

VPPH VPP during Program/

Erase Operations 3 11.4 12.0 12.6 V

VLKO VCC Program/Erase

Lock Voltage 2.0 V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12.0V, T = 25°C. These currents are

valid for all product versions (package and speeds).

2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of

ICCES and ICCR.

3. Block erases, word/byte programs and lock block operations are inhibited when VPP = VPPL and not guaranteed in the

range between VPPH and VPPL.

4. Automatic Power Savings (APS) reduces ICCR to less than 1 mA in static operation.

5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.

6. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer.

Default the device into read array or read Status Register mode before entering standby to ensure standby current levels.

E28F016SA

5.5 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

VCC = 5.0V ± 10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

3/5# Pin Set Low for 5V Operations

Temp Comm Extended

Sym Parameter Notes Typ Max Typ Max Units Test Conditions

IIL Input Load Current 1 ± 1 ± 1 µA VCC = VCC Max

VIN = VCC or GND

ILO Output Leakage

Current 1 ± 10 ± 10 µA VCC = VCC Max

VIN = VCC or GND

ICCS VCC Standby Current 1,5,6 50 100 70 250 µA VCC = VCC Max

CE0#, CE1#, RP# = VCC ±

0.2V

BYTE#, WP#, 3/5# = VCC

± 0.2V or GND ± 0.2V

24210mA

CC = VCC Max

CE0#, CE1#, RP# = VIH

BYTE#, WP#, 3/5# = VIH

or VIL

ICCD VCC Deep Power-

Down Current 1151060µA

RP# = GND ± 0.2V

BYTE# = GND ± 0.2V or

VCC ± 0.2V

ICCR1V

CC Read Current 1,4,5 50 60 55 70 mA VCC = VCC Max

CMOS: CE0#, CE1# =

GND ±

0.2V, BYTE# = GND ±

0.2V or VCC ± 0.2V,

Inputs = GND ± 0.2V or

VCC ± 0.2V

TTL: CE0#, CE1# = VIL,

BYTE# = VIL or VIH,

Inputs = VIL or VIH

f = 10 MHz, IOUT = 0 mA

ICCR2V

CC Read Current 1,4,5 30 35 30 35 mA VCC = VCC Max

CMOS: CE0#, CE1# =

GND ± 0.2V, BYTE# =

GND ± 0.2V or VCC ±

0.2V, Inputs = GND ±

0.2V or VCC ± 0.2V

TTL: CE0#, CE1# = VIL,

BYTE# = VIL or VIH,

Inputs = VIL or VIH

f = 5 MHz, IOUT = 0 mA

ICCW VCC Program Current

for Word or Byte 1 25 35 25 35 mA Program in Progress

ICCE VCC Block Erase

Current 1 18 25 18 25 mA Block Erase in Progress

ICCES VCC Erase Suspend

Current 1,2 5 10 5 10 mA CE0#, CE1# = VIH

Block Erase Suspended

28F016SA E

5.5 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

(Continued)

VCC = 5.0V ± 10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

3/5# Pin Set Low for 5V Operations

Temp Comm Extended

Sym Parameter Notes Typ Max Typ Max Units Test Conditions

IPPS VPP Standby/Read 1 ± 1 ± 10 ± 1 ± 10 µA VPP ≤ VCC

IPPR Current 65 200 65 200 µA VPP > VCC

IPPD VPP Deep Power-

Down Current 1 0.2 5 0.2 5 µA RP# = GND ± 0.2V

E28F016SA

5.5 DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE

(Continued)

VCC

= 5.0V ± 10%, 5.0V ± 5%,TA = 0°C to +70°C, -40°C to +85°C

3/5# Pin Set Low for 5V Operations

Temp Comm/Extended

Sym Parameter Notes Min Typ Max Units Test Conditions

IPPW VPP Program Current for

Word or Byte 1 7 12 mA VPP = VPPH

Program in Progress

IPPE VPP Block Erase

Current 1 5 10 mA VPP = VPPH

Block Erase in Progress

IPPES VPP Erase Suspend

Current 1 65 200 µA VPP = VPPH

Block Erase Suspended

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.0 VCC

+0.5 V

VOL Output Low Voltage 0.45 V VCC = VCC Min

IOL = 5.8 mA

VOH1 Output High Voltage 0.85

VCC VV

CC = VCC Min

IOH = –2.5 mA

VOH2 VCC

–0.4 VV

CC = VCC Min

IOH = –100 µA

VPPL VPP during Normal

Operations 3 0.0 6.5 V

VPPH VPP during Program/

Erase Operations 11.4 12.0 12.6 V

VLKO VCC Program/Erase

Lock Voltage 2.0 V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP = 12.0V, T = 25°C. These currents are

valid for all product versions (package and speeds).

2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum of

ICCES and ICCR.

3. Block erases, word/byte programs and lock block operations are inhibited when VPP = VPPL and not guaranteed in the

range between VPPH and VPPL.

4. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in static operation.

5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.

6. Standby current levels are not reached when putting the chip in standby mode immediately after reading the page buffer.

Default the device into read array or read Status Register mode before entering standby to ensure standby current levels.

28F016SA E

5.6 AC Characteristics–Read Only Operations:

COMMERCIAL AND EXTENDED TEMPERATURE(1)

VCC = 3.3V ± 10%, TA = 0°C to +70°C, –40°C to +85°C

Temp Commercial Extended

Speed –120 –150 –150

Sym Parameter VCC 3.3V ± 10% Units

Load 50 pF

Notes Min Max Min Max Min Max

tAVAV Read Cycle Time 120 150 150 ns

tAVQV Address to Output Delay 120 150 150 ns

tELQV CE# to Output Delay 2 120 150 150 ns

tPHQV RP# High to Output

Delay 620 750 750 ns

tGLQV OE# to Output Delay 2 45 50 50 ns

tELQX CE# to Output in Low Z 3 0 0 0 ns

tEHQZ CE# to Output in High Z 3 30 35 35 ns

tGLQX OE# to Output in Low Z 3 0 0 0 ns

tGHQZ OE# to Output in High Z 3 15 20 20 ns

tOH Output Hold from

Address, CE# or OE#

Change, Whichever

Occurs First

3000ns

FLQV

tFHQV BYTE# to Output Delay 3 120 150 150 ns

tFLQZ BYTE# Low to Output in

High Z 3 304040ns

ELFL

tELFH CE# Low to BYTE# High

or Low 3555ns

For Extended Status Register Reads

Temp Commercial Extended

Speed –120 –150

Symbol Parameter VCC 3.3V ± 10% Units

Load 50 pF

Notes Min Max Min Max

tAVEL Address Setup to CE# Going Low 3,4 0 0 ns

tAVGL Address Setup to OE# Going Low 3,4 0 0 ns

E28F016SA

5.6 AC Characteristics–Read Only Operations:

COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued)

VCC = 5.0V ± 10%, 5.0V ± 5%, TA = 0°C to +70°C. –40°C to +85°C

Temp Commercial Comm/Ext

Speed –70 –80 –100

Sym Parameter VCC 5.0V ± 5%V 5.0V ± 10%V 5.0V ± 10%V Units

Load 30 pF 50 pF 50%

Notes Min Max Min Max Min Max

tAVAV Read Cycle Time 70 80 100 ns

tAVQV Address to Output Delay 70 80 100 ns

tELQV CE# to Output Delay 2 70 80 100 ns

tPHQV RP# to Output Delay 400 480 550 ns

tGLQV OE# to Output Delay 2 30 35 40 ns

tELQX CE# to Output in Low Z 3 0 0 0 ns

tEHQZ CE# to Output in High Z 3 25 30 30 ns

tGLQX OE# to Output in Low Z 3 0 0 0 ns

tGHQZ OE# to Output in High Z 3 15 15 15 ns

tOH Output Hold from

Address, CE# or OE#

Change, Whichever

Occurs First

3000ns

FLQV

tFHQV

BYTE# to Output Delay 3 70 80 100 ns

tFLQZ BYTE# Low to Output in

High Z 3 253030ns

ELFL

tELFH CE# Low to BYTE# High

or Low 3555ns

28F016SA E

For Extended Status Register Reads

Temp Commercial Commercial Comm/Ext

Load 30 pF 50 pF 50 pF

Versions(5) VCC ± 5% 28F016SA-070(6) Units

VCC ± 10% 28F016SA-080(7) 28F016SA-100(7)

Sym Parameter Notes Min Max Min Max Min Max

tAVEL Address

Setup to CE#

Going Low

3,4 0 0 0 ns

tAVGL Address

Setup to OE#

Going Low

3,4 0 0 0 ns

NOTES:

1. See AC Input/Output Reference Waveforms for timing measurements,

Figures 7 and 8.

2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.

3. Sampled, not 100% tested.

4. This timing parameter is used to latch the correct BSR data onto the outputs.

5. Device speeds are defined as:

70/80 ns at VCC = 5.0V equivalent to

120 ns at VCC = 3.3V

100 ns at VCC = 5.0V equivalent to

150 ns at VCC = 3.3V

6. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for High Speed Test Configuration.

7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.

E28F016SA

HIGH ZHIGH Z

ADDRESSES STABLE

VALID OUTPUT

GND

5.0V

PHQV

AVQV

GLQV

ELQV

GLQX

ELQX

AVAV

EHQZ

GHQZ

ADDRESSES (A)

OE# (G)

WE# (W )

DATA (D/Q)

RP# (P)

AVGL

AVEL

CEx# (E)

(1)

0489_11

NOTE:

1. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

Figure 12. Read Timing Waveforms

28F016SA E

HIGH Z

ADDRESSES STABLE

AVQV

GLQV

ELQV

GLQX

ELQX

AVAV

EHQZ

GHQZ

ADDRESSES (A)

BYTE# (F)

DATA (DQ0-DQ7)

OE# (G)

AVFL

ELFL

FLQV

= t

AVQV

DATA

OUTPUT

= t

ELFL

HIGH Z DATA

OUTPUT

DATA OUTPUT

HIGH Z

DATA (DQ8-DQ15)

FLQZ

AVEL

AVGL

CEx #(E)

(1)

0489_12

NOTE:

1. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

Figure 13. BYTE# Timing Waveforms

E28F016SA

5.7 Power-Up and Reset Timings: COMMERCIAL/EXTENDED TEMPERATURE

RP#

3/5#

3.3V

V Power-Up

5.0V

(P)

(Y)

(3V,5V)

4.5V

PLYL

PL5V

YLPH

YHPH

Valid 5.0V Outputs

Valid Valid

Address

Data

Valid 3.3V Outputs

AVQV

(A)

(Q)

AVQV

PHQV

PHEL3

CE #

PHEL5

0489_13

Figure 14. VCC Power-Up and RP# Reset Waveforms

Symbol Parameter Notes Min Max Unit

tPLYL

tPLYH RP# Low to 3/5# Low (High) 0 µs

tYLPH

tYHPH 3/5# Low (High) to RP# High 1 2 µs

tPL5V

tPL3V RP# Low to VCC at 4.5V minimum

(to VCC at 3.0V min or 3.6V max) 20 µs

PHEL3 RP# High to CE# Low (3.3V VCC) 1 500 ns

tPHEL5 RP# High to CE# Low (5V VCC) 1 330 ns

tAVQV Address Valid to Data Valid for VCC = 5V ± 10% 3 80 ns

tPHQV RP# High to Data Valid for VCC = 5V ± 10% 3 480 ns

NOTES:

CE0#, CE1# and OE# are switched low after Power-Up.

1. The tYLPH/tYHPH and tPHEL3/tPHEL5 times must be strictly followed to guarantee all other read and program specifications.

2. The power supply may start to switch concurrently with RP# going low.

3. The address access time and RP# high to data valid time are shown for 5V VCC operation of the 28F016SA-080. Refer to

the AC Characteristics Read Only Operations for 3.3V VCC and all other speed options.

28F016SA E

5.8 AC Characteristics for WE#–Controlled Command Write Operations:

COMMERCIAL AND EXTENDED TEMPERATURE(1)

VCC = 3.3V ± 10%, TA = 0°C to +70°C, –40°C to +85°C

Temp Commercial Comm/Extended

Sym Parameter Notes Min Typ Max Min Typ Max Units

tAVAV Write Cycle Time 120 150 ns

tVPWH VPP Setup to WE# Going High 3 100 100 ns

tPHEL RP# Setup to CE# Going Low 480 480 ns

tELWL CE# Setup to WE# Going Low 10 10 ns

tAVWH Address Setup to WE# Going

High 2,6 75 75 ns

tDVWH Data Setup to WE# Going

High 2,6 75 75 ns

tWLWH WE# Pulse Width 75 75 ns

tWHDX Data Hold from WE# High 2 10 10 ns

tWHAX Address Hold from WE# High 2 10 10 ns

tWHEH CE# Hold from WE# High 10 10 ns

tWHWL WE# Pulse Width High 45 75 ns

tGHWL Read Recovery before Write 0 0 ns

tWHRL WE# High to RY/BY# Going

Low 100 100 ns

tRHPL RP# Hold from Valid Status

Data and RY/BY# High

30 0 ns

PHWL RP# High Recovery to WE#

Going Low 11µs

WHGL Write Recovery before Read 95 120 ns

tQVVL VPP Hold from Valid Status

Data and RY/BY# High

00µs

WHQV1 Duration of Word/Byte

Program Operation 4,5 5 9 Note

75 9 Note

7µs

tWHQV2 Duration of Block Erase

Operation 4 0.3 10 0.3 10 sec

E28F016SA

5.8 AC Characteristics for WE#–Controlled Command Write Operations:

COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued)

VCC = 5.0V ±10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

Temp Commercial Commercial Comm/Ext

Versions VCC ± 5% 28F016SA-070 Unit

VCC ± 10% 28F016SA-080 28F016SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

tAVAV Write Cycle

Time 70 80 100 ns

tVPWH V

Setup to

WE# Going

High

3 100 100 100 ns

tPHEL RP# Setup to

CE# Going

Low

480 480 480 ns

tELWL CE# Setup to

WE# Going

Low

000ns

AVWH Address Setup

to WE# Going

High

2,6 50 50 50 ns

tDVWH Data Setup to

WE# Going

High

2,6 50 50 50 ns

tWLWH WE# Pulse

Width 40 50 50 ns

tWHDX Data Hold

from WE#

High

20 0 0 ns

WHAX Address Hold

from WE#

High

210 10 10 ns

WHEH CE# Hold from

WE# High 10 10 10 ns

tWHWL WE# Pulse

Width High 30 30 50 ns

tGHWL Read

Recovery

before Write

000ns

28F016SA E

5.8 AC Characteristics for WE#–Controlled Command Write Operations:

COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued)

VCC = 5.0V ±10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

Temp Commercial Commercial Comm/Ext

Versions VCC ± 5% 28F016SA-070 Unit

VCC ± 10% 28F016SA-080 28F016SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

tWHRL WE# High to

RY/BY# Going

Low

100 100 100 ns

tRHPL RP# Hold from

Valid Status

(CSR, GSR,

BSR) Data

and RY/BY#

High

30 0 0 ns

PHWL RP# High

Recovery to

WE# Going

Low

111µs

tWHGL Write

Recovery

before Read

60 65 80 ns

tQVVL V

Hold from

Valid Status

(CSR, GSR,

BSR) Data

and RY/BY#

High

000µs

WHQV1Duration of

Word/Byte

Program

Operation

4,5 4.5 6 Note

74.5 6 Note

7µs

tWHQV2Duration of

Block Erase

Operation

4 0.3 10 0.3 10 0.3 10 sec

E28F016SA

NOTES:

CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

1. Read timings during data program and block erase are the same as for normal read.

2. Refer to command definition tables for valid address and data values.

3. Sampled, but not 100% tested.

4. Data program/block erase durations are measured to valid Status Register data.

5. Word/byte program operations are typically performed with 1 programming pulse.

6. Address and data are latched on the rising edge of WE# for all command write operations.

7. This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office

for more information.

WE# (W)

OE# (G)

RP# (P)

VPP

CEx # (E)

(V)

DEEP

POWER-DOWN

ADDRESSES (A)

WHEH

ELWL

WHDX

WHWL

WLWH

DVWH

VIH

PHWL

HIGH Z IN

QVVL

PPH

VPWH

READ EXTENDED

STATUS REGISTER DATA

DATA (D/Q)

WHQV1,2

WRITE DATA-WRITE OR

ERASE SETUP COMMAND

WRITE VALID ADDRESS

& DATA (DATA-WRITE) OR

ERASE CONFIRM COMMAND

AUTOMATED DATA-WRITE

OR ERASE DELAY

RY/BY# (R)

tWHRL

WHGL

ADDRESSES (A)

tAVAV

AVWH

ttWHAX

READ COMPATIBLE

STATUS REGISTER DATA

DIN

WRITE READ EXTENDED

A=RA

NOTE 1

NOTE 2

NOTE 3

NOTE 4

OUT

RHPL

GHWL

NOTE 5

PPL

tAVAV

AVWH

ttWHAX

0489_14

NOTES:

1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.

2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during data program/block erase operations.

4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

5. RP# low transition is only to show tRHPL; not valid for above read and program cycles.

Figure 15. AC Waveforms for Command Write Operations

28F016SA E

5.9 AC Characteristics for CE#–Controlled Command Write Operations:

COMMERCIAL AND EXTENDED TEMPERATURE(1)

VCC = 3.3V ±10%, TA = 0°C to +70°C, -40°C to +85°C

Temp Commercial Comm/Ext

Sym Parameter Speed -120 -150 Unit

Notes Min Typ Max Min Typ Max

tAVAV Write Cycle Time 120 150 ns

tVPEH VPP Setup to CE# Going High 3 100 100 ns

tPHWL RP# Setup to WE# Going Low 480 480 ns

tWLEL WE# Setup to CE# Going Low 0 0 ns

tAVEH Address Setup to CE# Going

High 2,6 75 75 ns

tDVEH Data Setup to CE# Going High 2,6 75 75 ns

tELEH CE# Pulse Width 75 75 ns

tEHDX Data Hold from CE# High 2 10 10 ns

tEHAX Address Hold from CE# High 2 10 10 ns

tEHWH WE Hold from CE# High 10 10 ns

tEHEL CE# Pulse Width High 45 75 ns

tGHEL Read Recovery before Write 0 0 ns

tEHRL CE# High to RY/BY# Going Low 100 100 ns

tRHPL RP# Hold from Valid Status

Data and RY/BY# High

30 0 ns

PHEL RP# High Recovery to CE#

Going Low 11µs

EHGL Write Recovery before Read 95 120 ns

tQVVL VPP Hold from Valid Status

Data and RY/BY# High

00µs

EHQV1 Duration of Word/Byte Program

Operation 4,5 5 9 Note

75 9 Note

7µs

tEHQV2 Duration of Block Erase

Operation 4 0.3 10 0.3 10 sec

E28F016SA

5.9 AC Characteristics for CE#–Controlled Command Write Operations:

COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued)

VCC = 5.0 to 10% , 5.0 ± 5%, TA = 0°C to +70°C, –40°C to +85°C

Temp Commercial Commercial Comm/Ext

Versions VCC ± 5% 28F016SA-070 Unit

VCC ± 10% 28F016SA-080 28F016SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

tAVAV Write Cycle

Time 70 80 100 ns

tVPEH VPP Setup to

CE# Going

High

3 100 100 100 ns

tPHWL RP# Setup to

WE# Going

Low

3 480 480 480 ns

tWLEL WE# Setup to

CE# Going Low 000ns

AVEH Address Setup

to CE# Going

High

2,6 50 50 50 ns

tDVEH Data Setup to

CE# Going

High

2,6 50 50 50 ns

tELEH CE# Pulse

Width 40 50 50 ns

tEHDX Data Hold from

CE# High 20 0 0 ns

EHAX Address Hold

from CE# High 210 10 10 ns

EHWH WE# Hold from

CE# High 10 10 10 ns

tEHEL CE# Pulse

Width High 30 30 50 ns

tGHEL Read Recovery

before Write 000ns

EHRL CE# High to

RY/BY# Going

Low

100 100 100 ns

28F016SA E

5.9 AC Characteristics for CE#–Controlled Command Write Operations:

COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued)

VCC = 5.0 to 10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

Temp Commercial Commercial Comm/Ext

Versions VCC ± 5% 28F016SA-070 Unit

VCC ± 10% 28F016SA-080 28F016SA-100

Sym Parameter Notes Min Typ Max Min Typ Max Min Typ Max

tRHPL RP# Hold from

Valid Status

GSR, BSR)

Data and

RY/BY# High

30 0 0 ns

PHEL RP# High

Recovery to

CE# Going Low

111µs

tEHGL Write Recovery

before Read 60 65 80 µs

tQVVL VPP Hold from

Valid Status

GSR, BSR)

Data and

RY/BY# High

000µs

EHQV1 Duration of

Word/Byte

Program

Operation

4,5 4.5 6 Note

74.5 6 Note

7µs

tEHQV2 Duration of

Block Erase

Operation

4 0.3 10 0.3 10 0.3 10 sec

NOTES:

CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

1. Read timings during data program and block erase are the same as for normal read.

2. Refer to command definition tables for valid address and data values.

3. Sampled, but not 100% tested.

4. Data program/block erase durations are measured to valid Status Register data.

5. Word/byte program operations are typically performed with 1 programming pulse.

6. Address and data are latched on the rising edge of CE# for all command write operations.

7. This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office

for more information.

E28F016SA

WE# (W)

OE# (G)

RP# (P)

VPP

CEx#(E)

(V)

DEEP

POWER-DOWN

ADDRESSES (A)

tAVAV

EHAX

EHWH

WLEL

tEHDX

EHEL

IL tELEH

tDVEH

VIH

PHEL

HIGH Z IN

tQVVL

PPH

PPL

tVPEH

READ EXTENDED

STATUS REGIST ER DA TA

DATA (D/Q)

EHQV1,2

WRITE DATA-WRITE OR

ERASE SETUP COMMAND

WRITE VALID ADDRESS

& DATA (DATA-WRITE) OR

ERASE CONFIRM COMMAND

AUTOMATED DATA-WRITE

OR ERASE DELAY

RY/BY# (R)

EHRL

ADDRESSES (A) IN

READ COMPATIBLE

STATUS REGISTER DATA

DIN

WRITE READ EXTENDED

A=RA

NOTE 1

NOTE 2

NOTE 3

NOTE 4

DOUT

AVEH

tRHPL

GHEL

NOTE 5

tAVAV

EHAXAVEH

EHGL

0489_15

NOTES:

1. This address string depicts data program/block erase cycles with corresponding verification via ESRD.

2. This address string depicts data program/block erase cycles with corresponding verification via CSRD.

3. This cycle is invalid when using CSRD for verification during data program/block erase operations.

4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

5. RP# low transition is only to show tRHPL; not valid for above read and program cycles.

Figure 16. Alternate AC Waveforms for Command Write Operations

28F016SA E

5.10 AC Characteristics for Page Buffer Write Operations:

COMMERCIAL AND EXTENDED TEMPERATURE(1)

VCC = 3.3V ± 10%, TA = 0°C to +70°C, –40°C to +85°C

Temp Commercial Comm/Ext

Sym Parameter Speed –120 –150 Unit

Notes Min Typ Max Min Typ Max

tAVAV Write Cycle Time 120 150 ns

tELWL CE# Setup to WE# Going Low 10 10 ns

tAVWL Address Setup to WE# Going Low 3 0 0 ns

tDVWH Data Setup to WE# Going High 2 75 75 ns

tWLWH WE# Pulse Width 75 75 ns

tWHDX Data Hold from WE# High 2 10 10 ns

tWHAX Address Hold from WE# High 2 10 10 ns

tWHEH CE# Hold from WE# High 10 10 ns

tWHWL WE# Pulse Width High 45 75 ns

tGHWL Read Recovery before Write 0 0 ns

tWHGL Write Recovery before Read 95 120 ns

E28F016SA

5.10 AC Characteristics for Page Buffer Write Operations:

COMMERCIAL AND EXTENDED TEMPERATURE(1) (Continued)

VCC = 5.0V ± 10%, 5.0V ± 5%, TA = 0°C to +70°C, –40°C to +85°C

Temp Commercial Commercial Comm/Ext

Sym Parameter Speed –70 –80 –100 Unit

VCC 5.0V ± 5% 5.0V ± 10% 5.0V ± 10%

Notes Min Typ Max Min Typ Max Min Typ Max

tAVAV Write Cycle Time 70 80 100 ns

tELWL CE# Setup to

WE# Going Low 000ns

AVWL Address Setup to

WE# Going Low 3000ns

DVWH Data Setup to

WE# Going High 2505050ns

WLWH WE# Pulse Width 40 50 50 ns

tWHDX Data Hold from

WE# High 2000ns

WHAX Address Hold

from WE# High 2101010ns

WHEH CE# Hold from

WE# High 10 10 10 ns

tWHWL WE# Pulse Width

High 30 30 50 ns

tGHWL Read Recovery

before Write 000ns

WHGL Write Recovery

before Read 60 65 80 ns

NOTES:

CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.

1. These are WE#–controlled write timings, equivalent CE#–controlled write timings apply.

2. Sampled, but not 100% tested.

3. Address must be valid during the entire WE# low pulse or the entire CE# low pulse for CE#-controlled writes.

28F016SA E

WE# (W)

CEx#(E)

ELWL

WHDX

WLWH

DVWH

HIGH Z

DATA (D/Q )

ADDRESSES (A)

WHAX

VALID

AVWL

WHEH

WHWL

0489_16

Figure 17. Page Buffer Write Timing Waveforms

(Loading Data to the Page Buffer)

E28F016SA

5.11 Erase and Word/Byte Write Performance, Cycling Performance and

Suspend Latency(3)

VCC = 3.3V ± 10%, VPP = 12.0V ± 0.6V, TA = 0°C to +70°C

Sym Parameter Notes Min Typ(1) Max Units Test Conditions

Page Buffer Byte Write Time 2,4 3.26 Note 6 µs

Page Buffer Word Write Time 2,4 6.53 Note 6 µs

tWHRH1 Word/Byte Program Time 2 9 Note 6 µs

tWHRH2 Block Program Time 2 0.6 2.1 sec Byte Prog. Mode

tWHRH3 Block Program Time 2 0.3 1.0 sec Word Prog. Mode

Block Erase Time 2 0.8 10 sec

Full Chip Erase Time 2 25.6 sec

Erase Suspend Latency Time

to Read 7.0 µs

Auto Erase Suspend Latency

Time to Write 10.0 µs

Erase Cycles 5 100,000 1,000,000 Cycles

VCC = 5.0V ± 10%, VPP = 12.0V ± 0.6V, TA = 0°C to +70°C

Sym Parameter Notes Min Typ(1) Max Units Test Conditions

Page Buffer Byte Write Time 2,4 2.76 Note 6 µs

Page Buffer Word Write Time 2,4 5.51 Note 6 µs

tWHRH1 Word/Byte Program Time 2 6 Note 6 µs

tWHRH2 Block Program Time 2 0.4 2.1 sec Byte Prog. Mode

tWHRH3 Block Program Time 2 0.2 1.0 sec Word Prog. Mode

Block Erase Time 2 0.6 10 sec

Full Chip Erase Time 2 19.2 sec

Erase Suspend Latency Time

to Read 5.0 µs

Auto Erase Suspend Latency

Time to Write 8.0 µs

Erase Cycles 5 100,000 1,000,000 Cycles

NOTES:

1. +25°C, VCC = 3.3V or 5.0V nominal, VPP = 12.0V nominal, 10K cycles.

2. Excludes system-level overhead.

3. These performance numbers are valid for all speed versions.

4. This assumes using the full Page Buffer to data program to the flash memory (256 bytes or 128 words).

5. Typical 1,000,000 cycle performance assumes the application uses block retirement techniques.

6. This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel Sales office

for more information.

28F016SA E

6.0 DERATING CURVES

290489-16.eps

Figure 18. ICC vs. Frequency (VCC = 5.5V) for x8

or x16 Operation

290489-18.eps

Figure 19. ICC during Block Erase

290489-19.eps

Figure 20. ICC vs. Frequency (VCC = 3.6V) for x8

or x16 Operation

290489-21.eps

Figure 21. IPP during Block Erase

E28F016SA

290489-24.eps

Figure 22. Access Time (tACC) vs. Output Loading

290489-25.eps

Figure 23. IPP during Word Write Operation

290489-26

Figure 24. IPP during Page Buffer Write

Operation

28F016SA E

7.0 MECHANICAL SPECIFICATIONS FOR TSOP

290489-28.eps

Figure 25. Mechanical Specifications of the 28F016SA 56-Lead TSOP Type 1 Package

Family: Thin Small Outline Package

Symbol Millimeters

Minimum Nominal Maximum Notes

A 1.20

A10.05

A20.965 0.995 1.025

b 0.100 0.150 0.200

c 0.115 0.125 0.135

D118.20 18.40 18.60

E 13.80 14.00 14.20

e 0.50

D 19.80 20.00 20.20

L 0.500 0.600 0.700

N56

∅

0°3°5°

Y 0.100

Z 0.150 0.250 0.350

E28F016SA

8.0 MECHANICAL SPECIFICATIONS FOR SSOP

1YCA1

See Detail A

Detail A

A2 R1

0528_20

Figure 26. Mechanical Specifications of the 56-Lead SSOP Package

Family: Shrink Small Outline Package

Symbol Millimeters

Minimum Nominal Maximum Notes

A 1.80 1.90

A1 0.47 0.52 0.57

A2 1.18 1.28 1.38

B 0.25 0.30 0.40

C 0.13 0.15 0.20

D 23.40 23.70 24.00

E 13.10 13.30 13.50

e10.80

He 15.70 16.00 16.30

N56

0.45 0.50 0.55

Y 0.10

a2° 3° 4°

b3°3°5°

R1 0.15 0.20 0.25

R2 0.15 0.20 0.25

28F016SA E

APPENDIX A

DEVICE NOMENCLATURE AND ORDERING

INFORMATION

DA = Commercial Temperature

56-Lead SSOP

E = Commercial Temperature

56-Lead TSOP

T = Extended Temperature

56-Lead SSOP

ACCESS SPEED

A2 68F000

1SA

-7

70 ns

100 ns

0489_18

Valid Combinations

Option Order Code VCC = 3.3V ± 10%,

50 pF Load VCC

= 5.0V ± 10%,

100 pF Load

VCC = 5.0V ± 5%,

30 pF Load

1 E28F016SA-070 E28F016SA-120 E28F016SA-080 E28F016SA-070

2 E28F016SA-100 E28F016SA-150 E28F016SA-100

3 DA28F016SA-070 DA28F016SA-120 DA28F016SA-080 DA28F016SA-070

4 DA28F016SA-100 DA28F016SA-150 DA28F016SA-100

5 DT28F016SA-100 DT28F016SA-150 DT28F016SA-150 DT28F016SA-150

E28F016SA

APPENDIX B

ADDITIONAL INFORMATION(1,2)

Order Number Document/Tool

297372

16-Mbit Flash Product Family User’s Manual

290490

DD28F032SA 32-Mbit FlashFile™ Memory Datasheet

290528

28F016SV FlashFile™ Memory Datasheet

290429

28F008SA 8-Mbit FlashFile™ Memory Datasheet

292092

AP-357 Power Supply Solutions for Flash Memory

292123

AP-374 Flash Memory Write Protection Techniques

292126

AP-377 16-Mbit Flash Product Family Software Drivers 28F016SA, 28F016SV,

28F016XS, 28F016XD

292144

AP-393 28F016SV Compatibility with 28F016SA

292159

AP-607 Multi-Site Layout Planning with Intel’s Flash File™ Components

294016

ER-33 ETOX™ Flash Memory Technology - Insight to Intel’s Fourth Generation

Process Innovation

297534

Small and Low-Cost Power Supply solution for Intel’s Flash Memory Products

(Technical Paper)

297508 FLASHBuilder Design Resource Tool

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should

contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.