1
FEATURES
DESCRIPTION
TPS2080, TPS2081, TPS2082 DUALTPS2085, TPS2086, TPS2087 QUAD
SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007www.ti.com
POWER-DISTRIBUTION SWITCHES
•80-m ΩHigh-Side MOSFET Switch•500 mA Continuous Current per Channel•Independent Thermal and Short-CircuitProtection With Overcurrent Logic Output•Operating Range: 2.7-V to 5.5-V•CMOS- and TTL-Compatible Enable Inputs•2.5-ms Typical Rise Time•Undervoltage Lockout•10 μA Maximum Standby Supply Current•Bidirectional Switch•Available in 8-Pin and 16-Pin SOIC Packages•Ambient Temperature Range, 0 °C to 85 °C•ESD Protection
The TPS2080, TPS2081, and TPS2082 dual and theTPS2085, TPS2086 and TPS2087 quadpower-distribution switches are intended forapplications where heavy capacitive loads and shortcircuits are likely to be encountered.
The TPS208x devices incorporate 80-m ΩN-channel MOSFET high-side power switches for power-distributionsystems that require multiple power switches in a single package. Each switch is controlled by an independentlogic enable input. Gate drive is provided by an internal charge pump designed to control the power-switch risetimes and fall times to minimize current surges during switching. The charge pump requires no externalcomponents and allows operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS208x limits the outputcurrent to a safe level by switching into a constant-current mode, pulling the overcurrent ( OCx) logic output low.When continuous heavy overloads and short circuits increase the power dissipation in the switch causing thejunction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from athermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switchremains off until valid input voltage is present. The TPS208x devices are designed to current limit at 1.0-A load.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
(1)
DUAL POWER DISTRIBUTION SWITCHES
TYPICAL PACKAGEDRECOMMENDEDENABLE
SHORT-CIRCUIT DEVICESMAXIMUM
CURRENT LIMITT
A
CONTINUOUS LOAD
SMALLAT 25 °CCURRENTEN1 EN2 OUTLINE(A)(A)
(D)
(2)
Active high Active high TPS2080D0°C to 85 °C Active high Active low 0.5 1.0 TPS2081DActive low Active low TPS2082D
QUAD POWER DISTRIBUTION SWITCHES
ENABLE RECOMMENDED TYPICAL PACKAGEDMAXIMUM SHORT-CIRCUIT DEVICESCONTINUOUS LOAD CURRENT LIMITT
A
SMALLCURRENT AT 25 °CEN1 EN2 EN3 DN4 OUTLINE(A) (A)
(D)
(2)
Active high Active high Active high Active high TPS2085D0°C to 85 °C Active high Active low Active high Active low 0.5 1.0 TPS2086DActive low Active low Active low Active low TPS2087D
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2081DR).
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TPS2082 FUNCTIONAL BLOCK DIAGRAM
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TPS2087 FUNCTIONAL BLOCK DIAGRAM
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SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007
TERMINAL FUNCTIONS
DUAL POWER-DISTRIBUTION SWITCHES
TERMINAL
NO. I/O DESCRIPTIONNAME
TPS2080 TPS2081 TPS2082
EN1 4 I Enable input. Active low turns on power switch.EN2 5 5 I Enable input. Active low turns on power switch.EN1 4 4 I Enable input. Active high turns on power switch.EN2 5 I Enable input. Active high turns on power switch.GND 1 1 1 I GroundIN1 2 2 2 I N-Channel MOSFET DrainIN2 3 3 3 I N-Channel MOSFET DrainOC 8 8 8 O Overcurrent. Open drain output active lowOUT1 7 7 7 O Power-switch outputOUT2 6 6 6 O Power-switch output
QUAD POWER-DISTRIBUTION SWITCHES
TERMINAL
NO. I/O DESCRIPTIONNAME
TPS2085 TPS2086 TPS2087
EN1 4 I Enable input. Active low turns on power switch.EN2 13 13 I Enable input. Active low turns on power switch.EN3 8 I Enable input. Active low turns on power switch.EN4 9 9 I Enable input. Active low turns on power switch.EN1 4 4 I Enable input. Active high turns on power switch.EN2 13 I Enable input. Active high turns on power switch.EN3 8 8 I Enable input. Active high turns on power switch.EN4 9 I Enable input. Active high turns on power switch.GNDA 1 1 1 Ground for IN1 and IN2 switch and circuitryGNDB 5 5 5 Ground for IN3 and IN4 switch and circuitryIN1 2 2 2 I N-channel MOSFET drainIN2 3 3 3 I N-channel MOSFET drainIN3 6 6 6 I N-channel MOSFET drainIN4 7 7 7 I N-channel MOSFET drainOCA 16 16 16 O Overcurrent indicator for switch 1 and switch 2. Active-low open drain output.OCB 12 12 12 O Overcurrent indicator for switch 3 and switch 4. Active low open drain outputOUT1 15 15 15 O Power-switch outputOUT2 14 14 14 O Power-switch outputOUT3 11 11 11 O Power-switch outputOUT4 10 10 10 O Power-switch output
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DETAILED DESCRIPTION
POWER SWITCH
CHARGE PUMP
DRIVER
ENABLE ( ENx or ENx)
OVERCURRENT ( OCx)
CURRENT SENSE
THERMAL SENSE
UNDERVOLTAGE LOCKOUT
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SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 m Ω(V
I(IN)
= 5V).Configured as a high-side switch, the power switch prevents current flow from OUTx to IN and IN to OUTx whendisabled. The power switch supplies a minimum of 500 mA per switch.
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gateof the MOSFET above the source. The charge pump operates from input voltages as low as 2.7V and requiresvery little supply current.
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associatedelectromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and falltimes of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reducethe supply current to less than 10 μA when a logic high is present on ENx or a logic low is present on ENx. Alogic low input on ENx or logic high on ENx restores bias to the drive and control circuits and turns the power on.The enable input is compatible with both TTL and CMOS logic levels.
The OCx open drain output is asserted (active low) when an overcurrent or over temperature condition isencountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently thanconventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitrysends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into itssaturation region, which switches the output into a constant current mode and holds the current constant whilevarying the voltage on the load.
The TPS208x implements a dual thermal trip to allow fully independent operation of the power distributionswitches. In an overcurrent or short-circuit condition the junction temperature rises. When the die temperaturerises to approximately 140 °C, the internal thermal sense circuitry checks to determine which power switch is inan overcurrent condition and turns off that switch, thus isolating the fault without interrupting operation of theadjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled approximately20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed. The( OCx) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a controlsignal turns off the power switch.
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ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATINGS TABLE
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
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SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE UNIT
V
I(IN)
Input voltage range
(2)
– 0.3 to 6 VV
O(OUTx)
Output voltage range
(2)
– 0.3 to V
I(IN)
+ 0.3 VV
I( ENx)
or V
I(ENx)
Input voltage range – 0.3 to 6 VI
O(OUTx)
Continuous output current Internally LimitedContinuous total power dissipation See Dissipation Rating TableT
J
Operating virtual junction temperature range 0 to 125 °CT
stg
Storage temperature range – 65 to 150 °CLead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260 °CHuman body model 2 kVESD Electrostatic discharge protection Machine model 200 VCharged device model (CDM) 750 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages are with respect to GND.
T
A
≤25 °C DERATING FACTOR T
A
= 70 °C T
A
= 85 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING=
D-8 725 mW 5.8 mW/ °C 464 mW 377 mWD-16 1123 mW 9 mW/ °C 719 mW 584 mW
MIN MAX UNIT
V
I(IN)
Input voltage 2.7 5.5 VV
I( ENx)
or V
I(ENx)
Input voltage 0 5.5 VI
O
Continuous output current (per switch) 0 500 mAT
J
Operating virtual junction temperature 0 125 °C
over recommended operating junction temperature range, V
I(IN)
= 5.5 V, I
O
= rated current, V
I( ENx)
= 0 V, V
I(ENx)
= V
I(INx)
(unlessotherwise noted)
SUPPLY CURRENT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
I( ENx)
= V
I(IN)
, T
J
= 25 °C 0.025 1Supply current, low-level
No Load on OUT μAV
I(ENx)
= 0 Voutput
– 40 °C≤T
J
≤125 °C 10Supply current, high-level V
I( ENx)
= 0 V, T
J
= 25 °C 85 110No Load on OUT μAoutput V
I(ENx)
= V
I(IN)
– 40 °C≤T
J
≤125 °C 100V
I( ENx)
= V
I(IN)
,Leakage current OUT connected to ground – 40 °C≤T
J
≤125 °C 100 μAV
I(ENx)
= 0 VV
I( ENx)
= 0 V,Reverse leakage current INx = high impedance T
J
= 25 °C 0.3 μAV
I(ENx)
= V
I(IN)
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ELECTRICAL CHARACTERISTICS (Continued)
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SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007
over recommended operating junction temperature range, V
I(IN)
= 5.5 V, I
O
= rated current, V
I( ENx)
= 0 V, V
I(ENx)
= V
I(INx)
(unlessotherwise noted)
POWER SWITCH
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
V
I(IN)
= 5 V, T
J
= 25 °C, I
O
= 0.5 A 80 100V
I(IN)
= 5 V, T
J
= 85 °C, I
O
= 0.5 A 90 120V
I(IN)
= 5 V, T
J
= 125 °C, I
O
= 0.5 A 100 135Static drain-source on-stater
DS(on)
mΩresistance
V
I(IN)
= 3.3 V, T
J
= 25 °C, I
O
= 0.5 A 90 125V
I(IN)
= 3.3 V, T
J
= 85 °C, I
O
= 0.5 A 110 145V
I(IN)
= 3.3 V, T
J
= 125 °C, I
O
= 0.5 A 120 165V
I(IN)
= 5.5 V, R
L
= 10 Ω, T
J
= 125 °C, C
L
= 1 μF 2.5t
r
Rise time, output msV
I(IN)
= 2.7 V, R
L
= 10 Ω, T
J
= 125 °C, C
L
= 1 μF 3V
I(IN)
= 5.5 V, R
L
= 10 Ω, T
J
= 125 °C, C
L
= 1 μF 4.4t
f
Fall time, output msV
I(IN)
= 2.7 V, R
L
= 10 Ω, T
J
= 125 °C, C
L
= 1 μF 2.5
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into accountseparately.
ENABLE INPUT V
I( ENx)
or V
I(ENx)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IH
High-level input voltage 2.7 V ≤V
I(IN)
≤5.5 V 2 V4.5 V ≤V
I(IN)
≤5.5 V 0.8V
IL
Low-level input voltage V2.7 V ≤V
I(IN)
≤4.5 V 0.4I
I
Input current V
I( ENx)
= 0 V and V
I(ENx)
= V
I(IN)
, or V
I( ENx)
= V
I(IN)
and V
I(ENx)
= 0 V – 0.5 0.5 μAt
on
Turnon time C
L
= 100 μF, R
L
= 10 μF 20 mst
off
Turnon time C
L
= 100 μF, R
L
= 10 μF 40 ms
CURRENT LIMIT
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
V
I(IN)
= 5 V, OUT connected to GND,I
OS
Short-circuit output current 0.7 1 1.3 ADevice enabled into short circuit
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into accountseparately.
UNDERVOLTAGE LOCKOUT
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Low-level input voltage 2 2.5 VHysteresis T
J
= 25 °C 100 mV
OVERCURRENT OCx
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Sink current
(1)
V
O
= 5 V 10 mAOutput low voltage I
O
= 5 mA, V
OL( OCx)
0.5 VOff-state current
(1)
V
O
= 5 V, V
O
= 3.3 V 1 μA
(1) Specified by design, not production tested.
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PARAMETER MEASUREMENT INFORMATION
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Figure 1. Test Circuit and Voltage Waveforms
Figure 2. Turnon Delay and Rise Time With 0.1- μF Load Figure 3. Turnoff Delay and Fall Time With 0.1- μF Load
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Turnon Delay and Rise Time With 1- μF Load Figure 5. Turnoff Delay and Fall Time With 1- μF Load
Figure 6. TPS2080, Short-Circuit Current, Device Figure 7. TPS2080, Threshold Trip Current With RampedEnabled Into Short Load on Enabled Device
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PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. OC Response With Ramped Load on Enabled Figure 9. Inrush Current With 100- μF, 220- μF and 470- μFDevice Load Capacitance
Figure 10. 4- ΩLoad Connected to Enabled Device Figure 11. 1- ΩLoad Connected to Enabled Device
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TYPICAL CHARACTERISTICS
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TURNON DELAY TIME TURNOFF DELAY TIMEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 12. Figure 13.
RISE TIME FALL TIMEvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 14. Figure 15.
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TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT DISABLEDvs vsJUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 16. Figure 17.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE INPUT-TO-OUTPUT VOLTAGEvs vsJUNCTION TEMPERATURE LOAD CURRENT
Figure 18. Figure 19.
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TYPICAL CHARACTERISTICS (continued)
SHORT-CIRCUIT OUTPUT CURRENT THRESHOLD TRIP CURRENTvs vsJUNCTION TEMPERATURE INPUT VOLTAGE
Figure 20. Figure 21.
UNDERVOLTAGE LOCKOUT CURRENT LIMIT RESPONSEvs vsJUNCTION TEMPERATURE PEAK CURRENT
Figure 22. Figure 23.
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APPLICATION INFORMATION
POWER-SUPPLY CONSIDERATIONS
OVERCURRENT
OC RESPONSES
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Figure 24. Typical Application
A 0.01- μF to 0.1- μF ceramic bypass capacitor between INx and GND, close to the device, is recommended.Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing theoutput with a 0.01- μF to 0.1- μF ceramic capacitor improves the immunity of the device to short-circuit transients.
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do notincrease the series resistance of the current path. When an overcurrent condition is detected, the devicemaintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs onlyif the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before thedevice is enabled or before V
I(IN)
has been applied (see Figure 6 ). The TPS208x senses the short andimmediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overloadoccurs, very high currents may flow for a short time before the current-limit circuit can react (see Figure 10 andFigure 11 ). After the current-limit circuit has tripped (reached the overcurrent trip threshold) the device switchesinto constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. Thecurrent is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device isexceeded (see Figure 8 ). The TPS208x is capable of delivering current up to the current-limit threshold withoutdamaging the device. Once the threshold has been reached, the device switches into its constant-current mode.
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition isencountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting fromthe inrush current flowing through the device, charging the downstream capacitor. The TPS208x devices aredesigned to reduce false overcurrent reporting. An internal overcurrent transient filter eliminates the need to useexternal components to remove unwanted pulses. Using low-ESR electrolytic capacitors on the output lowers theinrush current flow through the device during hot-plug events by providing a low impedance energy source,thereby reducing erroneous overcurrent reporting.
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POWER DISSIPATION AND JUNCTION TEMPERATURE
THERMAL PROTECTION
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Figure 25. Typical Circuit for OC Pin
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to passlarge currents. The thermal resistance of these packages is high compared to that of power packages; it is gooddesign practice to check power dissipation and junction temperature. Begin by determining the r
DS(on)
of theN-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use thehighest operating ambient temperature of interest and read r
DS(on)
from Figure 18 . Using this value, the powerdissipation per switch can be calculated by:P
D
= r
DS(on)
×I
2
Multiply this number by the total number of switches being used, to get the total power dissipation coming fromthe N-channel MOSFETs.
Finally, calculate the junction temperature:T
J
= P
D
×R
θJA
+ T
A
Where:
T
A
= Ambient Temperature °CR
θJA
= Thermal resistance SOIC = 172 °C/W (for 8 pin), 111 °C/W (for 16 pin)P
D
= Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generallysufficient to get a reasonable answer.
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present forextended periods of time. The faults force the TPS208x into constant current mode, which causes the voltageacross the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal tothe input voltage. The increased dissipation causes the junction temperature to rise to high levels. The protectioncircuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the thermal sensecircuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continuesto cycle in this manner until the load fault or input power is removed.
The TPS208x implements a dual thermal trip to allow fully independent operation of the power distributionswitches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die temperaturerises to approximately 140 °C, the internal thermal sense circuitry checks which power switch is in an overcurrentcondition and turns that power switch off, thus isolating the fault without interrupting operation of the adjacentpower switch. Should the die temperature exceed the first thermal trip point of 140 °C and reach 160 °C, bothswitches turn off. The OC open-drain output is asserted (active low) when overtemperature or overcurrentoccurs.
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UNDERVOLTAGE LOCKOUT (UVLO)l
GENERIC HOT-PLUG APPLICATIONS (see Figure 26 )
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SLVS202B – SEPTEMBER 2000 – REVISED OCTOBER 2007
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the inputvoltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design ofhot-insertion systems where it is not possible to turn off the power switch before input power is removed. TheUVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if theswitch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce EMIand voltage overshoots.
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.These are considered hot-plug applications. Such implementations require the control of current surges seen bythe main power supply and the card being inserted. The most effective way to control these surges is to limit andslowly ramp the current and voltage being applied to the card, similar to the way in which a power supplynormally turns on. Due to the controlled rise times and fall times of the TPS208x, these devices can be used toprovide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature of the TPS208xalso ensures the switch will be off after the card has been removed, and the switch will be off during the nextinsertion. The UVLO feature insures a soft start with a controlled rise time for every insertion of the card ormodule.
Figure 26. Typical Hot-Plug Implementation
By placing the TPS208x between the V
CC
input and the rest of the circuitry, the input power will reach thesedevices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing a slow voltageramp at the output of the device. This implementation controls system surge currents and provides ahot-plugging mechanism for any device.
Copyright © 2000 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS2080, TPS2081, TPS2082 DUAL TPS2085, TPS2086, TPS2087 QUAD
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2080D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2080DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2080DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2080DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2081D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2081DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2082D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2082DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2082DR ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2082DRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2085D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2085DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2085DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2085DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2086D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2086DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2087D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2087DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2087DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2087DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Jul-2008
Addendum-Page 1
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Jul-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2080DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2082DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2085DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2087DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Nov-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2080DR SOIC D 8 2500 340.5 338.1 20.6
TPS2082DR SOIC D 8 2500 340.5 338.1 20.6
TPS2085DR SOIC D 16 2500 333.2 345.9 28.6
TPS2087DR SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Nov-2010
Pack Materials-Page 2
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