W3DG6432V-BD1
1White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
September 2007
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADVANCED*
256MB- 32Mx64 SDRAM UNBUFFERED
The W3DG6432V is a 32Mx64 synchronous DRAM
module which consists of eight 16Mx16 SDRAM
com po nents in TSOP II package, and one 2Kb EEPROM
in an 8 pin TSSOP package for Serial Presence Detect
which are mounted on a 144 pin SO-DIMM mul ti lay er
FR4 Substrate.
* This product is under development, is not qualifi ed or characterized
and is subject to change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
DESCRIPTION
FEATURES
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the positive
edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3V ± 0.3V Power Supply
Dual Rank
144 Pin SO-DIMM PC 133 pinout
• BD1: 31.75mm (1.25")
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
A0 – A12 Address Inputs
BA0-1 Bank Address Inputs
DQ0-63 Data Input/Output
CK0,CK1 Clock Inputs
CKE0,CKE1 Clock Enable Inputs
CS0#,CS1# Chip Select Inputs
RAS# Row Address Strobe
CAS# Column Address Strobe
WE# Write Enable
DQM0-7 Data Masks
VCC Power Supply
VSS Ground
SDA Serial Data I/O
SCL Serial Clock
DNU Do Not Use
NC No Connect
PINOUT
PIN FRONT PIN BACK PIN FRONT PIN BACK PIN BACK PIN BACK
1V
SS 2V
SS 51 DQ14 52 DQ46 95 DQ21 96 DQ53
3 DQ0 4 DQ32 53 DQ15 54 DQ47 97 DQ22 98 DQ54
5 DQ1 6 DQ33 55 VSS 56 VSS 99 DQ23 100 DQ55
7 DQ2 8 DQ34 57 NC 58 NC 101 VCC 102 VCC
9 DQ3 10 DQ35 59 NC 60 NC 103 A6 104 A7
11 VCC 12 VCC 105 A8 106 BA0
13 DQ4 14 DQ36 107 VSS 108 VSS
15 DQ5 16 DQ37 109 A9 110 BA1
17 DQ6 18 DQ38 61 CK0 62 CKE0 111 A10/AP 112 A11
19 DQ7 20 DQ39 63 VCC 64 VCC 113 VCC 114 VCC
21 VSS 22 VSS 65 RAS# 66 CAS# 115 DQM2 116 DQM6
23 DQM0 24 DQM4 67 WE# 68 CKE1 117 DQM3 118 DQM7
25 DQM1 26 DQM5 69 CS0# 70 A12 119 VSS 120 VSS
27 VCC 28 VCC 71 CS1# 72 *A13 121 DQ24 122 DQ56
29 A0 30 A3 73 DNU 74 CK1 123 DQ25 124 DQ57
31 A1 32 A4 75 VSS 76 VSS 125 DQ26 126 DQ58
33 A2 34 A5 77 NC 78 NC 127 DQ27 128 DQ59
35 VSS 36 VSS 79 NC 80 NC 129 VCC 130 VCC
37 DQ8 38 DQ40 81 VCC 82 VCC 131 DQ28 132 DQ60
39 DQ9 40 DQ41 83 DQ16 84 DQ48 133 DQ29 134 DQ61
41 DQ10 42 DQ42 85 DQ17 86 DQ49 135 DQ30 136 DQ62
43 DQ11 44 DQ43 87 DQ18 88 DQ50 137 DQ31 138 DQ63
45 VCC 46 VCC 89 DQ19 90 DQ51 139 VSS 140 VSS
47 DQ12 48 DQ44 91 VSS 92 VSS 141 **SDA 142 **SCL
49 DQ13 50 DQ45 93 DQ20 94 DQ52 143 VCC 144 VCC
VOLTAGE KEY
* These pins are not used in this module.
** These pins should be NC in the system which
does not support SPD.
W3DG6432V-BD1
2White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
September 2007
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMH
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM0
RAS#
CAS#
CKE0
CKE1
CAS#: SDRAMs
CKE: SDRAMs
CKE: SDRAMs
WE
#
:
S
DRAMs
A0-A12: SDRAMs
BA0-1: SDRAMs
A0-A12
BA0-1
V
DD
V
SS
SDRAMs, SPD
SDRAMs, SPD
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQML CS#
DQM4
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQML
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM6
DQMH CS#
DQM2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQML
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM5
DQMH CS#
DQM1
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQML
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM7
DQMH CS#
DQM3
DQML
DQMH CS#
DQMH
DQML CS#
DQMH
DQML CS#
DQMH
DQML CS#
RAS#: SDRAMs
WE#
SERIAL PD
SDA
WP
SCL
A0 A1 A2
CS1#
CS0#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
SDRAM x 4
CK0
SDRAM x 4
CK1
Note: Data signals are terminated using 10Ω series resistors.
W3DG6432V-BD1
3White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
September 2007
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Units
Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V
Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 ~ 4.6 V
Storage Temperature TSTG -55 ~ +150 °C
Short Circuit Current IOS 50 mA
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C)
Parameter Symbol Min Max Unit Note
Supply Voltage VCC, VCCQ 3 3.6 V
Input High Voltage (Logic 1) All inputs VIH 2V
CC + 0.3 V 22
Input Low Voltage (Logic 0) All input VIL -0.3 0.8 V 22
Input Leakage Current:
Any input 0V ≤ VIN ≤ VCC
(All other pins not under test = 0V)
Command and
Address Inputs
II
-40 40 μA33
CK, S# -20 20 μA33
DQM -10 10 μA
Output High Voltage: DQ pins are
dislabled; 0V ≤ VIN ≤ VCCQ DQ IOZ -10 10 μA
Output High Voltage (IOUT = -4mA) VOH 2.4 V
Output Low Voltage (IOUT = 4mA) VOL 0.4 V
See notes on page 6
W3DG6432V-BD1
4White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
September 2007
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADVANCED
OPERATING CURRENT CHARACTERISTICS
(TA = 0°C to +70°C)
Parameter Symbol Max Units
77510
Operating Current:
Active Mode; Burst = 1; READ or WRITE; tRC = tRC(MIN) ICC1* 408 328 328 mA
Standby Current:
Power-Down Mode; All device banks idle; CKE = low
ICC2** 16 16 16 mA
Standby Current:
Active Mode; CS# = High: All device banks ac-
tive after tRCD met; No accesses in progress
CKE High ICC3N** 168 148 148 mA
CKE Low ICC3P*28 28 28 mA
Operating Current:
Burst Mode; Continuous burst; READ or WRITE; All device banks active
ICC4** 268 236 236 mA
Auto Refresh Current
CKE = HIGH; CS# = HIGH
tRCF = tRCF(MIN) ICC5**
1,334 1,136 1,136 mA
tRCF = 7.8125μs 200 200 200 mA
Self Refresh Current: CKE ≤ 0.2v Standard ICC6** 24 24 24 mA
NOTES:
I
CC specifi cation is based on QIMONDA components. Other DRAM manufactures specifi cation may be different.
* Value calculated as one module bank in the operating condition, and all other module banks in power-down mode
** Value calculated refl ects all module banks in the operating condition
W3DG6432V-BD1
5White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
September 2007
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADVANCED
COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
AC Characteristics Symbol 7 75 10 Units Notes
Parameter Min Max Min Max Min Max ns 27
Access time from CLK
(positive edge)
CL = 3 tAC(3) 5.4 5.4 6 ns
CL = 2 tAC(2) 5.4 6 6 ns
Input hold time tJH 0.8 0.8 1 ns
Input setup time tIS 1.5 1.5 2 ns
CLK high-level width tCH 2.5 2.5 3 ns
CLK low-level width tCL 2.5 2.5 3 ns
Clock cycle time CL = 3 tCK(3) 7 7.5 8 ns 24
CL = 2 tCK(2) 7.5 10 10 ns 24
CKE hold time tCKH 0.8 0.8 1 ns
CKE setup time tCKS 1.5 1.5 2 ns
Data-out high-impedance time tHZ 373737ns10
Data-out low-impedance time tLZ 000ns
Data-out hold time (load) tOH 333ns
Data-out hold time (no load) tOHN 1.8 1.8 1.8 ns 28
Active to Active command tRAS 37 120,000 44 120,000 50 120,000 ns 32
Active to Active command period tRC 60 66 70 ns
Active to Read or Write delay tRCD 15 20 20 ns
Refresh period tREF 64 64 64 ns
Auto Refresh period tRFC 66 66 70 ns
Precharge command period tRP 15 20 20 ns
Active bank a to Active bank b command tRRD 14 15 20 ns
Transition time tT0.3 1.2 0.3 1.2 0.3 1.2 ns 7
Write recovery time tWR
1 CKE +
7 ns
1 CKE +
7.5 ns
1 CKE +
7 ns ns 24
14 15 15 ns 25
Exit Self Refresh to Active command tXSR 67 75 80 ns 20
NOTE: See notes on page 6
• AC specifi cation is based on QIMONDA components. Other DRAM manufactures specifi cation may be different.
W3DG6432V-BD1
6White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
September 2007
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADVANCED
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VCC, VCCQ = +3.3V; f = 1 MHz; TA =
25ºC; pin under test based at 1.4V.
3. ICC is dependent on output loading and cycle rates. Specifi ed
values are obtained with minimum cycle time and the outputs
open.
4. Enables on-chip refresh and address counters.
5. The minimum specifi cations are used only to indicate cycle time at
which proper operation over the full temperature range is ensured.
6. An initial pause of 100μs is required after powerup, followed by
two AUTO REFRESH commands, up, followed by two AUTO
REFRESH commands,VCC and VCCQ must be powered up
simultaneously. VSS and VSSQ must be at the same potential.) The
two AUTO REFRESH command wake-ups should be repeated any
time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specifi cation, the clock
and CKE must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
9. Outputs measured at 1.5V with equivalent load:
10. tHZ defi nes the time at which the output achieves the open circuit
condition; it is not a reference to VOH or VOL. The last valid data
element will meet tOH before going High-Z.
11. AC timing and ICC test have VIL = 0V and VIH = 3V, with timing
referenced to 1.5V crossover point. If the input transition time
is longer than 1ns, then the timing is referenced at VIL(MAX) and
VIH(MIN) and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no more than once
every two clocks and are otherwise at valid VIH or VIL levels.
13. ICC specifi cations are tested after the device is properly initialized.
14. Timing actually specifi ed by tCKS; clock(s) specifi ed as a reference
only at minimum cycle rate.
15. Timing actually specifi ed by tWR and tRP' clock(s) specifi ed as a
reference only at minimum cycle rate.
16. Timing actually specifi ed by tWR.
17. Required clocks are specifi ed by JEDEC functionality and are not
dependent on any timing parameter.
18. The ICC current will increase or decrease proportionally according
to the amount of frequency alteration for the test condition.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 10ns for 10, and tCK = 7.5ns for 7 and 75.
22. VIH overshoot: VIH(MAX) = VCCQ + 2V for a pulse width ≤ 3ns, and
the pulse width cannot be greater than one third of the cycle rate.
VIL undershoot: VIL(MIN) = -2V for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable clock is defined
as a signal cycling within timing constraints specified for the clock
pin) during constraints specified for the clock pin) during in tWR,
and PRECHARGE commands). CKE may be used to reduce the
data rate.
24. Auto precharge mode only. The precharge timing budget (tRP)
begins 7ns for 75; 7.5ns for 7 and 7ns for 10 after the first clock
delay, after the last WRITE is executed. May not exceed limit set
for precharge mode.
25. Set for precharge mode.
26. JEDEC and PC100 specify three clocks.
27. tAC for 7/75 at CL = 3 with no load is 4.6ns and is guaranteed by
design.
28. Parameter guaranteed by design.
29. For 75, CL = 2 and tCK = 7.5ns; for 7, CL = 3 and tCK 7.5ns; for
10, CL= 2 and tCK = 10ns.
30. CKE is HIGH during refresh command period tRFC(MIN) else CKE is
LOW. The ICC6 limit is actually a nominal value and does not result
in a fail value.
31. Refer to component data sheet for timing waveforms.
32. The value of tRAS used in 75 speed grade module SPDs is
calculated from tRC - tRP = 45ns.
33. Leakage number reflects the worst case leakage possible through
the module pin, not what each memory device contributes.
Q
50pF
W3DG6432V-BD1
7White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
September 2007
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADVANCED
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
PACKAGE DIMENSIONS
Ordering Information Speed CAS Latency Height
W3DG6432V7BD1-xx 133MHz CL=2 31.75mm (1.25") TYP
W3DG6432V75BD1-xx 133MHz CL=3 31.75mm (1.25") TYP
W3DG6432V10BD1-xx 100MHz CL=2 31.75mm (1.25") TYP
Notes:
• Consult Factory for availability of RoHS products. (G = RoHS Compliant)
• For part numbering interpretation, please see "Part Numbering Guide" on page 8.
3.80 (0.150)
MAX
PIN 1
67.75 (2.666)
67.45 (2.656)
1.80 (0.071)
2.0
(0.079)
4.0
(0.157)
(2X)
60.60 (2.386)
0.80 (0.0315)
TYP
3.30 (0.13)
0.60 (0.024)
TYP
PIN 143
FR
O
NT VIEW
2.00 (0.079)
6.00 (0.236)
63.60 (2.504)
2.55 (0.100)
1.50 (0.059)
TYP
4.00 (0.157)
31.75± 0.15
(1.25± 0.006)
1.0± 0.1
(0.039± 0.004)
20.00 (0.787) TYP
PIN 144 PIN 2
BACK VIEW
ORDERING INFORMATION FOR D1
W3DG6432V-BD1
8White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
September 2007
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADVANCED
PART NUMBERING GUIDE
W 3 D G 6432 V xx B D1 -x G
WEDC
MEMORY
SDRAM
GOLD
DEPTH & BUS WIDTH
3.3 VOLTS
CLOCK SPEED (MHz)
7 = 133MHz @ CL = 2
75 = 133MHz @ CL = 3
10 = 100MHz @ CL = 2
10Ω TERMINATED RESISTORS
PACKAGE 144 PIN SO-DIMM
COMPONENT VENDOR NAME
(G = Qimonda)
Note: Consult factory for other vendor options
G = RoHS COMPLIANT
W3DG6432V-BD1
9White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
September 2007
Rev. 0
White Electronic Designs Corp. reserves the right to change products or specifi cations without notice.
ADVANCED
Document Title
256MB – 32Mx64 SDRAM UNBUFFERED
Revision History
Rev # History Release Date Status
Rev 0 Created September 2007 Advanced
