ES1020QI - Altera - Product.Network

May 2014 Altera Corporation

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ES1020QI Datasheet

The Altera Enpirion ES1020QI is an integrated 4-channel

controlled-on/controlled-off power-supply sequencer

with supply monitoring, fault protection and a “sequence

completed” signal (RESET). For larger systems, more than

four supplies can be sequenced by simply connecting a

wire between the SYSRESET pins of cascaded ICs. The

ES1020QI uses a patented, micropower 7x charge pump to

drive four external low-cost NFET switch gates above the

supply rail by 5.3V. These ICs can be biased from 5V

down to 1.5V by any supply.

External resistors provide flexible voltage threshold

programming of monitored rail voltages. Delay and

sequencing are provided by external capacitors for

ramp-up and ramp-down.

Additional I/O is provided for indicating and driving

the RESET state in various configurations.

For volume applications, other programmable options

and features are available.

Features

• Enables Arbitrary Turn-on and Turn-off Sequencing of

Up to Four Power Supplies (0.7V to 5V)

• Operates From 1.5V to 5V Supply Voltage

• Supplies VDD +5.3V of Charge Pumped Gate Drive

• Adjustable Voltage Slew Rate for Each Rail

• Multiple Sequencers Can be Daisy-Chained to Sequence

an Infinite Number of Independent Supplies

• Glitch Immunity

• Undervoltage Lockout for Each Supply

• Low ENABLE Input

• QFN Package

• Pb-free (RoHS-compliant)

Applications

•Graphics Cards

• FPGA/ASIC/Microprocessor/PowerPC Supply

Sequencing

•Network Routers

• Telecommunications Systems

FIGURE 1. TYPICAL ES1020QI APPLICATION

FIGURE 2. ES1020QI Block Diagram

EN

SYSRST

UVLOX

0.633V

RESET

DLY_ONX

1.26V

DLY_OFFX

1.26V

GATEX

LOGIC

1µA

BIAS

LOCK OUT

VDD

RISING DELAY

VDD+5V

Q-PUMP

1µA

1µA -1µA

30µs

FILTER

150ms

RISING DELAY

10ms

Enpirion® Power Datasheet

ES1020QI Power Sequencing Controller

10041 May 28, 2014 Rev A

Page 2

Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 2014 Altera Corporation

Pin Configurations

ES1020QI

(24 LD QFN)

TOP VIEW

Ordering Information

PART NUMBER

(Notes 1, 2) PART MARKING TEMP. RANGE (°C)

PACKAGE

(Pb-free) PKG. DWG. #

ES1020QI S1020 -40 to +85 24 Ld 4x4 QFN L24.4x4

NOTES:

1. Add “T” suffix for Tape and Reel. Please refer to Packing and Marking Information:

www.altera.com/support/reliability/packing/rel-packing-and-marking.html

2. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb

and Pb-free soldering operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ES1020QI Feature Matrix

PART

NAME EN/EN

CMOS/

TTL

GATE DRIVE

OR OPEN

DRAIN

OUTPUTS

REQUIRED

CONDITIONS

FOR INITIAL

START-UP

NUMBER OF

UVLO INPUTS

MONITORED

BY EACH

RESET

NUMBER OF

CHANNELS

THAT TURN OFF

WHEN ONE

UVLO FAULTS

PRESET OR

ADJUSTABLE

SEQUENCE

NUMBER OF

UVLO AND

PAIRS OF I/O FEATURES

ES1020QI EN CMOS Gate Drive 4 UVLO

1 EN

4 UVLO 4 Gates Time Adjustable

On and Off

4 Monitors

with 1 I/O

Auto Restart

1

2

3

4

5

6

18

17

16

15

14

13

24 23 22 21 20 19

7 8 9 10 11 12

EPAD

ENABLE_1

GATE_A

DLY_OFF_C

DLY_OFF_D

GATE_B

GATE_C

GATE_D

DLY_ON_B

NC

GND

UVLO_B

DLY_OFF_B

UVLO_D

DLY_ON_D

DLY_ON_C

UVLO_C

DLY_OFF_A

NC

UVLO_A

DLY_ON_A

SYSRST

VDD

RESET

(GND)

NC

10041 May 28, 2014 Rev A

Page 3

Enpirion Power Datasheet ES1020QI Power Sequencing ControllerMay 2014 Altera Corporation

Pin Descriptions

NAME

PIN NUMBER

DESCRIPTIONES1020QI

VDD 23 Chip Bias. Bias IC from nominal 1.5V to 5V.

GND 10 Bias Return. IC ground.

ENABLE_1 1 Input to start on/off sequencing. Input to initiate start of programmed sequencing of

supplies on or off. Enable functionality disabled for 10ms after UVLO is satisfied.

RESET 24 RESET Output. RESET provides low signal 150ms after all GATEs are fully enhanced.

Delay is for stabilization of output voltages. RESET asserts low upon UVLO not

being satisfied or ENABLE being deasserted. RESET outputs are open-drain, N-

channel FET and are guaranteed to be in correct state for VDD down to 1V and are

filtered to ignore fast transients on VDD and UVLO_X.

UVLO_A 20 Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout

referenced to an internal 0.633V reference. Filtered to ignore short (<30µs)

transients below programmed UVLO level.

UVLO_B 12

UVLO_C 17

UVLO_D 14

DLY_ON_A 21 Gate On Delay Timer Output. Allows programming of delay and sequence for VOUT

turn-on using a capacitor to ground. Each capacitor charged with 1µA 10ms after

turn-on initiated by ENABLE. Internal current source provides delay to associated

FET GATE turn-on.

DLY_ON_B 8

DLY_ON_C 16

DLY_ON_D 15

DLY_OFF_A 18 Gate Off Delay Timer Output. Allows programming of delay and sequence for VOUT

turn-off through ENABLE via a capacitor to ground. Each capacitor charged with

1µA internal current source to an internal reference voltage, causing corresponding

gate to be pulled down, thus turning off FET.

DLY_OFF_B 13

DLY_OFF_C 3

DLY_OFF_D 4

GATE_A 2 FET Gate Drive Output. Drives external FETs with 1µA current source to soft-start

ramp into load.

GATE_B 5

GATE_C 6

GATE_D 7

SYSRST 22 System Reset I/O. As an input, allows for immediate and unconditional latch-off of all

GATE outputs when driven low. This input can also be used to initiate programmed

sequence with ‘zero’ wait (no 10ms stabilization delay) from input signal on this pin

being driven high to first GATE. As an output, when there is a UV condition, this pin pulls

low. If common to other SYSRST pins in a multiple IC configuration, it causes

immediate and unconditional latch-off of all other GATEs on all other ES1020QI

sequencers.

GND EPAD Ground. Die Substrate. Can be left floating.

NC 9, 11, 19 No Connect

10041 May 28, 2014 Rev A

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Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 2014 Altera Corporation

Absolute Maximum Ratings (Note 5) Thermal Information

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V

GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V

UVLO, ENABLE, SYSRST. . . . . . . . . . . . . . .-0.3V to VDD + 0.3V

RESET, DLY_ON, DLYOFF. . . . . . . . . . . . . .-0.3V to VDD + 0.3V

Operating Conditions

VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . +1.5V to +5.5V

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

24 Ld 4x4 QFN Package (Notes 3, 4) 46 8

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . +125°C

Maximum Storage Temperature Range . . . . . .-65°C to +150°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.

4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

5. All voltages are relative to GND, unless otherwise specified.

Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating

temperature range, -40°C to +85°C.

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6) UNIT

UVLO

Falling Undervoltage Lockout Threshold VUVLOvth TJ = +25°C 619 633 647 mV

Undervoltage Lockout Threshold Tempco TCUVLOvth 40 µV/°C

Undervoltage Lockout Hysteresis VUVLOhys 10 mV

Undervoltage Lockout Threshold Range RUVLOvth Max VUVLOvth- Min VUVLOvth 7mV

Undervoltage Lockout Delay TUVLOdel ENABLE satisfied 10 ms

Transient Filter Duration tFIL VDD, UVLO, ENABLE glitch filter 30 µs

DELAY ON/OFF

Delay Charging Current DLY_ichg VDLY = 0V 0.92 11.08 µA

Delay Charging Current Range DLY_ichg_r DLY_ichg(max) - DLY_ichg(min) 0.08 µA

Delay Charging Current Temperature Coefficient TC_DLY_ichg 0.2 nA/°C

Delay Threshold Voltage DLY_Vth 1.238 1.266 1.294 V

Delay Threshold Voltage Temperature Coefficient TC_DLY_Vth 0.2 mV/°C

ENABLE, RESET AND SYSRST I/O

ENABLE Threshold VENh 0.5 VDD V

ENABLE Hysteresis VENh -VENl Measured at VDD = 1.5V 0.2 V

ENABLE Lockout Delay tdelEN_LO UVLO satisfied 10 ms

ENABLE Input Capacitance Cin_en 5 pF

RESET Pull-up Voltage Vpu_rst VDD V

RESET Pull-Down Current IRSTpd1 VDD = 1.5V, RST = 0.1V 5mA

IRSTpd3 VDD = 3.3V, RST = 0.1V 13 mA

IRSTpd5 VDD = 5V, RST = 0.1V 17 mA

RESET Delay after GATE High TRSTdel GATE = VDD+5V 160 ms

10041 May 28, 2014 Rev A

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Enpirion Power Datasheet ES1020QI Power Sequencing ControllerMay 2014 Altera Corporation

RESET Output Low VRSTlMeasured at VDD = 5V with 5k

pull-up resistors

0.1 V

RESET Output Capacitance COUT_RST 10 pF

SYSRST Pull-Up Voltage Vpu_srst VDD V

SYSRST Pull-Down Current Ipu_1.5 VDD = 1.5V 5 µA

Ipu_5 VDD = 5V 100 µA

SYSRST Low Output Voltage Vol_srst VDD = 1.5V, IOUT = 100µA 150 mV

SYSRST Output Capacitance Cout_srst 10 pF

SYSRST Low to GATE Turn-Off tdelSYS_G GATE = 80% of VDD + 5V 40 ns

GATE

GATE Turn-On Current IGATEon GATE = 0V 0.8 1.1 1.4 µA

GATE Turn-Off Current IGATEoff_l GATE = VDD, Disabled -1.4 -1.05 -0.8 µA

GATE Current Range IGATE_range Within IC IGATE max-min 0.35 µA

GATE Turn-On/Off Current Temperature Coefficient TC_IGATE 0.2 nA/°C

GATE Pull-Down High Current IGATEoff_h GATE = VDD, UVLO = 0V 88 mA

GATE High Voltage VGATEh VDD < 2V, TJ = +25°C VDD + 4.9V V

VGATEh VDD > 2V VDD + 5V VDD + 5.3V V

GATE Low Voltage VGATEl Gate Low Voltage, VDD = 1V 0 0.1 V

BIAS

IC Supply Current IVDD_5V VDD = 5V 0.20 0.5 mA

IVDD_3.3V VDD = 3.3V 0.14 mA

IVDD_1.5V VDD = 1.5V 0.10 mA

VDD Power-on Reset VDD_POR 1V

NOTE:

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating

temperature range, -40°C to +85°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6) UNIT

10041 May 28, 2014 Rev A

Page 6

Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 2014 Altera Corporation

Descriptions and Operation

The ES1020QI sequencer is a 4-channel voltage sequencing controller, and is designed for use in multiple-voltage

systems requiring power sequencing of various supply voltages. Individual voltage rails are gated on and off by

external N-Channel MOSFETs, the gates of which are driven by an internal charge pump to VDD + 5.3V (VQP) in a

user-programmed sequence.

The 4-channel ES1020QI ENABLE must be asserted low, and all four voltages to be sequenced must be above their

respective user-programmed undervoltage lockout (UVLO) levels before programmed output turn-on sequencing

can begin. Sequencing order and delay are determined by the choice of external capacitor values on the DLY_ON

and DLY_OFF pins. Once all four UVLO inputs and ENABLE are satisfied for 10ms (tdelEN_LO), the four DLY_ON

capacitors are simultaneously charged with 1µA current sources to the DLY_Vth level of 1.27V. As each DLY_ON

pin reaches the DLY_Vth level, its associated GATE turns on, with a 1µA source current to the charge pump voltage

(VQP) of VDD + 5.3V. Thus, all four GATEs sequentially turn on in the user defined order. Once at DLY_Vth, the

DLY_ON pins discharge so they are ready when next needed.

After the entire turn-on sequence has been completed and all GATEs have reached the charge pumped voltage

(VQP), a 160ms delay (TRSTdel) is started to ensure stability, after which the RESET output is released to go high.

Typical Performance Curves

FIGURE 3. UVLO THRESHOLD VOLTAGE FIGURE 4. DLY CHARGE CURRENT

FIGURE 5. SYSRST LOW TO OUTPUT LATCH-OFF

634

633

632

631

628

626

UV THRESHOLD (mV)

TEMPERATURE (°C)

627

-40 0 20 60-20 40 80 100

630

629

VDD = 5V

VDD = 1.5V

DLY CURRENT SOURCE (µA)

-40 0 20 60-20 40 80 100

TEMPERATURE (°C)

1.03

1.02

0.97

0.98

0.99

1.00

1.01

1.04

DLY_OFF/ON

VDD = +5V

VDD = 1.5V

1µs/DIV

5VOUT

GATE

SYSRST

2V/DIV

3.3VOUT

10041 May 28, 2014 Rev A

Page 7

Enpirion Power Datasheet ES1020QI Power Sequencing ControllerMay 2014 Altera Corporation

After turn-on, if any input falls below its UVLO point for longer than the glitch filter period (~30µs), it is considered

a fault. RESET and SYSRST are pulled low, and all GATEs are simultaneously also pulled low. In this mode, the

GATEs are pulled low with 88mA.

Normal shutdown mode is entered when no UVLO is violated and ENABLE is deasserted. When ENABLE is

deasserted, RESET is immediately asserted and pulled low. Next, all four shutdown ramp capacitors on the

DLY_OFF pins are charged with a 1µA source. When any ramp-capacitor reaches DLY_Vth, a latch is set, and a

current is sunk on the respective GATE pin to turn off its external MOSFET. When the GATE voltage is

approximately 0.6V, the GATE is pulled down the rest of the way at a higher current level. Each individual external

FET is thus turned off, which removes the voltages from the load in the user programmed sequence.

Table 1 shows the nominal time delay on the DLY_X pins for various capacitor values, from the start of charging to the

1.27V reference. This table does not include the 10ms of ENABLE lockout delay during a start-up sequence, but it does

represent the time from the end of the ENABLE lockout delay to the start of GATE transition. There is no ENABLE

lockout delay for a sequence-off, so this table illustrates the delay to GATE transition from a disable signal.

TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD

DLY PIN CAPACITANCE TIME(s)

Open 0.00006

100pF 0.00013

1000pF 0.0013

0.01µF 0.013

0.1µF 0.13

1µF 1.3

10µF 13

NOTE: Nom. TDEL_SEQ = Capacitor (µF)*1.3MΩ.

10041 May 28, 2014 Rev A

Page 8

Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 2014 Altera Corporation

Figure 6 shows the turn-on and Figure 7 shows the nominal turn-off timing diagram of the ES1020QI.

Delay and flexible sequencing possibilities include multiple series, parallel, or adjustable capacitors that can be used to

easily fine-tune timing over that offered by standard value capacitors.

FIGURE 6. ES1020QI TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM

UVLO_B

UVLO_C

UVLO_D

RESET

DLYON_A

DLYON_B

DLYON_C

DLYON_D

GATE_A

GATE_B

GATE_C

GATE_D

UVLO_A

VEN

DLY_Vth

VQPUMP

ENABLE (ES1020QI)

VUVLOVth

tRSTdel

tUVLOdel

VQPUMP-1V

VQPUMP

<tFIL

10041 May 28, 2014 Rev A

Page 9

Enpirion Power Datasheet ES1020QI Power Sequencing ControllerMay 2014 Altera Corporation

l

Typical Performance Waveforms

FIGURE 8. ES1020QI SEQUENCED TURN-ON FIGURE 9. ES1020QI SEQUENCED TURN-OFF

FIGURE 7. ES1020QI TURN-OFF TIMING DIAGRAM

ENABLE (ES1020QI)

RESET

DLYOFF_A

DLYOFF_B

DLYOFF_C

DLYOFF_D

GATE_D

GATE_C

GATE_B

GATE_A

VEN

UVLO_X>VUVLOVth

DLY_Vth

1V/DIV 40ms/DIV

5VOUT

3.3VOUT

2.5VOUT

RESET

ENABLE

1.5VOUT

1V/DIV 20ms/DIV

5VOUT

3.3VOUT

2.5VOUT

1.5VOUT

ENABLE

10041 May 28, 2014 Rev A

Page 10

Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 2014 Altera Corporation

l

Application Considerations

Timing Error Sources

In any system there are variance contributors. For the ES1020QI, timing errors are mainly contributed by three sources.

Capacitor Timing Mismatch Error

Obviously, the absolute capacitor value is an error source; thus, lower-percentage tolerance capacitors help to reduce

this error source. Figure 10 illustrates a difference of 0.57ms between two DLY_X outputs ramping to DLY_X threshold

voltage. These 5% capacitors were from a common source. In applications where two or more GATEs or LOGIC

outputs must have concurrent transitions, it is recommended that a common GATE drive be used to eliminate this

timing error.

DLY_X Threshold Voltage and Charging Current Mismatch

The two other error sources come from the IC itself and are found across the four DLY_X outputs. These errors are the

DLY_X threshold voltage (DLY_Vth) variance when the GATE_X charging and discharging current latches are set, and

the DLY_X charging current (DLY_ichg) variances to determine the time to next sequencing event. Both of these

parameters are bounded by specification. Figure 11 shows that, with a common capacitor, the typical error contributed

by these factors is insignificant, since both DLY_X traces overlay each other.

FIGURE 10. CAPACITOR TIMING MISMATCH

FIGURE 11. DLY_VTH AND DLY_ICHG TIMING MISMATCH

10041 May 28, 2014 Rev A

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Enpirion Power Datasheet ES1020QI Power Sequencing ControllerMay 2014 Altera Corporation

Revision History

The table lists the revision history for this document.

DATE REVISION CHANGE

May, 2014 1.0 Initial release.

10041 May 28, 2014 Rev A

Page 12

Enpirion Power Datasheet ES1020QI Power Sequencing Controller May 2014 Altera Corporation

Package Outline Drawing

L24.4x4

24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 4, 10/06

0 . 90 ± 0 . 1

5

C0 . 2 REF

TYPICAL RECOMMENDED LAND PATTERN

0 . 05 MAX.

( 24X 0 . 6 )

DETAIL "X"

( 24X 0 . 25 )

0 . 00 MIN.

( 20X 0 . 5 )

( 2 . 10 )

SIDE VIEW

( 3 . 8 TYP )

BASE PLANE

4

TOP VIEW

BOTTOM VIEW

712

24X 0 . 4 ± 0 . 1

13

4.00

PIN 1

18

INDEX AREA

24

19

4.00

2.5

0.50

20X

4X

SEE DETAIL "X"

- 0 . 05

+ 0 . 07

24X 0 . 23

2 . 10 ± 0 . 15

PIN #1 CORNER

(C 0 . 25)

1

SEATING PLANE

0.08 C

0.10 C

C

0.10 M C A B

A

B

(4X) 0.15

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension b applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

6.

either a mold or mark feature.

3.

5.

4.

2.

Dimensions are in millimeters.1.

NOTES:

10041 May 28, 2014 Rev A