LT3741
1
3741fb
TYPICAL APPLICATION
DESCRIPTION
High Power, Constant
Current, Constant Voltage,
Step-Down Controller
The LT
®
3741 is a fi xed frequency synchronous step-down
DC/DC controller designed to accurately regulate the output
current at up to 20A. The average current-mode controller
will maintain inductor current regulation over a wide output
voltage range of 0V to (VIN – 2V). The regulated current is
set by an analog voltage on the CTRL pins and an external
sense resistor. Due to its unique topology, the LT3741 is
capable of sourcing and sinking current. The regulated
voltage and overvoltage protection are set with a voltage
divider from the output to the FB pin. Soft-Start is provided
to allow a gradual increase in the regulated current during
startup. The switching frequency is programmable from
200kHz to 1MHz through an external resistor on the RT
pin or through the use of the SYNC pin and an external
clock signal.
Additional Features include an accurate external reference
voltage for use with the CTRL pins, an accurate UVLO/EN
pin that allows for programmable UVLO hysteresis, and
thermal shutdown.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7199560, 7321203 and others pending.
10V/20A Constant Current, Constant Voltage Step-Down Converter
FEATURES
APPLICATIONS
n Control Pin Provides Accurate Control of Regulated
Output Current
n ±1.5% Voltage Regulation Accuracy
n ±6% Current Regulation Accuracy
n 6V to 36V Input Voltage Range
n Wide Output Voltage Range Up to (VIN – 2V)
n Average Current Mode Control
n <1µA Shutdown Current
n Up to 94% Effi ciency
n Additional Pin for Thermal Control of Load Current
n Thermally Enhanced 4mm ¥ 4mm QFN and 20-Pin
FE Package
n General Purpose Industrial
n Super-Cap Charging
n Applications Needing Extreme Short-Circuit
Protection and/or Accurate Output Current Limit
n Constant Current or Constant Voltage Source
EN/UVLOEN/UVLO
HG
VIN
CBOOT
VREF
VC
CTRL1
CTRL2
LT3741
RT
SYNC
SW
LG
GND
SENSE+
SENSE–
VCC_INT
220nF
2.2µH
22µF
2.5m
FB
10nF
39.2k
5.6nF
82.5k
88.7k
3741 TA01a
12.1k
150µF
s2
10nF
RNTC
100µF
VIN
14V TO 36V
VOUT
10V
20A
1µF
SS
RHOT
45.3k
IOUT (A)
0 2 4 6 8 10 12 14 16 18
VOUT (V)
6
8
12
10
3741 TA01b
4
2
02220
VIN = 18V
VOUT = 10V
ILIMIT = 20A
VOUT vs IOUT
LT3741
2
3741fb
VIN Voltage ................................................................40V
EN/UVLO Voltage ........................................................6V
VREF Voltage ................................................................3V
CTRL1 and CTRL2 Voltage ..........................................3V
SENSE+ Voltage ........................................................40V
SENSE– Voltage ........................................................40V
VC Voltage ..................................................................3V
SW Voltage ...............................................................40V
CBOOT ......................................................................46V
(Note 1)
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3741EUF#PBF LT3741EUF#TRPBF 3741 20-Lead (4mm ¥ 4mm) Plastic QFN –40°C to 125°C
LT3741IUF#PBF LT3741IUF#TRPBF 3741 20-Lead (4mm ¥ 4mm) Plastic QFN –40°C to 125°C
LT3741EFE#PBF LT3741EFE#TRPBF LT3741FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3741IFE#PBF LT3741IFE#TRPBF LT3741FE 20-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
ABSOLUTE MAXIMUM RATINGS
20 19 18 17 16
6 7 8
TOP VIEW
21
GND
UF PACKAGE
20-LEAD (4mm s 4mm) PLASTIC QFN
9 10
5
4
3
2
1
11
12
13
14
15
EN/UVLO
VREF
CTRL2
GND
CTRL1
HG
GND
SYNC
RT
GND
VIN
VCC_INT
LG
CBOOT
SW
SS
FB
SENSE+
SENSE–
VC
TJMAX = 125°C, qJA = 37°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
FE PACKAGE
20-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
9
10
TOP VIEW
20
19
18
17
16
15
14
13
12
11
VCC_INT
GND
VIN
EN/UVLO
VREF
CTRL2
GND
CTRL1
SS
FB
LG
CBOOT
SW
HG
GND
SYNC
RT
VC
SENSE
–
SENSE+
21
GND
TJMAX = 125°C, qJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
RT Voltage...................................................................3V
FB Voltage ...................................................................3V
SS Voltage ..................................................................6V
VCC_INT Voltage ...........................................................6V
SYNC Voltage ..............................................................6V
Storage Temperature Range ................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
TSSOP .............................................................. 300°C
LT3741
3
3741fb
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, VSYNC = 0V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Voltage Range l636V
VIN Pin Quiescent Current (Note 2)
Non-Switching Operation
Shutdown Mode
Not Switching
VEN/UVLO = 0V, RT = 40k l
1.8
0.1
2.5
1
mA
µA
EN/UVLO Pin Falling Threshold 1.49 1.55 1.61 V
EN/UVLO Hysteresis 130 mV
EN/UVLO Pin Current VIN = 6V, EN/UVLO = 1.45V 5.5 µA
SYNC Pin Threshold 1V
CTRL1 Pin Control Range 0 1.5 V
CTRL1 Pin Current CTRL1 = 1.5V 100 nA
Reference
Reference Voltage (VREF Pin) l1.94 2 2.06 V
Inductor Current Sensing
Full Range SENSE+ to SENSE– V
CTRL1 = 1.5V l48 51 54 mV
SENSE+ Pin Current VSENSE+ = 6V 50 nA
SENSE– Pin Current With VOUT ~ 4V, VCTRL1 = 0V, VSENSE– = 6V 10 µA
Internal VCC Regulator (VCC_INT Pin)
Regulation Voltage l4.7 5 5.2 V
NMOS FET Driver
Non-Overlap time HG to LG 100 ns
Non-Overlap time LG to HG 60 ns
Minimum On-Time LG (Note 3) 50 ns
Minimum On-Time HG (Note 3) 80 ns
Minimum Off-Time LG (Note 3) 65 ns
High Side Driver Switch On-Resistance
Gate Pull Up
Gate Pull Down
VCBOOT – VSW = 5V
2.3
1.3
Low Side Driver Switch On-Resistance
Gate Pull Up
Gate Pull Down
VCC_INT = 5V
2.3
1
Switching Frequency
fSW RT = 40k
RT = 200k
l900
185
1000
200
1070
233
kHz
kHz
Soft-Start
Charging Current 11 µA
Voltage Regulation Amplifi er
Input Bias Current FB = 1.3V 850 nA
gm 800 µA/V
Feedback Regulation Voltage CTRL1 = 1.5V, ISENSE– = 23µA, VSENSE+ = 2V l1.192 1.21 1.228 V
LT3741
4
3741fb
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VIN = 12V, VEN/UVLO = 5V, VSYNC = 0V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Control Loop gm Amp
Offset Voltage VCM =4V l–3 0 3 mV
Input Common Mode Range
VCM(LOW)
VCM(HIGH) VCM(HIGH) Measured from VIN to VCM
0
2
V
V
Output Impedance 3.5 M
gm375 475 625 µA/V
Differential Gain 1.7 V/mV
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3741E is guaranteed to meet performance specifi cations
from 0°C to 125°C junction temperature. Specifi cations over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3741I is guaranteed to meet performance specifi cations over the –40°C
to 125°C operating junction temperature range.
Note 3: The minimum on and off times are guaranteed by design and are
not tested.
LT3741
5
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TYPICAL PERFORMANCE CHARACTERISTICS
EN/UVLO Threshold (Falling) EN/UVLO Pin Current IQ in Shutdown
VIN (V)
6
EN/UVLO THRESHOLD (V)
1.58
1.64
1.70
30
–50°C
130°C
3741 G01
1.52
1.46
1.40 12 18 24 36
VIN (V)
6
EN/UVLO PIN CURRENT (µA)
6
8
10
30
3741 G02
4
2
012 18 24 36
25°C
130°C
–50°C
VIN (V)
0
IQ (µA)
0.3
0.4
0.5
32
3741 G03
0.2
0.1
0816 24 40
130°C
25°C
Quiescent Current (Non-Switching) VREF Pin Voltage VREF Current Limit
VIN (V)
6
QUIESCENT CURRENT (mA)
1.2
1.6
2.0
30
3741 G04
0.8
0.4
012 18 24 36
TA = 25°C
TA = 130°C
TA = –50°C
TEMPERATURE (°C)
–50
VREF VOLTAGE (V)
2.00
2.01
2.06
2.05
2.04
2.03
2.02
90
3741 G05
1.99
1.98 –15 20 55 125
VIN = 36V
VIN = 6V
VIN (V)
6
ILIMIT (mA)
1.2
1.4
1.6
30
3741 G06
1.0
0.8 12 18 24 36
TA = 25°C
TA = 130°C
TA = –50°C
RT Pin Current Limit Soft-Start Pin Current
TEMPERATURE (°C)
–50
ILIMIT (µA)
70
80
90
90
3741 G08
60
50
40 –15 20 55 125
TEMPERATURE (°C)
–50
ISS (µA)
8
9
14
13
12
11
10
90
3741 G09
7
6–15 20 55 125
VIN = 36V
VIN = 6V
VCC_INT Current Limit
ILOAD (mA)
0
VCC_INT (V)
4
5
6
50
3741 G07
3
1
2
010 20 4030 60
VIN = 12V
TA = 25°C
LT3741
6
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TYPICAL PERFORMANCE CHARACTERISTICS
VCC_INT Load Reg at 12V Regulated Current vs VFB Overvoltage Threshold
Overvoltage Timeout Regulated Sense Voltage Common Mode Lockout
CBOOT-SW UVLO Voltage VCC_INT UVLO
TEMPERATURE (°C)
–50
1.50
VOLTAGE (V)
1.75
2.00
2.25
2.50
2.75
3.00
–15 20 55 90
3741 G11
125
TEMPERATURE (°C)
–50
2.50
UVLO (V)
2.75
3.00
3.25
3.50
3.75
4.00
–15 20 55 90
3741 G12
125
ILOAD (mA)
0
VCC_INT (V)
5.2
5.6
6.0
40
3741 G13
4.8
4.4
4.0 10 20 30 6050
25°C
VFB (V)
1.10
–200
–150
CONTROL CURRENT (%)
–100
–50
0
50
100
150
1.15 1.251.20 1.30
3741 G14
1.35
130°C
–50°C
TEMPERATURE (°C)
–50
OVERVOLTAGE THRESHOLD (V)
1.35
1.45
1.75
1.65
1.55
100
3741 G15
1.25 –25 0 25 50 75 125
TEMPERATURE (°C)
–50
OVERVOLTAGE TIMEOUT (µs)
15
17
19
90
3741 G16
13
11
9–15 20 55 125
VCTRL (V)
0
0
VSENSE+ – VSENSE– (mV)
10
20
30
40
50
60
0.5 1.0 1.5
3741 G17
2.0
TEMPERATURE (°C)
–50
CM LOCKOUT (V)
1.5
2.0
2.5
90
3741 G18
1.0
0.5
0–15 20 55 125
VIN = 6V
VIN = 36V
MEASURED VIN – VOUT
Internal UVLO
TEMPERATURE (°C)
–50
VIN (V)
4.0
4.5
5.0
90
3741 G10
3.5
3.0 –15 20 55 125
LT3741
7
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TYPICAL PERFORMANCE CHARACTERISTICS
Non-Overlap Time Minimum On-Time
Minimum Off-Time
Current Regulation Accuracy
CTRL1 = 1.5V, VIN = 12V
Current Regulation Accuracy
CTRL1 = 0.75V, VIN = 12V
HG Driver RDS(ON) LG Driver RDS(ON)
TEMPERATURE (°C)
–50
RDS(ON) ()
3
4
5
90
3741 G20
2
1
0–15 20 55 125
PULL-UP
PULL-DOWN
TEMPERATURE (°C)
–50
RDS(ON) ()
3
4
5
90
3741 G21
2
1
0–15 20 55 125
PULL-UP
PULL-DOWN
TEMPERATURE (°C)
–50
NON-OVERLAP TIME (ns)
90
120
150
90
3741 G23
60
30
0–15 20 55 125
HG TO LG
LG TO HG
TEMPERATURE (°C)
–50
MINIMUM ON-TIME (ns)
90
120
150
90
3741 G24
60
30
0–15 20 55 125
HG
LG
TEMPERATURE (°C)
–50
MINIMUM OFF-TIME (ns)
180
240
300
90
3741 G25
120
60
0–15 20 55 125
HG
LG
OUTPUT VOLTAGE (V)
0
–3
ACCURACY (%)
–2
–1
0
1
2
3
2.5 5.0 7.5 10
3741 G26
25°C
OUTPUT VOLTAGE (V)
0
–6
ACCURACY (%)
–4
–2
0
2
4
6
2.5 5.0 7.5 10
3741 G27
25°C
Overcurrent Threshold
CTRL_H (V)
0
0
VSENSE+ – VSENSE– (mV)
20
40
60
80
100
120
0.75 1.5 2.25 3.0
3741 G28
TEMPERATURE (°C)
–50
FREQUENCY (MHz)
0.9
1.2
1.5
90
3741 G36
0.6
0.3
0–15 20 55 125
1.2MHz
900kHz
220kHz
Oscillator Frequency
LT3741
8
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TYPICAL PERFORMANCE CHARACTERISTICS
VOUT vs IOUT
IOUT (A)
0246813579
VOUT (V)
10
15
25
20
3741 G22
5
010
VIN = 25V
VOUT = 20V
ILIMIT = 9.5A
VOUT vs IOUT
IOUT (A)
024681012141618
VOUT (V)
6
8
12
10
3741 G33
4
2
020
VIN = 24V
VOUT = 10V
ILIMIT = 18A
LOAD CURRENT (A)
0
EFFICIENCY (%)
100
90
80
70
95
75
85
POWER LOSS (W)
30
25
10
20
0
15
5
15
3741 G29
2520105
EFFICIENCY
POWER LOSS
VIN = 20V
VOUT = 5V
Effi ciency and Power Loss
vs Load Current
IOUT (A)
0 2 4 6 8 10 12 14 16 18 20 22 24
VOUT (V)
3
4
6
5
3741 G19
2
1
026
VIN = 20V
VOUT = 5V
ILIMIT = 24A
VOUT vs IOUT
Effi ciency and Power Loss
vs Load Current
Effi ciency and Power Loss
vs Load Current
LOAD CURRENT (A)
0
EFFICIENCY (%)
100
90
70
50
80
60
40
95
75
55
85
65
45
POWER LOSS (W)
12
10
4
8
0
6
2
15
3741 G37
20105
EFFICIENCY
POWER LOSS
VIN = 24V
VOUT = 10V
LOAD CURRENT (A)
0
EFFICIENCY (%)
100
90
80
70
95
75
85
POWER LOSS (W)
4.8
4.0
1.6
3.2
0
2.4
0.8
6
3741 G30
10842
EFFICIENCY
POWER LOSS
VIN = 25V
VOUT = 20V
LT3741
9
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5A Load Step Recovery
Voltage Regulation with 10A
Regulated Inductor Current
Common Mode Lockout
Shutdown and Recovery
1.5nF Soft-Start Capacitor
VOUT
20mV/DIV
AC-COUPLED
IL
2A/DIV
20ms/DIV 3741 G31
COUT = 470µF
VOUT
2V/DIV
IL
5A/DIV
100µs/DIV 3741 G34
VOUT
2V/DIV
IL
200mA/DIV
1ms/DIV
VIN = 7V
3741 G35
EN/UVLO
5V/DIV
VOUT
2V/DIV
IL
5A/DIV
100µs/DIV 3741 G32
COUT = 1mF
VOUT = 5V
10A LOAD
18A CURRENT LIMIT
TYPICAL PERFORMANCE CHARACTERISTICS
LT3741
10
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PIN FUNCTIONS
(QFN/TSSOP)
EN/UVLO (Pin 1/Pin 4): Enable Pin. The EN/UVLO pin
acts as an enable pin and turns on the internal current
bias core and subregulators at 1.55V. The pin does
not have any pull-up or pull-down, requiring a voltage
bias for normal part operation. Full shutdown occurs at
approximately 0.5V.
VREF (Pin 2/Pin 5): Buffered 2V reference capable of
0.5mA drive.
CTRL2 (Pin 3/Pin 6): Thermal control input used to reduce
the regulated current level.
GND (Pins 4,11,14, Exposed Pad Pin 21/Pins 2,7,16,
Exposed Pad Pin 21): Ground. The exposed pad must be
soldered to the PCB
CTRL1 (Pin 5/Pin 8): The CTRL1 pin sets the high level
regulated output current and overcurrent. The maximum
input voltage is internally clamped to 1.5V. The overcurrent
set point is equal to the high level regulated current level set
by the CTRL1 pin with an additional 23mV offset between
the SENSE+ and SENSE– pins.
SS (Pin 6/Pin 9): The Soft-Start Pin. Place an external
capacitor to ground to limit the regulated current during
start-up conditions. The soft-start pin has a 11µA charg-
ing current. This pin controls regulated output current
determined by CTRL1.
FB (Pin 7/Pin 10): Feedback Pin for Voltage Regulation
and Overvoltage Protection. The feedback voltage is 1.21V.
Overvoltage is also sensed through the FB pin. When the
feedback voltage exceeds 1.5V, the overvoltage lockout
prevents switching for 13s to allow the inductor current
to discharge.
SENSE+ (Pin 8/Pin 11): SENSE+ is the inverting input of
the average current mode loop error amplifi er. This pin is
connected to the external current sense resistor, RS. The
voltage drop between SENSE+ and SENSE– referenced to
the voltage drop across an internal resistor produces the
input voltages to the current regulation loop.
SENSE– (Pin 9/Pin 12): SENSE– is the non-inverting input
of the average current mode loop error amplifi er. The
reference current, based on CTRL1 or CTRL2 fl ows out of
the pin to the output side of the sense resistor, RS.
VC (Pin 10/Pin 13): VC provides the necessary comp-
ensation for the average current loop stability. Typical
compensation values are 20k to 50k for the resistor and
2nF to 5nF for the capacitor.
RT (Pin 12/Pin 14): A resistor to ground sets the switching
frequency between 200kHz and 1MHz. When using the
SYNC function, set the frequency to be 20% lower than
the SYNC pulse frequency. This pin is current limited to
60µA. Do not leave this pin open.
SYNC (Pin 13/Pin 15): Frequency Synchronization Pin.
This pin allows the switching frequency to be synchronized
to an external clock. The RT resistor should be chosen to
operate the internal clock at 20% slower than the SYNC
pulse frequency. This pin should be grounded when not
in use. When laying out board, avoid noise coupling to
or from SYNC trace.
HG (Pin 15/Pin 17): HG is the top-FET gate drive signal
that controls the state of the high-side external power
FET. The driver pull-up impedance is 2.3 and pull-down
impedance is 1.3.
SW (Pin 16/Pin 18): The SW pin is used internally as the
lower-rail for the fl oating high-side driver. Externally, this
node connects the two power-FETs and the inductor.
CBOOT (Pin 17/Pin 19): The CBOOT pin provides a fl oat-
ing 5V regulated supply for the high-side FET driver. An
external Schottky diode is required from the VCC_INT pin
to the CBOOT pin to charge the CBOOT capacitor when
the switch-pin is near ground.
LG (Pin 18/Pin 20): LG is the bottom-FET gate drive signal
that controls the state of the low-side external power-FET.
The driver pull-up impedance is 2.3 and pull-down
impedance is 1.0.
VCC_INT (Pin 19/Pin 1): A regulated 5V output for charging
the CBOOT capacitor. VCC_INT also provides the power for
the digital and switching subcircuits. Below 6V VIN, tie this
pin to the rail. VCC_INT is current limited to 50mA. Shutdown
operation disables the output voltage drive.
VIN (Pin 20/Pin 3): Input Supply Pin. Must be locally
bypassed with a 4.7F low-ESR capacitor to ground.
LT3741
11
3741fb
BLOCK DIAGRAM
–
+
–
+
PWM
COMPARATOR
HIGH SIDE
DRIVER CBOOT
HG
SW
LG
3k
LOW SIDE
DRIVER
RQ
S
gm AMP
gm = 475µA/V
RO = 3.5M
IOUT = 40µA
OSCILLATOR
2V REFERENCE
11µA
90k
1.5V
CURRENT
MIRROR
SYNC
RT
13
CTRL1
5
CTRL BUFFER
VOLTAGE
REGULATOR
AMP
gm = 850µA/V
SS
6
VC
10
CTRL2
3
VREF
2
EN/UVLO
VIN
1
17
VCC_INT 19
VIN 20
15
16
18
SENSE+
12 SYNCRONOUS
CONTROLLER
INTERNAL
REGULATOR
AND
UVLO
100nF
100nF
5.6µF
47µF1µF
0.1µF
150µF
s2
2.4µH
RS
5m
VOUT
10µF
VIN
SYNC
402k
133k
82.5k
–
+
8
SENSE–
9
FB 7
–
+
+
10k
1.21V
40.2k
40.2k
3741 F01
Figure 1. Block Diagram
(QFN Package)
LT3741
12
3741fb
OPERATION
The LT3741 utilizes fi xed-frequency, average current mode
control to accurately regulate the inductor current, inde-
pendently from the output voltage. This is an ideal solu-
tion for applications requiring a regulated current source.
The control loop will regulate the current in the inductor
at an accuracy of ±6%. Once the output has reached the
regulation voltage determined by the resistor divider from
the output to the FB pin and ground, the inductor current
will be reduced by the voltage regulation loop. In voltage
regulation, the output voltage has an accuracy of ±1.5%.
For additional operation information, refer to the Block
Diagram in Figure 1.
The current control loop has two reference inputs, deter-
mined by the voltage at the analog control pins, CTRL1 and
CTRL2. The lower of the two analog voltages on CTRL1
and CTRL2 determines the regulated output current. The
analog voltage at the CTRL1 pin is buffered and produces
a reference voltage across an internal resistor. The internal
buffer has a 1.5V clamp on the output, limiting the analog
control range of the CTRL1 and CTRL2 pins from 0V to
1.5V – corresponding to a 0mV to 51mV range on the
sense resistor, RS. The average current-mode control
loop uses the internal reference voltage to regulate the
inductor current, as a voltage drop across the external
sense resistor, RS.
A 2V reference voltage is provided on the VREF pin to al-
low the use of a resistor voltage divider to the CTRL1 and
CTRL2 pins. The VREF pin can supply up to 500A and is
current limited to 1mA.
The error amplifi er for the average current-mode control
loop has a common mode lockout that regulates the induc-
tor current so that the error amplifi er is never operated out
of the common mode range. The common mode range is
from 0V to 2V below the VIN supply rail.
The overcurrent set point is equal to the regulated current
level set by the CTRL1 pin with an additional 23mV offset
between the SENSE+ and SENSE– pins. The overcurrent
is limited on a cycle-by-cycle basis; shutting switching
down once the overcurrent level is reached. Overcurrent
is not soft-started.
The regulated output voltage is set with a resistor divider
from the output back to the FB pin. The reference at the
FB pin is 1.21V. If the output voltage level is high enough
to engage the voltage loop, the regulated inductor current
will be reduced to support the load at the output. If the
voltage at the FB pin reaches 1.5V (~25% higher than
the regulation level), an internal overvoltage fl ag is set,
shutting down switching for 13s.
The EN/UVLO pin functions as a precision shutdown
pin. When the voltage at the EN/UVLO pin is lower than
1.55V, the internal reset fl ag is asserted and switching is
terminated. Full shutdown occurs at approximately 0.5V
with a quiescent current of less than 1A in full shutdown.
The EN/UVLO pin has 130mV of built-in hysteresis. In
addition, a 5.5µA current source is connected to this pin
that allows any amount of hysteresis to be added with a
series resistor or resistor divider from VIN.
During startup, the SS pin is held low until the internal
reset goes low. Once reset goes low, the capacitor at the
soft-start pin is charged with an 11A current source.
The internal buffers for the CTRL1 and CTRL2 signals are
limited by the voltage at the soft-start pin, slowly ramping
the regulated inductor current to the current determined
by the voltage at the CTRL1 or CTRL2 pins.
The thermal shutdown is set at 163°C with 8°C hysteresis.
During thermal shutdown, all switching is terminated and
the part is in reset (forcing the SS pin low).
The switching frequency is determined by a resistor at
the RT pin. The RT pin is also limited to 60µA, while not
recommended, this limits the switching frequency to 2MHz
when the RT pin is shorted to ground. The LT3741 may
also be synchronized to an external clock through the use
of the SYNC pin.
LT3741
13
3741fb
APPLICATIONS INFORMATION
Programming Inductor Current
The analog voltage at the CTRL1 pin is buffered and
produces a reference voltage, VCTRL, across an internal
resistor. The regulated average inductor current is deter-
mined by:
IO=VCTRL1
30 •RS
where RS is the external sense resistor and IO is the aver-
age inductor current, which is equal to the output current.
Figure 2 shows the maximum output current vs RS. The
maximum power dissipation in the resistor will be:
P
RS =0.05V
()
2
RS
Table 1 contains several resistors values, the corresponding
maximum current and power dissipation in the sense resis-
tor. Susumu, Panasonic and Vishay offer accurate sense
resistors. Figure 3 shows the power dissipation in RS.
Table 1. Sense Resistor Values
MAXIMUM OUTPUT
CURRENT (A) RESISTOR, RS (mΩ) POWER DISSIPATION (W)
1 50 0.05
5 10 0.25
10 5 0.5
25 2 1.25
Inductor Selection
Size the inductor to have approximately 30% peak-to-
peak ripple. The overcurrent set point is equal to the
high level regulated current level set by the CTRL1 pin
with an additional 23mV offset between the SENSE+ and
SENSE– pins. The saturation current for the inductor
should be at least 20% higher than the maximum regulated
current. The following equation sizes the inductor for best
performance:
L=VIN •V
O–V
O
2
0.3 • fS•I
O•V
IN
⎛
⎝
⎜⎞
⎠
⎟
where VO is the output voltage, IO is the maximum regulated
current in the inductor and fS is the switching frequency.
Using this equation, the inductor will have approximately
15% ripple at maximum regulated current.
Table 2. Recommended Inductor Manufacturers
VENDOR WEBSITE
Coilcraft www.coilcraft.com
Sumida www.sumida.com
Vishay www.vishay.com
Würth Electronics www.we-online.com
NEC-Tokin www.nec-tokin.com
RS (m)
0
0
POWER DISSIPATION (W)
0.2
0.6
0.8
1.0
1.4
210 14
3741 F03
0.4
1.2
818 20
4612 16
RS (m)
0
MAXIMUM OUTPUT CURRENT (A)
10
20
30
5
15
25
4 8 12 16
3741 F02
2020 6 10 14 18
Figure 2. RS Value Selection for Regulated Output Current
Figure 3. Power Dissipation in RS
Switching MOSFET Selection
When selecting switching MOSFETs, the following
parameters are critical in determining the best devices for
a given application: total gate charge (QG), on-resistance
LT3741
14
3741fb
(RDS(ON)), gate to drain charge (QGD), gate-to-source
charge (QGS), gate resistance (RG), breakdown voltages
(maximum VGS and VDS) and drain current (maximum ID).
The following guidelines provide information to make the
selection process easier.
Both of the switching MOSFETs need to have their maximum
rated drain currents greater than the maximum inductor current.
The following equation calculates the peak inductor current:
IMAX =IO+VIN •V
O–V
O
2
2•f
S•L•V
IN
⎛
⎝
⎜⎞
⎠
⎟
where VIN is the input voltage, L is the inductance value, VO
is the output voltage, IO is the regulated output current and fS
is the switching frequency. During MOSFET selection, notice
that the maximum drain current is temperature dependant.
Most data sheets include a table or graph of the maximum
rated drain current vs temperature.
The maximum VDS should be selected to be higher than the
maximum input supply voltage (including transient) for both
MOSFETs. The signals driving the gates of the switching
MOSFETs have a maximum voltage of 5V with respect to the
source. During start-up and recovery conditions, the gate drive
signals may be as low as 3V. To ensure that the LT3741 recovers
properly, the maximum threshold should be less than 2V. For
a robust design, select the maximum VGS greater than 7V.
Power losses in the switching MOSFETs are related to the
on-resistance, RDS(ON); the transitional loss related to the gate
resistance, RG; gate-to-drain capacitance, QGD and gate-to-
source capacitance, QGS. Power loss to the on-resistance is an
Ohmic loss, I2 R DS(ON), and usually dominates for input voltages
less than ~15V. Power losses to the gate capacitance dominate
for voltages greater than ~12V. When operating at higher input
voltages, effi ciency can be optimized by selecting a high side
MOSFET with higher RDS(ON) and lower CGD. The power loss
in the high side MOSFET can be approximated by:
PLOSS = (ohmic loss) + (transition loss)
P
LOSS ≈VO
()
VIN
•I
O
2RDS(ON) •ρT
⎛
⎝
⎜⎞
⎠
⎟+
VIN •I
OUT
5V
⎛
⎝
⎜⎞
⎠
⎟•Q
GD +QGS
()
•2•R
G+RPU +RPD
()
()
•f
S
⎛
⎝
⎜⎞
⎠
⎟
where rT is a temperature-dependant term of the MOSFET’s
on-resistance. Using 70°C as the maximum ambient operat-
ing temperature, rT is roughly equal to 1.3. RPD and RPU
are the LT3741 high side gate driver output impedance,
1.3Ω and 2.3Ω respectively.
A good approach to MOSFET sizing is to select a high
side MOSFET, then select the low side MOSFET. The trade-
off between RDS(ON), QG, QGD and QGS for the high side
MOSFET is shown in the following example. VO is equal
to 4V. Comparing two N-channel MOSFETs, with a rated
VDS of 40V and in the same package, but with 8¥ different
RDS(ON) and 4.5¥ different QG and QGD:
M1: RDS(ON) = 2.3mΩ, QG = 45.5nC,
QGS = 13.8nC, QGD = 14.4nC , RG = 1
M2: RDS(ON) = 18mΩ, QG = 10nC,
QGS = 4.5nC, QGD = 3.1nC , RG = 3.5
Power loss for both MOSFETs is shown in Figure 4. Observe
that while the RDS(ON) of M1 is eight times lower, the power
loss at low input voltages is equal, but four times higher
at high input voltages than the power loss for M2.
Power loss within the low side MOSFET is almost entirely
from the RDS(ON) of the FET. Select a low side FET with
the lowest RDS(ON) while keeping the total gate charge QG
to 30nC or less.
Another power loss related to switching MOSFET selection
is the power lost to driving the gates. The total gate charge,
QG, must be charged and discharged each switching cycle.
The power is lost to the internal LDO within the LT3741.
The power lost to the charging of the gates is:
P
LOSS_LDO ≈ (VIN – 5V) • (QGLG + QGHG) • fS
where QGLG is the low side gate charge and QGHG is the
high side gate charge.
Whenever possible, utilize a switching MOSFET that
minimizes the total gate charge to limit the internal power
dissipation of the LT3741.
APPLICATIONS INFORMATION
LT3741
15
3741fb
Table 3. Recommended Switching FETs
VIN
(V)
VOUT
(V)
IOUT
(A) TOP FET BOTTOM FET MANUFACTURER
8 4 5-10 RJK0365DPA RJK0330DPB Renesas
www.renesas.com
24 4 5 RJK0368DPA RJK0332DPB
24 2-4 20 RJK0365DPA RJK0346DPA
12 2-4 10 FDMS8680 FDMS8672AS Fairchild
www.fairchildsemi.com
36 4 20 Si7884BDP SiR470DP Vishay
www.vishay.com
24 4 40 PSMN4R0-
30YL
RJK0346DPA NXP/Philips
www.nxp.com
Input Capacitor Selection
The input capacitor should be sized at 4µF for every 1A
of output current and placed very close to the high side
MOSFET. A small 1µF ceramic capacitor should be placed
near the VIN and ground pins of the LT3741 for optimal
noise immunity. The input capacitor should have a ripple
current rating equal to half of the maximum output current.
It is recommended that several low ESR ceramic capacitors
be used as the input capacitance. Use only type X5R or
X7R capacitors as they maintain their capacitance over a
wide range of operating voltages and temperatures.
Output Capacitor Selection
The output capacitors need to have very low ESR (equivalent
series resistance) to reduce output ripple. A minimum of
20µF/A of load current should be used in most designs.
The capacitors also need to be surge rated to the maximum
output current. To achieve the lowest possible ESR, several
low ESR capacitors should be used in parallel. Many
applications benefi t from the use of high density POSCAP
capacitors, which are easily destroyed when exposed to
overvoltage conditions. To prevent this, select POSCAP
capacitors that have a voltage rating that is at least 50%
higher than the regulated voltage
CBOOT Capacitor Selection
The CBOOT capacitor must be sized less than 220nF and
more than 50nF to ensure proper operation of the LT3741.
Use 220nF for high current switching MOSFETs with high
gate charge.
VCC_INT Capacitor Selection
The bypass capacitor for the VCC_INT pin should be larger
than 5µF for stability and has no ESR requirement. It
is recommended that the ESR be lower than 50m to
reduce noise within the LT3741. For driving MOSFETs
with gate charges larger than 10nC, use 0.5µF/nC of total
gate charge.
Soft-Start
Unlike conventional voltage regulators, the LT3741 utilizes
the soft-start function to control the regulated inductor
current. The charging current is 11µA and reduces the
regulated current when the SS pin voltage is lower than
CTRL1.
APPLICATIONS INFORMATION
Figure 4a. Power Loss Example for M1 Figure 4b. Power Loss Example for M2
Figure 4
INPUT VOLTAGE (V)
0
4
5
7
30
3741 F04a
3
2
10 20 40
1
0
6
MOSFET POWER LOSS (W)
TOTAL
OHMIC
TRANSITIONAL
INPUT VOLTAGE (V)
0
MOSFET POWER LOSS (W)
1.0
1.5
40
3741 F04b
0.5
010 20 30
2.5
2.0
TOTAL
OHMIC
TRANSITIONAL
LT3741
16
3741fb
Output Current Regulation
To adjust the regulated load current, an analog voltage is
applied to the CTRL1 pin. Figure 5 shows the regulated
voltage across the sense resistor for control voltages
up to 2V. Figure 6 shows the CTRL1 voltage created by
a voltage divider from VREF to ground. When sizing the
resistor divider, please be aware that the VREF pin is current
limited to 500µA. Above 1.5V, the control voltage has no
effect on the regulated inductor current.
APPLICATIONS INFORMATION
LT3741
VREF
R2
R1
3741 F06
CTRL1
Figure 5. Sense Voltage vs CTRL Voltage
Figure 6. Analog Control of Inductor Current
VCTRL (V)
0
0
VSENSE+ – VSENSE– (mV)
10
20
30
40
50
60
0.5 1.0 1.5
3741 F05
2.0
not leave this pin open under any condition. The RT pin
is also current limited to 60µA. See Table 4 and Figure 8
for resistor values and the corresponding switching
frequencies.
Table 4. Switching Frequency
SWITCHING FREQUENCY (MHz) RT (kΩ)
1 40.2
0.750 53.6
0.5 82.5
0.3 143
0.2 200
Figure 7. Output Voltage Regulation and Overvoltage Protection
Feedback Connections
LT3741 R2
VOUT
R1
3741 F07
FB
RT (k)
0
FREQUENCY (MHz)
0.4
0.8
1.2
0.2
0.6
1.0
100 200 300 400
3743 F08
500500 150 250 350 450
Figure 8. Frequency vs RT Resistance
Voltage Regulation and Overvoltage Protection
The LT3741 uses the FB pin to regulate the output voltage
and to provide a high speed overvoltage lockout to avoid
high voltage conditions. The regulated output voltage
is programmed using a resistor divider from the output
and ground (Figure 7). When the output voltage exceeds
125% of the regulated voltage level (1.5V at the FB pin),
the internal overvoltage fl ag is set, terminating switching.
The regulated output voltage must be greater than 1.5V
and is set by the equation:
VOUT =1.21V 1+R2
R1
⎛
⎝
⎜⎞
⎠
⎟
Programming Switching Frequency
The LT3741 has an operational switching frequency range
between 200kHz and 1MHz. This frequency is programmed
with an external resistor from the RT pin to ground. Do
LT3741
17
3741fb
APPLICATIONS INFORMATION
Thermal Shutdown
The internal thermal shutdown within the LT3741 engages
at 163°C and terminates switching and resets soft-start.
When the part has cooled to 155°C, the internal reset is
cleared and soft-start is allowed to charge.
Switching Frequency Synchronization
The nominal switching frequency of the LT3741 is
determined by the resistor from the RT pin to ground and
may be set from 200kHz to 1MHz. The internal oscillator
may also be synchronized to an external clock through the
SYNC pin. The external clock applied to the SYNC pin must
have a logic low below 0.3V and a logic high higher than
1.25V. The input frequency must be 20% higher than the
frequency determined by the resistor at the RT pin. Input
signals outside of these specifi ed parameters will cause
erratic switching behavior and subharmonic oscillations.
Synchronization is tested at 500kHz with a 200k RT resistor.
Operation under other conditions is guaranteed by design.
When synchronizing to an external clock, please be aware
that there will be a fi xed delay from the input clock edge to
the edge of switch. The SYNC pin must be grounded if the
synchronization to an external clock is not required. When
SYNC is grounded, the switching frequency is determined
by the resistor at the RT pin.
Shutdown and UVLO
The LT3741 has an internal UVLO that terminates switching,
resets all synchronous logic, and discharges the soft-start
capacitor for input voltages below 4.2V. The LT3741 also
has a precision shutdown at 1.55V on the EN/UVLO pin.
Partial shutdown occurs at 1.55V and full shutdown is
guaranteed below 0.5V with <1µA IQ in the full shutdown
state. Below 1.55V, an internal current source provides
5.5µA of pull-down current to allow for programmable
UVLO hysteresis. The following equations determine the
voltage divider resistors for programming the UVLO voltage
and hysteresis as confi gured in Figure 9.
R2 =VHYST
5.5µA
R1=1.55V •R2
VUVLO – 1.55V
⎛
⎝
⎜⎞
⎠
⎟
The EN/UVLO pin has an absolute maximum voltage of
6V. To accommodate the largest range of applications,
there is an internal Zener diode that clamps this pin. For
applications where the supply range is greater than 4:1,
size R2 greater than 375k.
Load Current Derating Using the CTRL2 Pin
The LT3741 is designed specifi cally for driving high power
loads. In high current applications, derating the maximum
current based on operating temperature prevents damage
to the load. In addition, many applications have thermal
limitations that will require the regulated current to be re-
duced based on load and/or board temperature. To achieve
this, the LT3741 uses the CTRL2 pin to reduce the effective
regulated current in the load. While CTRL1 programs the
regulated current in the load, CTRL2 can be confi gured to
reduce this regulated current based on the analog voltage
at the CTRL2 pin. The load/board temperature derating is
programmed using a resistor divider with a temperature
dependant resistance (Figure 10). When the board/load
temperature rises, the CTRL2 voltage will decrease. To
reduce the regulated current, the CTRL2 voltage must be
lower than voltage at the CTRL1 pin.
LT3741
VIN
R2
VIN
R1
3741 F09
EN/UVLO
Figure 9. UVLO Confi guration
LT3741
VREF
RNTC RX
RVRV
R2
R1
(OPTION A TO D)
3741 F10
CTRL2
B
RNTC
A
RNTC RX
D
RNTC
C
Figure 10. Load Current Derating vs Temperature
Using NTC Resistor
LT3741
18
3741fb
APPLICATIONS INFORMATION
the error amplifi er will be the compensation resistor, RC.
Use the following equation as a good starting point for
compensation component sizing:
RC=fS• L • 1000V
VO•RS
[Ω], CC=0.002
fS
[F]
where fS is the switching frequency, L is the inductance
value, VO is the output voltage and RS is the sense resistor.
For most applications, a 4.7nF compensation capacitor
is adequate and provides excellent phase margin with
optimized bandwidth. Please refer to Table 6 for recom-
mended compensation values.
Board Layout Considerations
Average current mode control is relatively immune to the
switching noise associated with other types of control
schemes. Placing the sense resistor as close as possible
to the SENSE+ and SENSE– pins avoids noise issues. Due
to sense resistor ESL (equivalent series inductance), a
10 resistor in series with the SENSE+ and SENSE– pins
with a 33nF capacitor placed between the SENSE pins is
recommended. Utilizing a good ground plane underneath
the switching components will minimize interplane noise
coupling. To dissipate the heat from the switching com-
ponents, use a large area for the switching mode while
keeping in mind that this negatively affects the radiated
noise.
Average Current Mode Control Compensation
The use of average current mode control allows for precise
regulation of the inductor and load currents. Figure 11
shows the average current mode control loop used in the
LT3741, where the regulation current is programmed by
a current source and a 3k resistor.
To design the compensation network, the maximum com-
pensation resistor needs to be calculated. In current mode
controllers, the ratio of the sensed inductor current ramp
to the slope compensation ramp determines the stability
of the current regulation loop above 50% duty cycle. In
the same way, average current mode controllers require
the slope of the error voltage to not exceed the PWM ramp
slope during the switch off-time.
Since the closed-loop gain at the switching frequency
produces the error signal slope, the output impedance of
–
+
gm
ERROR AMP
MODULATOR
LOAD
RC
LR
S
3k
VCTRL • 11µA/V
CC
3741 F11
Figure 11. LT3741 Average Current Mode Control Scheme
Table 6. Recommended Compensation Values
VIN (V) VO (V) IL (A) fSW (MHz) L (μH) RS (mΩ) RC (kΩ) CC (nF)
12 4 5 0.5 1.5 5 47.5 4.7
12 4 10 0.5 1.5 5 47.5 4.7
12 5 20 0.25 1.8 2.5 38.3 8.2
24 4 2 0.5 1.0 2.5 52.3 4.7
24 4 20 0.5 1.0 2.5 52.3 4.7
LT3741
19
3741fb
20A Super Capacitor Charger with 5V Regulated Output
EN/UVLOEN/UVLO
HG
VIN
CBOOT
VREF
CTRL1
CTRL2
LT3741
RT
SYNC
SW
LG
GND
VC
SENSE+
SENSE–
VCC_INT
100nF
L1
1.0µH
22µF
33nF
R1
2.5m
FB
10nF
47.5k L1: IHLP4040DZER1R0M01
M1: RJK0365DPA
M2: RJK0346DPA
R1: VISHAY WSL25122L500FEA
4.7nF
82.5k
50k
38.3k
10 10
3741 TA02
12.1k
150µF
s2
2.2µF
RNTC
470k
100µF
M1
M2
VIN
10V TO 36V
VOUT
20A MAXIMUM
1µF
SS
RHOT
45.3k
Effi ciency and Power Loss
vs Load Current
IOUT (A)
024681012141618202224
VOUT (V)
3
4
6
5
3741 TA02c
2
1
026
VIN = 20V
VOUT = 5V
ILIMIT = 20A
VOUT vs IOUT
LOAD CURRENT (A)
0
EFFICIENCY (%)
100
90
80
70
95
75
85
POWER LOSS (W)
30
25
10
20
0
15
5
15
3741 TA02b
2520105
EFFICIENCY
POWER LOSS
VIN = 20V
VOUT = 5V
TYPICAL APPLICATIONS
LT3741
20
3741fb
TYPICAL APPLICATIONS
20A LED Driver
EN/UVLOEN/UVLO
HG
VIN
CBOOT
VREF
CTRL1
CTRL2
LT3741
RT
SYNC
SW
LG
GND
VCH
SENSE+
SENSE–
VCC_INT
150nF L1
1.1µH
22µF
R1
2.5m
FB
10nF
82.5k
4.7nF
82.5k
47.5k
L1: MVR1261C-112ML
M1: VISHAY SiR462DP
M2: VISHAY SiR462DP
R1: VISHAY WSL25122L500FEA
3741 TA03
12.1k
2.2µF
RNTC
470k
100µF
M1
M2
VIN
12V TO 36V
VOUT
6V, 20A MAXIMUM
680µF
D1
1µF
SS
RHOT
45.3k
CONTROL
INPUT
33nF
10 10
LED Current Waveforms 10A to
20A Current Step
CTRL1
1V/DIV
ILED
5A/DIV
1ms/DIV 3741 TA03b
0.75V
1.5V
10A
20A
10A Single-Cell Lithium-Ion Battery Charger
EN/UVLO
CTRL1 HG
VIN
CBOOT
VREF
CTRL2
LT3741
RT
SYNC SW
LG
GND
VC
SENSE+
SENSE–
VCC_INT
220nF L1
2.2µH
3.6V
22µF
1%
5m
FB
1nF
82.5k
8.2nF
82.5k
30.1k
3741 TA04
12.1k
RNTC
470k
33µF
VIN
24V
VOUT
4.2V, 10A MAXIMUM
2.2µF
1µF
SS
RHOT
45.3k
µCONTROLLER
+
22nF
10
L1: IHLP4040DZER2R2M01
M1: RJK0365DPA
M2: RJKO346DPA
10
M1
M2
LT3741
21
3741fb
PACKAGE DESCRIPTION
4.00 ± 0.10
4.00 ± 0.10
NOTE:
1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220
VARIATION (WGGD-1)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
2019
1
2
BOTTOM VIEW—EXPOSED PAD
2.00 REF
2.45 ± 0.10
0.75 ± 0.05 R = 0.115
TYP
R = 0.05
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF20) QFN 01-07 REV A
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.00 REF 2.45 ± 0.05
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
PIN 1 NOTCH
R = 0.20 TYP
OR 0.35 × 45°
CHAMFER
2.45 ± 0.10
2.45 ± 0.05
UF Package
20-Lead Plastic QFN (4mm ¥ 4mm)
(Reference LTC DWG # 05-08-1710 Rev A)
LT3741
22
3741fb
PACKAGE DESCRIPTION
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
FE20 (CB) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
134
5678910
111214 13
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
2.74
(.108)
20 1918 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC 0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
3.86
(.152)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LT3741
23
3741fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 8/10 Revised to ±1.5% Voltage Regulation Accuracy in Features section
Revised Absolute Maximum Ratings to delete CBOOT-SW Voltage
Updated Electrical Characteristics section
Updated RT, HG and LG pin descriptions
Updated Block Diagram
Revised text, added a paragraph and revised equations in Applications Information section
Revised Table 4 and Switching Frequency Synchronization paragraph in the Applications Information section
Revised Typical Applications drawings and added vendor part numbers
Updated Related Parts
1
2
3, 4
10
11
13, 14
16, 17
19, 20, 24
24
B 9/10 Revised Voltage Regulator Amp value to gm = 800µA/V on Figure 1 Block Diagram 11
LT3741
24
3741fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
” LINEAR TECHNOLOGY CORPORATION 2010
LT 0910 REV B • PRINTED IN USA
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