K7M321825M-65 - Samsung Electronics

1Mx36 & 2Mx18 Flow-Through NtRAMTM

- 1 - Rev 0.0

May 2001

K7M321825M

K7M323625M Preliminary

1Mx36 & 2Mx18-Bit Flow Through NtRAMTM

The K7M323625M and K7M321825M are 37,748,736-bits Syn-

chronous Static SRAMs.

The NtRAMTM, or No Turnaround Random Access Memory uti-

lizes all bandwidth in any combination of operating cycles.

Address, data inputs, and all control signals except output

enable and linear burst order are synchronized to input clock.

Burst order control must be tied "High or Low".

Asynchronous inputs include the sleep mode enable(ZZ).

Output Enable controls the outputs at any given time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-chip

write pulse generation

and provides increased timing flexibility for incoming signals.

For read cycles, Flow-Through SRAM allows output data to

simply flow freely from the memory array.

The K7M323625M and K7M321825M are implemented with

SAMSUNG′s high performance CMOS technology and is avail-

able in 100pin TQFP and 119BGA packages. Multiple power

and ground pins minimize ground bounce.

GENERAL DESCRIPTIONFEATURES

LOGIC BLOCK DIAGRAM

• 3.3V+0.165V/-0.165V Power Supply.

• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O

• Byte Writable Function.

• Enable clock and suspend operation.

• Single READ/WRITE control pin.

• Self-Timed Write Cycle.

• Three Chip Enable for simple depth expansion with no data

contention .

• A interleaved burst or a linear burst mode.

• Asynchronous output enable control.

• Power Down mode.

• TTL-Level Three-State Outputs.

• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package).

NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung.

WE

BWx

CLK

CKE

CS1

CS2

ADV

OE

ZZ

DQa0 ~ DQd7 or DQa0 ~ DQb8

ADDRESS

REGISTER

CONTROL

LOGIC

A′0~A′1

36 or 18

DQPa ~ DQPd

BUFFER

DATA-IN

REGISTER

K

REGISTER

BURST

ADDRESS

COUNTER

WRITE

CONTROL

LOGIC

CONTROL

REGISTER

K

A [0:19]or

A [0:20]

LBO

A2~A19 or A2~A20

A0~A1

(x=a,b,c,d or a,b)

1Mx36 , 2Mx18

MEMORY

ARRAY

FAST ACCESS TIMES

Parameter Symbol -65 -75 -85 -90 Unit

Cycle Time tCYC 7.5 8.5 10 10 ns

Clock Access Time tCD 6.5 7.5 8.5 9.0 ns

Output Enable Access Time tOE 3.5 3.5 4.0 4.0 ns

1Mx36 & 2Mx18 Flow-Through NtRAMTM

- 2 - Rev 0.0

May 2001

K7M321825M

K7M323625M Preliminary

PIN CONFIGURATION(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

(20mm x 14mm)

DQPc

DQc0

DQc1

VDDQ

VSSQ

DQc2

DQc3

DQc4

DQc5

VSSQ

VDDQ

DQc6

DQc7

Vss

VDD

VSS

DQd0

DQd1

VDDQ

VSSQ

DQd2

DQd3

DQd4

DQd5

VSSQ

VDDQ

DQd6

DQd7

DQPd

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQPb

DQb7

DQb6

VDDQ

VSSQ

DQb5

DQb4

DQb3

DQb2

VSSQ

VDDQ

DQb1

DQb0

VSS

VDD

ZZ

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

A6

A7

CS1

CS2

BWd

BWc

BWb

BWa

CS2

VDD

VSS

CLK

WE

CKE

OE

ADV

A18

A17

A8

81 A9

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

A16

A15

A14

A13

A12

A11

A10

A19

N.C.

VDD

VSS

N.C.

A0

A1

A2

A3

A4

A5

31LBO

PIN NAME

Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.

A0 - A18

ADV

WE

CLK

CKE

CS1

CS2

BWx(x=a,b,c,d)

OE

ZZ

LBO

Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

Byte Write Inputs

Output Enable

Power Sleep Mode

Burst Mode Control

32,33,34,35,36,37,43

4445,46,47,48,49,50,

8182,83,84,99,100

85

88

89

87

98

97

92

93,94,95,96

86

64

31

VDD

VSS

N.C.

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

VDDQ

VSSQ

Power Supply(+3.3V)

Ground

No Connect

Data Inputs/Outputs

Output Power Supply

(2.5V or 3.3V)

Output Ground

15,16,41,65,91

14,17,40,66,67,90

38,39,42,43

52,53,56,57,58,59,62,63

68,69,72,73,74,75,78,79

2,3,6,7,8,9,12,13

18,19,22,23,24,25,28,29

51,80,1,30

4,11,20,27,54,61,70,77

5,10,21,26,55,60,71,76

K7M323625M(1Mx36)

VSS

1Mx36 & 2Mx18 Flow-Through NtRAMTM

- 3 - Rev 0.0

May 2001

K7M321825M

K7M323625M Preliminary

PIN CONFIGURATION(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin TQFP

(20mm x 14mm)

N.C.

VDDQ

VSSQ

N.C.

DQb8

DQb7

VSSQ

VDDQ

DQb6

DQb5

VSS

VDD

VSS

DQb4

DQb3

VDDQ

VSSQ

DQb2

DQb1

DQb0

N.C.

VSSQ

VDDQ

N.C.

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A10

N.C.

VDDQ

VSSQ

N.C.

DQa0

DQa1

DQa2

VSSQ

VDDQ

DQa3

DQa4

VSS

VDD

ZZ

DQa5

DQa6

VDDQ

VSSQ

DQa7

DQa8

N.C.

VSSQ

VDDQ

N.C.

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

A6

A7

CS1

CS2

BWb

BWa

CS2

VDD

VSS

CLK

WE

CKE

OE

ADV

A19

A18

A8

81 A9

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

A17

A16

A15

A14

A13

A12

A11

A20

N.C.

VDD

VSS

N.C.

A0

A1

A2

A3

A4

A5

31LBO

K7M321825M(2Mx18)

N.C.

PIN NAME

Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

SYMBOL PIN NAME TQFP PIN NO. SYMBOL PIN NAME TQFP PIN NO.

A0 - A19

ADV

WE

CLK

CKE

CS1

CS2

BWx(x=a,b)

OE

ZZ

LBO

Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

Byte Write Inputs

Output Enable

Power Sleep Mode

Burst Mode Control

32,33,34,35,36,37,43

44,45,46,47,48,49,50,

8081,82,83,84,99,100

85

88

89

87

98

97

92

93,94

86

64

31

VDD

VSS

N.C.

DQa0~a8

DQb0~b8

VDDQ

VSSQ

Power Supply(+3.3V)

Ground

No Connect

Data Inputs/Outputs

Output Power Supply

(2.5V or 3.3V)

Output Ground

15,16,41,65,91

14,17,40,66,67,90

1,2,3,6,7,25,28,29,30,

38,39,42,43,51,52,53,

56,57,75,78,79,95,96

58,59,62,63,68,69,72,73,74

8,9,12,13,18,19,22,23,24

4,11,20,27,54,61,70,77

5,10,21,26,55,60,71,76

1Mx36 & 2Mx18 Flow-Through NtRAMTM

- 4 - Rev 0.0

May 2001

K7M321825M

K7M323625M Preliminary

119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)

K7M323625M(1Mx36)

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

1234567

AVDDQ AAAAAVDDQ

BNC CS2AADV ACS2NC

CNC A A VDD A A NC

DDQc DQPc VSS NC VSS DQPb DQb

EDQc DQc VSS CS1VSS DQb DQb

FVDDQ DQc VSS OE VSS DQb VDDQ

GDQc DQc BWcABWbDQb DQb

HDQc DQc VSS WE VSS DQb DQb

JVDDQ VDD NC VDD NC VDD VDDQ

KDQd DQd VSS CLK VSS DQa DQa

LDQd DQd BWdNC BWaDQa DQa

MVDDQ DQd VSS CKE VSS DQa VDDQ

NDQd DQd VSS A1*VSS DQa DQa

PDQd DQPd VSS A0*VSS DQPa DQa

RNC ALBO VDD NC ANC

TNC NC AAAAZZ

UVDDQ TMS TDI TCK TDO NC VDDQ

PIN NAME

SYMBOL PIN NAME SYMBOL PIN NAME

A

A0,A1

ADV

WE

CLK

CKE

CS1

CS2

BWx

(x=a,b,c,d)

OE

ZZ

LBO

TCK

TMS

TDI

TDO

Address Inputs

Burst Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

Byte Write Inputs

Output Enable

Power Sleep Mode

Burst Mode Control

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

VDD

VSS

N.C.

DQa

DQb

DQc

DQd

DQPa~Pd

VDDQ

Power Supply

Ground

No Connect

Data Inputs/Outputs

Output Power Supply

1Mx36 & 2Mx18 Flow-Through NtRAMTM

- 5 - Rev 0.0

May 2001

K7M321825M

K7M323625M Preliminary

119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)

K7M321825M(2Mx18)

Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

1234567

AVDDQ AAAAAVDDQ

BNC CS2AADV ACS2NC

CNC A A VDD A A NC

DDQb NC VSS NC VSS DQPa NC

ENC DQb VSS CS1VSS NC DQa

FVDDQ NC VSS OE VSS DQa VDDQ

GNC DQb BWbA VSS NC DQa

HDQb NC VSS WE VSS DQa NC

JVDDQ VDD NC VDD NC VDD VDDQ

KNC DQb VSS CLK VSS NC DQa

LDQb NC VSS NC BWaDQa NC

MVDDQ DQb VSS CKE VSS NC VDDQ

NDQb NC VSS A1*VSS DQa NC

PNC DQPb VSS A0*VSS NC DQa

RNC ALBO VDD NC ANC

TNC AAAAAZZ

UVDDQ TMS TDI TCK TDO NC VDDQ

PIN NAME

SYMBOL PIN NAME SYMBOL PIN NAME

A

A0,A1

ADV

WE

CLK

CKE

CS1

CS2

BWx

(x=a,b)

OE

ZZ

LBO

TCK

TMS

TDI

TDO

Address Inputs

Burst Address Inputs

Address Advance/Load

Read/Write Control Input

Clock

Clock Enable

Chip Select

Byte Write Inputs

Output Enable

Power Sleep Mode

Burst Mode Control

JTAG Test Clock

JTAG Test Mode Select

JTAG Test Data Input

JTAG Test Data Output

VDD

VSS

N.C.

DQa

DQb

DQPa, Pb

VDDQ

Power Supply

Ground

No Connect

Data Inputs/Outputs

Output Power Supply