34 .80 7IRELESS IMPORTANT NOTICE Dear customer, As from August 2nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. Company name - Philips Semiconductors is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of each page "(c) Koninklijke Philips Electronics N.V. 200x. All rights reserved", shall now read: "(c) ST-NXP Wireless 200x All rights reserved". Web site - http://www.semiconductors.philips.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices previously obtained by sending an email to sales.addresses@www.semiconductors.philips.com, is now found at http://www.stnwireless.com under Contacts. If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless 34 .80 7IRELESS www.stnwireless.com PDIUSBD12 Universal Serial Bus peripheral controller with parallel bus Rev. 09 -- 11 May 2006 Product data sheet 1. General description The PDIUSBD12 is a cost- and feature-optimized USB peripheral controller. It is normally used in microcontroller-based systems and communicates with the system microcontroller over the high-speed general-purpose parallel interface. It also supports local DMA transfer. This modular approach to implementing a USB interface allows the designer to choose the optimum system microcontroller from the wide variety available. This flexibility cuts down development time, risks and costs, by allowing the use of the existing architecture, minimizing firmware investments. This results in the fastest way to develop the most cost-effective USB peripheral solution. The PDIUSBD12 fully conforms to Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s). It is also designed to be compliant with most device class specifications: imaging class, mass storage devices, communication devices, printing devices and human interface devices. The PDIUSBD12 is ideally suited for many peripherals, such as printer, scanner, external mass storage (Zip drive) and digital still camera. It offers an immediate cost reduction for applications that currently use SCSI implementations. The PDIUSBD12 low suspend power consumption along with the LazyClock output allows for easy implementation of equipment that is compliant to the ACPI, OnNow and USB power management requirements. The low operating power allows the implementation of bus powered peripherals. It also incorporates features, such as SoftConnect, GoodLink, programmable clock output, low frequency crystal oscillator, and integration of termination resistors. All of these features contribute to significant cost savings in the system implementation and at the same time ease the implementation of advanced USB functionality into peripherals. 2. Features Complies with Universal Serial Bus specification Rev. 2.0 Supports data transfer at full-speed (12 Mbit/s) High performance USB peripheral controller with integrated SIE, FIFO memory, transceiver and voltage regulator Compliant with most device class specifications High-speed (2 MB/s) parallel interface to any external microcontroller or microprocessor Fully autonomous DMA operation Integrated 320 B of multi-configuration FIFO memory PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus Double buffering scheme for main endpoint increases throughput and eases real-time data transfer Data transfer rates: 1 MB/s achievable in bulk mode, 1 Mbit/s achievable in isochronous mode Bus-powered capability with very good EMI performance Controllable LazyClock output during suspend Software-controllable connection to the USB bus (SoftConnect) Good USB connection indicator that blinks with traffic (GoodLink) Programmable clock frequency output Complies with the ACPI, OnNow and USB power management requirements Internal Power-On Reset (POR) and low-voltage reset circuit Available in SO28 and TSSOP28 pin packages Full industrial grade operation from -40 C to +85 C Full-scan design with high fault coverage (> 99 %) ensures high quality Operation with dual voltages: 3.3 V 0.3 V or extended 5 V supply range of 4.0 V to 5.5 V Multiple interrupt modes to facilitate both bulk and isochronous transfers 3. Ordering information Table 1. Ordering information Outside North America North America PDIUSBD12D PDIUSBD12D Package Temperature range Name Description SO28 plastic small outline package; 28 leads; -40 C to +85 C SOT136-1 body width 7.5 mm PDIUSBD12PW PDIUSBD12PW DH TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm PDIUSBD12_9 Product data sheet Version -40 C to +85 C SOT361-1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 2 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 4. Block diagram 6 MHz PLL UPSTREAM PORT 3.3 V D+ SoftConnect BIT CLOCK RECOVERY D- D+ 1.5 k INTEGRATED RAM ANALOG TX/RX MEMORY MANAGEMENT UNIT PHILIPS SIE VOLTAGE REGULATOR PARALLEL AND DMA INTERFACE 004aaa796 This is a conceptual block diagram and does not include each individual signal. Fig 1. Block diagram 5. Pinning information 5.1 Pinning DATA0 1 28 A0 DATA1 2 27 VOUT3.3 DATA2 3 26 D+ DATA3 4 25 D- GND 5 24 VCC DATA4 6 23 XTAL2 DATA5 7 DATA6 8 DATA7 9 PDIUSBD12 22 XTAL1 21 GL_N 20 RESET_N ALE 10 19 EOT_N 18 DMACK_N CS_N 11 17 DMREQ SUSPEND 12 CLKOUT 13 16 WR_N INT_N 14 15 RD_N 004aaa532 Fig 2. Pin configuration PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 3 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 5.2 Pin description Table 2. Pin description Symbol Pin Type[1] Description DATA0 1 IO2 bit 0 of bidirectional data; slew-rate controlled DATA1 2 IO2 bit 1 of bidirectional data; slew-rate controlled DATA2 3 IO2 bit 2 of bidirectional data; slew-rate controlled DATA3 4 IO2 bit 3 of bidirectional data; slew-rate controlled GND 5 P ground DATA4 6 IO2 bit 4 of bidirectional data; slew-rate controlled DATA5 7 IO2 bit 5 of bidirectional data; slew-rate controlled DATA6 8 IO2 bit 6 of bidirectional data; slew-rate controlled DATA7 9 IO2 bit 7 of bidirectional data; slew-rate controlled ALE 10 I Address Latch Enable: The falling edge is used to close the latch of the address information in a multiplexed address or data bus. Permanently tied to LOW for separate address or data bus configuration. CS_N 11 I chip select (active LOW) When the CS_N pin is LOW, ensure that the RESET_N pin is in inactive state; otherwise, the device will enter test mode. SUSPEND 12 I, OD4 device is in the suspend state CLKOUT 13 O2 programmable output clock (slew-rate controlled) INT_N 14 OD4 interrupt (active LOW) RD_N 15 I read strobe (active LOW) WR_N 16 I write strobe (active LOW). DMREQ 17 O4 DMA request DMACK_N 18 I DMA acknowledge (active LOW) EOT_N 19 I end of DMA transfer (active LOW); double up as VBUS sensing. EOT_N is only valid when asserted together with DMACK_N and either RD_N or WR_N. RESET_N 20 I reset (active LOW and asynchronous); built-in power-on reset circuit is present on-chip, so the pin can be tied HIGH to VCC When the RESET_N pin is LOW, ensure that the CS_N pin is in inactive state; otherwise, the device will enter test mode. GL_N 21 OD8 GoodLink LED indicator (active LOW) XTAL1 22 I crystal connection 1 (6 MHz) XTAL2 23 O crystal connection 2 (6 MHz); if the external clock signal, instead of the crystal, is connected to XTAL1, then XTAL2 should be floated VCC 24 P voltage supply (4.0 V to 5.5 V) To operate the IC at 3.3 V, supply 3.3 V to both the VCC and VOUT3.3 pins. D- 25 A USB D- data line PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 4 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus Table 2. Pin description ...continued Symbol Pin Type[1] Description D+ 26 A USB D+ data line VOUT3.3 27 P 3.3 V regulated output; to operate the IC at 3.3 V, supply a 3.3 V to both the VCC and VOUT3.3 pins A0 28 I address bit A0 = 1 -- Selects the command instruction A0 = 0 -- selects the data phase This bit is a don't care in a multiplexed address and data bus configuration and should be tied to HIGH. [1] P: power or ground; A: analog; I: input; O: Output; O2: Output with 2 mA drive; OD4: Output open-drain with 4 mA drive; OD8: Output open-drain with 8 mA drive; IO2: Input and output with 2 mA drive; O4: Output with 4 mA drive. PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 5 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 6. Functional description 6.1 Analog transceiver The integrated transceiver directly interfaces to USB cables through termination resistors. 6.2 Voltage regulator A 3.3 V regulator is integrated on-chip to supply the analog transceiver. This voltage is also provided as an output to connect to the external 1.5 k pull-up resistor. Alternatively, the PDIUSBD12 provides the SoftConnect technology with an integrated 1.5 k pull-up resistor. 6.3 PLL A 6 MHz-to-48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows the use of a low-cost 6 MHz crystal. ElectroMagnetic Interference (EMI) is also minimized because of the lower frequency crystal. No external components are needed for the operation of the PLL. 6.4 Bit clock recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4 x over-sampling principle. It can track jitter and frequency drift specified by Universal Serial Bus Specification Rev. 2.0. 6.5 Philips Serial Interface Engine (PSIE) The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel or serial conversion, bit stuffing or discarding stuffed bits, CRC checking or generation, PID verification or generation, address recognition, and handshake evaluation or generation. 6.6 SoftConnect The connection to the USB is accomplished by connecting D+ (for full-speed USB device) to HIGH through a 1.5 k pull-up resistor. In the PDIUSBD12, the 1.5 k pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established through a command sent by the external or system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection to the USB. Re-initialization of the USB bus connection can also be performed without requiring to pull out the cable. The PDIUSBD12 will check for USB VBUS availability before the connection can be established. The VBUS sensing is provided using pin EOT_N. For details, see Section 5.2. Sharing of the VBUS sensing and EOT_N can be easily accomplished by using the VBUS voltage as the pull-up voltage for the normally open-drain output of the DMA controller pin. Remark: The tolerance of internal resistors is higher (25 %) than that specified in Universal Serial Bus Specification Rev. 2.0 (5 %). The overall voltage specification for the connection, however, can still be met with good margin. The decision to make sure of this feature lies with users. PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 6 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 6.7 GoodLink A good USB connection indication is provided through the GoodLink technology. During enumeration, the LED indicator will momentarily blink on corresponding to the enumeration traffic. When the PDIUSBD12 is successfully enumerated and configured, the LED indicator will be permanently on. Subsequent successful (with acknowledgment) transfer to and from the PDIUSBD12 will blink off the LED. During suspend, the LED will be off. This feature provides a user-friendly indication on the status of the USB device, the connected hub and the USB traffic. It is a useful field diagnostics tool to isolate faulty equipment. This feature helps lower field support and hotline costs. 6.8 Memory Management Unit (MMU) and integrated RAM The difference between MMU and the integrated RAM buffer lies in the speed between USB, running in bursts of 12 Mbit/s and the parallel interface to the microcontroller. This allows the microcontroller to read and write USB packets at its own speed. 6.9 Parallel and DMA interface A generic parallel interface is defined for ease-of-use and speed, and allows direct interfacing to major microcontrollers. To a microcontroller, the PDIUSBD12 appears as a memory device with 8-bit data bus and 1-bit address line (occupying two locations). The PDIUSBD12 supports both multiplexed and non-multiplexed address and data bus. The PDIUSBD12 also supports Direct Memory Access (DMA) transfer that allows the main endpoint (endpoint 2) to directly transfer to and from the local shared memory. Both single-cycle and burst mode DMA transfers are supported. 6.10 Example of parallel interface to an 80C51 microcontroller In the example shown in Figure 3, the ALE pin is permanently tied to LOW to signify a separate address and data bus configuration. The A0 pin of the PDIUSBD12 connects to any of the 80C51 I/O ports. This port controls the command or data phase to the PDIUSBD12. The multiplexed address and data bus of the 80C51 can now be directly connected to the data bus of the PDIUSBD12. The address phase will be ignored by the PDIUSBD12. The clock input signal of the 80C51 (pin XTAL1) can be provided by output CLKOUT of the PDIUSBD12. PDIUSBD12 INT_N A0 DATA[7:0] 80C51 INTO/P3.2 ANY I/O PORT (for example, P3.3) P[0.7:0.0] /AD[7:0] WR_N WR/P3.6 RD_N RD/P3.7 CLKOUT CS_N XTAL1 ANY I/O PORT ALE 004aaa155 Fig 3. Example of a parallel interface to an 80C51 microcontroller PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 7 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 7. Direct Memory Access (DMA) transfer DMA allows an efficient transfer of a block of data between the host and local shared memory. Using a DMA Controller (DMAC), the data transfer between the main endpoint (endpoint 2) of the PDIUSBD12 and the local shared memory can occur autonomously, without the local CPU intervention. Preceding any DMA transfer, the local CPU receives from the host the necessary setup information and accordingly programs the DMA controller. Typically, the DMA controller is set up for demand transfer mode, and the Byte Count register and the address counter are programmed with the correct values. In this mode, transfers occur only when the PDIUSBD12 requests them and are terminated when the Byte Count register reaches zero. After the DMA controller is programmed, the DMA ENABLE bit of the PDIUSBD12 is set by the local CPU to initiate the transfer. The PDIUSBD12 can be programmed for single-cycle DMA or burst mode DMA. In single-cycle DMA, the DMREQ pin is deactivated for every single acknowledgment by DMACK_N before being re-asserted. In burst mode DMA, the DMREQ pin is kept active for the number of bursts programmed in the device before going inactive. This process continues until the PDIUSBD12 receives a DMA termination notice through pin EOT_N. This will generate an interrupt to notify the local CPU that the DMA operation is completed. For the DMA read operation, the DMREQ pin will only be activated whenever the buffer is full, signaling that the host has successfully transferred a packet to the PDIUSBD12. With the double buffering scheme, the host can start filling up the second buffer while the first buffer is being read out. This parallel processing increases the effective throughput. When the host does not completely fill up the buffer (less than 64 B or 128 B for single direction ISO configuration), the DMREQ pin will be deactivated at the last byte of the buffer, regardless of the current DMA burst count. It will be re-asserted on the next packet with a refreshed DMA burst count. Similarly, for DMA write operations, the DMREQ pin remains active whenever the buffer is not full. When the buffer is filled up, the packet is sent over to the host on the next IN token and DMREQ will be reactivated if the transfer was successful. Also, the double buffering scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt), the buffer needs to be completely filled up by the DMA write operation before data is sent to the host. The only exception is at the end of DMA transfer, when the reception of the EOT_N pin will stop the DMA write operation and the buffer content will be sent to the host on the next IN token. For isochronous transfers, the local CPU and DMA controller have to guarantee that they can sink or source the maximum packet size in one USB frame (1 ms). The assertion of pin DMACK_N automatically selects the main endpoint (endpoint 2), regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can be interleaved with normal I/O access to other endpoints. The DMA operation can be terminated by resetting the DMA ENABLE register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N. PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 8 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus The PDIUSBD12 supports DMA transfer in single address mode and it can also work in dual address mode of the DMA controller. In single address mode, the DMA transfer is done using the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In dual address mode, pins DMREQ, DMACK_N and EOT_N are not used; instead CS_N, WR_N and RD_N control signals are used. The I/O mode transfer protocol of the PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read cycle and the destination during the write cycle. Transfer needs to be done in two separate bus cycles, temporarily storing data in the DMAC. 8. Endpoint description The PDIUSBD12 endpoints are sufficiently generic to be used by various device classes ranging from imaging, printer, mass storage and communication device classes. The PDIUSBD12 endpoints can be configured for four operating modes, depending on the Set Mode command. The four modes are: Mode 0 Non-isochronous transfer (Non-ISO mode) Mode 1 Isochronous output only transfer (ISO-OUT mode) Mode 2 Isochronous input only transfer (ISO-IN mode) Mode 3 Isochronous input and output transfer (ISO-I/O mode) PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 9 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus Table 3. Endpoint configuration Endpoint number Endpoint index Transfer type Direction[1] Max. Packet size (bytes) control OUT 16 IN 16 OUT 16 IN 16 OUT 64 [4] IN 64 [4] control OUT 16 IN 16 generic[2] OUT 16 Mode 0 (Non-ISO mode) 0 0 1 1 generic[2] 2 3 2 generic[2][3] 4 5 Mode 1 (ISO-OUT mode) 0 0 1 2 1 3 2 4 IN 16 isochronous[3] OUT 128 [4] control OUT 16 IN 16 OUT 16 Mode 2 (ISO-IN mode) 0 0 1 generic[2] 1 2 3 IN 2 5 isochronous[3] IN 128 [4] control OUT 16 IN 16 generic[2] OUT 16 IN 16 OUT 64 [4] IN 64[4] 16 Mode 3 (ISO-I/O mode) 0 0 1 2 1 3 2 4 isochronous[3] 5 [1] IN: input for the USB host; OUT: output from the USB host. [2] Generic endpoints can be used either as bulk or interrupt endpoint. [3] The main endpoint (endpoint number 2) is double-buffered to ease synchronization with real-time applications and to increase throughput. This endpoint supports DMA access. [4] Denotes double buffering. The size shown is for a single buffer. PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 10 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 9. Main endpoint The main endpoint (endpoint number 2) is the primary endpoint for sinking or sourcing relatively large amounts of data. It implements the following features to ease this task: * Double buffering. This allows parallel operation between the USB access and the local CPU access, increasing throughput. Buffer switching is automatically handled. This results in transparent buffer operation. * DMA operation. This can be interleaved with normal I/O operation to other endpoints. * Automatic pointer handling during the DMA operation. No local CPU intervention is necessary when `crossing' the buffer boundary. * Configurable endpoint for either isochronous transfer or non-isochronous (bulk and interrupt) transfer. 10. Command summary Table 4. Command summary Name Destination Code (Hex) Transaction Set Address/Enable device D0 write 1 B Set Endpoint Enable device D8 write 1 B Set Mode device F3 write 2 B Set DMA device FB write or read 1 B Read Interrupt register device F4 read 2 B Select Endpoint control OUT 00 read 1 B (optional) control IN 01 read 1 B (optional) endpoint 1 OUT 02 read 1 B (optional) endpoint 1 IN 03 read 1 B (optional) endpoint 2 OUT 04 read 1 B (optional) endpoint 2 IN 05 read 1 B (optional) control OUT 40 read 1 B control IN 41 read 1 B endpoint 1 OUT 42 read 1 B endpoint 1 IN 43 read 1 B endpoint 2 OUT 44 read 1 B endpoint 2 IN 45 read 1 B Read Buffer selected endpoint F0 read n B Write Buffer selected endpoint F0 write n B Initialization commands Data flow commands Read Last Transaction Status PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 11 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus Table 4. Command summary ...continued Name Destination Code (Hex) Transaction Set Endpoint Status control OUT 40 write 1 B control IN 41 write 1 B endpoint 1 OUT 42 write 1 B endpoint 1 IN 43 write 1 B endpoint 2 OUT 44 write 1 B endpoint 2 IN 45 write 1 B Acknowledge Setup selected endpoint F1 none Clear Buffer selected endpoint F2 none Validate Buffer selected endpoint FA none Send Resume F6 none Read Current Frame Number F5 read 1 or 2 B General commands 11. Command description 11.1 Command procedure There are three basic types of commands: initialization, data flow and general. Respectively, these are used to initialize the function; for data flow between the function and the host; and some general commands. 11.2 Initialization commands Initialization commands are used during the enumeration process of the USB network. These commands are used to enable function endpoints. They are also used to set the USB assigned address. 11.2.1 Set Address/Enable Code (Hex) -- D0 Transaction -- write 1 B This command is used to set the USB assigned address and enable the function. 7 6 5 4 3 0 0 0 0 0 2 1 0 0 0 0 Power-on value ADDRESS ENABLE 004aaa797 ADDRESS: The value written becomes the address. ENABLE: Logic 1 enables this function. Fig 4. Set Address/Enable command: bit allocation PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 12 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 11.2.2 Set Endpoint Enable Code (Hex) -- D8 Transaction -- write 1 B The generic or isochronous endpoints can only be enabled when the function is enabled using the Set Address/Enable command. 7 6 5 4 3 2 1 0 X X X X X X X 0 Power-on value GENERIC/ISOCHRONOUS ENDPOINTS reserved; write 0 004aaa798 GENERIC OR ISOCHRONOUS ENDPOINTS: Logic 1 indicates that generic or isochronous endpoints are enabled. Fig 5. Set Endpoint Enable command: bit allocation 11.2.3 Set Mode Code (Hex) -- F3 Transaction -- write 2 B The Set Mode command is followed by two data writes. The first byte contains configuration bits. The second byte is the clock division factor byte. 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 Power-on value reserved NO LAZYCLOCK CLOCK RUNNING INTERRUPT MODE SoftConnect reserved; write 0 ENDPOINT CONFIGURATION 004aaa799 For bit allocation, see Table 5. Fig 6. Set Mode command, configuration byte: bit allocation PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 13 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus Table 5. Bit Set Mode command, configuration byte: bit allocation Symbol Description 7 to 6 ENDPOINT CONFIGURATION These two bits set endpoint configurations as follows: Mode 0 (Non-ISO mode) Mode 1 (ISO-OUT mode) Mode 2 (ISO-IN mode) Mode 3 (ISO-I/O mode) For details, see Section 8. 4 SoftConnect Logic 1 indicates that the upstream pull-up resistor will be connected if VBUS is available. Logic 0 means that the upstream resistor will not be connected. The programmed value will not be changed by a bus reset. 3 INTERRUPT MODE Logic 1 indicates that all errors and `NAK' are reported and will generate an interrupt. Logic 0 indicates that only OK is reported. The programmed value will not be changed by a bus reset. 2 CLOCK RUNNING Logic 1 indicates that internal clocks and PLL are always running even during the suspend state. Logic 0 indicates that the internal clock, crystal oscillator and PLL are stopped, whenever not needed. To meet the strict suspend current requirement, this bit must be set to logic 0. The programmed value will not be changed by a bus reset. 1 NO LAZYCLOCK Logic 1 indicates that CLKOUT will not switch to LazyClock. Logic 0 indicates that CLKOUT switches to LazyClock 1 ms after the SUSPEND pin goes HIGH. LazyClock frequency is 30 kHz 40 %. The programmed value will not be changed by a bus reset. 7 6 5 4 3 2 1 0 0 0 X X 1 0 1 1 Power-on value CLOCK DIVISION FACTOR reserved SET_TO_ONE SOF-ONLY INTERRUPT MODE 004aaa800 For bit allocation, see Table 6. Fig 7. Set Mode command, clock division factor byte: bit allocation PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 14 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus Table 6. Set Mode command, clock division factor byte: bit allocation Bit Symbol Description 7 SOF-ONLY INTERRUPT MODE Setting this bit to logic 1 will cause the interrupt line to be activated because of the Start-Of-Frame (SOF) clock only, regardless of the setting of PIN-INTERRUPT MODE, bit 5 of Set DMA. 6 SET_TO_ONE This bit must be set to logic 1 before any DMA read or DMA write operation. This bit should always be set to logic 1 after power. It is zero after power-on reset. 3 to 0 CLOCK DIVISION FACTOR The value indicates the clock division factor for CLKOUT. The output frequency is 48 MHz / (N + 1), where N is the clock division factor. The reset value is 11. This will produce an output frequency of 4 MHz that can then be programmed up or down by the user. The minimum value is 1, giving a frequency range of 4 MHz to 24 MHz. The minimum value of N is 0, giving a maximum frequency of 48 MHz. The maximum value of N is 11, giving a minimum frequency of 4 MHz. The PDIUSBD12 design ensures no glitching during frequency change. The programmed value will not be changed by a bus reset. 11.2.4 Set DMA Code (Hex) -- FB Transaction -- read or write 1 B The Set DMA command is followed by one data write or read to or from the DMA Configuration register. 11.2.4.1 DMA Configuration register During the DMA operation, the 2 B buffer header (status and byte length information) is not transferred to or from the local CPU. This allows the DMA data to be continuous and not interleaved by chunks of these headers. For DMA read operations, the header will be skipped by the PDIUSBD12. See Section 11.3.5 command. For DMA write operations, the header will be automatically added by the PDIUSBD12. This provides a clean and simple DMA data transfer. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Power-on value DMA BURST DMA ENABLE DMA DIRECTION AUTO RELOAD INTERRUPT PIN MODE ENDPOINT INDEX 4 INTERRUPT ENABLE ENDPOINT INDEX 5 INTERRUPT ENABLE 004aaa801 For bit allocation, see Table 7. Fig 8. Set DMA command: bit allocation PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 15 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus Table 7. Set DMA command: bit allocation Bit Symbol Description 7 ENDPOINT INDEX 5 INTERRUPT ENABLE Logic 1 allows an interrupt to be generated whenever the endpoint buffer is validated (see Section 11.3.8 command). Normally turned off for the DMA operation to reduce unnecessary CPU servicing. 6 ENDPOINT INDEX 4 INTERRUPT ENABLE Logic 1 allows an interrupt to be generated whenever the endpoint buffer contains a valid packet. Normally turned off for the DMA operation to reduce unnecessary CPU servicing. 5 INTERRUPT PIN MODE Logic 0 signifies a normal interrupt pin mode in which an interrupt is generated as a logical OR of all the bits in interrupt registers. Logic 1 signifies that the interrupt will occur when SOF clock is seen on the upstream USB bus. The other normal interrupts are still active. 4 AUTO RELOAD When this bit is set to logic 1, the DMA operation will automatically restart. 3 DMA DIRECTION This bit determines the direction of data flow during a DMA transfer. Logic 1 means from the external shared memory to the PDIUSBD12 (DMA write); logic 0 means from the PDIUSBD12 to the external shared memory (DMA read). 2 DMA ENABLE Writing logic 1 to this bit will start the DMA operation through the assertion of pin DMREQ. The main endpoint buffer must be full (for DMA read) or empty (for DMA write), before DMREQ is asserted. In single cycle DMA mode, the DMREQ is deactivated on receiving DMACK_N. In burst mode DMA, the DMREQ is deactivated after the number of burst is exhausted. It is then asserted again for the next burst. This process continues until EOT_N is asserted together with DMACK_N and either RD_N or WR_N, which will reset this bit to logic 0 and terminate the DMA operation. The DMA operation can also be terminated by writing logic 0 to this bit. 1 to 0 DMA BURST Selects the burst length for DMA operation: 00 Single-cycle DMA 01 Burst (4-cycle) DMA 10 Burst (8-cycle) DMA 11 Burst (16-cycle) DMA 11.3 Data flow commands Data flow commands are used to manage the data transmission between USB endpoints and the external microcontroller. Much of the data flow is initiated using an interrupt to the microcontroller. The microcontroller utilizes these commands to access and determine whether endpoint FIFOs have valid data. 11.3.1 Read Interrupt register Code (Hex) -- F4 Transaction -- read 2 B PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 16 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus This command indicates the origin of an interrupt. The endpoint interrupt bits (bits 0 to 5) are cleared by reading the Endpoint Last Transaction Status register through Read Last Transaction Status command. The other bits are cleared after reading Interrupt registers. 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Power-on value CONTROL OUT ENDPOINT CONTROL IN ENDPOINT ENDPOINT 1 OUT ENDPOINT 1 IN MAIN OUT ENDPOINT MAIN IN ENDPOINT BUS RESET SUSPEND CHANGE 004aaa802 For bit allocation, see Table 8. Fig 9. Interrupt register, byte 1: bit allocation 7 6 5 4 3 2 1 0 X X X X X X X 0 Power-on value DMA EOT reserved 004aaa803 DMA EOT: This bit signifies that the DMA operation is completed. Fig 10. Interrupt register, byte 2: bit allocation Table 8. Read Interrupt register, byte 1: bit allocation Bit Symbol Description 7 SUSPEND CHANGE When the PDIUSBD12 does not receive three SOFs, it will go into the suspend state and the SUSPEND CHANGE bit will be HIGH. Any change to the suspend or awake state will set this bit to HIGH and generate an interrupt. 6 BUS RESET After a bus reset, an interrupt will be generated and this bit will be logic 1. A bus reset is identical to a hardware reset through the RESET_N pin, except a bus reset generates an interrupt notification and the device is enabled at default address 0. PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 17 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 11.3.2 Select Endpoint Code (Hex) -- 00 to 05 Transaction -- read 1 B (optional) The Select Endpoint command initializes an internal pointer to the start of the selected buffer. Optionally, this command can be followed by a data read, which returns this byte. 7 6 5 4 3 2 1 0 Power-on value X X X X X X 0 0 FULL/EMPTY STALL reserved 004aaa804 FULL/EMPTY: Logic 1 indicates that the buffer is full, logic 0 indicates an empty buffer. STALL: Logic 1 indicates that the selected endpoint is in the stall state. Fig 11. Select Endpoint command: bit allocation 11.3.3 Read Endpoint Status Code (Hex) -- 80 to 85 Transaction -- read 1 B 7 6 5 4 3 2 1 0 0 0 0 x x 0 x x reserved SETUP PACKET reserved BUFFER 0 FULL BUFFER 1 FULL ENDPOINT STALLED 004aaa056 Fig 12. Read Endpoint Status: bit allocation 11.3.4 Read Last Transaction Status register Code (Hex) -- 40 to 45 Transaction -- read 1 B The Read Last Transaction Status command is followed by one data read that returns the status of the last transaction of the endpoint. This command also resets the corresponding interrupt flag in the Interrupt register, and clears the status, indicating that it was read. This command is useful for debugging purposes. The status information is overwritten for each new transaction because it keeps track of every transaction. PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 18 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 7 6 5 4 3 0 0 0 0 0 2 1 0 0 0 0 Power-on value DATA RECEIVE/TRANSMIT SUCCESS ERROR CODE (see table) SETUP PACKET DATA 0/1 PACKET PREVIOUS STATUS NOT READ 004aaa805 For bit allocation, see Table 9. Fig 13. Read Last Transaction Status register: bit allocation Table 9. Read Last Transaction Status register: bit allocation Bit Symbol Description 7 PREVIOUS STATUS NOT READ Logic 1 indicates a second event occurred before the previous status was read. 6 DATA0/1 PACKET Logic 1 indicates the last successful received or sent packet had a DATA1 PID. 5 SETUP PACKET Logic 1 indicates the last successful received packet had a SETUP token (this will always read 0 for IN buffers). 4 to 1 ERROR CODE See Table 10 0 DATA RECEIVE/TRANSMIT Logic 1 indicates that data has been successfully received SUCCESS or transmitted. Table 10. Error codes Error code (binary) Description 0000 no error 0001 PID encoding error; bits 7 to 4 are not the inversion of bits 3 to 0 0010 PID unknown; encoding is valid, but PID does not exist 0011 unexpected packet; packet is not of the type expected (= token, data or acknowledge), or SETUP token to a non-control endpoint 0100 token CRC error 0101 data CRC error 0110 time-out error 0111 never happens 1000 unexpected End-Of-Packet (EOP) 1001 sent or received NAK 1010 sent stall, a token was received, but the endpoint was stalled 1011 overflow error, the received packet was longer than the available buffer space 1101 bit stuff error 1111 wrong DATA PID; the received DATA PID was not what was expected PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 19 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 11.3.5 Read Buffer Code (Hex) -- F0 Transaction -- read multiple bytes (max. 130) The Read Buffer command is followed by a number of data reads that return contents of the selected endpoint data buffer. After each read, the internal buffer pointer is incremented by 1. The buffer pointer is reset to the top of the buffer by the Read Buffer command. This means that reading or writing a buffer can be interrupted by any other command (except for Select Endpoint). The data in the buffer is organized as follows: * * * * * Byte 0: reserved; can have any value Byte 1: number or length of data bytes Byte 2: data byte 1 Byte 3: data byte 2 and so on The first two bytes will be skipped in the DMA read operation. Therefore, the first read will get data byte 1, the second read will get data byte 2, and so on. The PDIUSBD12 can determine the last byte of this packet through the EOP termination of the USB packet. 11.3.6 Write Buffer Code (Hex) -- F0 Transaction -- write multiple bytes (max. 130) The Write Buffer command is followed by a number of data writes that load the endpoints buffer. Data must be organized in the same way as described in the Read Buffer command. The first byte (reserved) should always be 0. During the DMA write operation, the first two bytes will be bypassed. Therefore, the first write will write into data byte 1, the second write will write into data byte 2, and so on. For non-isochronous transfer (bulk or interrupt), the buffer must be completely filled before data is sent to the host and a switch to the next buffer occurs. The exception is at the end of the DMA transfer indicated by activation of EOT_N, when the current buffer content (completely full or not) will be sent to the host. Remark: There is no protection against writing or reading over a buffer's boundary, or against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation. Data in an OUT buffer is only meaningful after a successful transaction. The exception is during the DMA operation on the main endpoint (endpoint 2), in which case the pointer is automatically pointed to the second buffer after reaching the boundary (double buffering scheme). 11.3.7 Clear Buffer Code (Hex) -- F2 Transaction -- none PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 20 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus When a packet is completely received, an internal endpoint buffer full flag is set. All subsequent packets will be refused by returning a NAK. When the microcontroller has read data, it should free the buffer using the Clear Buffer command. When the buffer is cleared, new packets will be accepted. 11.3.8 Validate Buffer Code (Hex) -- FA Transaction -- none When the microprocessor has written data into an IN buffer, it should set the buffer full flag using the Validate Buffer command. This indicates that data in the buffer is valid and can be sent to the host when the next IN token is received. 11.3.9 Set Endpoint Status Code (Hex) -- 40 to 45 Transaction -- write 1 B A stalled control endpoint is automatically un-stalled when it receives a SETUP token, regardless of the content of the packet. If the endpoint should stay in its stalled state, the microcontroller can re-stall it. When a stalled endpoint is un-stalled (either by the Set Endpoint Status command or by receiving a SETUP token), it is also re-initialized. This flushes the buffer and if it is an OUT buffer it waits for a DATA0 PID, if it is an IN buffer it writes a DATA0 PID. Even when un-stalled, writing logic 0 to Set Endpoint Status initializes the endpoint. 7 6 5 4 3 2 1 0 X X X X X X X 0 Power-on value STALLED reserved 004aaa806 STALLED: Logic 1 indicates the endpoint is stalled. Fig 14. Set Endpoint Status: bit allocation 11.3.10 Acknowledge Setup Code (Hex) -- F1 Transaction -- none The arrival of a SETUP packet flushes the IN buffer, and disables the Validate Buffer and Clear Buffer commands for both IN and OUT endpoints. The microcontroller needs to re-enable these commands using the Acknowledge Setup command. This ensures that the last SETUP packet stays in the buffer and no packet can be sent back to the host, until the microcontroller has acknowledged explicitly that it has seen the SETUP packet. PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 21 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus The microcontroller must send the Acknowledge Setup command to both the IN and OUT endpoints. 11.4 General commands 11.4.1 Send Resume Code (Hex) -- F6 Transaction -- none Sends an upstream resume signal for 10 ms. This command is normally issued when the device is in suspend. The Resume command is not followed by a data read or write. 11.4.2 Read Current Frame Number Code (Hex) -- F5 Transaction -- read 1 or 2 B This command is followed by one or two data reads and returns the frame number of the last successfully received SOF. The frame number is returned least significant byte first. 7 6 5 4 3 2 1 0 X X X X X X X X least significant byte 7 6 5 4 3 2 1 0 0 0 0 0 0 X X X most significant byte 004aaa807 Fig 15. Read Current Frame Number 12. Interrupt modes Table 11. Interrupt modes SOF-ONLY INTERRUPT MODE[1] INTERRUPT PIN MODE[2] Interrupt types 0 0 Normal[3] 0 1 Normal + SOF [3] 1 X SOF only [1] Bit 7 of the clock division factor byte of the Set Mode command (see Table 6). [2] Bit 5 of the Set DMA command (see Table 7). [3] Normal interrupts from the Interrupt register. PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 22 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 13. Limiting values Table 12. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage VI input voltage Ilu latch-up current VI < 0 V or VI > VCC Vesd electrostatic discharge voltage ILI < 1 A Tstg storage temperature Ptot total power dissipation [1] Conditions [1] VCC = 5.5 V Min Max Unit -0.5 +6.0 V -0.5 VCC + 0.5 V V - 100 mA -2000 +2000 V -60 +150 C - 95 mW Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 14. Recommended operating conditions Table 13. Recommended operating conditions Min Typ Max Unit VCC1 Symbol Parameter supply voltage 1 apply VCC1 to VCC pin only [1] 4.0 - 5.5 V VCC2 supply voltage 2 apply VCC2 to both the VCC and VOUT3.3 pins [2] 3.0 - 3.6 V VI input voltage 0 - 5.5 V VI/O voltage on an input/output pin 0 - 5.5 V VIA(I/O) input voltage on analog I/O pins 0 - 3.6 V VO output voltage 0 - VCC V -40 - +85 C Tamb ambient temperature [1] Supply voltage (main mode). [2] Supply voltage (alternate mode). [3] Operating ambient temperature in free air. Conditions see Section 15 and Section 16 per device [3] 15. Static characteristics Table 14. Static characteristics (digital pins) Symbol Parameter Conditions Min Typ Max Unit Input levels VIL LOW-level input voltage - - 0.8 V VIH HIGH-level input voltage 2.0 - - V Vhys hysteresis voltage Schmitt trigger pins 0.4 - 0.7 V IOL = rated drive - - 0.4 V IOL = 20 A - - 0.1 V Output levels VOL LOW-level output voltage PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 23 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus Table 14. Static characteristics (digital pins) ...continued Symbol Parameter Conditions Min Typ Max Unit VOH HIGH-level output voltage IOH = rated drive 2.4 - - V IOH = 20 A VCC - 0.1 V - - V open-drain pins -5 - +5 A -5 - +5 A - - 15 A - 15 Leakage current IOZ off-state output current IL leakage current IS suspend current ICC supply current Table 15. Static characteristics (AI/O pins) Symbol Parameter oscillator stopped and inputs to GND/VCC mA Conditions Min Typ Max Unit hi-Z; 0 V < VIN < 3.3 V -10 - +10 A Leakage current data line leakage current IL(dl) Input levels VDI differential input sensitivity |(D+) - (D-)| 0.2 - - V VCM differential common mode range includes VDI range 0.8 - 2.5 V VSE single-ended receiver threshold 0.8 - 2.0 V Output levels VOL LOW-level output voltage RL of 1.5 k to 3.6 V - - 0.3 V VOH HIGH-level output voltage RL of 15 k to GND 2.8 - 3.6 V pin to GND - - 20 pF 29 - 44 1.1 - 1.9 k Capacitance input capacitance Cin Output resistance ZDRV driver output impedance steady state drive [1] Pull-up resistance pull-up resistance ZPU [1] SoftConnect = on Includes external resistors of 18 1 % on D+ and D-. 16. Dynamic characteristics Table 16. Dynamic characteristics (AI/O pins; full-speed) CL = 50 pF; RPU = 1.5 k on D+ to VCC; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit Driver characteristics tR rise time 10 % to 90 % 4 - 20 ns tF fall time 10 % to 90 % 4 - 20 ns tRFM rise time/fall time matching (tR/tF) 90 - 110 % VCRS output signal crossover voltage 1.3 - 2.0 V Driver timing tEOPT source EOP width see Figure 16 160 - 175 ns tDEOP differential data to EOP transition skew see Figure 16 -2 - +5 ns PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 24 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus Table 16. Dynamic characteristics (AI/O pins; full-speed) ...continued CL = 50 pF; RPU = 1.5 k on D+ to VCC; unless otherwise specified.[1] Symbol Parameter Conditions Min Typ Max Unit Receiver timing: -18.5 - +18.5 ns -9 - +9 ns 40 - - ns - - ns tJR1 receiver data jitter tolerance to next transition tJR2 receiver data jitter tolerance for paired transition tEOPR1 EOP width at receiver must reject as EOP; see Figure 16 [2] tEOPR2 EOP width at receiver must accept as EOP; see Figure 16 [2] 82 [1] Test circuit, see Figure 22. [2] Characterized but not implemented as production test. Guaranteed by design. tPERIOD CROSSOVER POINT EXTENDED CROSSOVER POINT DIFFERENTIAL DATA LINES SOURCE EOP WIDTH: tEOPT DIFFERENTIAL DATA TO SEO/EOP SKEW N x tPERIOD + tDEOP RECEIVER EOP WIDTH: tEOPR1, tEOPR2 004aaa808 tPERIOD is the bit duration corresponding with the USB data rate. Fig 16. Differential data-to-EOP transition skew and EOP width Table 17. Dynamic characteristics (parallel interface) Symbol Parameter Conditions Min Typ Max Unit ALE timing tLH ALE HIGH pulse width 20 - - ns tAVLL address valid to ALE LOW time 10 - - ns tLLAX ALE LOW to address transition time - - 10 ns Write timing tCLWL CS_N (DMACK_N) LOW to WR_N LOW time 0 [1] - - ns tWHCH WR_N HIGH to CS_N (DMACK_N) HIGH time 5 - - ns A0 valid to WR_N LOW time 0 [1] - - ns 130[2] tAVWL - - ns tWHAX WR_N HIGH to A0 transition time 5 - - ns tWL WR_N LOW pulse width 20 - - ns tWDSU write data setup time 30 - - ns tWDH write data hold time 10 - - ns tWC write cycle time 500[3] - - ns PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 25 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus Table 17. Dynamic characteristics (parallel interface) ...continued Symbol Parameter Conditions t(WC - WD) write command to write data Min Typ Max Unit 600 - - ns 0 [1] - - ns Read timing tCLRL CS_N (DMACK_N) LOW to RD_N LOW time 130[2] - - ns tRHCH RD_N HIGH to CS_N (DMACK_N) HIGH time 5 - - ns tAVRL A0 valid to RD_N LOW time 0 [1] - - ns tRL RD_N LOW pulse width 20 - - ns tRLDD RD_N LOW to data driven time - - 20 ns tRHDZ RD_N HIGH to data Hi-Z time - - 20 ns tRC read cycle time 500[3] - - ns t(WC - RD) write command to read data 600 - - ns [1] Can be negative. [2] For the DMA access only on the module 64th byte and the second last (EOT - 1) byte. [3] The tWC and tRC timing are valid for back-to-back data access only. tLH ALE tAVLL DATA[7:0] tLLAX ADDRESS DATA 004aaa809 Fig 17. ALE timing PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 26 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus CS_N DMACK_N tCLRL tCLWL tRHCH tWHCH tAVRL tAVWL tWHAX A0 COMMAND = 1, DATA = 0 tWL tWC WR_N t(WC - WD) t(WC - RD) tWDSU tWDH VALID DATA DATA[7:0] tRL tRC RD_N tRHNDV tRHDZ tRLDD DATA[7:0] VALID DATA VALID DATA 004aaa058 tRLDD Fig 18. Parallel interface timing (I/O and DMA) Table 18. Dynamic characteristics (DMA) Symbol Parameter Conditions Min Typ Max Unit Single-cycle DMA timing tAHRH DMACK_N HIGH to DMREQ HIGH time - - 330 ns tSHAH RD_N/WR_N HIGH to DMACK_N HIGH time 130 - - ns tRHSH DMREQ HIGH to RD_N/WR_N HIGH time 120 - - ns tEL EOT_N LOW pulse width 10 - - ns simultaneous DMACK_N, RD_N/WR_N and EOT_N LOW time Burst DMA timing tSLRL RD_N/WR_N LOW to DMREQ LOW time - - 40 ns tRHNDV RD_N (only) HIGH to next data valid - - 420 ns - - 40 ns EOT timing tELRL EOT_N LOW to DMREQ LOW time PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 27 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus tAHRH tRHSH DMREQ DMACK_N tSHAH RD_N/WR_N tEL EOT_N(1) 004aaa810 EOT_N is considered valid when DMACK_N, RD_N/WR_N and EOT_N are all LOW. Fig 19. Single-cycle DMA timing tRHSH DMREQ tSLRL DMACK_N tSHAH RD_N/WR_N 004aaa811 Fig 20. Burst DMA timing DMREQ tELRL DMACK_N RD_N/WR_N EOT_N 004aaa812 Fig 21. DMA terminated by EOT PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 28 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 17. Test information The dynamic characteristics of the analog I/O ports (D+ and D-) as listed in Table 16, were determined using the circuit shown in Figure 22. 1.5 k is internal DUT 22 test point 15 k CL = 50 pF 004aaa813 Fig 22. Load for D+ and D- PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 29 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 18. Package outline SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index Lp L 1 14 e bp 0 detail X w M 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 23. Package outline SOT136-1 (SO28) PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 30 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm D SOT361-1 E A X c HE y v M A Z 15 28 Q A2 (A 3) A1 pin 1 index A Lp 1 L 14 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.8 0.5 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT361-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 24. Package outline SOT361-1 (TSSOP28) PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 31 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 19. Soldering 19.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 19.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 19.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 32 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C. 19.5 Package related soldering information Table 19. Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] Soldering method Wave Reflow[2] BGA, HTSSON..T[3], LBGA, LFBGA, SQFP, SSOP..T[3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[4] suitable PLCC[5], SO, SOJ suitable suitable not recommended[5][6] suitable SSOP, TSSOP, VSO, VSSOP not recommended[7] suitable CWQCCN..L[8], PMFP[9], WQCCN..L[8] not suitable LQFP, QFP, TQFP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. PDIUSBD12_9 Product data sheet not suitable (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 33 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 20. Abbreviations Table 20. Abbreviations Acronym Description ACPI Advanced Configuration and Power Interface CPU Central Processing Unit CRC Cyclic Redundancy Code DMA Direct Memory Access DMAC Direct Memory Access Controller EMI ElectroMagnetic Interference FIFO First In, First Out ISO Isochronous MMU Memory Management Unit NAK Not Acknowledged OD Open-Drain PID Packet Identifier PLL Phase-Locked Loop POR Power-On Reset PSIE Philips Serial Interface Engine RAM Random Access Memory SCSI Small Computer System Interface SIE Serial Interface Engine SOF Start-Of-Frame USB Universal Serial Bus PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 34 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 21. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes PDIUSBD12_9 20060511 Product data sheet - PDIUSBD12-08 Modifications: Updated the following: * The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. * The symbols and parameters have been changed, wherever applicable, to comply with the new presentation and information standard of Philips Semiconductors. * * * Changed terminology interface device to peripheral controller. * * * Section 2 "Features": removed 8 kV in circuit ESD protection from the list. Figure 2 "Pin configuration" updated pin name for pin 24. Added additional description to pin 11 and pin 20. Modified Figure 3 "Example of a parallel interface to an 80C51 microcontroller". Section 11.3.5 "Read Buffer": updated the second paragraph. Table 12 "Limiting values": removed table note 2. PDIUSBD12-08 (9397 750 08969) 20011220 Product data - PDIUSBD12-07 PDIUSBD12-07 (9397 750 08117) 20011127 Product data - PDIUSBD12-06 PDIUSBD12-06 (9397 750 04979) 20010423 Product data - - PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 35 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 22. Legal information 22.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com. 22.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 22.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 22.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GoodLink -- is a trademark of Koninklijke Philips Electronics N.V. SoftConnect -- is a trademark of Koninklijke Philips Electronics N.V. 23. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 36 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 24. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 Endpoint configuration . . . . . . . . . . . . . . . . . . .10 Command summary . . . . . . . . . . . . . . . . . . . .11 Set Mode command, configuration byte: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Set Mode command, clock division factor byte: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Set DMA command: bit allocation . . . . . . . . . .16 Read Interrupt register, byte 1: bit allocation . .17 Read Last Transaction Status register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Error codes . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Interrupt modes . . . . . . . . . . . . . . . . . . . . . . . .22 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .23 Recommended operating conditions . . . . . . . .23 Static characteristics (digital pins) . . . . . . . . . .23 Static characteristics (AI/O pins) . . . . . . . . . . .24 Dynamic characteristics (AI/O pins; full-speed) . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Dynamic characteristics (parallel interface) . . .25 Dynamic characteristics (DMA) . . . . . . . . . . . .27 Suitability of surface mount IC packages for wave and reflow soldering methods . . . . . . . . . . . . .33 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .34 Revision history . . . . . . . . . . . . . . . . . . . . . . . .35 continued >> PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 37 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 25. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .3 Example of a parallel interface to an 80C51 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Set Address/Enable command: bit allocation . . .12 Set Endpoint Enable command: bit allocation . . .13 Set Mode command, configuration byte: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Set Mode command, clock division factor byte: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Set DMA command: bit allocation . . . . . . . . . . . .15 Interrupt register, byte 1: bit allocation . . . . . . . . .17 Interrupt register, byte 2: bit allocation . . . . . . . . .17 Select Endpoint command: bit allocation . . . . . . .18 Read Endpoint Status: bit allocation . . . . . . . . . .18 Read Last Transaction Status register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Set Endpoint Status: bit allocation . . . . . . . . . . . .21 Read Current Frame Number . . . . . . . . . . . . . . .22 Differential data-to-EOP transition skew and EOP width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 ALE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Parallel interface timing (I/O and DMA) . . . . . . . .27 Single-cycle DMA timing . . . . . . . . . . . . . . . . . . .28 Burst DMA timing . . . . . . . . . . . . . . . . . . . . . . . . .28 DMA terminated by EOT . . . . . . . . . . . . . . . . . . .28 Load for D+ and D- . . . . . . . . . . . . . . . . . . . . . . .29 Package outline SOT136-1 (SO28) . . . . . . . . . . .30 Package outline SOT361-1 (TSSOP28). . . . . . . .31 continued >> PDIUSBD12_9 Product data sheet (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 09 -- 11 May 2006 38 of 39 PDIUSBD12 Philips Semiconductors USB peripheral controller with parallel bus 26. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 6 Analog transceiver . . . . . . . . . . . . . . . . . . . . . . 6 Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . . 6 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . . 6 Philips Serial Interface Engine (PSIE) . . . . . . . 6 SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory Management Unit (MMU) and integrated RAM. . . . . . . . . . . . . . . . . . . . . . . . . 7 6.9 Parallel and DMA interface . . . . . . . . . . . . . . . . 7 6.10 Example of parallel interface to an 80C51 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Direct Memory Access (DMA) transfer . . . . . . 8 8 Endpoint description . . . . . . . . . . . . . . . . . . . . . 9 9 Main endpoint. . . . . . . . . . . . . . . . . . . . . . . . . . 11 10 Command summary . . . . . . . . . . . . . . . . . . . . 11 11 Command description . . . . . . . . . . . . . . . . . . . 12 11.1 Command procedure . . . . . . . . . . . . . . . . . . . 12 11.2 Initialization commands . . . . . . . . . . . . . . . . . 12 11.2.1 Set Address/Enable . . . . . . . . . . . . . . . . . . . . 12 11.2.2 Set Endpoint Enable . . . . . . . . . . . . . . . . . . . . 13 11.2.3 Set Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 11.2.4 Set DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11.2.4.1 DMA Configuration register . . . . . . . . . . . . . . 15 11.3 Data flow commands . . . . . . . . . . . . . . . . . . . 16 11.3.1 Read Interrupt register . . . . . . . . . . . . . . . . . . 16 11.3.2 Select Endpoint. . . . . . . . . . . . . . . . . . . . . . . . 18 11.3.3 Read Endpoint Status. . . . . . . . . . . . . . . . . . . 18 11.3.4 Read Last Transaction Status register . . . . . . 18 11.3.5 Read Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.3.6 Write Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.3.7 Clear Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11.3.8 Validate Buffer . . . . . . . . . . . . . . . . . . . . . . . . 21 11.3.9 Set Endpoint Status . . . . . . . . . . . . . . . . . . . . 21 11.3.10 Acknowledge Setup . . . . . . . . . . . . . . . . . . . . 21 11.4 General commands . . . . . . . . . . . . . . . . . . . . 22 11.4.1 Send Resume . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.4.2 Read Current Frame Number . . . . . . . . . . . . . 22 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 19.5 20 21 22 22.1 22.2 22.3 22.4 23 24 25 26 Interrupt modes . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Recommended operating conditions . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Test information. . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 23 23 23 24 29 30 32 32 32 32 33 33 34 35 36 36 36 36 36 36 37 38 39 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Date of release: 11 May 2006 Document identifier: PDIUSBD12_9