LT3462/LT3462A
1
Rev A
For more information www.analog.com
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Inverting 1.2MHz/2.7MHz
DC/DC Converters with
Integrated Schottky
The LT
®
3462/LT3462A are general purpose fixed fre‑
quency current mode inverting DC/DC converters. Both
devices feature an integrated Schottky and a low VCESAT
switch allowing a small converter footprint and lower
parts cost. The LT3462 switches at 1.2MHz while the
LT3462A switches at 2.7MHz. These high speeds enable
the use of tiny, low cost and low height capacitors and
inductors.
The LT3462/LT3462A operate in a dual inductor inverting
topology that filters both the input and output currents.
Very low output voltage ripple approaching 1mVP‑P can
be achieved when ceramic capacitors are used. Fixed fre‑
quency switching ensures a clean output free from low
frequency noise typically present with charge pump solu‑
tions. The 40V switch allows a VIN to VOUT differential of
up to 38V for dual inductor topologies.
Both devices provide a low impedance 1.265V reference
output to supply the feedback resistor network. A ground
referenced, high impedance FB input allows high feedback
resistor values without compromising output accuracy.
APPLICATIONS
All registered trademarks and trademarks are the property of their respective owners.
5V to –5V, 100mA Inverting DC/DC Converter Efficiency
n Integrated Schottky Rectifier
n Fixed Frequency 1.2MHz/2.7MHz Operation
n Very Low Noise: 1mVP-P Output Ripple
n Low VCESAT Switch: 270mV at 250mA
n –5V at 100mA from 5V Input
n –12V at 30mA from 3.3V Input
n Low Input Bias Current GND Based FB Input
n Low Impedance (40Ω) 1.265V Reference Output
n High Output Voltage: Up to –38V
n Wide Input Range: 2.5V to 16V
n Uses Tiny Surface Mount Components
n Low Shutdown Current: <10µA
n Low Profile (1mm) SOT‑23 (ThinSOT™) Package
n 8‑Lead DFN (2mm × 2mm × 0.75mm) Package,
LT3462A Only
n CCD Bias
n LCD Bias
n GaAs FET Bias
n General Purpose Negative Voltage Supply
V
IN
5V
22µH 22µH
267k
68.1k 10µF
22pF
1µF
1µF
VOUT
–5V
100mA
VIN
SW
FB
SDREF
GND
LT3462A
3462 TA01
D
LOAD CURRENT (mA)
0
EFFICIENCY (%)
75
70
65
60
55
3462 TA01b
20 40 8060 100
VIN = 3.3V
VIN = 5V
TA = 25°C
LT3462/LT3462A
2
Rev A
For more information www.analog.com
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Input Voltage (VIN) ....................................................16V
SW Voltage ...............................................................40V
D Voltage ............................................................... –40V
SDREF, FB Voltage ...................................................2.5V
Operating Ambient
Temperature Range (Note 3) ................–40°C to 85°C
(Note 1)
TOP VIEW
FB
GND
GND
SW
SDREF
D
NC
VIN
DC PACKAGE (LT3462A ONLY)
8-LEAD (2mm × 2mm) PLASTIC DFN
TJMAX = 125°C, θJA = 88.5°C/W
EXPOSED PAD (PIN 9) IS GND
9
4
1
2
36
5
7
8
1
2
3
6
5
4
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 125°C, θJA = 192°C/W
VIN
D
SDREF
SW
GND
FB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3462ES6#PBF LT3462ES6#TRPBF LTBBV 6‑Lead Plastic TSOT‑23 –40°C to 85°C
LT3462AES6#PBF LT3462AES6#TRPBF LTBGB 6‑Lead Plastic TSOT‑23 –40°C to 85°C
LT3462AEDC#PBF LT3462AEDC#TRPBF LHGH 8‑Lead (2mm × 2mm) Plastic DFN –40°C to 85°C
Consult ADI Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LT3462#orderinfo
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10sec)
(TSOT‑23 Package Only) ...................................300°C
LT3462/LT3462A
3
Rev A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Current flows out of the pin.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Minimum Operating Voltage 2.5 V
Maximum Operating Voltage 16 V
SDREF Voltage 10µA > ISDREF ≥ –80µA ●1.245 1.265 1.285 V
FB Pin Bias Current (Note 2) 15 50 nA
SDREF Minus FB Voltage 10µA > ISDREF ≥ –80µA ●1.235 1.263 1.285 V
Error Amp Offset Voltage –12 12 mV
SDREF Reference Source Current SDREF >1.2V ●120 180 µA
Supply Current FB = –0.05V, Not Switching
SDREF = 0V, FB = Open, VIN = 5V
2.9
6.5
3.6
10
mA
µA
SDREF Line Regulation 0.007 %/V
Switching Frequency (LT3462) ●0.8 1.2 1.6 MHz
Switching Frequency (LT3462A) ●2.0 2.7 3.5 MHz
Maximum Duty Cycle (LT3462) ●90 %
Maximum Duty Cycle (LT3462A) ●77 %
Switch Current Limit 300 420 mA
Switch VCESAT ISW = 250mA 270 350 mV
Switch Leakage Current VSW = 5V 0.01 1 µA
Rectifier Leakage Current VD = –40V 0.03 4 µA
Rectifier Forward Drop ISCHOTTKY = 250mA 800 1100 mV
SDREF Voltage Low ●0.20 V
SDREF Off‑State Pull‑Up Current 1 2 3 µA
SDREF Turn‑Off Current –300 –200 µA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 3V, unless otherwise noted.
Note 3: The LT3462E is guaranteed to meet specifications from 0°C to
70°C. Specifications over the –40°C to 85°C operating temperature range
are assured by design, characterization and correlation with statistical
process controls.
LT3462/LT3462A
4
Rev A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
(TSOT-23/DFN)
SW (Pin 1/Pin 4): Switch Pin. Connect to external induc‑
tor L1 and positive terminal of transfer cap.
GND (Pin 2/Pins 2, 3): Ground. Tie directly to local
ground plane.
FB (Pin 3/Pin 1): Feedback Pin. Connect resistive divider
tap here. Set R1 according to R1 = R2 • (VOUT/1.265V).
In shutdown, a proprietary shutdown bias current cancel‑
lation circuit allows the internal 3µA source to pull up the
SDREF pin, even with residual negative voltage on VOUT.
SDREF (Pin 4/Pin 8): Dual Function Shutdown and
1.265V Reference Output Pin. Pull to GND with exter‑
nal N‑FET to turn regulator off. Turn‑off pull‑down and
a 2µA internal source will pull SDREF up to turn‑on the
regulator. At turn‑on, a 180µA internal source pulls the
pin to the regulation voltage. The SDREF pin can supply
up to 80µA at 1.265V to bias the feedback resistor divider.
An optional soft‑start circuit capacitor connects from this
pin to –VOUT.
D (Pin 5/Pin 7): Anode Terminal of Integrated Schottky
Diode. Connect to negative terminal of transfer cap and
external inductor L2.
VIN (Pin 6/Pin 5): Input Supply Pin. Must be locally
bypassed.
Exposed Pad (NA/Pin 9): GND. The exposed pad should
be soldered to the PCB ground to achieve the rated ther‑
mal performance.
PIN FUNCTIONS
Oscillator Frequency (LT3462) Current Limit SDREF Minus FB Pin Voltage
Oscillator Frequency (LT3462A) FB Bias Current
Quiescent Current in
Shutdown Mode
TEMPERATURE (°C)
SDREF MINUS FB (V)
1.29
1.28
1.27
1.26
1.25
1.24
1.23
3462 G03
DUTY CYCLE (%)
10
CURRENT LIMIT (mA)
9080604020
3462 G02
30 50 70
480
360
240
120
0
3462 G05 3462 G06
TEMPERATURE (°C)
–40
FREQUENCY (MHz)
1.6
1.5
1.4
1.3
1.2
1.1
1.0 20 60
3462 G01
–20 0 40 80 100
TEMPERATURE (°C)
FREQUENCY (MHz)
3462 G04
3.2
3.0
2.8
2.6
2.4
2.2
2.0
TA = 25°C
SUPPLY VOLTAGE (V)
0
QUIESCENT CURRENT (A)
16
4 8 12
10
8
6
4
2
0
TA = 25°C
FB = N/C
TEMPERATURE (°C)
FB BIAS CURRENT (nA)
80 10040 60200–40 –20
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–40 20 60
–20 0 40 80
100
–40 20 60
–20 0 40 80 100
TA = 25°C
LT3462
LT3462A
LT3462/LT3462A
5
Rev A
For more information www.analog.com
BLOCK DIAGRAM
OPERATION
Figure 1. Block Diagram
The LT3462 uses a constant frequency, current mode
control scheme to provide excellent line and load regula‑
tion. Operation can be best understood by referring to the
Block Diagram in Figure 1. At the start of each oscillator
cycle, the SR latch is set, turning on the power switch
Q1. A voltage proportional to the switch current is added
to a stabilizing ramp and the resulting sum is fed into
the positive terminal of the PWM comparator. When this
voltage exceeds the voltage at the output of the EAMP, the
SR latch is reset, turning off the power switch. The level
at the output of the EAMP is simply an amplified version
of the difference between the feedback voltage and GND.
In this manner, the error amplifier sets the correct peak
current level to keep the output in regulation. If the error
amplifier’s output increases, more current is taken from
the output; if it decreases, less current is taken. One func‑
tion not shown in Figure 1 is the current limit. The switch
current is constantly monitored and not allowed to exceed
the nominal value of 400mA. If the switch current reaches
400mA, the SR latch is reset regardless of the output state
of the PWM comparator. This current limit cell protects
the power switch as well as various external components
connected to the LT3462.
SDREF is a dual function input pin. When driven low it
shuts the part down, reducing quiescent supply current
to less than 10µA. When not driven low, the SDREF pin
has an internal pull‑up current that turns the regulator on.
Once the part is enabled, the SDREF pin sources up to
180µA nominally at a fixed voltage of 1.265V through
external resistor R2 to FB. If there is no fault condition
present, FB will regulate to 0V, and VOUT will regulate to
1.265V • (–R1/R2). An optional soft‑start circuit uses the
fixed SDREF pull‑up current and a capacitor from SDREF
to VOUT to set the dV/dt on VOUT. In shutdown, an FB bias
current cancellation circuit supplies up to 150µA biasing
current to external resistor R1 while VOUT is lower than
FB. This function eliminates R2 loading of SDREF during
shutdown. As a result, supply current in shutdown may
exceed 10µA by the amount of current flowing in R1.
–
+
–
+
–
+
–
+
VOUT VOUT
D
R1 (EXTERNAL)
R2 (EXTERNAL)
FB
RAMP
GENERATOR
SHUTDOWN
BIAS CURRENT
CANCELLATION
1.2MHz*
OSCILLATOR
R
S
Q
A1
E AMP A2
COMP
DRIVER
RC
CC
SW
Q1
0.1Ω
GND
1.265V
REFERENCE
VIN
FB
SDREF
SDREF
SDREF
3462 F01
*LT3462A IS 2.7MHz
CS1
(EXTERNAL)
CS2 (EXTERNAL)
Q2
OFF 3µA
ON 180µA
ISRC
SHUTDOWN
CS1, CS2 OPTIONAL SOFT-START COMPONENTS
DO
LG
LT3462/LT3462A
6
Rev A
For more information www.analog.com
APPLICATIONS INFORMATION
Inrush Current
The LT3462 has a built‑in Schottky diode. When supply
voltage is applied to the VIN pin, the voltage difference
between VIN and VD generates inrush current flowing
from input through the inductor and the Schottky diode
to charge the flying capacitor to VIN. The maximum non‑
repetitive surge current the Schottky diode in the LT3462
can sustain is 1.5A. The selection of inductor and capaci‑
tor value should ensure the peak of the inrush current to
be below 1.5A. The peak inrush current can be calculated
as follows:
IP=V
IN – 0.6
L
C–1
exp – π
2L
C–1
⎛
⎝
⎜
⎜
⎜
⎞
⎠
⎟
⎟
⎟
where L is the inductance between supply and SW, and C
is the capacitance between SW and D.
Table 3 gives inrush peak currents for some component
selections.
Table 3. Inrush Peak Current
VIN (V) L (µH) C (µF) IP (A)
5 22 1 0.70
5 33 1 0.60
12 47 1 1.40
Inductor Selection
Each of the two inductors used with LT3462 should have
a saturation current rating (where inductance is approxi‑
mately 70% of zero current inductance ) of approximately
0.25A or greater. If the device is used in the charge pump
mode, where there is only one inductor, then its rating
should be 0.35A or greater. DCR of the inductors should
be less than 1Ω. For LT3462, a value of 22µH is suitable
if using a coupled inductor such as Sumida CLS62‑220.
If using two separate inductors, increasing the value to
47µH will result in the same ripple current. For LT3462A,
a value of 10µH for the coupled inductor and 22µH for
two inductors will be acceptable for most applications.
Capacitor Selection
Ceramic capacitors are recommended. An X7R or X5R
dielectric should be used to avoid capacitance decreasing
severely with applied voltage and at temperature limits.
The “flying” capacitor between the SW and D pins should
be a ceramic type of value 1µF or more. When used in
the dual inductor or coupled inductor topologies the fly‑
ing capacitor should have a voltage rating that is more
than the difference between the input and output voltages.
For the charge pump inverter topology, the voltage rat‑
ing should be more than the output voltage. The output
capacitor should be a ceramic type. Acceptable output
capacitance varies from 1µF for high VOUT (–36V), to 10µF
for low VOUT (–5V). The input capacitor should be a 1µF
ceramic type and be placed as close as possible to the
LT3462/LT3462A.
Layout Hints
The high speed operation of the LT3462 demands care‑
ful attention to board layout. You will not get advertised
performance with careless layout. Figure 2 shows the rec‑
ommended component placement. A ceramic capacitor
of 1µF or more must be placed close to the IC for input
supply bypassing.
R2
R1
GND
C3
L1
L2
C1
V
OUT
VIN
+
C4
C2
3462 F02
1
2
3 4
5
6
Figure 2. Suggested Layout
LT3462/LT3462A
7
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
Li+ to –8V Supply
–12V Efficiency3.3V to –12V with Soft-Start Circuit
–8V Efficiency
VIN
3.3V
L1
47µH
L2
47µH
R1
267k
R2
27.4k
C3
2.2µF
CS1
100nF
22nF
C4
15pF
C1
4.7µF
C2
1µF
VOUT
–12V
30mA
VIN
SW
FB
SDREF
GND
LT3462
C1: TAIYO YUDEN X5R JMK212BJ475MG
C2: TAIYO YUDEN X5R EMK212BJ105MG
C3: TAIYO YUDEN EMK316BJ225
L1, L2: MURATA LQH32CN470
3462 TA02a
OFF M1
D
LOAD CURRENT (mA)
0
EFFICIENCY (%)
80
75
70
65
60
55
50
3462 TA02b
105 2015 25
35
30
TA = 25°C
VIN = 3.3V
VIN
2.7V
TO 4.2V
L1A
22µH
L1B
22µH
R1
267k
R2
42.2k C3
4.7µF
C4
15pF
C1
4.7µF
C2
1µF
VOUT
–8V
VIN
SW
FB
SDREF
GND
LT3462
C1: TAIYO YUDEN X5R JMK212BJ475MG
C2: TAIYO YUDEN X5R EMK212BJ105MG
C3: TAIYO YUDEN LMK316BJ475
L1: SUMIDA CLS62-220 OR 2X MURATA LQH32CN330
3462 TA03a
D
LOAD CURRENT (mA)
0
20 3010 40
75
70
65
60
55
50
TA = 25°C
VIN = 3.3V
VOUT Reaches –12V in 750µs; Input
Current Peaks at 300mA without CS1
2ms/DIV
IIN
100mA/DIV
OFF
VOUT
10V/DIV
3462 TA02c
VOUT Reaches –12V in 7.5ms; Input
Current Peaks at 125mA with CS1 = 100nF
2ms/DIV
IIN
50mA/DIV
OFF
VOUT
10V/DIV
3462 TA02d
LT3462/LT3462A
8
Rev A
For more information www.analog.com
TYPICAL APPLICATIONS
V
IN
5V
L1
22µH
L2
22µH
R1
267k
R2
68.1k
C3
10µF
C4
22pF
C1
1µF
C2
1µF
VOUT
–5V
100mA
VIN
SW
FB
SDREF
GND
LT3462A
C1: TAIYO YUDEN JMK107BJ105MA
C2: TAIYO YUDEN EMK212BJ105MA
C3: MURATA GRM219R60J106KE19B
L1, L2: MURATA LQH32CN220
3462 TA05a
D
200ns/DIV 3462 TA05b
Switching Waveform
VOUT
1mV/DIV
AC‑COUPLED
VSW
10V/DIV
INDUCTOR
50mA/DIV
5V to –5V Supply (LT3462A)3.3V to –8V (LT3462A)
VIN
2.7V
TO 4.2V
L1A
10µH
L1B
10µH
R1
267k
R2
42.2k C3
4.7µF
C4
22pF
C1
1µF
C2
1µF
VOUT
–8V
35mA
VIN
SW
FB
SDREF
GND
LT3462A
C1: TAIYO YUDEN JMK107BJ105MA
C2: TAIYO YUDEN EMK212BJ105MA
C3: TAIYO YUDEN LMK316BJ475
L1: WURTH 50310057-100
3462 TA04a
D
LT3462/LT3462A
9
Rev A
For more information www.analog.com
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3462#packaging for the most recent package drawings.
2.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
0.64 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
1.37 ±0.10
(2 SIDES)
1
4
85
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DC8) DFN 0409 REVA
0.23 ±0.05
0.45 BSC
0.25 ±0.05
1.37 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.64 ±0.05
(2 SIDES)
1.15 ±0.05
0.70 ±0.05
2.55
±0.05
PACKAGE
OUTLINE
0.45 BSC
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
DC8 Package
8-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1719 Rev A)
LT3462/LT3462A
10
Rev A
For more information www.analog.com
PACKAGE DESCRIPTION
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MA
X
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
Please refer to http://www.linear.com/product/LT3462#packaging for the most recent package drawings.
LT3462/LT3462A
11
Rev A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 05/18 Add 2mm × 2mm 8‑lead DFN package information (A‑grade version only) to data sheet 1, 2, 4, 9
LT3462/LT3462A
12
Rev A
ANALOG DEVICES, INC. 2004-2018
D16961-0-5/18(A)
www.analog.com
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VIN
12V
L1
47µH
R1
432k
R2
15k C3
1µF
50V
C4
5pF
C1
1µF
C2
0.47µF
VOUT
–36V
36mA
VIN
SW
FB
SDREF
GND
LT3462
C1: TAIYO YUDEN X5R EMK212BJ105
C2: MURATA GRM42-6X7R474K50
C3: MURATA GRM42-6X7R474K50 ×2
D1: CENTRAL CMSH5-4-LTN
L1: MURATA LQH32CN470
3462 TA06a
D
D1
100nF
LOAD CURRENT (mA)
0
EFFICIENCY (%)
40
3462 TA06b
20 3010
85
80
75
70
65
60
TA = 25°C
VIN = 12V
12V to –36V DC/DC Converter –36V Efficiency