Data Sheet AS3931 standard 12557-002 AS3931 - 3 axis low power wakeup receiver DATA SHEET - Key Features Three axis wakeup pattern detection Three axis LF field strength measurement Antenna rotation for easy calibration High sensitivity and high dynamic range Wide operating frequency range Reliable, interference resistant wakeup decoding Highly protected differential inputs Ultra low power consumption Sophisticated power management logic that powers down the correlator if no data is received. Main characteristics - Wake up sensitivity: 300 Vpp LF carrier frequency range: 19 - 150 kHz Data rate: 2731 kB/s Current consumption in standby mode: 6.2 A Dynamic range: 60 dB - RSSI step: (V RSSI @ 1 mVpp input amp.): 175 mV General Description AS3931 is an ultra low power, three channel LF ASK receiver designed to operate in various applications such as LF identifications systems and LF tag receivers. AS3931 is able to detect a low frequency ASK-modulated signal by looking for a digital wakeup pattern and generates a WAKE signal after a successful pattern detection. The device incorporates an intelligent pattern detection algorithm that provides reliable operation in presence of strong interference. An RSSI signal can be generated at the RSSI pin for each receiver channel. Applications - LF identification systems LF tag receivers Three dimensional LF field strength measurement systems Ultra low power wake up systems Preliminary - Package, Pinout and Marking 16 pin TSSOP package Antenna rotation switch three independent LF receiver chains Wakeup output combining the three receiver chains Low power 32.768kHz crystal oscillator circuit Serial programming interface Voltage regulator with 2.4 V output, on/off switchable - - Input overload protection Input attenuator Ultra low power LF amplifier with logarithmic envelope output Robust data detector with adaptive slicing threshold that translates the logarithmic envelope into a digital data signal. Error tolerant digital pattern correlator that detects a given code sequence in the received data signal and generates a wakeup signal. Rev No: 002D5, Date: 2002/04/03 2 15 3 14 4 5 6 Each independent LF receiver chain contains: - 16 1 2 3 4 5 6 7 8 12557-002 - 1 AS3931 AS3931 contains: 13 12 11 7 10 8 9 VCC LF1N LF1P LF2N LF2P LF3N LF3P GND 9 10 11 12 13 14 15 16 XIN XOUT WAKE CS SCL SDA RSSI VREG Page 1 of 22 Data Sheet AS3931 Block Diagramm Wak e Log. Env. Amp 3 LF3P LF3N CS SCL SDA Detector 3 WAKE Control Logic Correlator 3 RSSI Data Multiplexer Multiplexer Wak e 3 Input Protection 3 Data 3 Input Attenu ator 3 Correlator 2 Multiplexer LF2P LF2N Detector 2 RSSI Buffer Multiplexer Log. Env. Amp 2 Wak e 1 Input Protection 2 Correlator 1 Wak e 2 Input Attenu ator 2 Detector 1 Data 1 Log. Env. Amp 1 LF1P LF1N Data 2 Input Protection 1 RSSI 1 Input Attenu ator 1 RSSI 2 Rotator RSSI 3 Antenna RSSI Preliminary VCC Regulator VREG Oscillator POR XIN XOUT GND Figure 1. Block Diagram of AS3931 Rev. No: 002D5, Dat e: 2002/04/03 Page 2 of 23 Data Sheet AS3931 Typical Application Circuit VCC RP C BAT Transmitting Antenna Receiving Antennas C REG VCC VREG LF1N RSSI RSSI LF1P SDA DATA LF2N SCL CLOCK LF2P AS3931 CS LF3N WAKE LF3P XOUT GND XIN CHIP SEL WAKE XTAL CA CB Figure 2. Typical application circuit Preliminary Recommended device values Name Description Value Unit C BAT power supply cap blocking cap 100 22 - 33 nF nF pF C REG CA oscillator cap 10 CB XTAL oscillator cap 10 pF crystal 32.768 kHz RP WAKE pull up resistor 100 k Note CC4 from MicroCrystal Table 1. Recommended device values L, R, C of receiving antennas depending on application; Rev. No: 002D5, Dat e: 2002/04/03 Page 3 of 23 Data Sheet AS3931 Block Description Antenna Rotator In order to achiev an optimum assignement of the antennas to the receiving channels, the connections of the antennas to the channels can be changed cyclically with a multiplexer (antenna rotator), which is controlled by an internal register. The register setting can be changed by the serial interface. Input attenuator Input signal attenuation is provided for each channel by means of connecting a 1.5 k resistor across the differential inputs. attenuation is controlled by an internal register. Input shortcutting The differential inputs can be shortcutted by register settings to measure the RSSI offset. In this case, the resistance between the differential inputs is reduced to approximately 500 . Input protection circuit Each signal input has a powerful input overload protection circuit consisting of two protection diodes in anti-parallel connection. Logarithmic envelope amplifiers The logarithmic envelope amplifiers amplify the ASK coded LF input signals. They generate Received Signal Strength Indicator (RSSI) signals which are proportional to the logarithm of the received field strengths within the specified dynamic range. These signals are used for data detection and distance measurements. The RSSI signals are bandwidth limited to reduce noise influence. The slope of the amplifiers in the low signal range can be controlled by register settings: a high slope for increased sensitivity but also increased current consumption and a weak slope with reduced current consumption are possible. Preliminary Detectors The detectors convert the logarithmic envelope signal containing ASK coded data into digital signals. Each detector consists of a lowpass filter for generation of an adaptive threshold and a slicing comparator. A preamble is required for a proper adaptation of the threshold prior to the decision of the first valid data bit. A constant positive threshold offset is included in the comparator to ensure no data output in case of no input signal. This increases the overall system noise immunity. Digital correlators AS3931 uses a 16 bit digital wakeup pattern. The identification of this pattern is performed by digital correlators. They use a sophisticated detection algorithm that provides high immunity against noise injection as a result of stochastic and periodic interferences. An active low WAKE signal is generated after a successful pattern identification. Otherwise WAKE is high. The correlators are reset by setting a register bit via the serial programming interface. In order to save power the correlators are stopped when no data has been received for a specified amount of time. The correlators can be configured regarding their error tolerance by register settings. Crystal oscillator The crystal oscillator generates the clock signal for the digital correlators. It has been optimized for a 32.768 kHz quartz crystal connected to pins XIN and XOUT. The oscillator provides extremely low current consumption, so it can be operated permanently by a battery. Rev. No: 002D5, Dat e: 2002/04/03 Page 4 of 23 Data Sheet AS3931 Regulator A regulator is implemented to provide the amplifiers and digital circuits with a stable and clean supply. Two regulated voltages (2.4 V and 3.0 V) can be selected by register settings. The regulator can be switched off, in this case the external supply voltage is bypassed to the amplifiers and digital circuits. The regulator shall only be switched off for external supply voltages not higher than 3.3V, otherwise the current consumption is significantly increased. The regulated voltage can be seen at the VREG pin, but may not be used to supply any other external circuits. Power On Reset (POR) A power on reset circuit guarantees proper circuit operation after power supply start up. All internal registers are reset to their default states after power on. After power on, the activ low WAKE output is activated and set to low. Pin Description PIN # PIN NAME PIN TYPE SIGNAL DESCRIPTION 1 VCC Supply Input Positive Supply Voltage 2 LF1N Analog Input Channel 1 negative input 3 LF1P Analog Input Channel 1 positive input 4 LF2N Analog Input Channel 2 negative input 5 LF2P Analog Input Channel 2 positive input Preliminary 6 LF3N Analog Input Channel 3 negative input 7 LF3P Analog Input Channel 3 positive input 8 GND Ground Negative Supply Voltage 9 XIN Analog Input Crystal Oscillator Pin 1 10 XOUT Analog Output Crystal Oscillator Pin 2 11 WAKE Open Drain Wake Up Detect output 12 CS Digital Input with Pulldown Chip Select 13 SCL Digital Input with Pulldown Serial Clock 14 SDA Digital Input with Pulldown Serial Data 15 RSSI Analog / Digital Received Signal Strenght Indicator signal / output Digital Testmode signal output Analog Output Regulator Output Voltage 16 VREG Table 2. Pin Description Rev. No: 002D5, Dat e: 2002/04/03 Page 5 of 23 Data Sheet AS3931 Basic Operation LF Transmission Protocol Data Pattern AS3931 basically identifies a 16 bit binary coded data pattern, which is ASK-modulated on a LF carrier. The pattern must contain 8 LOGIC 0 bits and 8 LOGIC 1 bits in order to be DC free. Furthermore, for a proper detector threshold adaptation it has to be ensured that there are no long groups of LOGIC 0 and LOGIC 1 bits. Therefore coding of the 16 bit binary data to 8 Manchester symbols is common. This means that 8 consecutive bit pairs are grouped to Manchester symbols whereas a Manchester symbol 1 is a HIGH to LOW transition and a Manchester symbol 0 is a LOW to HIGH transition. AS3931 supports the Manchester SYMBOL pattern C2 [hex] which in binary code is: 10 10 01 01 01 01 10 01. MSB is transmitted first. The Manchester SYMBOL pattern i.e. the binary DATA pattern can be changed on demand by a metal mask modification. Wake Up Frame The Wake Up Frame of AS3931 consists of a preamble used for detector threshold adaptation followed by the DATA pattern to be identified. We recommend a transmission protocol as shown on Figure 2. The preamble consists of a bit pattern 1010... with a specified number N of bits (N must be an even number in order to get complete 1/0 pairs). N is depending on the application and has influence on the wakeup and overload sensitivity. We recommend a minimum of N = 8 bits. LF Carrier Amplitude High Low Preamble N bits Data 5.86 ms (16 bits) Preliminary WAKE Figure 3. Wake Up Frame of AS3931 Modulation depth As indicated in Figure 3, amplitude modulation is done by switching the carrier amplitude to 100 % ( = High) if a bit is 1 and switching the carrier to m % ( = low) if a bit is 0; the off-percentage m may vary from 0 to 10 % , depending on the application. A larger m increases the noise immunity but decreases the large signal performance. Wake Up Detection A WAKE signal is generated if and only if all 8 LOGIC 1 data bits AND 7 or 8 LOGIC 0 data bits have been identified as correct. The wakeup detection criteria can be changed in two ways: the number of invalid zero bits can be changed from 0 to 3, and the detection of the first one bit can be allowed to be invalid. Both possibilities can be set independently by register settings. A valid Wake Up Frame can be detected at only one of the 3 channels or at more then one channel simultaneously. The single WAKE signals of each channel are ored together to a common WAKE signal ( Figure 3 ). Rev. No: 002D5, Dat e: 2002/04/03 Page 6 of 23 Data Sheet AS3931 WAKE signal clearing After a Wake Up detection, the WAKE output signal must be reset via the Serial Programming Interface. This is done by toggling the bit C5 in the Channel Select register from low to high and vice versa. WAKE signal after POR After a power on reset (POR), the WAKE signal is activated (LOW). Therefore, after startup the WAKE signal must be cleared as if a valid Wake Up would have been detected. RSSI operation The RSSI signal of a selected channel can be measured at the RSSI pin. Each channel can be selected by register settings. To calibrate the RSSI measurement, the LF inputs can be shortcutted with approximately 500 by internal register settings. Doing so, the RSSI voltage offset can be measured. The RSSI - signal is buffered at the RSSI pin. The buffer can be deactivated by register settings, in this case the RSSI pin is tristated (high impedance). However, if the CS signal is not activated, the RSSI pin is tristated. This has to be kept in mind when programming the AS3931 via the Serial Programming Interface (the CS signal is used to latch the serial data into the selected register at the falling edge of CS). Preliminary Rev. No: 002D5, Dat e: 2002/04/03 Page 7 of 23 Data Sheet AS3931 Configuring the AS3931 Serial Programming Interface AS3931 is programmed via an unidirectional three wire Serial Programming Interface.The 3 lines are: CS SCL SDA Chip Select, used for selecting AS3931 and for data latching. Serial Clock. Serial Data. A block of 8 bit data starting with the LSB is sent according to the diagram shown on Figure 4. The received block of 8 bit data is shifted into an 8 bit latch. The two LSB are register address bits and the remaining 6 bits are data bits. The register address bits A1 and A0 are decoded and the 6 data bits are stored into one of three 6 bit registers with the falling edge of CS. CS ADDRESS SDA A0 A1 DATA D0 D1 D2 D3 D4 D5 Preliminary SCL D = P: POWER ON REGISTER D = C: CHANNEL SELECT REGISTER D = T: TESTMODE REGISTER D = M: CORRELATOR MODE REGISTER Figure 4. Protocol of 8 bit data serial transmission Rev. No: 002D5, Dat e: 2002/04/03 Page 8 of 23 Data Sheet AS3931 Power On Register Register Address Bit Value A0 0 A1 0 Register Data Bit POR state Description P0 P1 1 1 Enable Channel 1 Enable Channel 2 P2 P3 P4 1 1 0 Enable Channel 3 Enable Regulator Antenna Rotator Bit 1 P5 0 Antenna Rotator Bit 2 Description P0, P1, P2 Channel enable P0, P1, P2 Mode 0 1 Channel disabled Channel enabled If the bit P0, P1 or P2 is set to 1, the related channel is enabled. That means, the logarithmic envelope amplifier and the correlator are enabled and ready to receive a Wake Up Frame. When disabled, the channel is off, taking no current except for the bias cell ot the amplifier. After a power on, all channels are enabled. Preliminary P3 Regulator enable P3 Mode 0 Regulator disabled 1 Regulator enabled P5, P4 Bit P3 enables the regulator (VREG 2.4 V) or switches off the regulator (VREG = VCC). If the regulator is switched off, then the voltage at Pin VCC is bypassed unregulated to the internal circuits. After a power on, the regulator is on. Antenna Rotator / Input shortcut P5 P4 Mode 0 0 Connection Mode 1 0 1 1 1 0 1 Connection Mode 2 Connection Mode 3 Amplifier Inputs shorted Bits P4 and P5 are used to set the Antenna Connection Mode or to shortcut the differential inputs of each amplifier. See Table 3 for the description of the rotator modes. Connection Mode 1 Connection Mode 2 Connection Mode 3 Antenna 1 Channel 1 Antenna 2 Channel 1 Antenna 3 Channel 1 Antenna 2 Channel 2 Antenna 3 Channel 2 Antenna 1 Channel 2 Antenna 3 Channel 3 Antenna 1 Channel 3 Antenna 2 Channel 3 Rev. No: 002D5, Dat e: 2002/04/03 Table 3. Antenna Rotation Modes Page 9 of 23 Data Sheet AS3931 Channel Select Register Register Address Bit Value A0 A1 1 0 Register Data Bit POR state Description C0 0 RSSI select Bit 1 C1 0 RSSI select Bit 2 C2 C3 0 0 RSSI output mode Bit 1 RSSI output mode Bit 2 C4 C5 0 0 RSSI step WAKE clear Description C0, C1 RSSI Channel Select C0 C1 Mode 0 0 Channel 1 1 0 0 1 Channel 2 Channel 3 1 1 VBG (T0=0), WAKE (T0=1) Bits C0 and C1 are used to select the channel whose RSSI signal is multiplexed to the RSSI pin. In case of both bits C0 and C1 set to 1, a bandgap voltage VBG (1.25 V) appears at the RSSI pin. If additionally the test modes are enabled (Bit T0 of the Test Mode Register set to 1), the WAKE signal (the 3 single WAKE signals of each correlator ored" togehter) is multiplexed to the RSSI pin. After power on, channel 1 is seleceted. . C3, C2 RSSI output mode Preliminary C3 C2 RSSI pin function 1) 0 0 high Z 0 1 1 0 1 1 RSSI signal of selected channel (analog output) WAKE or single WAKE 2) (digital output) not used C4 Bits C12 and C3 define the RSSI pin function. Notes: 1) the RSSI pin function also depends on the signal CS. If CS = 0, the RSSI pin is always in the high impedance state. This is also the case after power on. 2) The WAKE or single WAKE function is selected together with bits T0 - T2 and C0 - C1. See chapter Extended Operation" for a detailled description. Channel sensitivity C4 Mode 0 Input attenuators disabled 1 Input attenuators enabled C5 When bit C4 is set, a resistor (appr. 1.5 k) is connected across the differential inputs of each channel. This resistor reduces the Q-factor of the antenna resonant circuit, therefore the received signal is reduced too. The amount of damping depends on the Q-factor of the antenna circuit. WAKE clear Bit C5 is used to reset the activ low WAKE pin after the pin has been set as a result of receiving a valid code word by one of the 3 channels. Setting Bit C5 to 1, the WAKE pin is reset to high and held in high 0 no effect state, so to enable the channels for the next wake up signal, the bit C5 1 WAKE = H must be toggled to 0 afterwards. Bit C5 is set to 1 during power on, so the bit C5 has to be toggled high and low after a power on too. C5 Mode Rev. No: 002D5, Dat e: 2002/04/03 Page 10 of 23 Data Sheet AS3931 Test Mode Register Register Address Bit Value A0 A1 0 1 Register Data Bit POR state Description T0 0 Test Mode Enable T1 0 Test Mode Select Bit 1 T2 T3 0 --- Test Mode Select Bit 2 not used T4 T5 1 0 RSSI Step Voltage Select Description T0 Test Mode Enable T0 WAKE pin function Bit T0 is used to define the pin function of the WAKE pin When bit T0 is reset to 0, the WAKE pin is used for normal Wake Up detection, which means that the combined WAKE signal ( = the single 0 WAKE WAKE signals of all correlators "ored" together) is connected to the 1 Test Mode signals WAKE pin. The WAKE pin is set if at least one channel detects a valid wake up message. When bit T0 is set to 1, testmode signals are multiplexed to the WAKE pin according to the selected test mode (T1, T2). After power on, the normal wake up detection mode is selected. T2, T1 Test Mode Select Preliminary T2 T1 WAKE pin signal 0 0 DATA of selected channel 0 1 1 1 0 1 WAKE of selected channel not used not used T4 When bit T0 is set to 1, the following signals can be mapped to the WAKE pin (see also Figure 1 for signal description): DATA received bit stream of the selected channel WAKE detected wake up of the selected channel For the DATA and WAKE signal select the desired channel by setting Bits C0 and C1. RSSI step select T4 Mode 0 1 Low RSSI step High RSSI step T5 T4 is used to switch between a high and a low RSSI step. See section Extended Operation" for a detailled description of RSSI steps. Voltage Select T5 Mode 0 1 VREG = 2.4 V VREG = 3.0 V Rev. No: 002D5, Dat e: 2002/04/03 T5 is used to select the internal regulator voltage. Page 11 of 23 Data Sheet AS3931 Correlator Mode Register Register Address Bit Value A0 1 A1 1 Register Data Bit POR state Description M0 M1 0 0 Correlator Off First One-Bit Detection Mode M2 M3 M4 0 1 1 Zero-Bit Detection Mode bit1 Zero-Bit Detection Mode bit2 M5 --- detector treshold select not used Description M0 Correlator Off M0 Mode 0 1 Correlators enabled Correlators off M1 Bit M0 is used to simultanously turn off all 3 correlators. This is done by turning off the correlator clocks. This can be used to reduce power consumption when the Direct Data Mode is used. First One-Bit detection M0 Mode 0 1 first One-Bit must be valid first One-Bit need not to be valid Preliminary M3, M2 Bit M1 selects the detection mode of the first One-Bit in the data pattern. If set to 1, the first One-Bit may be sent, but if it gets lost due to bad transmission, then the correlator does not decide for an error. Note that this setting increases the error tolerance of the correlators, which in turn reduces the immunity against parasitic wakeups (WAKE detection when no data has been sent, due to noise or interferences) Zero-Bit Detection Mode M3 M2 Mode 0 0 1 0 1 0 not used 2 invalid Zero-Bits allowed 1 invalid Zero-Bits allowed 1 1 0 invalid Zero-Bits allowed M4 Bits M2 and M3 select the number of Zero-Bits that are allowed to be invalid. A high level of allowed invalid Zero-Bits increases the error tolerance related to noise or interferences, that means that the propability for the detection of a valid WAKE pattern increases. Note that in turn the immunity against parasitic wakeups (WAKE detection when no data has been sent, due to noise or interferences) is reduced. Detector Time Constant M4 Mode Bit M4 is used to switch between a large and a small of the detector treshold adaption filter. A large is recommendet, because it increases 0 small 1 large the noise margin. A small can be used to improve the wake sensitivity when non-specified wake-patterns are used. Rev. No: 002D5, Dat e: 2002/04/03 Page 12 of 23 Data Sheet AS3931 Extended Operation Power Management Sleep Mode In sleep mode, all channels are switched off, taking no current except for the bias cells of the amplifiers. Sleep mode is entered by register setting, bits P0, P1, P2 set to 0. The remaining elements that take current are the oscillator and the regulator (if used). The Serial Programming Interface remains active also in the sleep mode. Standby Mode In standby mode, selected channels are switched on, ready to receive data. The amplifier of the selected channel is on, whereas the correlator is powered down as long as no input signal is detected at the input. The standby mode is entered by enabling the related channel when setting bits P0, P1 or P3. In the standby mode, the current consumption increases by the amplifier currents compared to the sleep mode. Receive Mode An enabled channel automatically changes from the standby mode to the receive mode as soon as a input signal is detected. The channel stays in receive mode as long as a input signal is detected. In receive mode, the correlator of the channel is active, scanning the input signal wafeform for a valid wake up pattern. The channel goes back to standby mode if no input signal is detected for more then a fixed timeout period. The timeout period is approximately 21 ms. By this operating principle it is guaranteed, that the correlators are only active and taking current as long as it is really necessary. Regulator on / off The regulator can be switched off to reduce the current consumption. When switching off, the supply voltage is bypassed unregulated to the internal circuits, so VREG = VCC. Otherwise, the internal voltage is regulated to 2.4 V. Switching off the regulator saves about 1 A of current. The regulator should only be switched off, when VCC is not higher then 3.3 V, otherwise the current consumption is increased because the internal circuits will then take more current. Preliminary Typical current consumptions in the different modes Table 4 gives an overview of the typical current consumptions in the different modes. All three channels are used in this case. Power consumption of course can be further reduced when not all three channels are enabled. Operating Mode Regulator off, VCC = 2.4 V Regulator on, VREG = 2.4 V Sleep Standby Receive 0.34 A 6.2 A 7.6 A 1.15 A 7.0 A 8.4 A Table 4. Typical current consumptions RSSI step The RSSI step is defined as the change in the RSSI signal voltage if the input amplitude steps from zero to a defined (small) value. For example when changing the input signal amplitude from zero to 1 mVpp, the RSSI signal makes a step of appr. 175 mV if the bit T4 is set to 1 (compare to Figure 6 on page 21). If not needed, this step can be reduced to a lower value (T4 = 0), which decreases the current consumption of each channel by appr. 120 nA. Rev. No: 002D5, Dat e: 2002/04/03 Page 13 of 23 Data Sheet AS3931 Antenna Rotation The 3 possible input signals can be distributed to the 3 channels in 3 different connection modes. Using this feature, the differences between the individual antenna voltages and also the differences of the individual RSSI-voltages of the channels can be handled. For example to eliminate the differences of the RSSI-voltages it is possible to use only one channel and to multiplex it to each antenna. The Antenna Rotation Modes are selected by the Bits P4 and P5. Input Attenuation and Input shortcutting All differential LF-inputs are each shorted by approximately 500 when setting Bits P4 and P5 both to 1. This can be used to measure the RSSI-voltage with no input signal present, therefore the RSSI offset can be calibrated. It should be taken into account that the shortcut resistance can not be made zero due to design restrictions, so the input signal cancellation is not 100 % ( depending on the antenna circuit). Similar to the input shortcutting option, a 1.5 k resistor can be connencted across the differential inputs when setting bit C4 to 1. This input attenuation allows handling of very strong input signals by damping the antenna circuit. The damping depends on the Q-factor of the receiver circuits. WAKE signal at the RSSI pin The WAKE signal, which is normally available at the WAKE pin, can be mapped to the RSSI pin additionally, which then becomes a digital output. To do this, set the following bits: T0 = 1 C0 = 1 and C1 = 1 in the Test Mode Register in the Channel Select Register Note that the RSSI pin is only activ if the CS signal is activ (CS = 0), otherwise RSSI is high Z. Single WAKE operation The single WAKE signals of each channel can be mapped to the WAKE pin. Normally, the 3 WAKE signals are ored" togehter and mapped to the WAKE pin, so the channel with the strongest input signal will generate a WAKE signal. To map a single WAKE signal to the WAKE pin, make the following steps: Preliminary 1 2 3 Enable Test Mode: Select Test Mode: Select Channel: set T0 = 1 in Test Mode Register set T1 = 1 and T2 = 0 in Test Mode Register set C0 and C1 in the Channel Select Register Additionally the single WAKE signals can also be mapped to the RSSI pin, which then becomes a digital output pin. To do this, make this additional step: 4 Select RSSI output mode set C2 = 0 and C3 = 1 in the Channel Select Register The RSSI pin is only activ if the CS signal is activ (CS = 0), otherwise RSSI is high Z. Note that it is possible to operate the WAKE pin in the normal mode first (that is all three single WAKE signals ored together) and after a wake up detection, to use the Single WAKE mode to check which channel received the wake pattern. This must be done before clearing the WAKE pin. Direct DATA Mode In Direct Data Mode, the received DATA of a selected channel can be mapped to the WAKE pin. The DATA signal is the digital output of the detector and is normally fed to the correlator, where it is scanned for the WAKE pattern (see also Figure 1). To get the DATA signal at the WAKE pin, make the following steps: 1 2 3 Enable Test Mode: Select Test Mode: Select Channel: Rev. No: 002D5, Dat e: 2002/04/03 set T0 = 1 in Test Mode Register set T1 = 0 and T2 = 0 in Test Mode Register set C0 and C1 in the Channel Select Register Page 14 of 23 Data Sheet AS3931 Additionally the Direct DATA signals can also be mapped to the RSSI pin, which then becomes a digital output pin. To do this, make this additional step: 4 Select RSSI output mode set C2 = 0 and C3 = 1 in the Channel Select Register Note that the RSSI pin is only activ if the CS signal is activ (CS = 0), otherwise RSSI is high Z. Correlator Modes Operation of the correlators can be modified regarding the error tolerances for the One-Bits and the Zero-Bits. In case of the One-Bits, only the first One-Bit can be allowed to be invalid. In case of the Zero-Bits, the number of Zero-Bits which are allowed to be invalid can be set from 0 to 2. Please take into account that an increased error tolerance also reduces the immunity against parasitic wakeups (WAKE detection when no data has been sent, due to noise or interferences). Treshold Adaption Filter Time Constant Bit M4 is used to switch between a large and a small of the detector treshold adaption filter. A large is recommendet, because it increases the noise margin. A small can be used to improve the wake sensitivity when non-specified wakepatterns are used. Preliminary Rev. No: 002D5, Dat e: 2002/04/03 Page 15 of 23 Data Sheet AS3931 Electrical Specification Absolute Maximum Ratings Symbol Parameter Min Max V CC Positive supply voltage -0.5 GND Analog ground Voltage at every input pin 0 GND-0.5 V CC +0.5 V -100 100 mA 800 V -55 125 C 260 C V in I in Input current into any pin except supply VESD Electrostatic discharge T s tg Storage temperature T le a d Lead temperature Units Note 5.5 V 1) 0 V 2) 3) Notes: 1) max. Vcc can be increased up to 6.6 V via metal change on request 2) 3) HBM: R=1.5 k, C=100 pF 260 deg C for 10 sec (Reflow and Wave Soldering), 360 deg C for 3 sec (Manual soldering). Preliminary Recommended Operating Conditions Symbol Parameter Min Typ Max Unit Note V CC positive supply voltage 2.4 3.0 3.3 V 1) GND TA Analog Ground Operating Ambient Temperature Range 0 -20 0 0 65 V C Notes: 1) In case that the internal regulator is used and the supply voltage is only slightly above 2.4 V, the regulator will feed trough the supply voltage to the regulator output with a negligible voltage drop. Rev. No: 002D5, Dat e: 2002/04/03 Page 16 of 23 Data Sheet AS3931 Electrical Characteristics Note: all parameters refer to T a m b = 25 C, V c c = 5.5 V, f IN = 20 kHz, register settings as after POR except T4=0 (RSSI step = low), transmission protocoll according to Figure 3 (page 6) and application circuit according to Figure 2 and Table 1 (page 3) and input signal wafeform definitions according to Figure 5 (page 19) unless otherwise specified Symbol Parameter Conditions Min f IN LF input carrier frequency range 19 BR bit rate 1) 2.704 BM Manchester Symbol 2) Rate Manchester Code 3) Word number of preamble bits 1.352 Typ Max Units 150 kHz 2.731 2.758 kB/s 1.365 1.379 kS/s GENERAL W N p re m off-percentage Regulator Voltage T POR Power On Reset 7) time operating current --- 0 6) hex 8 10) V REG I CC C2 T5 = 1 T5 = 0 CS = low; all channels on; VCC = 2.4V; regulator off; 2.30 2.85 5 2.4 3.0 10 % 2.55 3.15 V V ms sleep mode 0.34 A standby mode receiving mode 6.2 7.6 A A Preliminary receiving mode with regulator on (VREG=2.4V) Z IN differential small sig. input impedance 8.4 A 2 M input attenuator active 1.5 k input shortcutting active 0.5 k kHz normal operation f XT AL crystal oscillator frequency Crystal type: CC4 from MicroCrystal V in ,m in minimum differential input voltage for wake up detection 8 ) V in ,m a x maximum differential input voltage for wake up detection 8 ) RSSI step = high; VREG = 2.4 V; 20 kHz < f IN < 50 kHz; t ris e < 70 s and t fa ll < 10) 70 s 32.768 WAKEUP I W AKE WAKE pin current Rev. No: 002D5, Dat e: 2002/04/03 N p re = 8; 0 < m < 10 % ; 300 N p re = 8, m = 0 % 0.7 350 Vpp Vpp N p re = 16, m = 10 % Voltage at WAKE pin V OL < 0.4 V 1 mA Page 17 of 23 Data Sheet AS3931 Electrical Characteristics (continued) Symbol Parameter Conditions Min Typ Max Units 1.7 V RSSI V RSSI RSSI output voltage range V RSSI0 RSSI output voltage (RSSI offset) RSSI output voltage 4) step RSSI output voltage step 4) logarithmic input voltage range V ST EP V ST EP V L OG S RSSI C RSSI I RSSI T s te p RSSI slope in log. range cap. loading of RSSI pin RSSI buffer current RSSI voltage step 5) time 0.95 V IN = 0 0.95 V V IN = 1 mV p p , RSSI step = high 175 mV V IN = 1 mV p p , RSSI step = low 100 mV V IN = 1 mV p p , RSSI step = high 0.3 RSSI step = high 300 11.5 RSSI buffer activ C L = 10 pF, R L = 1 M; mV Input signal amplitude 63.2mVpp; CS from low to high (Buffer activation in presence of a strong input signal); channel switching from ChA (63.2 mVpp) to ChB (0 mVpp) 9 ) , with CS deactivation of 10 s mV/dB 10 pF 5 A 280 420 s 300 440 s Preliminary V RIP RSSI Ripple Voltage RSSI buffer activ, C L = 10 pF, R L = 1 M; V I N = 1 mV pp ; I IH Digital Input current Pins SCL, SDA, CS V IH = 2.4 V 20 mV Serial Programming Interface 30 60 100 A Notes: 1) 2) 3) 4) 5) 6) The bit rate correlates with the crystal oscillator clock frequency f c l k as follows: B R = f C L K /12 The Manchester symbol rate correlates with the Bit Rate as follows: B M = B R /2 Codeword can be changed by metal option The RSSI step is the change of the RSSI output voltage when the input signal amplitude changes from 0 to specified value Time to step from initial RSSI value to 95% of the final value VREG output may not be used as a supply for other circuits 7) 8) 9) 10) To ensure proper startup conditions, the supply voltage VCC must be ramped up to its final value during T P O R Values refer to production test ChA may be any channel 1 - 3, whereas ChB may be any other remaining channel. For the definitions of m, t ris e and t fa ll see Figure 5, page 19 Rev. No: 002D5, Dat e: 2002/04/03 Page 18 of 23 Data Sheet AS3931 Input signal wafeform definition trise tfall Ve Vin Ve Vinlow Figure 5 Input signal wafeform Preliminary Definitions: Vin Vinlow Ve m t ris e t fa ll LF input signal amplitude if a 1" is transmitted [mVpp] LF input signal amplitude if a 0" is transmitted [mVpp] voltage error for t ris e / t fa ll definitions [mV] off-percentage [% ] time for the signal amplitude to change from Vinlow to Vin, with 10% error time for the signal amplitude to change from Vin to Vinlow, with 10% error The following relations apply: Vinlow = m * Vin 100 Ve = 0.05 * Vin Rev. No: 002D5, Dat e: 2002/04/03 ( m < 10% ) Page 19 of 23 Data Sheet AS3931 Typical characteristics Note: all graphs refer to T amb = 27 C and V REG = 2.4 V RSSI-characteristic (typical) RSSI-step low RSSI-step high Figure 6. RSSI-characteristic Preliminary Rev. No: 002D5, Dat e: 2002/04/03 Page 20 of 23 Data Sheet AS3931 RSSI-Offset vs. V REG (V) RSSI-Offset vs. Temp. VREG temp ( C) RSSI-step @ 1mV pp vs. Temp. RSSI-step @ 1mVpp vs. V REG (V) Preliminary ( C ) RSSI-step @ 300 V pp vs. frequency Rev. No: 002D5, Dat e: 2002/04/03 VREG ( V ) RSSI-step @ 1mVpp vs. frequency Page 21 of 23 Data Sheet AS3931 Package information Physical dimensions of 16 pin TSSOP package. Preliminary Common Dimensions Symbol Minimal (mm) Nominal (mm) Maximal (mm) A - - 1.20 A1 0.05 - 0.15 b 0.19 - 0.30 D 4.90 - 5.10 e 0.65 BSC E - 6.40 - E1 4.30 - 4.50 L 0.45 - 0.75 0 - 8 Rev. No: 002D5, Dat e: 2002/04/03 Page 22 of 23 Data Sheet AS3931 Contact austriamicrosystems AG A 8141 Schloss Premstatten, Austria T. +43 (0) 3136 500 0 F. +43 (0) 3136 525 01 info@austriamicrosystems.com Copyright Copyright (c) 2001 austriamicrosystems. Trademarks registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. Authors Notice: Start Document is AS3931_001D4.doc; red: changes for D5 release pink: changes for 002 edition colors will be changed to black in the official doc. Preliminary Rev. No: 002D5, Dat e: 2002/04/03 Page 23 of 23