CY2XL11
100 MHz LVDS Clock Generator
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-42886 Rev. *F Revised March 18, 2011
Features
■One low-voltage differential signaling (LVDS) output pair
■Output frequency: 100 MHz
■External crystal frequency: 25 MHz
■Low RMS phase jitter at 100 MHz, using 25 MHz crystal
(637 kHz to 10 MHz): 0.53 ps (typical)
■Pb-free 8-Pin TSSOP package
■Supply voltage: 3.3 V or 2.5 V
■Commercial temperature range
Functional Description
The CY2XL1 1 is a PLL based high performance clock generator
with a crystal oscillator interface and one LVDS output pair. It is
optimized to generate PCI Express, FC, and other high-
performance clock frequencies. It also produces an output
frequency that is four times the crystal frequency. It uses
Cypress’s low-noise VCO technology to achieve less than 1 ps
typical RMS phase jitter , that meets high-performance systems’
jitter requirements.
Output
Divider
OE
Crystal
Oscillator CLK#
Low-Noise PLL CLK
XOUT
XIN
External
Crystal
Logic Block Diagram
Pinouts
Figure 1. Pin Diagram - 8-Pin TSSOP
1
2
36
7
8
XOUT
XIN OE
VSS
VDD
CLK#
45
VDD
CLK
Tabl e 1. Pin Definition – 8-Pin TS SOP
Pin Number Pin Name I/O Type Description
1, 8 VDD Power 3.3 V or 2.5 V power supply. All supply current flows through pin 1
2 VSS Power Ground
3, 4 XOUT, XIN XTAL output and input Parallel resonant crystal interface
5 OE CMOS input Output enable. When HIGH, the output is enabled. When LOW, the
output is high-impedance
6,7 CLK#, CLK LVDS output Differential clock output
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CY2XL11
Document Number: 001-42886 Rev. *F Page 2 of 9
Frequency Table
Input Crystal Frequency (MHz) PLL Multiplier Value Output Frequency (MHz)
25 4 100
Absolute Maximum Conditions
Parameter Description Condition Min Max Unit
VDD Supply voltage – –0.5 4.4 V
VIN[1] Input voltage, DC Relative to VSS –0.5 VDD + 0.5 V
TSTemperature, storage Non operating –65 150 °C
TJTemperature, junction – – 135 °C
ESDHBM ESD protection (human body model) JEDEC STD 22-A114-B 2000 – V
UL–94 Flammability rating At 1/8 inch V–0
ΘJA[2] Thermal resistance, junction to ambient 0 m/s airflow 100 °C/W
1 m/s airflow 91
2.5 m/s airflow 87
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated using Apache Sentinel TI software. The board is derived fr om the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. Outputs are terminated with 100Ω between CLK and CLK#. Refer to Figure 8 on page 5.
4. IDD includes ~4 mA of current that is dissip ated externally in the output termination resistor.
5. Not 100% tested, guaranteed by design and characterization.
6. Refer to Figure 2 on page 4.
7. Refer to Figure 3 on page 4.
Operating Conditions
Parameter Description Min Max Unit
VDD 3.3 V supply voltage 3.135 3.465 V
2.5 V supply voltage 2.375 2.625 V
TAAmbient temp erature –5 70 °C
TPU Power up time for all VDD to reach minimum specified voltage (ensure power
ramps is monotonic) 0.05 500 ms
DC Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit
IDD[4] Power supply current with output
terminated VDD = 3.465 V, OE = VDD, output terminated – – 120 mA
VDD = 2.625 V, OE = VDD, output terminated – – 115 mA
VOD[6] LVDS differential output voltage VDD = 3.3 V or 2.5 V , RTERM = 100 Ω between
CLK and CLK# 247 – 454 mV
ΔVOD[6] Change in VOD between comple-
mentary output states VDD = 3.3 V or 2.5 V , RTERM = 100 Ω between
CLK and CLK# ––50mV
VOS[7] LVDS offset output voltage VDD = 3.3 V or 2.5 V , RTERM = 100 Ω between
CLK and CLK# 1.125 – 1.375 V
ΔVOS Change in VOS between comple-
mentary output states VDD = 3.3 V or 2.5 V , RTERM = 100 Ω between
CLK and CLK# ––50mV
IOZ Output leakage current Three-state output, unterminated, measured
on one pin while floating the other pin,
OE = VSS
–35 – 35 μA
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Document Number: 001-42886 Rev. *F Page 3 of 9
VIH Input high voltage, OE pin – 0.7 ×
VDD ––V
VIL Input low voltage, OE pin – – – 0.3 ×
VDD V
IIH Input high current, OE pin OE = VDD ––115µA
IIL Input low current, OE pin OE = VSS –50 – – µA
CIN Input capacitance, OE pin – – 15 – pF
CINX Pin capacitance, XIN & XOUT – – 4.5 – pF
DC Electrical Characteristics (continued)
Parameter Description Test Conditions Min Typ Max Unit
AC Electrical Characteristics[3]
Parameter Description Min Typ Max Unit
FOUT Output frequency – – 100 – MHz
TR, TF[8] Output rise or fall time 20% to 80% of full output swing – 0.5 1.0 ns
TJitter(φ)[11] RMS phase jitter (random) FOUT =100 MHz, (637 kHz–10 MHz) – 0.53 – ps
TDC[9] Duty cycle Measured at zero crossing point 45 – 55 %
TOHZ[10] Output disable time Time from fa lling edge on OE to
stopped outputs (Asynchronous) ––100ns
TOE[10] Output enable time Time from rising edge on OE to
outputs at a valid frequency
(Asynchronous)
––120ns
TLOCK Startup time Time for CLK to reach valid
frequency measured from the time
VDD = VDD(min.)
––5ms
Crystal Characteristics
Parameter Description Min Max Unit
Mode of oscillation Fundamental –
F Frequency 25 25 MHz
ESR Equivalent series resistance – 50 Ω
CSShunt capacitan c e –7pF
Notes
8. Refer to Figure 4 on page 4.
9. Refer to Figure 5 on page 4.
10.Refer to Figure 6 on page 4.
11. Refer to Figure 7 on page 5.
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Document Number: 001-42886 Rev. *F Page 4 of 9
Switching Waveforms
Figure 2. Output Voltage Swing
Figure 3. Output Offset Voltage
Figure 4. Ou tput Rise or Fall Time
Figure 5. Duty Cycle Timing
Figure 6. Output Enabl e and Dis ab le Timin g
CLK
CLK#
VOD2
VOD1
ΔVOD = VOD1 - VOD2
CLK
50Ω
CLK#
50ΩVOS
20%
80%
TR
CLK 20%
80%
CLK#
TF
CLK
TPW
TPERIOD
TDC = TPW
TPERIOD
CLK#
OE
CLK High Impedance
TOHZ TOE
VIL
VIH
CLK#
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CY2XL11
Document Number: 001-42886 Rev. *F Page 6 of 9
Package Drawing and Dimensions
Figure 9. 8-Pin Thin Sh runk Small Outline Package (4.40 MM Body) Z 8
Ordering Information
Part Number Package Description Product F low
CY2XL11ZXC 8-pin TSSOP Commercial, –5°C to 70°C
CY2XL11ZXCT 8-pin TSSOP - Tape and Reel Commercial, –5°C to 70°C
CY2XL11ZXI 8-pin TSSOP Industrial
CY2XL11ZXI(T) 8-pin TSSOP - Tape and Reel Industrial
Ordering Code Definitions
T = Tape and Reel
Temp erature Range: C = Commercial
Pb-free
Package Type
Part Identifier
Family
Company ID: CY = Cypress
xxCY xxx
Z X T
C
51-85093-*C
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Document Number: 001-42886 Rev. *F Page 7 of 9
Acronyms Document Conventions
Units of Measures
Acronym Description
CLKOUT Clock output
CMOS Complementary metal oxide semiconductor
DPM Die pick map
EPROM Erasabl e programmable read only memory
LVDS Low-voltage differential signaling
NTSC National television system committee
OE Output enable
PAL Phase alternate line
PD Power down
PLL Phase locked loop
PPM Parts per million
TTL Transistor transistor logic
Symbol Unit of Measure
°C degrees Celsius
kHz kilohertz
kΩkilohms
MHz megahertz
MΩmegaohms
µA microamperes
µs microseconds
µV microvolts
µVrms microvolts root-mean-square
mA milliamperes
mm millimeters
ms milliseconds
mV millivolts
nA nanoamperes
ns nanoseconds
nV nanovolts
Ωohms
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Document Number: 001-42886 Rev. *F Page 8 of 9
Document History Page
Document Title: CY2XL11 100 MHz LVDS Cloc k Genera tor
Document Number: 001 - 42886
REV. ECN NO. Submission
Date Orig. of
Change Description of Change
** 2117527 See ECN WWZ/KVM
/AESA New data sheet
*A 2669117 03/05/2009 KVM/
AESA Changed crystal and output frequency
Removed MSL spec
Changed IIL value from -20 uA to -50 uA
Changed IIH value from 20 uA to 115 uA
Changed phase jitter value from 1 to 0.53 ps
Changed junction temp from 125°C to 135°C
Changed IDD from 150 mA to 120 mA
Rise / fall time changed to 350 ps to 500ps
Changed Data Sheet Status to Final
*B 2700242 04/30/2009 KVM/
PYRS Typo correction
Reformatted AC and DC tables
Added IDD spec for 2.5V
Added CINX and TLOCK specs
Changed CIN from 7pF to 15pF
*C 2718433 06/12/2009 WWZ/HMT No change. Submit to ECN for product launch.
*D 2764787 09/18/2009 KVM Add clause to IOZ Test Conditions
Change VOD limits from 250/450 mV to 247/454 mV
Add max limit for TR, TF: 1.0 ns
Change TOE max from 100 ns to 120 ns
Change TLOCK max from 10 ms to 5 ms
*E 3067416 10/20/20 BASH Added the industrial part in Ordering Information table.
Updated the package diagram.
Added Ordering Code Definition, Acronyms, and Document Con v entions.
*F 3199831 03/18/11 CXQ No change. Sunset review spec.
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Document Number: 001-42886 Rev. *F Revised March 18, 2011 Page 9 of 9
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY2XL11
© Cypress Semico nducto r Co rpor ation , 20 07-2 011. The information cont ai ned he rein is subj ect to chang e with out no tice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypre ss prod uc ts are n ot war r ant ed no r inte nd ed to be us ed fo r
medical, life supp or t, l if e savin g, cr it ical control or safety applications, unless pursuant to a n express written agre em en t w it h C ypr ess. Fu rth erm ore, Cyp ress doe s not auth ori ze i t s products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protec tion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunctio n with a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. C ypress reserves the right to make changes without further notice to th e materials de scribed herei n. Cypress d oes not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreemen t.
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