LTC4352IMS#TRPBF - Linear Technology Corporation

LTC4352

4352fa

Typical applicaTion

DescripTion

Low Voltage Ideal Diode

Controller with Monitoring

The LTC

4352 creates a near-ideal diode using an external

N-channel MOSFET. It replaces a high power Schottky diode

and the associated heat sink, saving power and board area.

The ideal diode function permits low loss power ORing

and supply holdup applications.

The LTC4352 regulates the forward voltage drop across

the MOSFET to ensure smooth current transfer in diode-

OR applications. A fast turn-on reduces the load voltage

droop during supply switch-over. If the input supply fails

or is shorted, a fast turn-off minimizes reverse currents.

The controller operates with supplies from 2.9V to 18V.

For lower voltages, an external supply is needed at the

VCC pin. Power passage is disabled during undervoltage

or overvoltage conditions. The controller also features an

open MOSFET detect circuit that flags excessive voltage

drop across the pass transistor in the on state. A REV pin

enables reverse current, overriding the diode behavior

when desired.

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

ThinSOT and PowerPath are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners.

2.9V to 18V Ideal Diode

FeaTures

applicaTions

n Low Loss Replacement for Power Diode

n Controls N-Channel MOSFET

n 0V to 18V Supply ORing or Holdup

n 0.5μs Turn-On and Turn-Off Time

n Undervoltage and Overvoltage Protection

n Open MOSFET Detect

n Status and Fault Outputs

n Hot Swappable

n Reverse Current Enable Input

n 12-Pin MSOP and DFN (3mm × 3mm) Packages

n Redundant Power Supplies

n Supply Holdup

n Telecom Infrastructure

n Computer Systems and Servers

VCC

REV

LTC4352

STATUS

FAULT

MOSFET ON

STATUS

0.1µF*

TO LOAD

2.9V TO 18V

Si7336ADP

*OPTIONAL

FAULT

0.1µF

4352 TA01

CPO VIN

SOURCE GATE

GND

OUT

Power Dissipation vs Load Current

LOAD CURRENT (A)

POWER DISSIPATION (W)

2.5

2.0

1.5

1.0

0.5

4.0

3.0

3.5

24 6 8

4352 TA01b

DIODE (SBG1025L)

MOSFET (Si7336ADP)

POWER

SAVED

LTC4352

4352fa

absoluTe MaxiMuM raTings

VIN, SOURCE Voltages ...................................–2V to 24V

VCC Voltage .................................................. –0.3V to 7V

OUT Voltage ...................................................–2V to 24V

CPO, GATE Voltages (Note 3) ..................... –0.3V to 30V

CPO D.C. Current ...................................................10mA

UV, OV, REV Voltages ................................ –0.3V to 24V

FA U LT, STATUS Voltages ............................ –0.3V to 24V

(Notes 1, 2)

orDer inForMaTion

FA U LT, STATUS Currents ..........................................5mA

Operating Ambient Temperature Range

LTC4352C ................................................ 0°C to 70°C

LTC4352I .............................................–40°C to 85°C

LTC4352H .......................................... –40°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec)

MS Package ...................................................... 300°C

pin conFiguraTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4352CDD#PBF LTC4352CDD#TRPBF LDPJ 12-Pin (3mm × 3mm) Plastic DFN 0°C to 70°C

LTC4352IDD#PBF LTC4352IDD#TRPBF LDPJ 12-Pin (3mm × 3mm) Plastic DFN –40°C to 85°C

LTC4352HDD#PBF LTC4352HDD#TRPBF LDPJ 12-Pin (3mm × 3mm) Plastic DFN –40°C to 150°C

LTC4352CMS#PBF LTC4352CMS#TRPBF 4352 12-Lead Plastic MSOP 0°C to 70°C

LTC4352IMS#PBF LTC4352IMS#TRPBF 4352 12-Lead Plastic MSOP –40°C to 85°C

LTC4352HMS#PBF LTC4352HMS#TRPBF 4352 12-Lead Plastic MSOP –40°C to 150°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

TOP VIEW

DD PACKAGE

12-PIN (3mm × 3mm) PLASTIC DFN

1SOURCE

GATE

CPO

GND

OUT

REV

VIN

VCC

STATUS

FAULT 67

VIN

VCC

STATUS

FAULT

SOURCE

GATE

CPO

GND

OUT

REV

TOP VIEW

MS PACKAGE

12-LEAD PLASTIC MSOP

TJMAX = 150°C, θJA = 43°C/W

EXPOSED PAD (PIN 13) PCB GND CONNECTION OPTIONAL

TJMAX = 150°C, θJA = 164°C/W

LTC4352

4352fa

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VSOURCE = VIN, VOUT = VIN, VCC Open, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Supplies

VIN Input Operating Range

With External 2.9V to 4.7V VCC Supply

With External 4.7V to 6V VCC Supply

2.9

VCC

VCC(EXT) VCC External Supply Range l2.9 6 V

VCC(INT) VCC Internal Regulator Voltage l3.5 4.1 4.7 V

IIN VIN Supply Current

VIN = 0V, VCC = 5V, VOUT = 18V

VIN = 0V, VCC = 5V, VOUT = 18V (LTC4352H)

1.4

–10

–13

–25

µA

ICC External VCC Supply Current VCC = 5V, VIN = 0V l1.25 2.5 mA

VCC(UVLO) VCC Undervoltage Lockout Threshold VCC Rising l2.45 2.57 2.7 V

ΔVCC(HYST) VCC Undervoltage Lockout Hysteresis l50 70 90 mV

Ideal Diode Control

VFWD(REG) Forward Regulation Voltage (VIN − VOUT)l10 25 40 mV

ΔVGATE MOSFET Gate Drive (VGATE – VSOURCE) VFWD = 0.1V, I = 0 and –1μA l5 6.1 7.5 V

tON(GATE) GATE Turn-On Delay CGATE = 10nF, VFWD = 0.2V l0.25 0.5 µs

tOFF(GATE) GATE Turn-Off Delay CGATE = 10nF, VFWD = −0.2V l0.2 0.5 µs

Input/Output Pins

VUV,OV(TH) UV, OV Threshold Voltage VUV Falling, VOV Rising l490 500 510 mV

ΔVUV,OV(HYST) UV, OV Threshold Hysteresis l2.5 5 8.5 mV

VREV(TH) REV Threshold Voltage

(LTC4352H)

0.8

1.0

1.2

1.25

IUV,OV UV, OV Current V = 0.5V l0 ±1 µA

IREV REV Current VREV = 1V l7 10 13 µA

IOUT OUT Current VOUT = 0V, 12V l–13 200 µA

ISOURCE SOURCE Current VSOURCE = 0V l–85 –130 µA

ICPO(UP) CPO Pull-Up Current VCPO = VIN = 2.9V

VCPO = VIN = 18V

–60

–50

–90

–75

–115

–100

µA

IGATE GATE Fast Pull-Up Current

GATE Fast Pull-Down Current

GATE Off Pull-Down Current

VFWD = 0.2V, ΔVGATE = 0V, VCPO = 17V

VFWD = –0.2V, ΔVGATE = 5V

VUV = 0V, ΔVGATE = 2.5V

–1.5

1.5

100

145

µA

IFLT,STAT(IN) STATUS, FAULT Leakage Current V = 18V l0 ±1 µA

IFLT,STAT(UP) STATUS, FAULT Pull-Up Current V = 0V l–8 –10 –12 µA

VOL STATUS, FAULT Output Low Voltage I = 1.25mA l0.2 0.4 V

VOH STATUS, FAULT Output High Voltage I = –1μA lVCC – 1 VCC – 0.5 V

ΔVGATE(ST) MOSFET On Detect Threshold STATUS Pulls Low, VFWD = 50mV

STATUS Pulls Low, VFWD = 50mV (LTC4352H)

0.3

0.28

0.7

1.1

VFWD(FLT) Open MOSFET Threshold (VIN – VOUT) FAULT Pulls Low l200 250 300 mV

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating for extended periods may affect device reliability and

lifetime.

Note 2: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to GND unless otherwise

specified.

Note 3: Internal clamps limit the GATE and CPO pins to a minimum of 5V

above, and a diode below SOURCE. Driving these pins to voltages beyond

the clamp may damage the device.

LTC4352

4352fa

Typical perForMance characTerisTics

OUT Current vs Voltage CPO Voltage vs Current GATE Voltage vs Current

STATUS, FAULT Output Low

Voltage vs Current

STATUS, FAULT Output High

Voltage vs Current

VIN Current vs Voltage

VIN Current vs Voltage with

External VCC VCC Current vs Voltage

TA = 25°C, VIN = 12V, VSOURCE = VIN, VOUT = VIN,

VCC Open, unless otherwise noted.

VIN (V)

IIN (mA)

0.4

0.8

1.6

36 9 12

4352 G01

15 18

1.2

VIN (V)

–50

IIN (µA)

100

150

300

12 3 4

4352 G02

250

200

VCC = 5V

VCC (V)

ICC (mA)

0.50

0.25

0.75

1.00

1.50

12 3 4

4352 G03

1.25

VIN = 0V

VOUT (V)

–50

IOUT (µA)

100

150

200

300

36 9 12

4352 G04

1815

250

ICPO (µA)

–1

VCPO –VSOURCE (V)

–20 –40 –60 –80

4352 G05

–120–100

VIN = 2.9V

VIN = 18V

IGATE (µA)

–1

VGATE –VSOURCE (V)

–20 –40 –60 –80

4352 G06

–120–100

VIN = 2.9V

VIN = 18V

VOUT = VIN – 0.1V

CURRENT (mA)

VOL (V)

0.6

0.4

0.2

0.8

12 3 4

4352 G07

CURRENT (µA)

VOH (V)

2.5

2.0

1.5

1.0

0.5

4.0

3.0

3.5

–2 –4 –6 –8

4352 G08

–10 –12

LTC4352

4352fa

pin FuncTions

VIN (Pin 1): Voltage Sense and Supply Input. Connect this

pin to the power input side of the MOSFET. The low voltage

supply VCC is generated from VIN. The voltage sensed at

this pin is used to control the MOSFET gate.

VCC (Pin 2): Low Voltage Supply. Connect a 0.1μF capacitor

from this pin to ground. When VIN ≥ 2.9V, this pin provides

decoupling for an internal regulator that generates a 4.1V

supply. For applications where VIN < 2.9V, connect an

external supply voltage in the range 2.9V to 6V to this pin.

UV (Pin 3): Undervoltage Comparator Input. Connect this

pin to an external resistive divider from VIN. If the volt-

age at this pin falls below 0.5V, an undervoltage fault is

detected and the MOSFET is turned off. The comparator

has a built-in hysteresis of 5mV. Tie to VCC if unused.

OV (Pin 4): Overvoltage Comparator Input. Connect this

pin to an external resistive divider from VIN. If the volt-

age at this pin rises above 0.5V, an overvoltage fault is

detected and the MOSFET is turned off. The comparator

has a built-in hysteresis of 5mV. Tie to GND if unused.

STATUS (Pin 5): MOSFET Status Output. This pin is pulled

low by an open-drain output when the external MOSFET

is on. An internal 10µA current source pulls this pin up

to a diode below VCC. It may be pulled above VCC using

an external pull-up. Tie to GND or leave open if unused.

FAULT (Pin 6): Fault Output. This pin is pulled low by an

open-drain output when a fault occurs. This fault could

either be an undervoltage fault, an overvoltage fault, or

an open MOSFET fault. The external MOSFET is turned off

for undervoltage and overvoltage faults, while it is left on

for open MOSFET fault. An internal 10µA current source

pulls this pin up to a diode below VCC. It may be pulled

above VCC using an external pull-up. Tie to GND or leave

open if unused.

REV (Pin 7): Reverse Current Enable Input. Connect this

pin to GND for normal diode operation that blocks reverse

current. Driving this pin above 1V fully turns on the MOSFET

gate to allow reverse current. An internal 10µA current

source pulls this pin to GND.

OUT (Pin 8): Output Voltage Sense Input. Connect this

pin to the output side of the MOSFET. The voltage sensed

at this pin is used to control the MOSFET gate.

GND (Pin 9): Device Ground.

CPO (Pin 10): Charge Pump Output. Connect a capacitor

from this pin to the SOURCE pin. The value of this capaci-

tor is approximately 10x the gate capacitance (CISS) of the

MOSFET switch. The charge stored on this capacitor is

used to pull-up the gate during a fast turn-on. Leave this

pin open if fast turn-on is not needed.

GATE (Pin 11): MOSFET Gate Drive Output. Connect this

pin to the gate of the external N-channel MOSFET switch.

An internal clamp limits the gate voltage to 6.1V above,

and a diode below SOURCE. During fast turn-on a 1.5A

pull-up charges GATE to CPO. During fast turn-off a 1.5A

pull-down discharges GATE to SOURCE.

SOURCE (Pin 12): MOSFET Gate Drive Return. Connect

this pin to the source of the external N-channel MOSFET

switch.

EXPOSED PAD (Pin 13, DD Package Only): Exposed pad

may be left open or connected to device ground.

LTC4352

4352fa

–

CP4 DISABLE

LDO

VIN

0.5V

CP2

CP1

CP3

OV FAULT

*DD PACKAGE ONLY GND

10µA

VCC

EXPOSED PAD*

FAULT

STATUS

REV

OUT

SOURCE

GATE

CPO

100µA

UV FAULT

VCC LOW

2.57V

–

OPEN

MOSFET

DETECT

10µA

VCC

CP6

CP5

ENABLE

REVERSE

CURRENT

0.7V

SOURCE

GATE

GATE OFF

–

CHARGE

PUMP

f = 3MHz

VCC

25mV

AMP

LDO

4352 FD

10µA

12 10

139

4.1V

FuncTional DiagraM

LTC4352

4352fa

operaTion

The LTC4352 controls either single or back-to-back

N-channel MOSFETs in order to emulate an ideal diode.

Dual MOSFETs eliminate current flow from the input to the

output in an input undervoltage or overvoltage condition.

When enabled, an amplifier (AMP) monitors the voltage

between the VIN and OUT pins, and drives the GATE pin.

The amplifier controls the gate of the external MOSFET

to servo its forward voltage drop (VIN – OUT) to 25mV.

The gate voltage rises to enhance the MOSFET if the load

current causes more than 25mV of drop. For large output

currents the MOSFET gate is driven fully on and the voltage

drop is equal to ILOAD • RDS(ON).

In the case of an input supply short-circuit, when the

MOSFET is conducting, a large reverse current starts

flowing from the load towards the input. The AMP detects

this failure condition as soon as it appears, and turns off

the MOSFET by pulling down the GATE pin. The REV pin

can be used to allow reverse current, overriding the diode

behavior.

The AMP quickly pulls-up the GATE pin whenever it senses

a large forward voltage drop. An external capacitor between

the CPO and SOURCE pins is needed for fast gate pull-up.

This capacitor is charged up, at device power-up, by the

internal charge-pump. This stored charge is used for the

fast gate pull-up.

The GATE pin sources current from the CPO pin, and sinks

current to the SOURCE and GND pins. Internal clamps

limit the GATE to SOURCE voltage to 6.1V, and the CPO to

SOURCE voltage to 6.7V.

The same clamps also limit the CPO

and GATE pins to a diode voltage below the SOURCE pin.

OV, UV, and VCC comparators, CP1 to CP3, control power

passage. The MOSFET is held off whenever the OV pin

is above 0.5V, the UV pin is below 0.5V, or the VCC pin is

below 2.57V. There is a 40µs delay from all three condi-

tions becoming good to GATE being allowed to turn on.

Overvoltage causes a fast turn-off, while undervoltage

activates a 100μA pull-down on GATE after a 7μs delay.

Open-drain pull-down, M1, pulls the STATUS pin low when

the GATE to SOURCE voltage exceeds 0.7V, to indicate that

power is passing through the MOSFET. The FAULT output,

M2, pulls low during an undervoltage or overvoltage fault

condition. It also pulls low when GATE is fully on and

the forward voltage drop exceeds 250mV, indicating the

MOSFET has too much current or has failed open circuit.

Note that this open MOSFET fault does not turn off the

MOSFET unlike the undervoltage and overvoltage faults.

LDO is a low dropout regulator that generates a 4.1V

supply at the VCC pin from the VIN input. When a supply

below 2.9V is being ORed, an external supply in the 2.9V

to 6V range is required at the VCC pin. Comparator CP4

will disable LDO when VIN is below VCC.

LTC4352

4352fa

High availability systems often employ parallel-connected

power supplies or battery feeds to achieve redundancy

and enhance system reliability. ORing diodes have been

a popular means of connecting these supplies at the

point of load. Diodes with storage capacitors also hold

up supply voltages when an input voltage sags or has a

brownout. The disadvantage of these approaches is the

diode’s significant forward voltage drop and the resulting

power loss. Additionally, diodes provide no information

concerning the status of the sourcing supply. Separate

control must therefore be added to ensure that a supply

that is out of range is not allowed to affect the load.

The LTC4352 solves these problems by using an external

N-channel MOSFET as the pass element (see Figure 1).

The MOSFET is turned on when power is being passed,

allowing for a low voltage drop from the supply to the load.

When the input source voltage drops below the output

common supply voltage it turns off the MOSFET, thereby

matching the function and performance of an ideal diode.

Power Supply Configuration

The LTC4352 can operate with supplies down to 0V. This

requires powering the VCC pin with an always present

external supply in the 2.9V to 6V range. If not always

present, a series 470Ω resistor or Schottky diode limits

device power dissipation and backfeeding of low VCC

supply when VIN is high. For a 2.9V to 4.7V VCC supply,

VIN should be lower than VCC. A 0.1µF bypass capacitor

should also be connected between the VCC and GND pins,

close to the device. Figure 2 illustrates this.

If VIN operates above 2.9V then the external supply at

VCC is not needed. The 0.1µF capacitor is still required

for bypassing.

applicaTions inForMaTion

Figure 1. 12V Ideal Diode with Status and Fault Indicators

VCC

REV

LTC4352

STATUS

FAULT

0.1µF

2.7k

D1: GREEN LED LN1351C

D2: RED LED LN1261CAL

MOSFET

FAULT

2.7k

TO LOAD

12V

Si7336ADP

0.1µF

4352 F01

CPO VIN

SOURCE GATE

GND

OUT

Figure 2. Power Supply Configurations

VCC LTC4352

TO LOAD

0V TO VCC

VIN GATE OUT

0.1µF

2.9V TO 4.7V

GND

VCC LTC4352

TO LOAD

0V TO 18V

4352 F02

VIN GATE OUT

GND

VCC LTC4352

TO LOAD

2.9V TO 18V

VIN GATE OUT

0.1µF

GND

0.1µF

4.7V TO 6V

LTC4352

4352fa

Figure 3. Start-up Waveform for Single MOSFET Application

VOLTAGE

(5V/DIV)

TIME (2.5ms/DIV) 4352 FO3

CPO

GATE

OUT

VIN, SOURCE

VCC

VIN = 5V

C2 = 0.1µF

applicaTions inForMaTion

N-channel MOSFETs. The maximum allowable drain-source

voltage, BVDSS, must be higher than the supply voltages

as the full supply voltage can appear across the MOSFET

when the input falls to 0V.

The FAULT pin pulls low to signal an open MOSFET fault

whenever the forward voltage drop across the enhanced

MOSFET exceeds 250mV. The RDS(ON) should be small

enough to conduct the maximum load current while not

triggering such a fault (when using FAULT), and to stay

within the MOSFET’s power rating at the maximum load

current.

CPO Capacitor Selection

The recommended value of the capacitor between the

CPO and SOURCE pins is approximately 10x the input

capacitance, CISS, of the MOSFET. A larger capacitor takes

a correspondingly longer time to charge up by the internal

charge pump. A smaller capacitor suffers more voltage

drop during a fast gate turn-on event as it shares charge

with the MOSFET gate capacitance.

CPO and GATE Start-Up

In single MOSFET applications, CPO is initially pulled up

to a diode below the SOURCE pin (Figure 3). In back-to-

back MOSFET applications, CPO starts off at 0V, since

SOURCE is near ground (Figure 4). CPO starts ramping

up 10µs after VCC clears its undervoltage lockout level.

Another 40µs later, GATE will also start ramping up with

CPO if UV, OV and VIN – OUT conditions allow it to. The

ramp rate is decided by the CPO pull-up current into the

combined CPO and GATE pin capacitances. An internal

clamp limits the CPO voltage to 6.7V above SOURCE,

while the final GATE voltage is determined by the forward

drop servo amplifier.

MOSFET Selection

The LTC4352 drives N-channel MOSFETs to conduct the

load current. The important features of the MOSFET are

its threshold voltage, the maximum drain-source voltage

BVDSS, and the on-resistance RDS(ON).

The gate drive for the MOSFET is guaranteed to be between

5V and 7.5V. This allows the use of logic level threshold

Figure 4. Start-up Waveform for Back-to-Back MOSFET Application

VOLTAGE

(5V/DIV)

TIME (2.5ms/DIV) 4352 FO4

CPO

GATE

OUT

VIN

VCC

VIN = 5V

C2 = 0.1µF

LTC4352

4352fa

applicaTions inForMaTion

Figure 6. Inrush and Ideal Diode Control on a Hot Swap Card

LTC4352

PLUG-IN CARD

CONNECTORSBACKPLANE

Si7336ADP

TO LOAD

4352 F06

VIN

UV CPO

SOURCE GATE OUT

GND

12V

GND

105k

0.1µF

10k

R6 10Ω

5.11k

Z1: DIODES INC. SMAJ12A

Inrush Control

The LTC4352 can be used for inrush control in applications

where the input supply is hot-plugged. See Figure 6. The

CPO capacitor is omitted, since fast turn-on with stored

charge is not desired here. Undervoltage holds the gate

off till the short pin makes contact. 40µs after the UV level

is satisfied, the MOSFET gate ramps up due to the CPO

pull-up current. A RC network on the gate further slows

down the output dV/dt, while allowing fast turn-off during

reverse current or overvoltage conditions. Resistor RG

prevents high frequency oscillations in Q2. A dedicated

hot swap controller may be needed if overcurrent protec-

tion is also desired.

Undervoltage and Overvoltage Protection

Unlike a regular diode, the LTC4352 can prevent out of

range input voltages from affecting the load voltage. This

requires back-to-back MOSFETs, and resistive dividers

from the input to the UV and OV pins. For an example,

see Figure 5.

MOSFET Q2 is required to block conduction through the

body diode of Q1 when its gate is held off. The resistive

dividers set up the input voltage range where the ideal

diode control is allowed to operate. Outside this range,

the gate is held off and the FAULT pin pulls low.

When using a CPO capacitor in circuit with back-to-back

MOSFETs, there will be a large inrush current to the load

capacitance due to the fast gate turn-on after UV, OV levels

are met. Without the capacitor, the inrush will depend on

the CPO pull-up current charging up the gate capacitance.

Figure 5. 5V Ideal Diode with UV and OV Protection

LTC4352

FAULT

STATUS

VCC

31.6k

3.09k

TO LOAD

Si7336ADP

0.1µF

4352 F05

CPOVIN SOURCE GATE OUT

0.15µF

REV

GND

LTC4352

4352fa

SOURCE

LTC4352

TO LOAD

Si7336ADP

4352 F07

VIN GATE OUT

0.1µF

GND

12V

CPO

Figure 7. 5V Ideal Diode with External 12V Powering CPO for

Faster Start-up and Refresh

applicaTions inForMaTion

External CPO Supply

The internal charge pump takes milliseconds to charge

up the CPO pin capacitor especially during device power

up. This time can be shortened by connecting an external

supply to the CPO pin. A series resistor is needed to limit

the current into the internal clamp between the CPO and

SOURCE pins. The CPO supply should also be higher than

the main input supply to meet the gate drive requirements

of the MOSFET. Figure 7 shows such a 5V ideal diode ap-

plication, where a 12V supply is connected to the CPO pin

through a 1k resistor. The 1k limits the current into the

CPO pin to 5.3mA, when the SOURCE pin is grounded.

Input Transient Protection

When the capacitances at the input and output are very

small, rapid changes in current can cause transients that

exceed the 24V Absolute Maximum Rating of the VIN and

OUT pins. In ORing applications using a single MOSFET, one

surge suppressor connected from OUT to ground clamps

all the inputs. In the absence of a surge suppressor, an

output capacitance of 10μF is sufficient in most applications

to prevent the transient from exceeding 24V. Back-to-back

MOSFET applications, depending on voltage levels, may

require a surge suppressor on each supply input.

Design Example

The following design example demonstrates the calcula-

tions involved for selecting components in a 12V system

with 10A maximum load current (see Figure 1).

First, calculate the RDS(ON) of the MOSFET to achieve the

desired forward drop at full load. Assuming a VFWD of

50mV (which is comfortably below the 200mV minimum

open MOSFET fault threshold):

RDS ON

( )

≤VFWD

ILOAD

=50mV

10A =5mΩ

The Si7336ADP offers a good solution, in a SO-8 sized

package, with a maximum RDS(ON) of 4mΩ and BVDSS of

30V. The maximum power dissipation in the MOSFET is:

P = I2LOAD • RDS(ON) = (10A)2 • 4mΩ = 0.4W

With a maximum steady-state thermal resistance, θJA,

of 65°C/W, 0.4W causes a modest 26°C rise in junction

temperature of the Si7336ADP above the ambient.

The input capacitance, CISS, of the Si7336ADP is about

6500pF. Slightly exceeding the 10x recommendation, a

0.1µF capacitor is selected for C2.

LTC4352

4352fa

Figure 8. Recommended PCB Layout for Power MOSFET

DRAWING IS NOT TO SCALE!

VIA TO GROUND PLANE

SOURCE

GATE

LTC4352 MSOP-12

GND

OUT

VIN

VCC

VIA TO GROUND PLANE

CURRENT FLOWCURRENT FLOW

W W

TRACK WIDTH W:

0.03˝ PER AMPERE

ON 1OZ CU FOIL

FROM INPUT

SUPPLY

TO LOAD

SO-8

4352 F08

applicaTions inForMaTion

LEDs, D1 and D2, require around 3mA for good luminous

intensity. Accounting for a 2V diode drop and 0.5V VOL,

R1 and R2 are set to 2.7k.

PCB Layout Considerations

Connect the VIN and OUT pin traces as close as possible

to the MOSFET’s terminals. Keep the traces to the MOSFET

wide and short to minimize resistive losses. The PCB traces

associated with the power path through the MOSFET should

have low resistance. See Figure 8.

It is also important to put C1, the bypass capacitor for the

VCC pin, as close as possible between VCC and GND. Also

place C2 near the CPO and SOURCE pins. Surge suppres-

sors, when used, should be mounted close to the LTC4352

using short lead lengths.

LTC4352

4352fa

Typical applicaTions

Plug-in Card Supply Holdup Using Ideal Diode at Input

Ideal Diode with Reverse Input Protection

LTC4352

PLUG-IN CARDCONNECTORSBACKPLANE

Si7336ADP

4352 TA02

VIN

SOURCE GATE OUT

GND

TO LOAD12V

GND

CHOLDUP

HOT SWAP

CONTROLLER

VCC

REV

LTC4352

STATUS

FAULT

0.1µF

10A LOAD

SMAJ17A

1N4148

BAT85

3.5V TO 9V

Si4438DY

0.1µF

4352 TA04

CPO VIN

SOURCE GATE

GND

OUT

LTC4352

4352fa

DD Package

12-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1725 Rev A)

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ± 0.10

0.75 ±0.05

R = 0.115

TYP

127

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD12) DFN 0106 REV A

0.23 ± 0.05

PIN 1 NOTCH

R = 0.20 OR

0.25 × 45°

CHAMFER

2.38 ±0.10

2.25 REF

0.45 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.25 ± 0.05

2.25 REF

2.38 ±0.05

1.65 ±0.05

2.10 ±0.05

0.70 ±0.05

3.50 ±0.05

PACKAGE

OUTLINE

0.45 BSC

package DescripTion

MS Package

12-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1668 Rev Ø)

MSOP (MS12) 1107 REV Ø

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.22 – 0.38

(.009 – .015)

TYP

0.86

(.034)

REF

0.650

(.0256)

BSC

12 11 10 9 8 7

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.42 ± 0.038

(.0165 ± .0015)

TYP

0.65

(.0256)

BSC

4.039 ± 0.102

(.159 ± .004)

(NOTE 3)

0.1016 ± 0.0508

(.004 ± .002)

1 2 3 4 5 6

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

0.406 ± 0.076

(.016 ± .003)

REF

4.90 ± 0.152

(.193 ± .006)

LTC4352

4352fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 12/10 Added H-grade information

Revised FAULT pin description in Pin Functions

Revised Functional Diagram

Added text to Operation section

Revised Figures 2, 5, 6 in Applications Information

Added new Typical Application

Revised Typical Application and Related Parts list

2,3

8, 10

LTC4352

4352fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2008

LT 1210 REV A • PRINTED IN USA

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTC1473/LTC1473L Dual PowerPath™ Switch Driver N-Channel, 4.75V to 30V/3.3V to 10V, SSOP-16

LTC1479 PowerPath Controller for Dual Battery Systems Three N-Channel Drivers, 6V to 28V, SSOP-36

LTC4350 Hot Swappable Load Share Controller N-Channel, 1.5V to 12V, Share Bus, SSOP-16

LTC4354 Negative Voltage Diode-OR Controller and Monitor Dual N-Channel, –4.5V to –80V, SO-8, DFN-8

LTC4355 Positive High Voltage Ideal Diode-OR and Monitor Dual N-Channel, 9V to 80V, SO-16, DFN-14

LTC4357 Positive High Voltage Ideal Diode Controller N-Channel, 9V to 80V, MSOP-8, DFN-6

LTC4358 5A Ideal Diode Internal N-Channel, 9V to 26.5V, TSSOP-16, DFN-14

LTC4411 2.6A Low Loss Ideal Diode in ThinSOT™ Internal P-Channel, 2.6V to 5.5V, 40μA IQ, SOT-23

LTC4412/LTC4412HV Low Loss PowerPath Controller in ThinSOT P-Channel, 2.5V to 28V/36V, 11μA IQ, TSOT-23

LTC4413/LTC4413-1 Dual 2.6A, 2.5V to 5.5V, Ideal Diodes in DFN-10 Dual Internal P-Channel, 2.5V to 5.5V, DFN-10

LTC4414 36V Low Loss PowerPath Controller for Large PFETs P-Channel, 3V to 36V, 30μA IQ, MSOP-8

LTC4416/LTC4416-1 36V Low Loss Dual PowerPath Controller for Large PFETs Dual P-Channel, 3.6V to 36V, 70μA IQ, MSOP-10

VCC

REV

LTC4352

STATUS

FAULT

0.1µF

VIN1

0V TO 18V

Si7336ADP

TO LOAD

0.1µF

CPO VIN

SOURCE GATE

GND

OUT

VCC

REV

LTC4352

STATUS

FAULT

0.1µF

VIN2

0V TO 18V

Si7336ADP

0.1µF

CPO VIN

SOURCE GATE

GND

OUT

4352 TA03

0V to 18V Ideal Diode-OR