HYMD212G726K4-L - SK Hynix - Product.Network

HYMD212G726K4-K/H/L

128Mx72 Registered DDR SDRAM DIMM

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev.0.1/Apr.01

DESCRIPTION

Hynix HYMD212G726K4-K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory

Modules (DIMMs) which are organized as 128Mx72 high-speed memory arrays. HynixHYMD212G726K4-K/H/L series

consists of eighteen stacked 128Mx4 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.

HynixHYMD212G726K4-K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of industry

standard. It is suitable for easy interchange and addition.

Hynix HYMD212G726K4-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous opera-

tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are

latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising

and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All

input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and

burst lengths allow variety of device operation in high performance memory system.

HynixHYMD212G726K4-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is

implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•1GB (128M x 72) Registered DDR DIMM based on

stacked 128Mx4 DDR SDRAM

•JEDEC Standard 184-pin dual in-line memory module

(DIMM)

•Error Check Correction (ECC) Capability

•Registered inputs with one-clock delay

•Phase-lock loop (PLL) clock driver to reduce loading

•2.5V +/- 0.2V VDD and VDDQ Power supply

•All inputs and outputs are compatible with SSTL_2

interface

•Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz

•Programmable CAS Latency 2 / 2.5 supported

•Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

•Internal four bank operations with single pulsed RAS

•Auto refresh and self refresh supported

•8192 refresh cycles / 64ms

ORDERING INFORMATION

Part No. Power Suppy Clock Frequency Interface Form Factor

HYMD212G726K4-K VDD=2.5V

VDDQ=2.5V

133MHz (*DDR266A)

SSTL_2 184pin Registered DIMM

5.25 x 1.25 x 0.15 inch

HYMD212G726K4-H 133MHz (*DDR266B)

HYMD212G726K4-L 100MHz (*DDR200)

PRELIMINARY

* JEDEC Defined Specifications compliant

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 2

PIN DESCRIPTION

PIN ASSIGNMENT

Pin Pin Description Pin Pin Description

CK0, /CK0 Differential Clock Inputs VDDQ DQs Power Supply

CS0 Chip Select Input VSS Ground

CKE0 Clock Enable Input VREF Reference Power Supply

/RAS, /CAS, /WE Commend Sets Inputs VDDSPD Power Supply for SPD

A0 ~ A12 Address SA0~SA2 E2PROM Address Inputs

BA0, BA1 Bank Address SCL E2PROM Clock

DQ0~DQ63 Data Inputs/Outputs SDA E2PROM Data I/O

CB0~CB7 Data Strobe Inputs/Outputs WP Write Protect Flag

DQS0~DQS17 Data Strobe Inputs/Outputs VDDID VDD Identification Flag

DM0~DM8 Data-in Mask DU Do not Use

VDD Power Supply NC No Connection

/RESET Reset Enable FETEN FET Enable

Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name

1VREF 32 A5 62 VDDQ 93 VSS 124 VSS 154 /RAS

2DQ0 33 DQ24 63 /WE 94 DQ4 125 A6 155 DQ45

3VSS 34 VSS 64 DQ41 95 DQ5 126 DQ28 156 VDDQ

4DQ1 35 DQ25 65 /CAS 96 VDDQ 127 DQ29 157 /CS0

5DQS0 36 DQS3 66 VSS 97 DQS9 128 VDDQ 158 /CS1*

6DQ2 37 A4 67 DQS5 98 DQ6 129 DQS12 159 DM5

7VDD 38 VDD 68 DQ42 99 DQ7 130 A3 160 VSS

8DQ3 39 DQ26 69 DQ43 100 VSS 131 DQ30 161 DQ46

9NC 40 DQ27 70 VDD 101 NC 132 VSS 162 DQ47

10 /RESET 41 A2 71 NC 102 NC 133 DQ31 163 NC

11 VSS 42 Vss 72 DQ48 103 A13* 134 CB4 164 VDDQ

12 DQ8 43 A1 73 DQ49 104 VDDQ 135 CB5 165 DQ52

13 DQ9 44 CB0 74 VSS 105 DQ12 136 VDDQ 166 DQ53

14 DQS1 45 CB1 75 DU 106 DQ13 137 CK0 167 NC, FETEN*

15 VDDQ 46 VDD 76 DU 107 DQS10 138 /CK0 168 VDD

16 DU 47 DQS8 77 VDDQ 108 VDD 139 VSS 169 DM6

17 DU 48 A0 78 DQS6 109 DQ14 140 DQS17 170 DQ54

18 VSS 49 CB2 79 DQ50 110 DQ15 141 A10 171 DQ55

19 DQ10 50 VSS 80 DQ51 111 CKE1* 142 CB6 172 VDDQ

20 DQ11 51 CB3 81 VSS 112 VDDQ 143 VDDQ 173 NC

21 CKE0 52 BA1 82 VDDID 113 BA2* 144 CB7 174 DQ60

22 VDDQ Key 83 DQ56 114 DQ20 key 175 DQ61

23 DQ16 53 DQ32 84 DQ57 115 A12 145 VSS 176 VSS

24 DQ17 54 VDDQ 85 VDD 116 VSS 146 DQ36 177 DM7

25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178 DQ62

26 VSS 56 DQS4 87 DQ58 118 A11 148 VDD 179 DQ63

27 A9 57 DQ34 88 DQ59 119 DQS11 149 DQS13 180 VDDQ

28 DQ18 58 VSS 89 VSS 120 VDD 150 DQ38 181 SA0

29 A7 59 BA0 90 WP 121 DQ22 151 DQ39 182 SA1

30 VDDQ 60 DQ35 91 SDA 122 A8 152 VSS 183 SA2

31 DQ19 61 DQ40 92 SCL 123 DQ23 153 DQ44 184 VDDSPD

* These are not used on this module but may be used for other module in 184pin DIMM family

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 3

FUNCTIONAL BLOCK DIAGRAM

SCL

Serial PD

A0 A1 A2

SA0 SA1 SA2

47KSDA

Notes:

1. DQ-to-I/O wiring may be changed within byte

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

3. VDDID strap connections(for memory device VDD, VDDQ);

STRAP OUT(OPEN) : VDD=VDDQ.

STRAP IN (Vss) : VDD = VDDQ

4. Address and control resistors should be 22 Ohms

5. FETEN may be wired to respective DRAMs(QFC pin)

or tab(FETEN) pin (TBD).

CK0, /CK0 --------- PLL*

* Wire per clock loading table/wiring diagrams

/RCS0 -->/CS : SDRAMs D0-D17

/RCS1 -->/CS : SDRAMs D18 -D35

RBA0-RBA1--> : BA0-BA1: SDRAMs D0-D35

RA0 -R A12 -->A0 -A12 : SDRAMs D0 -D35

/RRAS --> /RAS : SDRAMs D0 -D35

/RCAS --> /CAS : SDRAMs D0 -D35

RCKE0 --> CKE : SDRAMs D0 -D17

RCKE1 --> CKE : SDRAMs D18-D35

/RWE --> /WE : SDRAMs D0 -D35

/CS0

/CS1

BA0-BA1

A0-A12

/RAS

/CAS

CKE0

CKE1

/WE

PCK

/PCK /RESET

DQ0

DQ1

DQ2

DQ3 D0

/CSDQS

DQS0

I/O 0

I/O 1

I/O 2

I/O 3

DQ8

DQ9

DQ10

DQ11 D1

/CS

DQS

DQS1

I/O 0

I/O 1

I/O 2

I/O 3

DQ16

DQ17

DQ18

DQ19 D2

/CSDQS

DQS2

I/O 0

I/O 1

I/O 2

I/O 3

DQ24

DQ25

DQ26

DQ27 D3

/CSDQS

DQS3

I/O 0

I/O 1

I/O 2

I/O 3

DQ32

DQ33

DQ34

DQ35 D4

/CS

DQS

DQS4

I/O 0

I/O 1

I/O 2

I/O 3

DQ40

DQ41

DQ42

DQ43 D5

/CSDQS

DQS5

I/O 0

I/O 1

I/O 2

I/O 3

DQ48

DQ49

DQ50

DQ51 D6

/CS

DQS

DQS6

I/O 0

I/O 1

I/O 2

I/O 3

DQ56

DQ57

DQ58

DQ59 D7

/CSDQS

DQS7

I/O 0

I/O 1

I/O 2

I/O 3

CB0

CB1

CB2

CB3 D8

/CS

DQS

DQS8

I/O 0

I/O 1

I/O 2

I/O 3

DQS9

DQS10

DQS11

DQS12

DQS13

DQ4

DQ5

DQ6

DQ7 D9

/CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQ12

DQ13

DQ14

DQ15 D10

/CSDQS

I/O 0

I/O 1

I/O 2

I/O 3

DQ20

DQ21

DQ22

DQ23 D11

/CSDQS

I/O 0

I/O 1

I/O 2

I/O 3

DQ28

DQ29

DQ30

DQ31 D12

/CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

DQ36

DQ37

DQ38

DQ39 D13

/CSDQS

I/O 0

I/O 1

I/O 2

I/O 3

DQ44

DQ45

DQ46

DQ47 D14

/CS

DQS

DQS14

I/O 0

I/O 1

I/O 2

I/O 3

DQ52

DQ53

DQ54

DQ55 D15

/CSDQS

DQS15

I/O 0

I/O 1

I/O 2

I/O 3

DQ60

DQ61

DQ62

DQ63 D16

/CSDQS

DQS16

I/O 0

I/O 1

I/O 2

I/O 3

CB4

CB5

CB6

CB7 D17

/CS

DQS

DQS17

I/O 0

I/O 1

I/O 2

I/O 3

/CS

DQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CSDQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CSDQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CSDQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CS

DQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CS

DQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CSDQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CS

DQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CS

DQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CS

DQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CSDQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CS

DQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CSDQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CSDQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CS

DQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CSDQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CS

DQS DM

I/O 0

I/O 1

I/O 2

I/O 3

/CS

DQS DM

I/O 0

I/O 1

I/O 2

I/O 3

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

Vss

/RCS1

/RCS0 ..

. .

VDDSPD

VREF

VSS

VDDID

D0 -D17

.. Strap:see Note 4

VDD

SPD

VDDQ =

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 4

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

Note :

1. VDDQ must not exceed the level of VDD.

2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.

3. The value of VREF is approximately equal to 0.5VDDQ.

AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)

Note :

1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

Parameter Symbol Rating Unit

Ambient Temperature TA0 ~ 70 oC

Storage Temperature TSTG -55 ~ 125 oC

Voltage on Any Pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V

Voltage on VDD relative to VSS VDD -0.5 ~ 3.6 V

Voltage on VDDQ relative to VSS VDDQ -0.5 ~ 3.6 V

Output Short Circuit Current IOS 50 mA

Power Dissipation PD18 W

Soldering Temperature ⋅ Time TSOLDER 260 ⋅ 10 oC ⋅ Sec

Parameter Symbol Min Typ. Max Unit Note

Power Supply Voltage VDD 2.3 2.5 2.7 V

Power Supply Voltage VDDQ 2.3 2.5 2.7 V1

Input High Voltage VIH VREF + 0.15 -VDDQ + 0.3 V

Input Low Voltage VIL -0.3 -VREF - 0.15 V2

Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V

Reference Voltage VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V3

Parameter Symbol Min Max Unit Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31 V

Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V1

Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V2

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 5

AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Parameter Value Unit

Reference Voltage VDDQ x 0.5 V

Termination Voltage VDDQ x 0.5 V

AC Input High Level Voltage (VIH, min) VREF + 0.31 V

AC Input Low Level Voltage (VIL, max) VREF - 0.31 V

Input Timing Measurement Reference Level Voltage VREF V

Output Timing Measurement Reference Level Voltage VTT V

Input Signal maximum peak swing 1.5 V

Input minimum Signal Slew Rate 1V/ns

Termination Resistor (RT)50 Ω

Series Resistor (RS)25 Ω

Output Load Capacitance for Access Time Measurement (CL)30 pF

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 6

CAPACITANCE (TA=25oC, f=100MHz )

Note :

1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V

2. Pins not under test are tied to GND.

3. These values are guaranteed by design and are tested on a sample basis only.

OUTPUT LOAD CIRCUIT

Parameter Pin Symbol Min Max Unit

Input Capacitance A0 ~ A12, BA0, BA1 CIN1 512 pF

Input Capacitance RAS, CAS, WE CIN2 512 pF

Input Capacitance CKE0 CIN3 512 pF

Input Capacitance CS0 CIN4 512 pF

Input Capacitance CK0, CK0 CIN5 512 pF

Data Input / Output Capacitance DQ0 ~ DQ63, DQS0 ~ DQS17 CIO1 811 pF

Data Input / Output Capacitance CB0 ~ CB7 CIO2 811 pF

VREF

VTT VTT

RT=50ΩRT=50Ω

RS=25ΩZo=50Ω

CL=30pF

Output

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 7

DC CHARACTERISTICS I (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Note :

1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V

2. DOUT is disabled, VOUT=0 to 2.7V

3. These values are device characteristics.

DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V)

Parameter Symbol Min. Max Unit Note

Input Leakage Current ILI -5 5uA 1

Output Leakage Current ILO -5 5uA 2

Output High Voltage VOH VTT + 0.76 -VIOH = -15.2mA

Output Low Voltage VOL -VTT - 0.76 VIOL = +15.2mA

Parameter Symbol Test Condition Speed Unit Note

-K -H -L

Operating Current IDD0

One bank; Active - Precharge ; tRC=tRC(min);

tCK= tCK(min) ; DQ,DM and DQS inputs changing

twice per clock cycle ; address and control inputs

changing once per clock cycle

2610 2610 2520 mA

Operating Current IDD1

One bank ; Active - Read - Precharge ; Burst

Length = 2 ; tRC=tRC(min); tCK= tCK(min) ;

address and control inputs changing once per clock

cycle

3060 3060 2880 mA

Precharge Power Down

Standby Current IDD2P All banks idle ; Power down mode ; CKE= Low,

tCK= tCK(min) 720 mA

Idle Standby Current IDD2F CS = High, All banks idle ; tCK= tCK(min) ; CKE =

High ; address and control inputs changing once

per clock cycle. VIN = VREF for DQ, DQS, and DM 1440 1440 1260 mA

Active Power Down

Standby Current IDD3P One bank active ; Power down mode ; CKE= Low,

tCK= tCK(min) 900 mA

Active Standby Current IDD3N

/CS= HIGH, CKE = HIGH; One bank; Active-

Precharge; tRC = tRAS(max); tCK = t CK(min); DQ,

DM and DQS inputs changing twice per clock cycle;

Address and other control inputs changing once per

clock cycle

1800 mA

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 8

DC CHARACTERISTICS II (TA=0 to 70oC, Voltage referenced to VSS = 0V) -Continued -

Parameter Symbol Test Condition Speed Unit Note

-K -H -L

Operating Current IDD4R Burst = 2 ; Reads; Continuous burst; One bank

active; Address and control inputs changing once

per clock cycle; tCK = tCK(min); IOUT = 0mA 4320 4320 3780

mAOperating Current IDD4W

Burst = 2; Writes; Continuous burst; One bank

active; Address and control inputs changing once

per clock cycle; tCK = tCK(min); DQ, DM, and DQS

inputs changing twice per clock cycle

5220 5220 4320

Auto Refresh Current IDD5 tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,

10*tCK for DDR266A & DDR266B at 133Mhz;

distributed refresh 4680 4680 4410

Self Refresh Current IDD6 CKE =< 0.2V; External clock on;

tCK = tCK(min)

Normal 108 mA

Low Power 54 mA

Operating Current - Four

Bank Operation IDD7 Four bank interleaving with BL=4 Refer to the

following page for detailed test condition 6210 6210 5850 mA

Note : Power consumption by PLL, Register, PCB is not included in this table

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 9

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter Symbol -K(DDR266A) -H(DDR266B) -L(DDR200) Unit Note

Min Max Min Max Min Max

Row Cycle Time tRC 60 -65 -70 -ns

Auto Refresh Row Cycle Time tRFC 75 -75 -80 -ns

Row Active Time tRAS 45 120K 48 120K 50 120K ns

Active to Read with Auto Precharge Delay tRAP 20 -20 -20 -ns 16

Row Address to Column Address Delay tRCD 20 -20 -20 -ns

Row Active to Row Active Delay tRRD 15 -15 -15 -ns

Column Address to Column Address Delay tCCD 1-1-1-CK

Row Precharge Time tRP 20 -20 -20 -ns

Last Data-in to Precharge Delay Time tDPL 15 -15 -15 -ns

Last Data-In to Read Command tDRL 1-1-1-CK

Auto Precharge Write Recovery + Precharge

Time tDAL 5-5-4-CK 15

System Clock Cycle Time CL = 2.5 tCK 7.5 15 7.5 15 10 15 ns

CL = 2 7.5 15 10 15 10 15 ns

Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 CK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 CK

Data-Out edge to Clock edge Skew tAC -0.75 0.75 -0.75 0.75 -0.8 0.8 ns

DQS-Out edge to Clock edge Skew tDQSCK -0.75 0.75 -0.75 0.75 -0.8 0.8 ns

DQS-Out edge to Data-Out edge Skew tDQSQ -0.5 -0.5 -0.6 ns

Data-Out hold time from DQS tQH tHPmin

-tQHS -tHPmin

-tQHS -ns 1, 10

Clock Half Period tHP tCH/L

min -tCH/L

min -ns 1,9

Data Hold Skew Factor tQHS -0.75 -0.75 -1ns 10

Valid Data Output Window tDV tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ ns

Data-out high-impedance window from

CK, /CK tHZ -1.2 0.8 ns

Data-out low-impedance window from

CK, /CK tLZ -1.2 0.8 ns

Input Setup Time (fast slew rate) tIS 0.9 -0.9 -1.0 -ns 2,3,5,6

Input Hold Time (fast slew rate) tIH 0.9 -0.9 -1.0 -ns 2,3,5,6

Input Setup Time (slow slew rate) tIS 1.1 -1.1 -1.1 -ns 2,4,5,6

Input Hold Time (slow slew rate) tIH 1.1 -1.1 -1.1 -ns 2,4,5,6

Input Pulse Width tIPW 2.2 2.2 -ns 6

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 10

AC CHARACTERISTICS (AC operating conditions unless otherwise noted) - continued -

Note :

1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, CS, RAS, CAS, WE.

3. For command/address input slew rate >=1.0V/ns

4. For command/address input slew rate >=0.5V/ns and <1.0V/ns

This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

5. CK, /CK slew rates are >=1.0V/ns

6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by

design or tester correlation

7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.

8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete

Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).

10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of

tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to

n-channel variation of the output drivers.

Parameter Symbol -K(DDR266A) -H(DDR266B) -L(DDR200) Unit Note

Min Max Min Max Min Max

Write DQS High Level Width tDQSH 0.35 -0.35 -0.35 -CK

Write DQS Low Level Width tDQSL 0.35 -0.35 -0.35 -CK

Clock to First Rising edge of DQS-In tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 CK

Data-In Setup Time to DQS-In (DQ & DM) tDS 0.5 -0.5 -0.6 -ns 6,7,

11~13

Data-in Hold Time to DQS-In (DQ & DM) tDH 0.5 -0.5 -0.6 -ns 6,7,

11~13

DQ & DM Input Pulse Width tDIPW 1.75 -1.75 -2-ns

Read DQS Preamble Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 CK

Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 CK

Write DQS Preamble Setup Time tWPRES 0-0-0-CK

Write DQS Preamble Hold Time tWPREH 0.25 -0.25 -0.25 -CK

Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 CK

Mode Register Set Delay tMRD 2-2-2-CK

Exit Self Refresh to Any Execute Command tXSC 200 -200 -200 -CK 8

Average Periodic Refresh Interval tREFI -15.6 -15.6 -15.6 us

Input Setup / Hold Slew-rate Delta tIS Delta tIH

V/ns ps ps

0.5 0 0

0.4 +50 0

0.3 +100 0

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 11

11.This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF

+/-310mV for a duration of up to 2ns.

13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS

slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1 = 0.5V/ns

and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.

14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotonic.

15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK

is equal to the actual system clock cycle time.

Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,

tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)

Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock

16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be

tRAS - BL/2 x tCK.

Input Setup / Hold Slew-rate Delta tDS Delta tDH

V/ns ps ps

0.5 0 0

0.4 +75 +75

0.3 +150 +150

I/O Input Level Delta tDS Delta tDH

mV ps ps

+280 +50 +50

(1/SlewRate1)-(1/SlewRate2) Delta tDS Delta tDH

ns/V ps ps

0 0 0

+/-0.25 +50 +50

+/- 0.5 +100 +100

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 12

SIMPLIFIED COMMAND TRUTH TABLE

Note :

1. DM states are Don’t Care. Refer to below Write Mask Truth Table.

2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Registering duing Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP

period from Prechagre command.

3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+tRP).

4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented

to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.

5. If A10/AP is High when Row Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be

precharged.

Command CKEn-1 CKEn CS RAS CAS WE ADDR A10/

AP BA Note

Extended Mode Register Set HXL L L L OP code 1,2

Mode Register Set HXL L L L OP code 1,2

Device Deselect HXHX X X X1

No Operation LHHH

Bank Active HXL L H H RA V1

Read HXLHLHCA LV1

Read with Autoprecharge H1,3

Write HXLHL L CA LV1

Write with Autoprecharge H1,4

Precharge All Banks HXL L HLXHX1,5

Precharge selected Bank LV1

Read Burst Stop HXLH H LX1

Auto Refresh H H L L L H X1

Self Refresh

Entry HL L L L H

Exit LHHX X X 1

LHHH

Precharge

Power Down

Mode

Entry HLHX X X

LHHH 1

Exit LHHX X X 1

LHHH 1

Active Power

Down Mode

Entry HLHX X X

LV V V 1

Exit LHX1

( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

HYMD212G726K4-K/H/L

Rev.0.1/Apr.01 13

PACKAGE DIMENSIONS

PLL

Front

128.95

5.077

131.35

5.171

133.35

5.25

43.18

1.7

3.0

.118

17.80

.700

.394

10.0

0.098

2.5

(2) 0

(2X)4.00

.157

Back Side

(Front)

4.24

.167

6.81TSOP

.268max.TSOP

1.27+/-0.10

0.05+/-0.004

SERIAL PRESENCE DETECT

Rev.0.0 / Apr.01

SPD SPECIFICATION

(128Mx72 DDR SDRAM Registered DIMM)

HYMD212G726K4-K/H/L

128Mx72 DDR SDRAM Registered DIMM

Rev.0.0 / Apr.01

SERIAL PRESENCE DETECT

Byte# Function Description Function Supported Hexa Value Note

KHLKHL

0Number of Bytes written into serial memory at module

manufacturer 128 Bytes 80h

1Total number of Bytes in SPD device 256 Bytes 08h

2Fundamental memory type DDR SDRAM 07h

3Number of row address on this assembly 13 0Dh 1

4Number of column address on this assembly 11 0Bh 1

5Number of physical banks on DIMM 2Bank 02h

6Module data width 72 Bits 48h

7Module data width (continued) -00h

8Module voltage Interface levels(VDDQ) SSTL 2.5V 04h

9DDR SDRAM cycle time at CAS Latency=2.5(tCK) 7.5ns 7.5ns 10ns 75h 75h A0h 2

10 DDR SDRAM access time from clock at CL=2.5 (tAC) +/-0.75ns +/-0.75ns +/-0.8ns 75h 75h 80h 2

11 Module configuration type ECC 02h

12 Refresh rate and type 7.8us & Self refresh 82h

13 Primary DDR SDRAM width x4 04h

14 Error checking DDR SDRAM data width x4 04h

15 Minimum clock delay for back-to-back random column

address(tCCD) 1 CLK 01h

16 Burst lengths supported 2,4,8 0Eh

17 Number of banks on each DDR SDRAM 4 Banks 04h

18 CAS latency supported 2, 2.5 0Ch

19 CS latency 001h

20 WE latency 102h

21 DDR SDRAM module attributes Registered, PLL 26h

22 DDR SDRAM device attributes : General +/-0.2Voltage tolerance 00h

23 DDR SDRAM cycle time at CL=2.0(tCK) 7.5ns 10ns 10ns 75h A0h A0h 2

24 DDR SDRAM access time from clock at CL=2.0(tAC) +/-0.75ns +/-0.75ns +/-0.8ns 75h 75h 80h 2

25 DDR SDRAM cycle time at CL=1.5(tCK) -00h 2

26 DDR SDRAM access time from clock at CL=1.5(tAC) -00h 2

27 Minimum row precharge time(tRP) 20ns 20ns 20ns 50h 50h 50h

28 Minimum row activate to row active delay(tRRD) 15ns 15ns 15ns 3Ch 3Ch 3Ch

29 Minimum RAS to CAS delay(tRCD) 20ns 20ns 20ns 50h 50h 50h

30 Minimum active to precharge time(tRAS) 45ns 45ns 50ns 2Dh 2Dh 32h

31 Module row density 512MB 80h

32 Command and address signal input setup time(tIS) 0.9ns 0.9ns 1.2ns 90h 90h C0h

33 Command and address signal input hold time(tIH) 0.9ns 0.9ns 1.2ns 90h 90h C0h

34 Data signal input setup time(tDS) 0.5ns 0.5ns 0.6ns 50h 50h 60h

35 Data signal input hold time(tDH) 0.5ns 0.5ns 0.6ns 50h 50h 60h

Based on Stacked 32Mx8 DDR SDRAM with SSTL_2, 4Banks & 8K Refresh

Bin Sort

K(DDR266A@CL=2), H(DDR266B@CL=2.5), L(DDR200@CL=2)

HYMD212G726K4-K/H/L

128Mx72 DDR SDRAM Registered DIMM

Rev.0.0 / Apr.01

SERIAL PRESENCE DETECT

Byte # Function Description Function Supported Hexa Value Note

KHLKHL

36~61 Superset information(may be used in future) -00h

62 SPD Revision code Initial release 00h

63 Checksum for Bytes 0~62 -E6h 11h D7h

64 Manufacturer JEDEC ID Code Hynix JEDEC ID ADh

65~71 --------- Manufacturer JEDEC ID Code -00h

72 Manufacturing location

Hynix(Korea Area)

HSA(United States Area)

HSE(Europe Area)

HSJ(Japan Area)

Singapore

Asia Area

0*h

1*h

2*h

3*h

4*h

5*h

73 Manufacture part number(Hynix Memory Module) H48h

74 -------- Manufacture part number(Hynix Memory Module) Y59h

75 -------- Manufacture part number(Hynix Memory Module) M4Dh

76 Manufacture part number (DDR SDRAM) D44h

77 Manufacture part number(Memory density) 232h

78 Manufacture part number(Module Depth) 131h

79 ------- Manufacture part number(Module Depth) 232h

80 Manufacture part number(Module type) G47h

81 Manufacture part number(Data width) 737h

82 -------Manufacture part number(Data width) 232h

83 Manufacture part number(Refresh, # of Bank.) 6(8K refresh,4Bank) 36h

84 Manufacture part number(Package ) K4Bh

85 Manufacture part number(Component configuration) 434h

86 Manufacture part number(Hyphen) ‘-’2Dh

87 Manufacture part number(Minimum cycle time) KHL4Bh 48h 4Ch

88~90 Manufacture part number(T.B.D) Blank 20h

91 Manufacture revision code(for Component) Blank 20h

92 Manufacture revision code (for PCB) 030h

93 Manufacturing date(week) - - 3

94 Manufacturing date(Year) - - 3

95~98 Module serial number - - 4

99~127 Manufacturer specific data (may be used in future) Undefined 00h 5

128~255 Open for customer use Undefined 00h 5

Note : 1. The bank address is excluded

2. This value is based on the component specification

3. These bytes are programmed by code of date week & date year

4. These bytes apply to Hynix’s own Module Serial Number system

5. These bytes undefined and coded as ‘00h’

6. Refer to Hynix Web Site