M50FLW080AK5G - STMicroelectronics

1/53June 2005

M50FLW080A

M50FLW080B

8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors)

3V Supply Firmware Hub / Low Pin Count Flash Memory

FEATURES SUMMARY

■FLASH MEMORY

– Compatible with either the LPC interface

or the FWH interface (Intel Spec rev1.1)

used in PC BIOS app lications

– 5 Signal Communication Interface

supporting Read and Write Operations

– 5 Additional General Purpose Inputs for

platform design flexibility

– Synchronized with 33MHz PCI clock

■16 BLOCKS OF 64 KBYTES

– 13 blocks of 64 KBytes each

– 3 blocks, subdivided into 16 uniform

sectors of 4 KBytes each

Two blocks at the top and one at the

bottom (M50FL W08 0A )

One block at the top and two at the bottom

(M50FLW080B)

■ENHANCED SECURITY

– Hardware Write Protect Pins for Block

Protection

– Register-based Read and Write

Protection

– Individual Lock Register for Each 4 KByte

Sector

■SUPPLY VOLTA GE

–V

CC = 3.0 to 3.6V for Program, Erase and

Read Operat io ns

–V

PP = 12V for Fast Program and Erase

■TWO INTERFACES

– Auto Detec tion of Firm ware Hub (FWH) or

Low Pin Count (LPC) Memory Cycles for

Embedded Operation with PC Chipsets

– Address/Address Multiplexed (A/A Mux)

Interface for programming equipment

compatibility.

■PROGRAMMING TIME: 10µs typical

■PROGRAM/ERASE CONTROLLER

– Embedded Program and Erase algorithms

– Status Register Bits

Figure 1. Packages

■PROGRAM/ERASE SUSPEND

– Read other Blocks/Sectors during

Program Suspend

– Program other Blocks/Sectors during

Erase Susp e nd

■ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Device Code (M50FLW080A): 80h

– Device Code (M50FLW080B): 81h

TSOP32 (NB)

8 x 14mm

PLCC32 (K)

TSOP40 (N)

10 x 20mm

M50FLW080A, M50FLW080B

2/53

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram (FWH/LPC Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Logic Diagram (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Signal Names (FWH/LPC Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Signal Names (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. PLCC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. TSOP32 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. TSOP40 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Addresses (M50FLW080A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Addresses (M50FLW080B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Firmware Hub/Low Pin Count (FWH/LPC) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 10

Input/Output Communications (FWH0/LAD0-FWH3/LAD3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Input Communication Frame (FWH4/LFRAME).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Identification Inputs (ID0-ID3).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

General Purpose Inputs (GPI0-GPI4).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Interface Configuration (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Interface Reset (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

CPU Reset (INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Clock (CLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Top Block Lock (TBL).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reserved for Future Use (RFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A0-A10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write En abl e (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Row/Column Address Select (RC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

VPP Optional Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. Memory Identification Input Configuration (LPC mode). . . . . . . . . . . . . . . . . . . . . . . . . . 12

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Firmware Hub/Low Pin Count (FWH/LPC) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3/53

M50FLW080A, M50FLW080B

Bus Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. FWH Bus Read Field Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. FWH Bus Read Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. FWH Bus Write Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. LPC Bus Read Field Definitions (1-Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. LPC Bus Read Waveforms (1-Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. LPC Bus Write Field Definitions (1 Byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10.LPC Bus Write Waveforms (1 Byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12. Electronic Signature Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Quadruple Byte Program Command (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Double/Quadruple Byte Program Command (FWH Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Sector Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 13. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program/Erase Controller Status (Bit SR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Erase Suspend Status (Bit SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Erase Status (Bit SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program Status (Bit SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

VPP Status (Bit SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Program Suspend Status (Bit SR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Block/Sector Protection Status (Bit SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Reserved (Bit SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 14. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

M50FLW080A, M50FLW080B

4/53

FIRMWARE HUB/LOW PIN COUNT (FWH/LPC) INTERFACE CONFIGURATION REGISTERS . . . 24

Lock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Write Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Read Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Lock Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 15. Configuration Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 16. Lock Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 17. General Purpose Inputs Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Firmware Hub/Low Pin Count (FWH/LPC) General Purpose Input Register . . . . . . . . . . . . . . 25

Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PROGRAM AND ERASE TIMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 18. Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 20. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 21. FWH/LPC Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 22. A/A Mux Interface AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 11.FWH/LPC Interface AC Measurement I/O Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 12.A/A Mux Interface AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 13.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 23. Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 24. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 14.FWH/LPC Interface Clock Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 25. FWH/LPC Interface Clock Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 15.FWH/LPC Interface AC Signal Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 26. FWH/LPC Interface AC Signal Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 16.Reset AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 27. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 17.A/A Mux Interface Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 28. A/A Mux Interface Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 18.A/A Mux Interface Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 29. A/A Mux Interface Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 19.PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline . . . . . . . . 36

Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data 37

Figure 20.TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline . . . . . . . . . . 38

Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data. . . 38

Figure 21.TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline. . . . . . . . . 39

Table 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . 39

5/53

M50FLW080A, M50FLW080B

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 33. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

APPENDIX A.BLOCK AND SECTOR ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 34. M50FLW080A Block, Sector and Lock Register Addresses . . . . . . . . . . . . . . . . . . . . . . 41

Table 35. M50FLW080B Block, Sector and Lock Register Addresses . . . . . . . . . . . . . . . . . . . . . . 43

APPENDIX B.FLOWCHARTS AND PSEUDO CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 22.Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 23.Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only). . . . . 46

Figure 24.Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . 47

Figure 25.Program Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . 48

Figure 26.Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) . . . . . . . . . . . . . . . . 49

Figure 27.Sector/Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 28.Erase Suspend and Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 51

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

M50FLW080A, M50FLW080B

6/53

SUMMARY D ESCRIPTION

The M50F LW080 is a 8 Mb it (1M x8) non- volatile

memory that can be read, erased and repro-

grammed. These operations can be performed us-

ing a single low voltage (3.0 to 3.6V) supply. For

fast programming and fast erasing on production

lines, an optional 12V power supply can be used

to reduce the erasing and programming time.

The memory is divided into 16 Uniform Blocks of

64 KBytes each, three of which are divided into 16

uniform sectors of 4 KBytes each (see APPENDIX

A. for details). All blocks and sectors can be

erased independently. So, it is possible to pre-

serve valid data while old data is erased. Blocks

can be protected individually to prevent accidental

program or e ra se commands from modifyin g their

contents.

Program and erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of

programming or erasing the memory by taking

care of all of the special operations that are re-

quired to update the memory contents. The end of

a program or erase operation can be detected and

any error conditions identified. The com mand set

to control the memory is consistent with the JE-

DEC standards.

Two differen t bus inte rfaces are suppor ted by the

memory:

■The primary interface, the FWH/LPC

Interface, uses Intel’s proprietary Firmware

Hub (FWH) and Low Pin Count (LPC)

protocol. This has been designed to remove

the need for the ISA bus in current PC

Chipsets. The M50FLW080 acts as the PC

BIOS on the Low Pin Count bus for these PC

Chipsets.

■The secondary interface, the Address/

Address Multiplexed (or A/A Mux) Interface, is

designed to be compatible with current Flash

Programmers, for production line

programming prior to fitting the device in a PC

Motherboard.

The memory is supplied with all the bits erased

(set to ’1’).

7/53

M50FLW080A, M50FLW080B

Figure 2. Logic Diagram (FWH/LPC Interface)

Figure 3. Logic Diagram (A/A Mux Interface)

Table 1. Signal Names (FWH/LPC Interface)

Table 2. Signal Names (A/A Mux Interface)

AI09229B

FWH4/LFRAME

FWH0/LAD0

FWH3/LAD3

VCC

M50FLW080A

M50FLW080B

CLK

VSS

TBL

INIT

ID0-ID3

GPI0-

GPI4

VPP

AI09230B

DQ0-DQ7

VCC

M50FLW080A

M50FLW080B

VSS

A0-A10

VPP

FWH0/LAD0-

FWH3/LAD3 Input/Outp ut Co mm un ica tio ns

FWH4/

LFRAME Input Communication Frame

ID0-ID3 Ide nt i fic atio n Inputs

(ID0 and ID1 are Reserved for

Future Use (RFU) in LPC mode)

GPI0-GPI4 General Purpose Inputs

IC Interface Configuration

RP Interface Reset

INIT CPU Re set

CLK Clock

TBL Top Block Lock

WP Write Protect

RFU Reserved for Future Use. Leave

disconnected

VCC Supply Voltage

VPP Optional Supply Voltage for Fast

Program and Erase Operations

VSS Ground

NC Not Connected Internally

IC Interface Configuration

A0-A10 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

GOutput En ab le

WWrite Enable

RC Row/Co lum n Ad dre ss Sele ct

RP Interface Reset

VCC Supply Voltage

VPP Optional Supply Voltage for Fast

Program and Erase Operations

VSS Ground

NC Not Connected Internally

M50FLW080A, M50FLW080B

8/53

Figure 4. PLCC Connections

Note: Pins 27 and 28 are not internally connected.

Figure 5. TSOP32 Connections

AI09231C

GPI4

FWH4/LFRAME

RFU

ID1/RFU

ID0/RFU

FWH0/LAD0

FWH1/LAD1

FWH2/LAD2

FWH3/LAD3

RFU

GPI1

TBL

ID3

ID2

GPI0

CLK

VSS

VCC

GPI2

RFU

VPP

VCC

M50FLW080A

M50FLW080B

GPI3

IC (VIL)

RFU

INIT

VSS

DQ0

A10

VPP

VCC

VSS

VCC

DQ7

IC (VIH)

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

VSS

A/A Mux A/A Mux

A/A MuxA/A Mux

AI09701B

DQ0

A4 A3

DQ7

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A/A Mux

ID1/RFU

FWH1/LAD1

FWH2/LAD2

GPI3

TBL ID2

GPI0

RFU

GPI4

NC FWH4/LFRAME

RFU

FWH3/LAD3

VSS

RFU

CLK

VPP

VCC M50FLW080A

M50FLW080B

16 17

ID3

VSS

INIT

GPI2 FWH0/LAD0

GPI1 ID0/RFU

IC (VIH)

VPP

VCC

A10

VSS

9/53

M50FLW080A, M50FLW080B

Figure 6. TSOP40 Connections

Table 3. Addresses (M50FLW080A) Table 4. Addresses (M50FLW080B)

Note: Also see APPENDIX A., Table 34. and Table 35 . for a full listing of the Block Addr esses.

AI09232C

DQ0

A4 A3

VSS

VCC

DQ7

DQ5

DQ1

DQ2

DQ3

DQ4

DQ6

A/A Mux

ID1/RFU

FWH1/LAD1

FWH2/LAD2

GPI3

TBL ID2

GPI0

VCC

IC (VIL)

RFU

GPI4

VSS

FWH4/LFRAME

RFU

FWH3/LAD3

VSS

VCC

RFU

CLK

VPP

VCC

M50FLW080A

M50FLW080B

20 21

ID3

NC INIT

NC NC

GPI2 FWH0/LAD0

GPI1 ID0/RFU

VSS

IC (VIH)

VPP

VCC

A10

VSS

VCC

Block Size

(KByte) A dd res s Ra ng e Sector Size (KB y te)

64 F0000h-FFFFFh 16 x 4 KBytes

64 E0000h-EFFFFh 16 x 4 KBytes

64 D0000h-DFFFFh

13 x 64 KBytes

64 C0000h-CFFFFh

64 B0000h-BFFFFh

64 A0000h-AFFFFh

64 90000h-9FFFFh

64 80000h-8FFFFh

64 70000h-7FFFFh

64 60000h-6FFFFh

64 50000h-5FFFFh

64 40000h-4FFFFh

64 30000h-3FFFFh

64 20000h-2FFFFh

64 10000h-1FFFFh

64 00000h-0FFFFh 16 x 4 KBytes

Block Size

(KByte) A dd res s Ra ng e Sector Size (KB y te)

64 F0000h-FFFFFh 16 x 4 KBytes

64 E0000h-EFFFFh

13 x 64 KBytes

64 D0000h-DFFFFh

64 C0000h-CFFFFh

64 B0000h-BFFFFh

64 A0000h-AFFFFh

64 90000h-9FFFFh

64 80000h-8FFFFh

64 70000h-7FFFFh

64 60000h- 6FFFFh

64 50000h- 5FFFFh

64 40000h- 4FFFFh

64 30000h-3FFFFh

64 20000h-2FFFFh

64 10000h-1FFFFh 16 x 4 KBytes

64 00000h-0FFFFh 16 x 4 KBytes

M50FLW080A, M50FLW080B

10/53

SIGNAL DESCRIPTIONS

There are two distin ct bus interf aces available on

this device. The active interface is selected before

power-up, or during Reset, using the Interface

Configuration Pin, IC.

The signals for each interface are discussed in the

Firmware Hub/Low Pin Count (FWH/LPC) Signal

Descriptions section and the Address/Address

Multiplexed (A/A Mux) Signal Descriptions sec-

tio n, re spec tive ly, while t he supp ly s ignal s ar e dis-

cussed in the Supply Signal Descriptions section.

Firmware Hub/Low Pin Count (FWH/LPC)

Signal Descriptions

Please see Figure 2. and Table 1..

Input/Output Communications (FWH0/LAD0-

FWH3/LAD3). All Input and Output Communica-

tions with the memory take place on these pins.

Addresses and Data fo r Bus Read and Bu s Write

operations are encoded on these pins.

Input Communication Frame (FWH4/

LFRAME). The Input Communication Frame

(FWH4/LFRAME) signal indicates the start of a

bus operation. When Input Communication Frame

is Low, VIL, on the rising edge of the Clock, a new

bus operation is initiated. If Input Communication

Frame is Low, VIL, during a bus operation then the

operation is aborted. W hen Input Com munication

Frame is High, VIH, the current bus operation is ei-

ther proceeding or the bus is idle.

Identification Inputs (ID0-ID3). Up to 16 memo-

ries can be addressed on a bus, in the Firmware

Hub (FWH) mode. The Identification Inputs allow

each devi ce to be giv en a uni que 4- bit addres s . A

‘0’ is signified on a pin by driving it Low, VIL, or

leaving it floating (since there is an internal pull-

down resistor, with a value of RIL). A ‘1’ is signified

on a pin by driving it High, VIH (and there will be a

leakage current of ILI2 through the pin).

By convention, the boot memory must have ad-

dress ‘000 0’, and al l additio nal memori es are giv -

en addresses, allocated sequentially, from ‘0001’.

In the Low Pin Count (LPC) mode, the identifica-

tion Inputs (ID2-ID3) can address up to 4 memo-

ries on a bus. In the LPC mode, the ID0 and ID1

signals are Reserved for Future Use (RFU). The

value on address A20-A21 is compared to the

hardware strap ping on the ID2-ID3 lines to sele ct

the memory that is being addressed. For an ad-

dress bit to be ‘1’, the corresponding ID pin can be

left floating or driven Low, VIL (again, with the in-

ternal pull- down resistor, wi th a value of RIL). F or

an address bit to be ‘0’, the corresponding ID pin

must be dr iv en H ig h, VIH (and there will be a leak-

age current of ILI2 through th e pin, as spec ified in

Table 24.). For details, see Table 5..

General Purpose Inputs (GPI0-GPI4). The

General Pu rp os e Inp uts can be us ed a s d igi tal in -

puts for the CPU to read, with their contents being

availabl e in the Gener al Purpose Inputs Regis ter.

The pins must have stable data throughout the en-

tire cycle that reads the General Purpose Input

High, VIH, and must not be left floating.

Interface Configuration (IC). The Interface Con-

figuration input selects whether the FWH/LPC in-

terface or the Address/Address Multiplexed (A/A

Mux) Interface is used . The state of the Interface

Configuration, IC, should not be changed during

operation of the memory device, except for select-

ing the desired interface in the period before pow-

er-up or during a Reset.

To select the FWH/LPC Interface, the Interface

Configuration pin should be left to float or driven

Low, VIL. To select the Address/Address Multi-

pl exed (A/ A Mux) Inter face, the pin shoul d be driv-

en High, VIH. An internal pull-down resistor is

included with a value of RIL; there will be a leakage

cu rrent of ILI2 through each pin when pulled to VIH.

Interface Reset (RP). The Interface Reset (RP)

input is used to reset the device. When Interface

Reset (RP) is driven Low, VIL, the memory is in

Reset mode (the outputs go to high impedance,

and the current cons um pti on is min im iz ed). Wh en

RP is driven High, VIH, the device is in normal op-

eration. After exiting Reset mode, the memory en-

ters Read mode.

CPU Reset (INIT). The CPU Reset, INIT, signal

is used to Reset the device when the CPU is reset.

It behaves identically to Interface Reset, RP, a nd

the inter nal Reset line i s the logical OR (el ectric al

AND) of RP and INIT.

Clock (CLK). The Clock, CLK, input is used to

clock the signals in and out of the Input/Output

Communication Pins, FWH0/LAD0-FWH3/LAD3.

The Clock conforms to the PCI specification.

Top Block Lock (TBL). The Top Block Lock in-

put is used to prevent the Top Block (Block 15)

from being ch anged. When T op Block Lock , TBL,

is driven Lo w, VIL, program and erase operat ions

in the T op Bl ock ha ve no ef fect, reg ardles s of the

state of the Lock Register. When Top Block Lock,

TBL, is driven High, VIH, the protection of the Block

is determ ined by the Lo ck Regist ers. The sta te of

Top Block Lock, TBL, does not affect the protec-

tion of the Main Blocks (Blocks 0 to 14). For de-

tails, see APPENDIX A..

Top Block Lock, TBL, must be set prior to a pro-

gram or erase operation being in itiated, and mu st

not be changed until the operation has completed,

otherwise unpredictable results may occur. Simi-

larly, unpredictable behavior is possible if WP is

11/53

M50FLW080A, M50FLW080B

changed during Program or Erase Suspend, and

care should be taken to avoid this.

Write Protect (WP). The Write Protect input is

used to prevent the M ain Blocks (Blocks 0 to 14)

from being changed. When Write Protect, WP, is

driven Low , VIL, Pr o gr am and Erase oper ati ons in

the Main Blocks have n o effect, regardl ess of the

state of the Lock Register. When Write Protect,

WP, is driv en High, V IH, the protection of the Block

or Sector is determined by the Lock Registers. The

state of Write Protect, WP, does not affect the pro-

tection of the Top Block (Block 15). For details,

see APPENDIX A..

Write Protect, WP, must be set prior to a Program

or Erase operation is initiated, and must not be

changed unti l the operation has comp leted other-

wise unpredictable results may occur. Similarly,

unpredictable behavior is possible if WP is

changed during Program or Erase Suspend, and

care should be taken to avoid this.

Reserved for Future Use (RFU). Reserved for

Future Use (RFU). These pins do not presently

have assigned functions. They must be left discon-

nected, except for ID0 and ID1 (when in LPC

mode) which can be left connected. The electrical

characteristics for these signals are as d escribed

in the “Identification Inputs (ID0-ID3).” section.

Address/Address Multiplexed (A/A Mux)

Signal Descriptions

Please see Figure 3. and Table 2..

Address Inputs (A0-A10). The Address Inputs

are used to set the Row Address bits (A0-A10) and

the Column Address bits (A11-A19). They are

latched du r ing any bu s operation by the Row/Col-

umn Address Select input, RC.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outp uts hold the d ata that is to be written to

or read from the memory. They output the data

stored at the selected address during a Bus Read

operation . Du ri ng Bu s Wr it e o perati on s they c arr y

the commands that are sent to the Com mand In-

terface of the internal state machine. The Data In-

puts/Outputs, DQ0-DQ7, are latched during a Bus

Write operation.

Output Enable (G). The Output Enable signal, G,

controls the ou tput bu ffer s during a B us Re ad op -

eration.

Write Enable (W). The Write Enable signal, W,

controls th e B us Wr i te o per ation of the Comma nd

Interface.

Row/Column Address Select (RC). The Row/

Column Address Select input selects whether the

Address Inputs are to be latched into the Row Ad-

dress bits (A0-A10) or the Column Address bits

(A11-A19). The Row Address bits are latched on

the falling edge of RC whereas the Column Ad-

dress bits are latched on its rising edge.

Supply Signal Descriptions

The Supply Signals are the same for both interfac-

es.

VCC Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (read, pro-

gram, erase, etc.) .

The Command Interface is disabled when the VCC

Supply Voltage is less than the Lockout Voltage,

VLKO. This is to prevent Bus Write operations from

accidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time, the operation aborts, and the memory

contents that were being altered will be invalid. Af-

ter VCC becom es valid , the Com man d Inter fa ce is

reset to Read mode.

A 0.1µF capacitor should be connected between

the VCC Supply V oltage pin s and the VSS Ground

pin to decouple the current surges from the power

supply. Both VCC Supply Voltage pins must be

connected to the power supply. The PCB track

widths mu st be suffi cient to carr y the currents re-

quired during program and erase operations.

VPP Optional Supply Voltage. The VPP Optional

Supply Voltage pin is used to select the Fast Pro-

gram (see the Quadruple Byte Program command

description in A/A Mux interface and the Double/

Quadrup le B yte Pro gr am c omm and d es crip tion in

FWH mode) and Fast Erase options of the memo-

ry.

When VPP = VCC, program and erase operations

take place as normal. When VPP = VPPH, Fast Pro-

gram and Erase operations are used. Any other

voltage input to VPP will result in undefined behav-

ior, and should not be used.

VPP should not be set to VPPH for more than

80 hours during the life of the memory.

VSS Ground. VSS is the referen ce for all the v olt-

age measure men ts.

M50FLW080A, M50FLW080B

12/53

Table 5. Memory Identification Input Configuration (LPC mode)

BUS OPERATIONS

The two in terfaces, A/A Mux and FW H/LPC, sup-

port similar operations, but with different bus sig-

nals and timings. The Firmware Hub/Low Pin

Count (FWH/LPC) Interface offers full functional-

ity, while the Address/Address Multiplexed (A/A

Mux) Interface is orientated for erase and program

operations.

See the sections below, The Firmware Hub/Low

Pin Count (FWH/LPC) Bus Operations and Ad-

dress/Address Multiplexed (A/A Mux) Bus Opera-

tions, for details of the bus operations on each

interface.

Firmware Hub/Low Pin Count (FWH/LPC) Bus

Operations

The M50FLW0 80 aut omatical ly ide ntifies the ty pe

of FWH/LPC protocol from the first received nibble

(START nibble) and decodes the data that it re-

ceives afterwards, according to the chosen FWH

or LPC mode. The Firmware Hub/Low Pin Count

(FWH/LPC) Interface consists of four data signals

(FWH0/LAD0-FWH3/LAD3), one control line

(FWH4/LFRAME) and a clock (CLK).

Protection against accidental or malicious data

corruption is achieved using two additional signals

(TBL and WP). And two reset signals (RP and

INIT) are available to put the memory into a known

state.

The data, control and clock signals are designed

to be compa tib le wit h PC I elec tr ical spec ifi catio ns.

The inter face operates with clock s peeds of up to

33MHz.

The following operations can be performed using

the appropr iate bus cycles : Bus Read, Bus Wri te,

Standby, Reset and Block Protection.

Bus Read. Bus Read operations are used to read

from the memory cells, specific registers in the

Command Interface or Firmware Hub/Low Pin

Count Registers. A valid Bus Read operation

starts on the risi ng edge of the Clock si gnal wh en

the Input Communication Frame, FWH4/

LFRAME, is Low, VIL, and the correct Start cycle

is present on FWH0/LAD0-FWH3/LAD3. On sub-

sequent clock cycles the Host will send to the

memory:

■ID Select, Address and other control bits on

FWH0-FWH3 in FWH mode.

■Type+Dir Address and other control bits on

LAD0-LAD3 in LPC mode.

The device responds by outputting Sync data until

the wait states have elapsed, followed by Data0-

Data3 and Data4-Data7.

See Table 6. and T abl e 8., a nd Figure 7. and Fig-

ure 9., for a descripti on of the Fiel d definition s for

each clock cycle of the transfer. See Table 26.,

and Figure 15., for details on the timings of the sig-

nals.

Bus Write. Bus Write operations are used to write

to the Command Interface or Firmware Hub/Low

Pin Count Registers. A valid Bus Write operation

starts on the risi ng edge of the Clo ck si gnal wh en

Input Communication Frame, FWH4/LFRAME, is

Low, VIL, and the c or rect Sta rt cy cle is pr esent on

FWH0/LAD0-FWH3/LAD3. On subsequent Clock

cycles the Host will send to the memory:

■ID Select, Address, other control bits, Data0-

Data3 and Data4- Data 7 on FWH0-FW H3 in

FWH mode.

■Cycle Type + Dir, Address, other control bits,

Data0-Da ta3 and Data 4-Data7 on LAD0-

LAD3.

The device responds by outputting Sync data until

the wait states have elapsed.

See Table 7. and T abl e 9., a nd Figure 8. and Fig-

ure 10., for a description of the Field definitions for

each clock cycle of the transfer. See Table 26.,

and Figure 15., for details on the timings of the sig-

nals.

Bus Abort. The Bus Abort operation can be used

to abort the current bus operation immediately. A

Bus Ab ort occur s when FWH4/LFR AME is driv en

Low, VIL, during the bus operation. The device

puts the Input/Output Communication pins,

FWH0/LAD0-FWH3/LAD3, to high impedance.

Memory Number ID3 ID2 A21 A20

1 (Boot memory) VIL or float VIL or float 11

2VIL or float VIH 10

3VIH VIL or float 01

4VIH VIH 00

13/53

M50FLW080A, M50FLW080B

Note that, during a Bus Write operation, the Com-

mand Interface starts executing the command as

soon as the data is fully received. A Bus Abort dur-

ing the final TAR cycles is not guaranteed to abort

the command. The bus, however, will be released

immediately.

Standby. When FWH4/LFRAME is High, VIH, the

device is put into Standby mode, where FWH0/

LAD0-FW H3 /LA D3 ar e put in to a high- im ped anc e

state and the Supply Current is reduced to the

Standby level, ICC1.

Reset. During the Reset mode, all internal circuits

are switched off, the device is deselected, and the

outputs ar e put to hi gh-impedance . The devi ce is

in the Reset mode when Interface Reset, RP, or

CPU Reset, INIT, is driven Low, VIL. RP or INIT

must be he ld Low, VIL, for tPLPH. The memory re-

verts t o the Read mode up on return from the Re -

set mode, and the Lock Registers return to their

default states regardless of their states before Re-

set. If RP or INIT goes Low, VIL, during a Program

or Erase operation, the operation is aborted and

the affected m emory cell s no longer co ntain valid

data. The device can take up to tPLRH to abort a

Program or Erase operation.

Block Protection. Block Protection can be

forced using the signals Top Block Lock, TBL, and

Write Protect, WP, regardless of the state of the

Lock Regist er s.

Address/Address Multiplexed (A/A Mux) Bus

Operations

The Address/Address Multiplexed (A/A Mux) Inter-

face has a more traditional-style interface. The sig-

nals con si st of a mu lti plexed a ddr es s signals (A0 -

A10), data signals, (DQ0-DQ7) and three control

signals (RC, G, W). An addit ional signal, RP, can

be used to reset the memory.

The Address/Address Multiplexed (A/A Mux) Inter-

face is included for use by Flash Programming

equipment fo r faster factory pro grammin g. Only a

subset of the features available to the Firmware

Hub (FWH)/Low Pin Count (LPC) Interface are

available; these include all the Commands but ex-

clude the Security features and other registers.

The following operations can be performed using

the appropr iate bus cycles : Bus Read, Bus Wri te,

Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux)

Interface is sele cted, all the blocks are unprot ect-

ed. It is not possible to protect any blocks through

this interface.

Bus Read. Bus Read operations are used to read

the contents of the Memory Array, the Electronic

Signature or the Status Register. A valid Bus Read

operation begins by latching the Row Address and

Column Address signals into the memory using

the Address Inputs, A0-A10, and the Row/Column

Address Select RC. Write Enable (W) and Inter-

face Reset (RP) must be High, VIH, and Output

Enable, G , Low, VIL. The Data Inputs /Outputs will

output the value, according to the timing con-

straints specified in Figure 17., and Table 28..

Bus Write. Bus Write operations are used to write

to the Command Interface. A valid Bus Write oper-

ation begins by latching the Row Address and Col-

umn Address signals into the memory using the

Address Inputs, A0-A10, and the Row/Column Ad-

dress Select RC. The data should be set up on the

Data Inputs/Outputs; Output Enable, G, and In te r -

face Reset, RP , m ust be Hig h, V IH; an d W rite En-

able, W, must be Low, VIL. The Data Inputs/

Outputs are latched on the rising edge of Write En-

able, W. See Figure 18., and Table 29., for details

of the timing requirements.

Output Disable. The data outputs are high-im-

pedance when the Output Enable, G, is at VIH.

Reset. During the Reset mode, all internal circuits

are switched off, the device is deselected, and the

outputs ar e put at hi gh-impedance . The devi ce is

in the Reset mode when RP is Lo w , V IL. RP must

be held Low, VIL for tPLPH. If RP goes Low, VIL,

during a Program or Erase operation, the opera-

tion is aborted, an d the affecte d memory cells no

longer contain valid data. The memory can take up

to tPLRH to abort a Program or Erase operation.

M50FLW080A, M50FLW080B

14/53

Table 6. FWH Bus Read Field Definitions

Figure 7. FWH Bus Read Waveforms

Clock

Cycle

Number

Clock

Cycle

Count Field FWH0-

FWH3 Memory

I/O Description

1 1 START 1101b I On the rising edge of CLK with FWH4 Low, the contents of FWH0-

FWH3 indicate the start of a FWH Read cycle.

21IDSELXXXXI

Indicates which FWH Flash Memory is selected. The value on

FWH0-FWH3 is compared to the IDSEL strapping on the FWH

Flash Memory pins to select which FWH Flash Memory is being

addressed.

3-9 7 ADDR XXXX I

A 28-bit address is transferred, with the most significant nibble

first. For the multi-byte read operation, the least significant bits

(MSIZE of them) are treated as Don't Care, and the read operation

is started w ith ea ch of these bits reset to 0. Ad dre ss lines A2 0-2 1

and A23-27 are treated as Don’t Care during a normal memory

array access, with A22=1, but are taken into account for a register

access, with A22=0. (See Table 15.)

10 1 MSIZE XXXX I

This one clock cycle is driven by the host to determine the number

of Bytes that will be transferred. M50FLW080 supports: single

Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer

(0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b).

11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround

cycle.

12 1 TAR 1111b

(float) OThe FWH Fl as h Mem or y tak es c o nt r ol o f F WH0 - FWH 3 du ri n g t hi s

cycle.

13-14 2 WSYNC 0101b O The FWH Flash Memory drives FWH0-FWH3 to 0101b (short

wait-sync) for two clock cycles, indicating that the data is not yet

available. Two wait-states are always included.

15 1 RSYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating

that data will be available during the next clock cycle.

16-17M=2nDATAXXXX O Data transfer is two CLK cycles, starting with the least significant

nibbl e. If mult i-Byt e read oper ation i s enabled , repeat cyc le-16 an d

cycle-17

times, where

n = 2MSIZE

+1 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate

a turnaround cycle.

+1 1TAR

1111b

(float) N/A The FWH Flash Memory floats its outputs, the host takes control

of FWH0-FWH3.

AI08433B

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START IDSEL ADDR MSIZE TAR SYNC DATA TAR

117123M2

15/53

M50FLW080A, M50FLW080B

Table 7. FWH Bus Write Field Definitions

Figure 8. FWH Bus Write Waveforms

Clock

Cycle

Number

Clock

Cycle

Count Field FWH0-

FWH3 Memory

I/O Description

1 1 START 1110b I On the rising edge of CLK with FWH4 Low, the contents of

FWH0-FWH3 indicate the start of a FWH Write Cycle.

21IDSELXXXXI

Indicates which FWH Flash Memory is selected . The value on

FWH0-FWH3 is compared to the IDSEL strapping on the FWH

Flash Memo ry pi ns to sel e ct whi c h FW H Fl as h Memo r y is be in g

addressed.

3-9 7 ADDR XXXX I

A 28-bit address is transferred, with the most significant nibble

first. Address lines A20-21 and A2 3-27 are treated as Don’t

Care du ri ng a n orm al me mor y ar ray acce ss, wit h A2 2=1, but are

taken into account for a register access, with A22=0. (See Table

15.)

10 1 MSIZE XXXX I 0000(Single Byte Transfer) 0001 (Double Byte Transfer) 0010b

(Quadruple Byte Transfer).

11-18 M=2/4/8 DATA XXXX I

Data transfer is two cycles, starting with the least significant

nibble. (The first pair of nibbles is that at the address with A1-

A0 set to 00, the second pair with A1-A0 set to 01, the third

pair with A1-A0 set to 10, and the fourth pair with A1-A0 set

to 11. In Double Byte Program the first pair of nibbles is that at

the address with A0 set to 0, the second pair with A0 set to 1)

+1 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround

cycle.

+1 1TAR

1111b

(float) OThe FWH Flash Memory takes control of FWH0-FWH3 during

this cycle.

+1 1 SYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b,

indicating it has received data or a command.

+1 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b,

indicating a turnaround cycle.

+1 1TAR

1111b

(float) N/A The FWH Flash Memory floats its outputs and the host takes

control of FWH0-FWH3.

AI08434B

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START IDSEL ADDR MSIZE DATA TAR SYNC TAR

1171M212

M50FLW080A, M50FLW080B

16/53

Table 8. LPC Bus Read Field Definitions (1-Byte)

Figure 9. LPC Bus Read Waveforms (1-Byte)

Clock Cy cle

Number

Clock

Cycle

Count Field LAD0-

LAD3 Memory

I/O Description

1 1 START 0000b I On the rising edge of CLK with LFRAME Low, the contents

of LAD0-LAD3 must be 0000b to indicate the start of a

LPC cycle.

CYCTYPE

+ DIR 0100b I Indicates the type of cycle and selects 1-byte reading. Bits

3:2 mu st be 01b. B it 1 i ndic ates t he di recti on of tran sfer: 0b

for read. Bit 0 is Don’t Care.

3-10 8 ADDR XXXX I

A 32-bit address is transferred, with the most significant

nibble first. A23-A31 must be set to 1. A22=1 for memory

acces s, and A2 2=0 for regist er acc ess. Table 5. shows the

appropriate values for A21-A20.

11 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to indicate a

turnaround cycle.

12 1 TAR 1111b

(float) OThe LPC Flash Memory takes control of LAD0-LAD3

during this cycle.

13-14 2 WSYNC 0101b O

The LPC Flash Memory drives LAD0-LAD3 to 0101b

(short wait-sync) for two clock cycles, indicating that the

data is not yet available. Two wait-states are always

included.

15 1 RSYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating that data will be available during the next clock

cycle.

16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with the least

significant nibble.

18 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3 to 1111b to

indicate a turnaround cycle.

19 1 TAR 1111b

(float) N/A The LPC Flash Memory fl oats its outputs, the host takes

control of LAD0-LAD3.

AI04429

CLK

LFRAME

LAD0-LAD3

Number of

clock cycles

START CYCTYPE

+ DIR ADDR TAR SYNC DATA TAR

1182322

17/53

M50FLW080A, M50FLW080B

Table 9. LPC Bus Write Field Definitions (1 Byte)

Figure 10. LPC Bus Write Waveforms (1 Byte)

Table 10. A/A Mux Bus Operations

Clock

Cycle

Number

Clock

Cycle

Count Field LAD0-

LAD3 Memory

I/O Description

1 1 START 0000b I On the risin g ed ge of CL K with LFR AM E Low, the contents

of LAD0-LAD3 must be 0000b to indicate the start of a LPC

cycle.

CYCTY

PE +

DIR 011Xb I Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1

indicates the direction of transfer: 1b for write. Bit 0 is don’t

care (X).

3-10 8 ADDR XXXX I

A 32-bit address is transferred, with the most significant

nibble first. A23-A31 must be set to 1. A22=1 for memory

access, and A22=0 for register access. Tab le 5. sho ws the

appropriate values for A21-A20.

11-12 2 DATA XXXX I Data transfer is two cycles, starting with the least significant

nibble.

13 1 TAR 1111b I The host drives LAD0-LAD3 to 1111b to indicate a

turnaround cycle.

14 1 TAR 1111b

(float) OThe LPC Flash Memory takes control of LAD0-LAD3 during

this cycle.

15 1 SYNC 0000b O The LPC Flash Memory drives LAD0-LAD3 to 0000b,

indicating it has received data or a command.

16 1 TAR 1111b O The LPC Flash Memory drives LAD0-LAD3 to 1111b,

indicating a turnaround cycle.

17 1 TAR 1111b

(float) N/A The LPC Flash Memory floats its outputs and the host takes

control of LAD0-LAD3.

Operation G WRP VPP DQ7-DQ0

Bus Read VIL VIH VIH Don't Care Data Output

Bus Write VIH VIL VIH VCC or VPPH Data Input

Output Dis ab le VIH VIH VIH Don't Care Hi-Z

Reset VIL or VIH VIL or VIH VIL Don't Care Hi-Z

AI04430

CLK

LFRAME

LAD0-LAD3

Number of

clock cycles

START CYCTYPE

+ DIR ADDR DATA TAR SYNC TAR

1182212

M50FLW080A, M50FLW080B

18/53

COMMAND INTERFACE

All Bus Write operations to the device are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An in ternal Pr ogram /Erase Control ler han-

dles all tim ings, and veri fies the cor rect execution

of the Program and Erase commands. The Pro-

gram/Eras e Controlle r provid es a Sta tus Registe r

whose outpu t may be read a t any time to monitor

the progress or the result of the operation.

The Command Interface reverts to the Read mode

when power is first applied, or when exiting from

Reset. Command sequences must be followed ex-

actly. Any invalid combination of commands will be

ignored. See Tabl e 11. for the available Command

Codes.

Table 11. Command Codes

The following commands are the basic commands

used to read from, wr ite to, and configure the de-

vice. The following text descriptions should be

read in conjunction with Table 13..

Read Memory Array Command. The Read

Memory Array command returns the device to its

Read mode, where it behaves like a ROM or

EPROM . One Bus Write cyc le is required to issue

the Read Memory Array command and return the

device to Read mode. Once the command is is-

sued, the device remains in Read mode until an-

other com mand is is sued. Fro m Read m ode, Bus

Read operations access the memory array.

If the Program/Erase Controller is executing a Pro-

gram or Erase operation, the device will not accept

any Read Memory Array commands until the oper-

ation has completed.

For a multibyte read, in the FWH mode, the ad-

dress, that was transmitted with the command, will

be aut omatically aligne d, acco rding to the MS IZE

granularity. For example, if MSIZE=7, regardless

of any values that are provided for A6-A0, the first

output will be from the location for which A6-A0 are

all ‘0’s.

Read Status Register Command. The Read

Sta tus Register command is used to read the Sta-

tus Register. One Bus Write cycle is required to is-

sue the Read Status Register command. Once the

command is issued, subsequent Bus Read opera-

tions read the Status Register until another com-

mand is issued. See the section on the Status

Read Electronic Signatur e Command. The

Read Electronic Signature command is used to

read the Manufacturer Code and the Device Code.

One Bus Write cycle is required to issue the Read

Electronic Signature command. Once the com-

mand is issued, the Manufacturer Code and De-

vice Code can be read using conventional Bus

Read operations, and the addresses shown in Ta-

ble 12..

Table 12. Electronic Signature Codes

Note: 1. A22 should be ‘1’, and the ID lines and upper ad dress bits

should be set according to the rules illustrated in Table 5. ,

Table 6. and Table 8..

The device remains in this mode until another

command is issued. That is, subsequent Bus

Read operations continue to read the Manufactur-

er Code, or the Device Code, and not the Memory

Array.

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time.

The Program command works by changing appro-

priate bits from ‘1’ to ‘0’. (It cannot change a bit

from ‘0’ back to ‘1’. Attempting to do so will not

modify the value of the bit. Only the Erase com-

mand can set bits back to ‘1’. and does so for all of

the bits in the block.)

Two Bus Write operations are required to issue the

Program command. The second Bus Write cycle

latches th e address an d data, and star ts the Pro-

gram/Erase Controller.

Hexa-

decimal Command

10h Alternative Program Setup, Double/

Quadruple Byte Program Setup, Chip

Erase Confirm

20h Block Erase Setup

32h Sector Erase Setup

40h Program, Double/Quadruple Byte

Program Setup

50h Clear Status Register

70h Read Status Register

80h Chip Erase Setup

90h Read Electronic Signature

B0h Program/Erase Suspend

D0h Program/Erase Resume, Block Erase

Confirm, Sector Erase Confirm

FFh Read Memory Array

Code Address1Data

Manufacturer Code ...00000h 20h

Device Co de M50FLW080A

M50FLW080B ...00001h 80h

81h

19/53

M50FLW080A, M50FLW080B

Once the command is issued, subsequent Bus

Read operations read the value in the Status Reg-

ister. (See the section on the Status Register for

details on the definitions of the Status Register

bits.)

If the address falls in a protected block, the Pro-

gram operati on will abort, th e data in the mem ory

array will not be changed, and the Status Register

will indicate the error.

During the Program operation, the memory will

only accept the Read Status Register command

and the Program/Erase Suspend command. All

other commands are ignored.

See Fi gure 22. , for a suggested flowchart on using

the Program command. Typical Program times are

given in Table 18..

Quadruple Byte Program Command (A/A Mux

Interface). The Quadruple Byte Program Com-

mand is used to program four adjacent Bytes in

the memory array at a time. The four Bytes must

differ only for addresses A0 and A1. Programming

should not be attempted when VPP is not at VPPH.

Five Bus Write operations are required to issue the

command. The second, third and fourth Bus Write

cycles latch the respec tive address es and da ta of

the first, second and third Bytes in the Program/

Erase Controller. The fifth Bus Write cycle latches

the address and data of the fourth Byte and starts

the Program/Erase Controller. Once the command

is issued, subsequent Bus Read operations read

the value in th e Status Regi ster. (Se e the sec tion

on the Status Register for details on the definitions

of the Status Register bits.)

During the Quadruple Byte Program operation, the

memory will only accept the Read Status Register

and Program/Erase Suspend commands. All other

commands are ignored.

Note that the Quad ruple Byte Progra m command

cannot change a bit set to ‘0’ back to ‘1’ and at-

temptin g to do so wi ll not modify i ts va lue. O ne of

the erase commands must be used to set all of the

bits in the block to ‘1’.

See Fi gure 24. , for a suggested flowchart on using

the Quadruple Byte Program command. Typical

Qua druple By te Program times are given in Table

18..

Double/Quadruple Byte Program Command

(FWH Mode). The Double/Quadruple Byte Pro-

gram Comma nd can be used to pro gram two /four

adjacent Bytes to the memory array at a time. The

two Bytes must differ only for address A0; the four

Bytes must differ only for addresses A0 and A1.

Two Bus Write operations are required to issue the

command. The second Bus Write cycle latches the

start address and two/four data Bytes and starts

the Program/Erase Controller. Once the command

is issued, subsequent Bus Read operations read

the conte nts o f th e Sta tus R egi ste r. (Se e the s ec -

tion on the S tatus Regist er for details on the defi-

nitions of the Status Register bits.)

During the Double/Quadruple Byte Program oper-

ation the memory will only accept the Read Status

All other commands are ignored.

Note that the Double/Quadruple Byte Program

command cannot change a bit set to ‘0’ back to ‘1’

and attempting to do so will not modify its value.

One of t he erase c ommands must be u sed to s et

all of the bits in the block to ‘1’.

See Fi gure 23. , for a suggested flowchart on using

the Double/Quadruple Byte Program command.

Typical Double/Quadruple Byte Program times

are given in Table 18..

Chip Erase Command. The Chip Erase Com-

mand erases the entire memory array, setting all

of the bits to ‘1’. All previous data in the memory

array are lost. This command, though, is only

available under the A/A Mux interface.

Two Bus Write operations are required to issue the

command, and to start the Program/Erase Con-

troller. O nce the c ommand is i ssued, subs equent

Bus Read operations read the contents of the Sta-

tus Registe r. (See the sec tion on the St atus Reg-

ister for details on the definitions of the Status

Erasin g should not be attempted when VPP is not

at VPPH, otherwise the result is uncertain.

During the Chip E rase o peration , the memor y will

only accept the Read Status Register command.

All other commands are ignored.

See Fi gure 26. , for a suggested flowchart on using

the Chip Erase command. Typical Chip Erase

times are given in Table 18..

Block Erase Command. The Block Erase com-

mand is used to erase a block, setting all of the bits

to ‘1’. All previous data in the block are lost.

Two Bus Write operations are required to issue the

command. The second Bus Write cycle latches the

block address and starts the Program/Erase Con-

troller. O nce the c ommand is i ssued, subs equent

Bus Read operations read the contents of the Sta-

tus Registe r. (See the sec tion on the St atus Reg-

ister for details on the definitions of the Status

If the block, or if at least one sector of the block (for

the block s that a re split i nto sect ors), is pr otected

(FWH/LPC only) then the Block Erase operation

will abort, the data in the block will not be changed,

and the Status Register will indicate the error.

During the Bl ock Er ase o per at ion the memory wil l

only accept the Read Status Register and Pro-

gram/Erase Suspend commands. All other com-

mands are igno re d.

M50FLW080A, M50FLW080B

20/53

See Fi gure 27. , for a suggested flowchart on using

the Block Erase command. Typical Block Erase

times are given in Table 18..

Sector Erase Command. The Sector Erase

command is used to erase a Uniform 4-KByte Sec-

tor, setting all of the bits to ‘1’. All previous data in

the sector are lost.

Two Bus Write operations are required to issue the

command. The second Bus Write cycle latches the

Sector address and starts the Program/Erase

Controller. Once the command is issued, subse-

quent Bus Read operations read the contents of

the Status Register. (See the section on the Status

If the Sector is protected (FWH/LPC only), the

Sector Erase operation will abort, the data in the

Sector will not be c han ged , an d the Sta tus Regi s -

ter will indicate the error.

During the Sector Erase operation the memory will

only accept the Read Status Register and Pro-

gram/Erase Suspend commands. All other com-

mands are igno re d.

See Fi gure 27. , for a suggested flowchart on using

the Sector Erase Command. Typical Sector Erase

times are given in Table 18..

Clear Status Register Command. The Clear

Status Register command is used to reset Statu s

Bus Wr ite is requir ed to issue th e comm and. On ce

the command is issued, the device returns to its

previou s mode, su bsequ ent Bus Rea d operat ions

co ntinue to ou tput t he data fr om the same area , as

before.

Once set, these Status Register bits remain set.

They do

not

automatically return to ‘0’, for exam-

pl e, whe n a ne w pr ogra m or er as e comma nd i s is-

sued. If an error has occurred, it is essential that

any error bits in the Status Register are cleared, by

issuing the Clear Status Register command, be-

fore attempting a new program or erase com-

mand.

Program/Era se Suspend Command. The Pro-

gram/Erase Suspend command is used to p ause

the Program/Erase Controller during a program or

Sector/Block Erase operation. One Bus Write cy-

cle is required to issue the command.

Once the c ommand has be en issued, it is nec es-

sary to poll the Program/Erase Controller Status

bit until the Program/Erase Controller has paused.

No other commands are accepted until the Pro-

gram/Eras e Controller has pa used. After the Pro-

gram/Erase Controller has paused, the device

continues to output the contents of the Status Reg-

ister until another command is issued.

During the polling period, between issuing the Pro-

gram/Erase Suspend command and the Program/

Erase Cont roller pausin g, it is poss ible for the op -

eration to complete. Once the Program/Erase

Controller Status bit indicates that the Program/

Erase Contro ller is no longer active, the Program

Suspend Status bit or the Erase Suspend Status

bit can be used to determine if the operation has

completed or is suspended.

During Program/Erase Suspend, the Read Memo-

ry Array, Read Status Register, Read Electronic

Signature and Program/Erase Resume com-

mands will be accepted by the Command Inter-

face. Additi on all y, if the su spe nded operat ion was

Sector Erase or Block Erase then the program

command will also be accepted. However, it

should be noted that only the Sectors/Blocks not

being erased may be read or programmed correct-

ly.

See Figure 25., and Figure 28., for suggested

flowcharts on using the Program/Erase Suspend

command. Typical times and delay durations are

given in Table 18..

Program/Erase Resume Command. The Pro-

gram/Erase Resume command can be used to re-

start the Program/Erase Controller after a

Program/Erase Suspend has paused it. One Bus

Write cycle is required to issue the command.

Once the command is issued, subsequent Bus

Read operations read the contents of the Status

21/53

M50FLW080A, M50FLW080B

Table 13. Commands

Note: 1. For all commands: the first cycle is a Write. For the first three commands (Read Memory, Read Status Register, Read Electronic

Signature), the se cond and next cyc l es are READ. For t he remaining commands, the second and next cycles are WRITE.

BA = Any address in the Block, SA = Any address in the Sector. X = Don’t Care, except that A22=1 (for FWH or LPC mode), and

A21 and A20 ar e set accordin g to the rules shown in Table 5. (for LPC mode)

2. After a Read Memory Array command, re ad the memory as normal until another command is issued.

3. After a Read Stat us Register command, read the St atus Register as normal until another co mmand is issued.

4. After the eras e and program commands read the St atus Register until the command completes and another co mmand is issued.

5. After the Clear Status Register command bits SR1, SR3, SR4 and SR5 in the Status Register are reset to ‘0’.

6. While an operation is being Program/Erase Suspended, the Read Memory Array, Read Status Register, Program (during Erase

Suspend) and Program/Erase Resume commands can be issued.

7. The Program/Erase Resume command caus es the Prog ram/Erase suspended opera tion to resu me. Read the Sta tus Register until

the Program/ Eras e Controller completes and the memory returns to Read Mode.

8. Do not use Invalid or Reserved commands.

9. Multiple Byte Program PA= start address, A0 (Double Byte Program) A0 and A1 (Quadruple Byte Program) are Don`t Care. PD is

two or four Bytes depending on Msize code.

10. “1+” indicates that there is one write cycle, f ollowed by any number of read cycles.

11. Configuration regist ers a re a cce ssed dir ectly wit ho ut us ing any spec ific command code. A single Bu s Writ e or Bus Read Op erat ion

is all that is needed.

12. Addresses A1, A2, A3 and A4 must be consecutive addresses, differing only in address bits A0 and A1.

Command

Cycle

Bus Operations(1)

1st 2nd 3rd 4th 5th

Addr Data Addr Data Addr Data Addr Data Addr Data

Read Memory

Array(2,10,11) 1+ X FFh Read

Addr Read

Data (Read

Addr2) (Read

Data2) (Read

Addr3) (Read

Data3) (Read

Addr4) (Read

Data4)

Read Status

Reg (X) (Status

Reg) (X) (Status

Reg)

Read Electronic

Signature(10) 1+ X 90h or

98h Sig

Addr Signat

ure (Sig

Addr) (Signat

ure) (Sig

Addr) (Signat

ure) (Sig

Addr) (Signat

ure)

Program / Multiple

Byte program

(FWH)(4,9,11) 2X

40h or

10h Prog

Addr Prog

Data

Quadruple Byte

Program

(A/A Mux)(4,12) 5X 30hA1

Prog

Data1 A2 Prog

Data2 A3 Prog

Data3 A4 Prog

Data4

Chip Erase (4) 2X 80h X 10h

Block Erase(4) 2 X 20h BA D0h

Sector Erase(4) 2 X 32h SA D0h

Clear Status

Program/Erase

suspend(6) 1X B0h

Program/Erase

resume(7) 1XD0h

Invalid reserved(8)

1X 00h

1X 01h

1X 60h

1X 2Fh

1XC0h

M50FLW080A, M50FLW080B

22/53

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

The bits in the Status Registe r convey specifi c in-

formation about the progress of the operation.

To read the Status Register, the Read Status Reg-

ister command can be issued. The Status Register

is automatically read after Program, Erase and

Program/Erase Resume commands are issued.

The Status Register can be read from any ad-

dress.

The text descriptions, below, should be read in

co njuncti on wit h Tabl e 14., w her e the m eani ngs of

the Status Register bits are summarized.

Program/Erase Controller Status (Bit SR7).

T his bit indicates whether the Program/Erase Con-

troller is active or inactive. When the Program/

Erase Controller Status bit is ‘0’, the Program/

Erase Controller is active; when the bit is ‘1’, the

Program/Erase Controller is inactive.

The Pro gram/Eras e Controll er Status is ‘0’ imme -

diately afte r a Prog ram/Er ase Suspe nd comma nd

is issued, until the Program/Erase Controller paus-

es. After the Program/Erase Controller pauses,

the bit is ‘1’.

The end of a Program and Erase operation can be

found by polling the Program/Erase Controller

Status bit c an be polled. The other bi ts in the Sta -

tus Register should not be tested until the Pro-

gram/Erase Controller has completed the

operation (an d the Progra m/Erase Contr oller Sta-

tus bit is ‘1’).

After the Program/Erase Controller has completed

its operation, the Erase Status, Program Status,

VPP Status and Block/Sector Protection Status

bits should be tested for errors.

Erase Suspend Status (Bit SR6). This bit indi-

cates that an Eras e operatio n has bee n su spend -

ed, and that it is waiting to be resumed. The Erase

Suspend Status should only be considered valid

when the Program/Erase Controller Status bit is ‘1’

(Program/Erase Controller inactive). After a Pro-

gram/Erase Suspend command is issued, the

memory may still complete the operation rather

than entering the Suspend mode.

When the Erase Suspend Status bit is ‘0’, the Pro-

gram/Erase Controller is active or has completed

its operation. When the bit is ‘1’, a Program/Erase

Suspend command has been issued and the

memory is waiting for a Program/Erase Resume

command.

When a Program/Erase Resume command is is-

sued, the Erase Suspend Status bit returns to ‘0’.

Erase Status (Bit SR5). This bit indicates if a

problem has occurred during the erasing of a Sec-

tor or Bloc k. The Erase Status bit sh ould be read

once the Program/Erase Controller Status bit is ‘1’

(Program/Erase Controller inactive).

When the Eras e Status bit is ‘0’, the me mory has

successfully verified that the Sector/Block has

been erase d correctly. Wh en the Erase St atus bit

is ‘1’, the Program/Erase Controller has applied

the maximum number of pulses to the Sector/

Block and still failed to verify that the Sector/Block

has been erased correctly.

Once the Erase Stat us bit is s et to ‘1’, it c an only

be reset to ‘0’ by a Clear Status Register com-

mand, or by a hardware reset. If it is set to ‘1’, it

should be reset before a new Program or Erase

comma nd is is sued, o the rwise the new co mma nd

will appear to have failed, too.

Program Status (Bit SR4). T his bit indi cates if a

problem has occurred during the programming of

a byte. The Program Status bit should be read

once the Program/Erase Controller Status bit is ‘1’

(Program/Erase Controller inactive).

When the Program Status bit is ‘0’, the memory

has successfully verified that the byte has been

programmed correct ly. When th e Program Status

bit is ‘1’, the Program/Erase Controller has applied

the maximum number of pulses to the byte and still

failed to verify that the byte has been programmed

correctly.

Once the Program Status bit is set to ‘1’, it can only

be reset to ‘0’ by a Clear Status Register com-

mand, or by a hardware reset. If it is set to ‘1’, it

should be reset before a new Program or Erase

comma nd is is sued, o the rwise the new co mma nd

will appear to have failed, too.

VPP Status (Bit SR3). This bit indicates whether

an inva lid voltage wa s detect ed on the VPP pin at

the beginning of a Program or Erase operation.

The VPP pin is only sampled at the beginning of

the operation. Indeterminate results can occur if

VPP becomes invalid during a Program or Erase

operation.

Once the VPP Status bit set to ‘1’, it can only be re-

set to ‘0’ b y a C lear Stat us Regi ster comma nd, or

by a har dware reset. If it is set to ‘1’, it shou ld be

reset before a new Program or Erase command is

issued, otherwise the new command will appear to

have failed, too.

Program Suspend Status (Bit SR2). This bit in-

dicates that a Program operation has been sus-

pended, and that it is waiting to be resum ed. The

Program Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is ‘1’ (Program/Erase Controller inactive).

After a Program/Erase Suspend command is is-

sued, the memory may still complete the operation

instead of entering the Suspend mode.

23/53

M50FLW080A, M50FLW080B

When the Program Suspend Status bit is ‘0’, the

Program/Erase Controller is active, or has com-

pleted its operation. When the bit is ‘1’, a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

su me command.

When a Program/Erase Resume command is is-

sued, the Program Suspend Status bit returns to

‘0’.

Block/Sector Protection Status (Bit SR1). The

Block/S ector Protection Status bit can be used to

identify if the Program or Erase operation has tried

to modify the contents of a protected block or sec-

tor. When the Block/Sector Protection Status bit is

reset to ‘ 0’ , n o Pr ogra m or Era se o perati on s hav e

been attempted on protected blocks or sectors

since the last Clear Status Register command or

hardware reset. When the Block/Sector Protection

Status bit is ‘1’, a Program or Erase operation has

been attempted on a protected block or sector.

Once it is set to ‘1’, the Block/Sector Protection

Status bit can only be reset to ‘0’ by a Clear Status

set to ‘1’, it should be reset before a new Program

or Erase command is issued, otherwise the new

command will appear to have failed, too.

Using the A/A Mux Interface, the Block/Sector Pro-

tection Status bit is always ‘0’.

Reserved (Bit SR0). Bit 0 of the Status Register

is reserved. Its value should be masked.

Table 14. Status Register Bits

Note: 1. For Program operations duri ng Erase Suspend, the SR6 bit is ‘1’ , ot herwise the SR6 bit is ‘0’.

Operation SR7 SR6 SR5 SR4 SR3 SR2 SR1

Program active ‘0’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Program suspended ‘1 X(1) ‘0’ ‘0’ ‘0’ ‘1’ ‘0’

Program completed successfully ‘1’ X(1) ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Program failure due to VPP Error ‘1’ X(1) ‘0’ ‘1’ ‘1’ ‘0’ ‘0’

Program failure due to Block/Sector Protection

(FWH/LPC Interface only) ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘1’

Program failure due to cell failure ‘1’ X(1) ‘0’ ‘1’ ‘0’ ‘0’ ‘0’

Erase active ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’

Erase failure due to VPP Error ‘1’ ‘0’ ‘1’ ‘0’ ‘1’ ‘0’ ‘0’

Erase failure due to Block/Sector Protection

(FWH/LPC Interface only) ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘1’

Erase failure due to failed cell(s) in block or sector ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’

M50FLW080A, M50FLW080B

24/53

FIRMWARE HUB/LOW PIN COUNT (FWH/LP C) INTERFACE CONFIGURATION

REGISTERS

When the Fir mware Hub Inter face/Low Pin Co unt

is selected, several additional registers can be ac-

cessed. These registers control the protection sta-

tus of the Blocks/Sectors, read the General

Purpose Input pins and identify the memory using

the manufacturer code. See Table 15. for the

memory map of the Configuration Registers. The

Configuration registers are accessed directly with-

out using any specific command code. A single

Bus Write or Bus Read Operation, with the appro-

priate address (including A22=0), is all that is

needed.

Lock Registers

The Lock Registers control the protection status of

the Blocks/S ectors. Each Blo ck/Sector has its o wn

Lock Regis ter. T hree bi ts wit hin each Lock Regi s -

ter control the protection of each Block/Sector: the

Write Lock Bit, the Read Lock Bit and the Lock

Down Bit.

The Lock Registers can be read and written. Care

should be taken, though, when writing. Once the

Lock Down Bit is set, ‘1’, further modifications to

the Lock Register cannot be made until it is

cleared again by a reset or power-up.

See Table 16. for details on the bit definitions of

the Lock Registers.

Write Lock. The Write Lock Bit determines

whether the contents of the Block/Sector can be

modified (using the Program or Erase Command).

When the Wri te Lo ck Bit is s et, ‘ 1’ , the B lo ck/S ec -

tor is write protected – any operations that attempt

to change the data in the Block/Sector will fail, and

the Status Regi ste r will report the error. Wh en the

Write Loc k Bit is reset, ‘0 ’, the Block/Se ctor is not

write protec ted by the Lock Reg ister, and may be

modified, unless it is write protected by some other

means.

If the Top Block Lock signal, TBL, is Low, VIL, then

the Top Block (Block 15) is write protected, and

cannot be modified. Similarly, if the Write Protect

signal, WP, is Low, VIL, then the Main Blocks

(Blocks 0 to 14) are write protected, and cannot be

modified. For details, see APPENDIX A. and Table

16..

After power-up, or reset, the Write Lock Bit is al-

ways set to ‘1’ (write-protected).

Read Lock. The Read Lock bit determines

whether the contents of the Block/Sector can be

read (in Read mode). When the R ead Lock Bit is

set, ‘1’, the Block/Sector is read protected – any

operation that attempts to read the contents of the

Block/Sector will read 00h instead. When the

Read Lock B it is rese t, ‘0’, rea d ope ra tio ns are al -

lowed in th e Bloc k/Se ctor, an d retu rn the value of

the data tha t had b een progra mmed in t he Block/

Sector.

After power-up, or reset, the Read Lock Bit is al-

ways reset to ‘0’ (not read-protected).

Lock Down. The Lock Down Bit provides a

mechanis m for pr otecti ng s oftwa re data fr om sim-

ple ha cking and ma licious a ttack. When the Lock

Down Bit is set, ‘1’, further modification to the

Write Lock, Read Lock and Lock Down Bits cannot

be performed. A reset, or power-up, is required be-

fore changes to these bits can be made. When the

Lock Down Bit is reset, ‘0’, the Write Lock, Read

Lock and Lock Down Bits can be changed.

Table 15. Configuration Register Map

Note: In LPC mo de, a mos t s ignific ant n ibble , F, must b e added t o the memor y addr es s. Fo r all regi ster s, A 22=0, and t he remai ning addres s

bits should be set according to the rules shown in the ADDR field of Table 6. to Table 9. .

Mnemonic Register Name Memory

Address Default

Value Access

Lock Registers (For details, see APPENDIX A.)

GPI_REG Firmware Hub/Low Pin Count (FWH/LPC) General

Purpose Input Register FBC0100h N/A R

MANU _R E G Manu fac turer Code Regis te r FBC00 00 h 20h R

25/53

M50FLW080A, M50FLW080B

Table 16. Lock Register Bit Definitions

Note: 1. Applies to the registers t hat are defined in Table 34. and Table 35. .

Table 17. General Purpose Inputs Register Definition

Note: 1. Applies to the General Purpo se Inputs Register (GPI- RE G).

Firmware Hub/Low Pin Count (FWH/LPC)

General Purpose Input Register

The FWH/LPC General Purpose Input Register

holds the state of the General Purpose Input pins,

GPI0-GPI4. When this register is read, the state of

these pins is returned. This register is read-only.

Writing to it has no effect.

The signals on the FWH/LPC Interface General

Purpose Input pins should remain constant

throughout the whole Bus Read cycle.

Manufacturer Code Register

Reading the Manufacturer Code Register returns

the value 20h, which is the Manufacturer Code for

STMicroelectronics. This register is read-only.

Writing to it has no effect.

Bit Bit Name Value Function (1)

7-3 Reserved

2 Read-Lock ‘1’ Bus Read operations in this Block or Sector always return 00h.

‘0’ Bus read operations in this Block or Sector return the Memory Array contents.

(Default value).

1 Lock-Down ‘1’ Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a

‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset

to ‘0’ following a Reset (using RP or INIT) or after power-up.

‘0’ Read-Lock and Write-Lock can be changed by writing new values to them. (Default

value).

0Write-Lock ‘1’ Pro gr a m an d Er a se op erat i o ns in th i s Bl o ck or Se ct o r w il l se t an er ro r in th e Stat u s

‘0’ Program and Erase operations in this Block or Sector are executed and will modify

the Block or Se cto r con ten ts.

Bit Bit Name Value Function (1)

7-5 Reserved

4GPI4 ‘1’ Input Pin GPI4 is at VIH

‘0’ Input Pin GPI4 is at VIL

3GPI3 ‘1’ Input Pin GPI3 is at VIH

‘0’ Input Pin GPI3 is at VIL

2GPI2 ‘1’ Input Pin GPI2 is at VIH

‘0’ Input Pin GPI2 is at VIL

1GPI1 ‘1’ Input Pin GPI1 is at VIH

‘0’ Input Pin GPI1 is at VIL

0GPI0 ‘1’ Input Pin GPI0 is at VIH

‘0’ Input Pin GPI0 is at VIL

M50FLW080A, M50FLW080B

26/53

PROGRAM AND ERASE TIMES

The Program and Erase times are shown in Table

18..

Table 18. Program and Erase Times

Note: 1. TA = 25°C, VCC = 3.3V

2. Sampled only, not 100% tested.

3. Time to progra m two Bytes.

4. Time to program four Bytes.

5. Time obtained ex ecuting the Quadrupl e Byte Progra m command.

Param ete r Interfa ce Te st Co nd itio n Min Typ(1) Max Unit

Byte Progr am 10 200 µs

Double By te Pro gr am FWH VPP = 12V ± 5% 10(3) 200 µs

Quadruple Byte Program A/A Multiplexed

FWH VPP = 12V ± 5% 10(4) 200 µs

Block Program VPP = 12V ± 5% 0.1(5) 5s

VPP = VCC 0.4 5

Sector Erase (4 KBytes)(2) VPP = 12V ± 5% 0.4 4 s

VPP = VCC 0.5 5

Block Erase (64 KBytes) VPP = 12V ± 5% 0.75 8 s

VPP = VCC 110

Chip Erase A/A Multip lex ed VPP = 12V ± 5% 10 s

Program/Erase Suspend to Program pause(2) 5µs

Program/Erase Suspend to Block Erase/

Sector Erase pau se(2) 30 µs

27/53

M50FLW080A, M50FLW080B

MAXIMUM RATING

Stressing the dev ice above the ratin g lis ted in the

Absolute Maximum Ratin gs table ma y cause pe r-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other cond itions above those in dicated in the

Operating sections of this specification is not im-

plie d. Exposu re to Abso lute Max imum Rat ing con-

ditions for extended periods may affect device

reliability. Refer also to the STMicroelectronics

SURE Program and other relevant quality docu-

ments.

Table 19. Absolute Ma ximum Ratings

Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and

the European direct ive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU

2. Minimum voltage may undershoot to –2V for less than 20ns during transitions. Maximum voltage may overshoot to VCC + 2V for

less than 20ns during transitions.

3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Symbol Parameter Min. Max. Unit

TSTG Storage Temp era tur e –65 1 50 ° C

TLEAD Lead Temperature during Soldering See note 1°C

VIO Input or Output range 2–0.50 VCC + 0.6 V

VCC Supply Voltage –0.50 4 V

VPP Program Voltage –0.6 13 V

VESD Elect ros tatic Dis ch arg e Voltage (Human Body mode l) 3–2000 2000 V

M50FLW080A, M50FLW080B

28/53

DC AND AC PARA METERS

This section summarizes the operating measure-

ment condi tions, an d the DC and AC characteri s-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 20., Table 21.

and Table 22.. Designers should check that the

operating conditions in their circuit match the oper-

ating conditions when relying on the quoted pa-

rameters.

Table 20. Operating Conditions

Table 21. FWH/LPC Interface AC Measurement Conditions

Table 22. A/A Mux Interface AC Measurement Conditions

Figure 11. FWH/LPC Interface AC Measurement I/O Waveforms

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 3.0 3.6 V

TAAmbient Operating Temperature –20 85 °C

Parameter Value Unit

Load Capacitance (CL)10 pF

Input Rise and Fall Times ≤ 1.4 ns

Input Pulse Voltages 0.2 VCC and 0.6 VCC V

Input and Output Timing Ref. Voltages 0.4 VCC V

Parameter Value Unit

Load Capacitance (CL)30 pF

Input Rise and Fall Times ≤ 10 ns

Input Pulse Voltages 0 to 3 V

Input and Output Timing Ref. Voltages 1.5 V

AI03404

0.6 VCC

0.2 VCC

0.4 VCC

IO > ILO

IO < ILO IO < ILO

Input and Output AC Testing Waveform

Output AC Tri-state Testing Waveform

29/53

M50FLW080A, M50FLW080B

Figure 12. A/A Mux Interface AC Measurement I/O Waveform

Figure 13. AC Me asurement Load Circuit

Table 23. Impedance

Note: 1. Sampled only, not 100% test ed.

2. Se e PCI Specifi ca t ion.

3. TA = 25°C, f = 1MHz.

Symb ol Parame te r Test Co nd itio n Min Max Uni t

CIN(1) Input Capacitance VIN = 0V 13 pF

CCLK(1) Clock Capacitanc e VIN = 0V 312pF

LPIN(2) Recommended Pin

Inductance 20 nH

AI01417

1.5V

AI08430

VDD

CL includes JIG capacitance

16.7kΩ

DEVICE

UNDER

TEST

0.1µF

VDD

0.1µF

VPP

16.7kΩ

M50FLW080A, M50FLW080B

30/53

Table 24. DC Characteristics

Note: 1. Sampled only, not 100% test ed.

2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs.

3. ID0 and ID1 are RFU in LPC mode.

Symbol Parameter Interface Test Condition Min Max Unit

VIH Input High Voltage FWH 0.5 VCC VCC + 0.5 V

A/A Mux 0.7 VCC VCC + 0.3 V

VIL Input Low Voltage FWH/LPC –0.5 0.3 VCC V

A/A Mux -0.5 0.8 V

VIH(INIT)INIT Input High Voltage FWH/LPC 1.1 VCC + 0.5 V

VIL(INIT)INIT Input Low Voltage FWH/LPC –0.5 0.2 VCC V

ILI(2) Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA

ILI2 IC, IDx Input Leakage

Current IC, ID0, ID1, ID2, ID3(3) = VCC 200 µA

RIL IC, IDx Input Pull Low

Resistor 20 100 kΩ

VOH Output High Voltage FWH/LPC IOH = –500µA0.9 VCC V

A/A Mux IOH = –100µAVCC – 0.4 V

VOL Output Low Voltage FWH/LPC IOL = 1.5mA 0.1 VCC V

A/A Mux IOL = 1.8mA 0.45 V

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA

VPP1 VPP Voltage 33.6V

VPPH VPP Voltage

(Fast Erase) 11.4 12.6 V

VLKO(1) VCC Lockout Voltage 1.8 2.3 V

ICC1 Supply Current (Standby) FWH/LPC

FWH4/LFRAME = 0.9VCC

VPP = VCC

All other inputs 0.9VCC to 0.1VCC

VCC = 3.6V, f(CLK) = 33MHz

100 µA

ICC2 Supply Current (Standby) FWH/LPC

FWH4/LFRAME = 0.1 VCC, VPP =

VCC

All other inputs 0.9 VCC to 0.1 VCC

VCC = 3.6V, f(CLK) = 33MHz

10 mA

ICC3 Supply Current

(Any internal operation

active) FWH/LPC VCC = VCC max, VPP = VCC

f(CLK) = 33MHz

IOUT = 0mA 60 mA

ICC4 Supply Current (Read) A/A Mux G = VIH, f = 6MHz 20 mA

ICC5(1) Supply Current

(Program/Erase) A/A Mu x Program /E ra se Co ntr olle r Act ive 20 mA

IPP VPP Supply Curren t

(Read/Standby) VPP > VCC 400 µA

IPP1(1) VPP Supply Cur ren t

(Program/Erase active) VPP = VCC 40 mA

VPP = 12V ± 5% 15 mA

31/53

M50FLW080A, M50FLW080B

Figure 14. FWH/LPC Interface Clock Waveform

Table 25. FWH/LPC Interface Clock Characteristics

Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed

by design rather than tested. Refer to PCI Specification.

Symbol Param et er Test Co nd ition Va lue Unit

tCYC CLK Cycle Time(1) Min 30 ns

tHIGH CLK Hig h Time Min 11 ns

tLOW CLK Low Time Min 11 ns

CLK Slew Ra te peak to peak Min 1 V/ns

Max 4 V/ns

AI03403

tHIGH tLOW

0.6 VCC

tCYC

0.5 VCC

0.4 VCC

0.3 VCC

0.2 VCC

0.4 VCC, p-to-p

(minimum)

M50FLW080A, M50FLW080B

32/53

Figure 15. FWH/LPC Interface AC Signal Timing Waveforms

Table 26. FWH/LPC Interface AC Signal Timing Characteristics

Note: 1. The timing measur ements for Activ e/Float trans itions are de fined when the current through the pin equals t he leak age current spec-

ification.

2. Applies to all inputs except CLK and FWH4.

Symbol PCI

Symbol Parameter Value Unit

tCHQV tval CLK to Data Out Min 2 ns

Max 11 ns

tCHQX(1) ton CLK to Active

(Float to Active Delay) Min 2 ns

tCHQZ toff CLK to Inactive

(Active to Float Delay) Max 28 ns

tAVCH

tDVCH tsu Input Set-u p Time(2) Min 7 ns

tCHAX

tCHDX thInput Ho ld Time(2) Min 0 ns

tFLCH Input Set-up time on FWH4 Min 10 ns

tCHFH Input Ho ld tim e on FW H4 Min 5 ns

CLK

FWH0-FWH3/

LAD0-LAD3

VALID

tCHQV tCHQZ

tCHQX

tCHDX

tDVCH

VALID

OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA

AI09700

tCHFH

tFLCH

FWH4

START CYCLE

33/53

M50FLW080A, M50FLW080B

Figure 16. Reset AC Waveforms

Table 27. Reset AC Characteristics

Note: 1. See Chapter 4 of the PCI Spec ification.

Symbol Parameter Test Condition Value Unit

tPLPH RP or INIT Reset Pulse Width Min 100 ns

RP or INIT Slew Rate(1) Rising edge only Min 50 mV/ns

tPHFL RP or INIT High to FWH4 /

LFRAME Low FWH/LPC Interface only Min 30 µs

tPHWL

tPHGL RP High to Wr it e Enab le or Outp ut

Enable Lo w A/A Mux Interface on ly Min 50 µs

RP, INT

Ai09705

W, G, FWH4/LFRAME

tPLPH tPHWL, tPHGL, tPHFL

M50FLW080A, M50FLW080B

34/53

Figure 17. A/A Mux Interface Read AC Waveforms

Table 28. A/A Mux Interface Read AC Characteristics

Note: 1. G may be delayed up to tCHQV – tGLQV after the rising edge of RC without impact on tCHQV.

Symbol Parameter Test Condition Value Unit

tAVAV Read Cycle Time Min 250 ns

tAVCL Row Addre ss Val id to RC Low Min 50 ns

tCLAX RC Low to Row Address Transition Min 50 ns

tAVCH Column Address Valid to RC high Min 50 ns

tCHAX RC High to Column Address Transition Min 50 ns

tCHQV(1) RC High to Output Valid Max 150 ns

tGLQV(1) Output Enable Low to Output Valid Max 50 ns

tPHAV RP High to Row Address Valid Min 1 µs

tGLQX Output Enable Low to Output Transition Min 0 ns

tGHQZ Output Enable High to Output Hi-Z Max 50 ns

tGHQX Output Hold from Output Enable High Min 0 ns

AI03406

tAVAV

tCLAX tCHAX

tGLQX

tGLQV

tGHQX

VALID

A0-A10

DQ0-DQ7

tCHQV

tGHQZ

COLUMN ADDR VALID

tPHAV

ROW ADDR VALID NEXT ADDR VALID

tAVCL tAVCH

35/53

M50FLW080A, M50FLW080B

Figure 18. A/A Mux Interface Write AC Waveforms

Table 29. A/A Mux Interface Write AC Characteristics

Note: 1. Sampled only, not 100% test ed.

2. Ap pl i c a b l e i f VPP is seen as a logic input (VPP < 3.6V) .

Symbol Parameter Test Condition Value Unit

tWLWH Write Enable Low to Write Enable High Min 100 ns

tDVWH Data Valid to Write Enable High Min 50 ns

tWHDX Write Enable High to Data Transition Min 5 ns

tAVCL Row Addre ss Val id to RC Low Min 50 ns

tCLAX RC Low to Row Address Transition Min 50 ns

tAVCH Column Address Valid to RC High Min 50 ns

tCHAX RC High to Column Address Transition Min 50 ns

tWHWL Write Enable High to Write Enable Low Min 100 ns

tCHWH RC High to Write Enable High Min 50 ns

tVPHWH(1) VPP High to Write Enable High Min 100 ns

tWHGL Write Enable High to Output Enable Low Min 30 ns

tWHRL Write Enable High to RB Lo w Min 0 ns

tQVVPL(1,2) Output Valid, RB High to VPP Low Min 0 ns

AI04185

tCLAX

tCHAX

tWHDXtDVWH

VALID SRD

A0-A10

DQ0-DQ7

tCHWH

tAVCL

tAVCH

R2 C2

tWLWH

tWHWL

VPP

tVPHWH tWHGL

tQVVPL

DIN1 DIN2

Write erase or

program setup

Write erase confirm or

valid address and data

Automated erase

or program delay Read Status

another command

M50FLW080A, M50FLW080B

36/53

PACKAGE MECHANICAL

Figure 19. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Outline

Note: Drawing is not to scale.

PLCC-A

E3 E1 E

1 N

0.51 (.020)

1.14 (.045)

D2 D2

37/53

M50FLW080A, M50FLW080B

Table 30. PLCC32 – 32 pin Rectangular Plastic Leaded Chip Carrier, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 3.18 3.56 0.125 0.140

A1 1.53 2.41 0.060 0.095

A2 0.38 – 0.015 –

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

CP 0.10 0.004

D 12.32 12.57 0.485 0.495

D1 11.35 11.51 0.447 0.453

D2 4.78 5.66 0.188 0.223

D3 7.62 – – 0.300 – –

E 14.86 15.11 0.585 0.595

E1 13.89 14.05 0.547 0.553

E2 6.05 6.93 0.238 0.273

E310.16– –0.400– –

e 1.27 – – 0.050 – –

F 0.00 0.13 0.000 0.005

R 0.89 – – 0.035 – –

N32 32

M50FLW080A, M50FLW080B

38/53

Figure 20. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Outline

Note: Drawing is not to scale.

Table 31. TSOP32 – 32 lead Plastic Thin Small Outline, 8x14 mm, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 0.950 1.050 0.0374 0.0413

α05 05

B 0.170 0.270 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D 13.800 14.200 0.5433 0.5591

D1 12.300 12.500 0.4843 0.4921

e 0.500 – – 0.0197 – –

E 7.900 8.100 0.3110 0.3189

L 0.500 0.700 0.0197 0.0276

N32 32

TSOP-a

1 N

N/2

DIE

LA1

39/53

M50FLW080A, M50FLW080B

Figure 21. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline

Note: Drawing is not to scale.

Table 32. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A1.200 0

A1 0.050 0.150 0 0

A2 0.950 1.050 0 0

B 0.170 0.270 0 0

C 0.100 0.210 0 0

CP 0.100 0

D 19.800 20.200 1 1

D1 18.300 18.500 1 1

e0.500––0––

E 9.900 10.100 0 0

L 0.500 0.700 0 0

α05 05

N40 40

TSOP-a

1 N

N/2

DIE

LA1

M50FLW080A, M50FLW080B

40/53

PART NUMBERING

Table 33. Ordering Information Scheme

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

Example: M50FLW080 A K 5 T G

Device Type

M50 = Flash Memory for PC BIOS

Architecture

FL = Firmware Hub/Low Pin Count Interface

Operatin g Voltage

W = VCC = 3.0 to 3.6V

Device Function

080 = 8 Mbit (x8), Uniform Blocks and Sectors

Array Matrix

A = 2 x 16 x 4KByte top sectors + 1 x 16 x 4KByte bottom sectors

B = 1 x 16 x 4KByte top sectors + 2 x 16 x 4KByte bottom sectors

Package

K = PLCC32

NB = TSOP32: 8 x 14mm

N = TSOP40: 10 x 20mm

Device Grade

5 = Temperature range –20 to 85 °C.

Device tested with standard test flow

Option

blank = Standard Pa ck ing

T = Tape and Reel Packing

Plating Technology

blank = Standard Sn Pb plati ng

G = Lead-Free, RoHS compliant, Sb2O3-free and TBBA-free

41/53

M50FLW080A, M50FLW080B

APPENDIX A. BLOCK AND SECTOR ADDRESS TABLE

Table 34. M50FLW080A Block, Sector and Lock

Block

Size

(KByte)

Address

Range

Block

No and

Type

Sector

Size

(KByte)

Sector

No Register

Address

FF000h-

FFFFFh

(Top)

447 FBFF002

FE000h-

FEFFFh 446 FBFE002

FD000h-

FDFFFh 445 FBFD002

FC000h-

FCFFFh 444 FBFC002

FB000h-

FBFFFh 443 FBFB002

FA000h-

FAFFFh 442 FBFA002

F9000h-

F9FFFh 441 FBF9002

F8000h-

F8FFFh 440 FBF8002

F7000h-

F7FFFh 439 FBF7002

F6000h-

F6FFFh 438 FBF6002

F5000h-

F5FFFh 437 FBF5002

F4000h-

F4FFFh 436 FBF4002

F3000h-

F3FFFh 435 FBF3002

F2000h-

F2FFFh 434 FBF2002

F1000h-

F1FFFh 433 FBF1002

F0000h-

F0FFFh 432 FBF0002

EF000h-

EFFFFh

(Main)

431 FBEF002

EE000h-

EEFFFh 430 FBEE002

ED000h-

EDFFFh 429 FBED002

EC000h-

ECFFFh 428 FBEC002

EB000h-

EBFFFh 427 FBEB002

EA000h-

EAFFFh 426 FBEA002

E9000h-

E9FFFh 425 FBE9002

E8000h-

E8FFFh 424 FBE8002

E7000h-

E7FFFh 423 FBE7002

E6000h-

E6FFFh 422 FBE6002

E5000h-

E5FFFh 421 FBE5002

E4000h-

E4FFFh 420 FBE4002

E3000h-

E3FFFh 419 FBE3002

E2000h-

E2FFFh 418 FBE2002

E1000h-

E1FFFh 417 FBE1002

E0000h-

E0FFFh 416 FBE0002

Block

Size

(KByte)

Address

Range

Block

No and

Type

Sector

Size

(KByte)

Sector

No Register

Address

M50FLW080A, M50FLW080B

42/53

Note: In LPC mode, a most significant nibble, F, must be added to

the memory address. For all registers, A22=0, and the re-

maining address bits should be set according to the rules

shown in th e ADDR fie l d of Table 6. to Tab l e 9. .

64 D0000h-

DFFFFh 13

(Main) FBD0002

64 C0000h-

CFFFFh 12

(Main) FBC0002

64 B0000h-

BFFFFh 11

(Main) FBB0002

64 A0000h-

AFFFFh 10

(Main) FBA0002

64 90000h-

9FFFFh 9

(Main) FB90002

64 80000h-

8FFFFh 8

(Main) FB80002

64 70000h-

7FFFFh 7

(Main) FB70002

64 60000h-

6FFFFh 6

(Main) FB60002

64 50000h-

5FFFFh 5

(Main) FB50002

64 40000h-

4FFFFh 4

(Main) FB40002

64 30000h-

3FFFFh 3

(Main) FB30002

64 20000h-

2FFFFh 2

(Main) FB20002

64 10000h-

1FFFFh 1

(Main) FB10002

Block

Size

(KByte)

Address

Range

Block

No and

Type

Sector

Size

(KByte)

Sector

No Register

Address

0F000h-

0FFFFh

(Main)

415 FB0F002

0E000h-

0EFFFh 414 FB0E002

0D000h-

0DFFFh 413 FB0D002

0C000h-

0CFFFh 412 FB0C002

0B000h-

0BFFFh 411 FB0B002

0A000h-

0AFFFh 410 FB0A002

09000h-

09FFFh 4 9 FB09002

08000h-

08FFFh 4 8 FB08002

07000h-

07FFFh 4 7 FB07002

06000h-

06FFFh 4 6 FB06002

05000h-

05FFFh 4 5 FB05002

04000h-

04FFFh 4 4 FB04002

03000h-

03FFFh 4 3 FB03002

02000h-

02FFFh 4 2 FB02002

01000h-

01FFFh 4 1 FB01002

00000h-

00FFFh 4 0 FB00002

Block

Size

(KByte)

Address

Range

Block

No and

Type

Sector

Size

(KByte)

Sector

No Register

Address

43/53

M50FLW080A, M50FLW080B

Table 35. M50FLW080B Block, Sector and Lock

Block

Size

(KByte)

Address

Range

Block

No and

Type

Sector

Size

(KByte)

Sector

No Register

Address

FF000h-

FFFFFh

(Top)

447 FBFF002

FE000h-

FEFFFh 446 FBFE002

FD000h-

FDFFFh 445 FBFD002

FC000h-

FCFFFh 444 FBFC002

FB000h-

FBFFFh 443 FBFB002

FA000h-

FAFFFh 442 FBFA002

F9000h-

F9FFFh 441 FBF9002

F8000h-

F8FFFh 440 FBF8002

F7000h-

F7FFFh 439 FBF7002

F6000h-

F6FFFh 438 FBF6002

F5000h-

F5FFFh 437 FBF5002

F4000h-

F4FFFh 436 FBF4002

F3000h-

F3FFFh 435 FBF3002

F2000h-

F2FFFh 434 FBF2002

F1000h-

F1FFFh 433 FBF1002

F0000h-

F0FFFh 432 FBF0002

64 E0000h-

EFFFFh 14

(Main) FBE0002

64 D0000h-

DFFFFh 13

(Main) FBD0002

64 C0000h-

CFFFFh 12

(Main) FBC0002

64 B0000h-

BFFFFh 11

(Main) FBB0002

64 A0000h-

AFFFFh 10

(Main) FBA0002

64 90000h-

9FFFFh 9

(Main) FB90002

64 80000h-

8FFFFh 8

(Main) FB80002

64 70000h-

7FFFFh 7

(Main) FB70002

64 60000h-

6FFFFh 6

(Main) FB60002

64 50000h-

5FFFFh 5

(Main) FB50002

64 40000h-

4FFFFh 4

(Main) FB40002

64 30000h-

3FFFFh 3

(Main) FB30002

64 20000h-

2FFFFh 2

(Main) FB20002

Block

Size

(KByte)

Address

Range

Block

No and

Type

Sector

Size

(KByte)

Sector

No Register

Address

M50FLW080A, M50FLW080B

44/53

Note: In LPC mode, a most significant nibble, F, must be added to

the memory address. For all registers, A22=0, and the re-

maining address bits should be set according to the rules

shown in th e ADDR fie l d of Table 6. to Tab l e 9. .

1F000h-

1FFFFh

(Main)

431 FB1F002

1E000h-

1EFFFh 430 FB1E002

1D000h-

1DFFFh 429 FB1D002

1C000h-

1CFFFh 428 FB1C002

1B000h-

1BFFFh 427 FB1B002

1A000h-

1AFFFh 426 FB1A002

19000h-

19FFFh 425 FB19002

18000h-

18FFFh 424 FB18002

17000h-

17FFFh 423 FB17002

16000h-

16FFFh 422 FB16002

15000h-

15FFFh 421 FB15002

14000h-

14FFFh 420 FB14002

13000h-

13FFFh 419 FB13002

12000h-

12FFFh 418 FB12002

11000h-

11FFFh 417 FB11002

10000h-

10FFFh 416 FB10002

Block

Size

(KByte)

Address

Range

Block

No and

Type

Sector

Size

(KByte)

Sector

No Register

Address

0F000h-

0FFFFh

(Main)

415 FB0F002

0E000h-

0EFFFh 414 FB0E002

0D000h-

0DFFFh 413 FB0D002

0C000h-

0CFFFh 412 FB0C002

0B000h-

0BFFFh 411 FB0B002

0A000h-

0AFFFh 410 FB0A002

09000h-

09FFFh 4 9 FB09002

08000h-

08FFFh 4 8 FB08002

07000h-

07FFFh 4 7 FB07002

06000h-

06FFFh 4 6 FB06002

05000h-

05FFFh 4 5 FB05002

04000h-

04FFFh 4 4 FB04002

03000h-

03FFFh 4 3 FB03002

02000h-

02FFFh 4 2 FB02002

01000h-

01FFFh 4 1 FB01002

00000h-

00FFFh 4 0 FB00002

Block

Size

(KByte)

Address

Range

Block

No and

Type

Sector

Size

(KByte)

Sector

No Register

Address

45/53

M50FLW080A, M50FLW080B

APPENDIX B. FLOWCHARTS AND PSEUDO CODES

Figure 22. Program Flowchart and Pseudo Code

Note: 1. A Status check of SR1 (Pro te cted Block/Se ctor) , SR3 (VPP invalid) and SR4 (P rogram Error) can be made a ft er each Program op-

eration by following the correct command sequence.

2. If an error is found, the Status Register must be c l eared before further Program/Erase Controller operations .

Write 40h or 10h

AI09092

Start

Write Address

and Data

Read Status

YES

SR7 = 1

YES

SR3 = 0

SR4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Program command:

– Write 40h or 10h

– Write Address and Data

(memory enters read status state after

the Program command)

do:

– Read Status Register

– If SR7=0 and a Program/Erase Suspend

command has been executed

– SR7 is set to 1

– Enter suspend program loop

If SR3 = 1,

– Enter the "VPP invalid" error handler

If SR4 = 1,

– Enter the "Program error" error handler

YES

End

YES

SR1 = 0 Program to Protected

Block/Sector Error (1, 2)

If SR1 = 1,

– Enter the "Program to protected

block/sector" error handler

Suspend

Loop

YES

FWH/LPC

Interface

Only

M50FLW080A, M50FLW080B

46/53

Figure 23. Double/Quadruple Byte Program Flowchart and Pseudo code (FWH Mode Only)

Note: 1. A Status check of SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation by following the correct

command sequence.

2. If an error is found, the Status Register must be cleared before further Program/E rase operati ons.

3. A0 and/or A1 are treated as Don’t Care (A 0 for Double Byte Program and A1-A0 f or Quadruple By te Program).

For Double Byte Program: Starting at the Start Addr ess, the fi rst data Byte is programmed at the even address , and the sec ond at

the odd address.

For Quadrup le By te Pr ogram : Start ing at the Start Ad dres s, t he fir st data By te is prog rammed at the addre ss th at has A1-A0 at 00,

the second at the address that has A1-A0 at 01, the third at the address that has A1-A0 at 10, and the fourth at the address that

has A1-A0 at 11.

AI09093

Read Status

YES

SR7 = 1

YES

SR3 = 0

SR4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Double/Quadruple Byte Program command:

– write 40h or 10h

– write Start Address and 2/4 Data Bytes

(3)

(memory enters read status state after

the Double/Quadruple Byte Program command)

do:

– Read Status Register

– If SR7=0 and a Program/Erase Suspend

command has been executed

– SR7 is set to 1

– Enter suspend program loop

If SR3 = 1, VPP invalid error:

– error handler

If SR4 = 1, Program error:

– error handler

Suspend

Loop

YES

Write 40h or 10h

Start

Write Start Address

and 2/4 Data Bytes

(3)

YES

End

YES

SR1 = 0 Program to Protected

Block/Sector Error (1, 2) If SR1 = 1,

Program to protected block/sector error:

– error handler

47/53

M50FLW080A, M50FLW080B

Figure 24. Quadruple Byte Program Flowcha rt and Pseudo Code (A/A Mux Interface Only)

Note: 1. A Status check of SR3 (VPP invalid) and SR4 (Program Error) can be made after each Program operation by following the correct

command sequence.

2. If an error is found, the Status Register must be c l eared before further Program/Erase Controller operations .

3. Address1, Address 2, Address 3 and Address 4 must be cons ecutive addresses differing only for address bit s A0 and A1.

AI09099

Write Address 4

& Data 4

(3)

Read Status

YES

SR7 = 1

YES

SR3 = 0

SR4 = 0

VPP Invalid

Error (1, 2)

Program

Error (1, 2)

Quadruple Byte Program command:

– write 30h

– write Address 1 & Data 1

(3)

– write Address 2 & Data 2

(3)

– write Address 3 & Data 3

(3)

– write Address 4 & Data 4

(3)

(memory enters read status state after

the Quadruple Byte Program command)

do:

– Read Status Register

– If SR7=0 and a Program/Erase Suspend

command has been executed

– SR7 is set to 1

– Enter suspend program loop

If SR3 = 1, VPP invalid error:

– error handler

If SR4 = 1, Program error:

– error handler

End

YES

Suspend

Loop

YES

Write 30h

Start

Write Address 1

& Data 1

(3)

Write Address 2

& Data 2

(3)

Write Address 3

& Data 3

(3)

M50FLW080A, M50FLW080B

48/53

Figure 25. Program Susp end and Re sume Flowchart and Pseudo Code

Note: 1. If an error is found, the Status Register must be c l eared before further Program/Erase operations.

2. Any address within the bank can equally be used.

Write 70h

AI08426B

Read Status

YES

SR7 = 1

YES

SR2 = 1

Program Continues

Write a read

Command

Program/Erase Suspend command:

– write B0h

– write 70h

do:

– read Status Register

while SR7 = 0

If SR2 = 0 Program completed

Write D0h Program/Erase Resume command:

– write D0h to resume the program

– if the Program operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

Read data from

another address

Start

Write B0h

Program Complete

Write FFh

Read Data

49/53

M50FLW080A, M50FLW080B

Figure 26. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only)

Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

Write 80h

AI08428B

Start

Write 10h

Read Status

YES

SR7 = 1

YES

SR3 = 0

SR4, SR5 = 0

VPP Invalid

Error (1)

Command

Sequence Error (1)

Chip Erase command:

– write 80h

– write 10h

(memory enters read Status Register after

the Chip Erase command)

do:

– read Status Register

while SR7 = 0

If SR3 = 1, VPP invalid error:

– error handler

If SR4, SR5 = 1, Command sequence error:

– error handler

YES

SR5 = 0 Erase Error (1) If SR5 = 1, Erase error:

– error handler

End

YES

M50FLW080A, M50FLW080B

50/53

Figure 27. Sector/Block Erase Flowchart and Pseudo Code

Note: 1. If the Block Erase command is used on a block that is split into 4KByte sectors, each of the 16 sectors of the block should be un-

locked before performing the erase operation.

2. If an error is found, the Status Register must be c l eared before further Program/Erase Controller operations .

Write 20h/32h

AI09094

Start

Write Block/Sector

Address and D0h

Read Status

YES

SR7 = 1

YES

SR3 = 0

SR4, SR5 = 0

VPP Invalid

Error (1)

Command

Sequence Error (1)

Block/Sector Erase command:

– Write 20h/32h

– Write Block/Sector Address and D0h

(memory enters read Status Register after

the Block/Sector Erase command)

do:

– Read Status Register

– If SR7=0 and a Program/Erase Suspend

command has been executed

– SR7 is set to 1

– Enter suspend program loop

If SR3 = 1,

– Enter the "VPP invalid" error handler

If SR4, SR5 = 1,

– Enter the "Command sequence"error handler

YES

SR5 = 0 Erase Error (1)

YES

Suspend

Loop

If SR5 = 1,

– Enter the "Erase Error" error handler

End

YES

SR1 = 0 Erase to Protected

Block/Sector Error (1)

If SR1 = 1,

– Enter the "Erase to protected Block/Sector"

error handler

YES

FWH/LPC

Interface

Only

51/53

M50FLW080A, M50FLW080B

Figure 28. Erase Suspend and Resume Flowchart and Pseudo Code

Write 70h

AI08429B

Read Status

YES

SR7 = 1

YES

SR6 = 1

Erase Continues

Program/Erase Suspend command:

– write B0h

– write 70h

do:

– read Status Register

while SR7 = 0

If SR6 = 0, Erase completed

Write D0h

Read data from

another block/sector

Program

Start

Write B0h

Erase Complete

Write FFh

Read Data

Program/Erase Resume command:

– write D0h to resume erase

– if the Erase operation completed

then this is not necessary.

The device returns to Read as

normal (as if the Program/Erase

suspend was not issued).

M50FLW080A, M50FLW080B

52/53

REVISION HISTORY

Table 36. Document Revision History

Date Version Revision Details

02-Feb -2 004 0.1 Fir st Iss ue

21-Apr-2004 0.2 TSOP32 package added

24-May -2 00 4 1.0 Fir st pu blic relea se

18-Aug-2004 2.0 Pins 2 and 5 of the TSOP32 Connections illustration corrected

21-Jun-2005 3.0 Datasheet status changed to Full Datasheet.

53/53

M50FLW080A, M50FLW080B

Informatio n furnis hed is believ ed to be a ccurate and reli able. Howe ver, STMic roelectr onics assumes no r esponsib ility for th e consequences

of use of such inf ormation nor for any infringement of p atents or other right s of third part ies which may result fr om its use. No license is granted

by implication or otherwise under any pat ent or pat ent rights o f STMicroelectr onics. Spec ifications mentioned in this publicati on are subject

to change wi thout notic e. T his pub licat ion su persed es and repl aces all info rmat ion previou sly su pplie d. STMicroele ctro nics prod ucts ar e not

authorize d for use as critical components in life s upport devices or s ystems witho ut express written approval of STMicr oelectronics.

The ST logo is a regis tered trad emark of STMicr oelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Ko ng - India - Israe l - Italy - Japan -

Malaysia - Ma lta - Morocco - Singapore - Spain - Sweden - Switz erland - United Kingdom - United States of America