LTC3829
1
3829fc
For more information www.linear.com/LTC3829
3-Phase, Single Output
Synchronous Step-Down
DC/DC Controller with Diffamp
TYPICAL APPLICATION
DESCRIPTION
The LT C
®
3829 is a high performance 3-phase single output
synchronous step-down DC/DC switching controller that
drives all N-channel synchronous power MOSFET stages.
A constant frequency current mode architecture allows a
phase-lockable frequency of up to 770kHz. Power loss and
noise due to ESR of the input capacitors are minimized by
operating the three controller output stages out of phase.
The LTC3829 can be configured for 6-phase operation,
has DCR temperature compensation, and output foldback
current limiting. This device features a precision 0.6V
reference and a power good indicator.
Light load efficiency is optimized by using a choice of
output Stage Shedding or Burst Mode operation. A dif-
ferential amplifier provides true remote sensing of the
output voltage at the point of load.
The LTC3829 is available in both low profile 38-pin 5mm
× 7mm QFN and Exposed Pad FE packages.
FEATURES
APPLICATIONS
n Optional Nonlinear Control for Fast Response
n ±0.75%, 0.6V Reference Accuracy
n PWM, Stage Shedding™ or Burst Mode
®
Operation
n High Efficiency: Up to 95%
n RSENSE or DCR Current Sensing
n Programmable DCR Temperature Compensation
n Phase-Lockable Fixed Frequency: 250kHz to 770kHz
n True Remote Sense Differential Amplifier
n Programmable Active Voltage Positioning (AVP)
n Triple N-Channel MOSFET Synchronous Drive
n Wide VIN Range: 4.5V to 38V Operation
n VOUT Range: 0.6V to 5V without Diffamp
n VOUT Range: 0.6V to 3.3V with Diffamp
n Clock Input and Output for 6-Phase Operation
n Adjustable Soft-Start or VOUT Tracking
n 38-Pin (5mm × 7mm) QFN and FE Packages
n Notebook and Palmtop Computers
n Telecom Systems
n Portable Instruments
n DC Power Distribution Systems
+
+
INTVCC
BOOST1
BOOST2
BOOST3
FREQ
ITH
TK/SS
SENSE1+
SENSE1
PGND
BG1
SW1
TG1
4.7µF
SW3 SW2 SW1
0.1µF
680pF
100k
5k
20k
20k
22µF
35V
×3
VIN
6V TO 28V
COUT
470µF
4V
×4
VOUT
1.2V
50A
SENSE2+
SENSE2
BG2
SW2
TG2
SENSE3+
SENSE3
BG3
SW3
TG3
SGND
DIFFOUT
VFB
DIFFN
DIFFP
0.6µH
VIN
VIN
0.002Ω
0.6µH 0.002Ω
0.6µH
3829 TA01
0.002Ω
VIN
LTC3829
L, LT , LT C , LT M , Burst Mode, OPTI-LOOP, PolyPhase, Linear Technology, the Linear logo are
registered trademarks and Stage Shedding, No RSENSE are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by
U.S. Patents, including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 6498466,
6674274, 6611136.
LOAD CURRENT (A)
0.1
70
EFFICIENCY (%)
POWER LOSS (W)
75
80
85
90
1 10 100
3829 TA01b
65
60
55
50
95
100
4
6
8
10
12
2
0
14
16
VIN = 12V
VOUT = 1.5V
EFFICIENCY
POWER LOSS
Efficiency
LTC3829
2
3829fc
For more information www.linear.com/LTC3829
Input Supply Voltage (VIN) ......................... 40V to0.3V
Topside Driver Voltages (BOOSTn) ............. 46V to0.3V
Switch Voltage (SWn) ................................... 40V to –5V
Boosted Driver Voltage (BOOSTn – SWn) .... 6V to0.3V
INTVCC, PGOOD, RUN, EXTVCC ................... 6V to0.3V
ITEMP, IFAST, VFB Pin Voltages ............INTVCC to0.3V
TK/SS, FREQ, DIFFP, DIFFN, DIFFOUT, ISET
AVP, ILIM, MODE, PLLIN Voltages .........INTVCC to0.3V
(Note 1)
ABSOLUTE MAXIMUM RATINGS
13 14 15 16
TOP VIEW
39
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1DIFFN
DIFFP
RUN
AVP
SENSE1+
SENSE1
SENSE2+
SENSE2
TK/SS
FREQ
SENSE3+
SENSE3
SW1
BG1
BG2
SW2
TG2
BOOST2
VIN
INTVCC
EXTVCC
BG3
SW3
TG3
DIFFOUT
ITEMP
IFAST
MODE
CLKOUT
BOOST1
TG1
VFB
ITH
ISET
ILIM
PGOOD
PLLIN
BOOST3
23
22
21
20
9
10
11
12
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS SGND/PGND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TOP VIEW
FE PACKAGE
38-LEAD PLASTIC TSSOP
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
ITEMP
DIFFOUT
DIFFN
DIFFP
RUN
AVP
SENSE1+
SENSE1
SENSE2+
SENSE2
TK/SS
FREQ
SENSE3+
SENSE3
VFB
ITH
ISET
ILIM
PGOOD
IFAST
MODE
CLKOUT
BOOST1
TG1
SW1
BG1
BG2
SW2
TG2
BOOST2
VIN
INTVCC
EXTVCC
BG3
SW3
TG3
BOOST3
PLLIN
39
TJMAX = 125°C, θJA = 25°C/W
EXPOSED PAD (PIN 39) IS SGND/PGND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
ITH Voltage ............................................ INTVCC to0.3V
SENSE+n, SENSEn................................... 5.7V to0.3V
Operating Junction Temperature Range
(Notes 2, 3) ............................................ 4C to 125°C
Storage Temperature Range .................. 6C to 125°C
Lead Temperature (Soldering, 10 sec) (FE) ........... 300°C
LTC3829
3
3829fc
For more information www.linear.com/LTC3829
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3829EUHF#PBF LTC3829EUHF#TRPBF 3829 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
LTC3829IUHF#PBF LTC3829IUHF#TRPBF 3829 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
LTC3829EFE#PBF LTC3829EFE#TRPBF LTC3829 38-Lead Plastic TSSOP –40°C to 125°C
LTC3829IFE#PBF LTC3829IFE#TRPBF LTC3829 38-Lead Plastic TSSOP –40°C to 125°C
Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LT C Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Voltage Range 4.5 38 V
VOUT Output Voltage Range 0.6 5.0 V
VFB Regulated Feedback Voltage ITH Voltage = 1.2V (Note 4) –40°C to 85°C
ITH Voltage = 1.2V (Note 4) TJ = 125°C
l
l
0.5955
0.593
0.600
0.600
0.6045
0.607
V
V
IFB Feedback Current (Note 4) –15 –50 nA
VREFLNREG Reference Voltage Line Regulation VIN = 4.5V to 38V (Note 4) 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 4)
Measured in Servo Loop,
ITH Voltage = 1.2V to 0.7V
Measured in Servo Loop,
ITH Voltage = 1.2V to 1.6V
l
l
0.01
–0.01
0.1
–0.1
%
%
gmTransconductance Amplifier gmITH = 1.2V, Sink/Source 5µA (Note 4) 2.2 mmho
IQInput DC Supply Current
Normal Mode
Shutdown
(Note 5)
VIN = 15V
VRUN = 0V
4
40
60
mA
µA
DFMAX Maximum Duty Factor In Dropout, fOSC = 500kHz 93 94 %
UVLO Undervoltage Lockout VINTVCC Ramping Down l3.0 3.3 3.6 V
UVLO Hyst UVLO Hysteresis 0.6 V
VOVL Feedback Overvoltage Lockout Measured at VFB l0.64 0.66 0.68 V
ISENSE1,2,3+SENSE+ Pins Bias Current Each Channel, VSENSE1,2,3 = 3.3V,
VDIFFP = 3.3V
l±1 ±2 µA
ITEMP DCR Tempco Compensation Current VITEMP = 0.2V l9 10 11 µA
ITK/SS Soft-Start Charge Current VTK/SS = 0V l1.0 1.25 1.5 µA
VRUN RUN Pin On Threshold VRUN Rising l1.1 1.22 1.35 V
RUN Pin On Hysteresis 100 mV
VSENSE(MAX) Maximum Current Sense Threshold
(E-Grade)
VFB = 0.5V, VSENSE1,2,3 = 3.3V
ILIM = 0V
ILIM = Float
ILIM = INTVCC
l
l
l
25
45
68
30
50
75
35
55
82
mV
mV
mV
Maximum Current Sense Threshold
(I-Grade)
VFB = 0.5V, VSENSE1,2,3 = 3.3V
ILIM = 0V
ILIM = Float
ILIM = INTVCC
l
l
l
23
43
66
30
50
75
37
57
84
mV
mV
mV
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN = 5V, unless otherwise noted. (Note 2)
(Note 2)
LTC3829
4
3829fc
For more information www.linear.com/LTC3829
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN = 5V, unless otherwise noted. (Note 2)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TG1,2,3 tr
TG1,2,3 tf
TG Transition Time
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
BG1,2,3 tr
BG1,2,3 tf
BG Transition Time
Rise Time
Fall Time
(Note 6)
CLOAD = 3300pF
CLOAD = 3300pF
25
25
ns
ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver 30 ns
BG/TG t2D Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver 30 ns
tON(MIN) Minimum On-Time (Note 7) 90 ns
INTVCC Linear Regulator
VINTVCC Internal VCC Voltage 6V < VIN ≤ 38V 4.8 5.0 5.2 V
VLDO INT INTVCC Load Regulation ICC = 0mA to 20mA 0.5 2.0 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive l4.5 4.7 V
VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V 50 100 mV
VLDOHYS EXTVCC Hysteresis 200 mV
Oscillator and Phase-Locked Loop
fNOM Nominal Frequency VFREQ = 1.2V 450 500 550 kHz
fLOW Lowest Frequency VFREQ = 0V 210 250 290 kHz
fHIGH Highest Frequency VFREQ ≥ 2.4V 700 770 850 kHz
RPLLN PLLIN Input Resistance 100
IFREQ Frequency Setting Current 9 10 11 µA
IISET Shed and Burst Mode Program
Current
6.5 7.5 8.5 µA
CLKOUT Phase (Relative to Controller 1) Non-Shedding Mode
Channel 2 and 3 Shedding
60
180
Deg
Deg
CLKHIGH Clock High Output Voltage 4 5 V
CLKLOW Clock Low Output Voltage 0 0.2 V
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V 0 ±2 µA
VPG PGOOD Trip Level, Either Controller VFB with Respect to Set Output Voltage
VFB Ramping Negative
VFB Ramping Positive
–12
8
–10
10
–7
13
%
%
Differential Amplifier
ADA Gain l0.997 1 1.003 V/V
RIN Input Resistance Measured at DIFFP Input 80
VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.5V,
IDIFFOUT = 100µA
2.5 mV
PSRR Power Supply Rejection Ratio 5V < VIN < 38V 100 dB
ICL Maximum Output Current 3 mA
VOUT(MAX) Maximum Output Voltage INTVCC = 5V, IDIFFOUT = 300µA VINTVCC – 1.4 VINTVCC – 1.1 V
GBW Gain-Bandwidth Product (Note 8) 3 MHz
SR Slew Rate (Note 8) 2 V/µs
LTC3829
5
3829fc
For more information www.linear.com/LTC3829
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Nonlinear Fast Transit Mode
IFAST Fast Transient Programmable Current VIFAST = 400mV 9 10 11 µA
AVP (Active Voltage Positioning)
ISINK Sink Current of AVP Pin SENSE+ = 1.2V 250 µA
ISOURCE Source Current of AVP Pin SENSE+ = 1.2V 2 mA
VAVP-VO(MAX) Maximum Voltage Drop VAVP to VOSENSE+ = 1.2V 180 mV
VAVP Maximum AVP Voltage l2.5 V
On-Chip Driver
TG RUP TG Pull-Up RDS(ON) TG High 2.6 Ω
TG RDOWN TG Pull-Down RDS(ON) TG Low 1.5 Ω
BG RUP BG Pull-Up RDS(ON) BG High 4 Ω
BG RDOWN BG Pull-Down RDS(ON) BG Low 1.1 Ω
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN = 5V, unless otherwise noted. (Note 2)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3829 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3829E is guaranteed to meet performance specifications
from 0°C to 85°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3829I is guaranteed to meet performance specifications over the
full –40°C to 125°C operating junction temperature range.
Note 3: TJ is calculated from the ambient temperature, TA, and power
dissipation, PD, according to the following formula:
LTC3829UHF: TJ = TA + (PD • 34°C/W)
LTC3829FE: TJ = TA + (PD • 25°C/W)
Note 4: The LTC3829 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time
Considerations in the Applications Information section).
Note 8: Guaranteed by design.
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step-Up (0A to 75A, 75A/µs)
(Nonlinear Operation)
Load Step-Up (0A to 75A, 75A/µs)
(Normal Operation)
VOUT
100mV/DIV
AC-COUPLED
VSW1
10V/DIV
VSW2
10V/DIV
VSW3
10V/DIV
2µs/DIV 3829 G01
75mV
VOUT
100mV/DIV
AC-COUPLED
VSW1
10V/DIV
VSW2
10V/DIV
VSW3
10V/DIV
2µs/DIV 3829 G02
95mV
LTC3829
6
3829fc
For more information www.linear.com/LTC3829
TYPICAL PERFORMANCE CHARACTERISTICS
Phase Shedding Transition Phase Shedding Transition
Prebiased Output at 2V Coincident Tracking
Current Sense Threshold
vs ITH Voltage
Quiescent Current vs Input
Voltage without EXTVCC INTVCC Line Regulation
INPUT VOLTAGE (V)
0
2.00
INTV
CC
VOLTAGE (V)
2.50
2.25
3.00
2.75
3.50
3.25
4.75
4.50
4.25
4.00
3.75
5.25
510 15 20
3829 G09
25 4030 35
5.00
VITH (V)
0
–40
V
SENSE
(mV)
–20
0
20
40
60
80
0.5 1 1.5 2
3829 G10
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
RUN
2V/DIV
VOUT1 = 3.3V
VOUT2 = 1.5V
1V/DIV
2ms/DIVVIN = 12V
NO LOAD
3829 G06
VOUT1
VOUT2
INPUT VOLTAGE (V)
4
3.5
SUPPLY CURRENT (mA)
3.7
4.1
4.3
4.5
5.5
4.9
14 24
3829 G08
3.9
5.1
5.3
4.7
34 40
VSW1
10V/DIV
VSW2
10V/DIV
VSW3
10V/DIV
VOUT
50mV/DIV
AC-COUPLED
4µs/DIVVIN = 12V
VOUT = 1.5V
TRANSITION LOAD CURRENT = 18.6A
3829 G03
VSW1
10V/DIV
VSW2
10V/DIV
VSW3
10V/DIV
VOUT
50mV/DIV
AC-COUPLED
4µs/DIVVIN = 12V
VOUT = 1.5V
TRANSITION LOAD CURRENT = 5.3A
3829 G04
VOUT
1V/DIV
VFB
500mV/DIV
TK/SS
500mV/DIV
2ms/DIVVIN = 12V
VOUT = 3.3V
3829 G05
LTC3829
7
3829fc
For more information www.linear.com/LTC3829
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense Threshold
vs Common Mode Voltage
Maximum Current Sense Voltage
vs Duty Cycle
Maximum Current Sense Voltage
vs Feedback Voltage
(Current Foldback)
TK/SS Pull-Up Current
vs Temperature
VSENSE COMMON MODE VOLTAGE (V)
0
0
CURRENT SENSE THRESHOLD (mV)
10
30
40
50
245
90
3829 G11
20
1 3
60
70
80 ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
TEMPERATURE (°C)
–50
1.1
TK/SS CURRENT (µA)
1.2
1.3
1.4
1.5
–25 0 25 50
3829 G14
75 100 125
DUTY CYCLE (%)
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
60
80
100
80
3829 G12
40
20
50
70
90
30
10
02010 4030 60 70 90
50 100
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
FEEDBACK VOLTAGE (V)
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
60
80
100
0.4 0.5
3829 G13
40
20
50
70
90
30
10
00.1 0.2 0.3 0.6
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
Shutdown (RUN) Threshold
vs Temperature
TEMPERATURE (°C)
–50
1.0
RUN PIN VOLTAGE (V)
1.1
1.2
1.3
ON
OFF
1.4
–25 0 25 50
3829 G15
75 100 125
Regulated Feedback Voltage
vs Temperature
TEMPERATAURE (°C)
–50
FB
0.600
0.602
25 75
3829 G16
0.598
0.596
–25 0 50 100 125
0.594
0.592
Undervoltage Lockout Threshold
(INTVCC) vs Temperature
Oscillator Frequency
vs Temperature
TEMPERATURE (°C)
–50
FREQUENCY (kHz)
600
700
25 75
3829 G17
500
400
–25 0 50 100 125
300
200
VFREQ ≥ 2.4V
VFREQ = 1.2V
VFREQ = 0V
TEMPERATURE (°C)
–50
2.5
UVLO THRESHOLD (V)
2.7
3.1
3.3
3.5
50
4.3
3829 G18
2.9
0
–25 75 100
25 125
3.7
3.9
4.1 RISING
FALLING
Oscillator Frequency
vs Input Voltage
INPUT VOLTAGE (V)
0
0
FREQUENCY (kHz)
200
400
600
800
5 10 15 20
3829 G19
25 30 35 40
VFREQ ≥ 2.4V
VFREQ = 1.2V
VFREQ = 0V
LTC3829
8
3829fc
For more information www.linear.com/LTC3829
PIN FUNCTIONS
DIFFN (Pin 1/Pin 3): Negative Input of Remote Sensing
Differential Amplifier. Connect this to the remote load
ground pin.
DIFFP (Pin 2/Pin 4): Positive Input of Remote Sensing
Differential Amplifier. Must connect this to the remote load
positive terminal directly even when diffamp is not used.
RUN (Pin 3/Pin 5): Run Control Input. A voltage above
1.22V on this pin turns on the IC. There is a 1.0µA pull-up
current for this pin. Once the RUN pin rises above 1.22V,
an additional 4.5µA pull-up current is added to the pin.
AVP (Pin 4/Pin 6): Active Voltage Positioning Load Slope
Programming Pin. A resistor tied between this pin and the
DIFFP pin sets the load slope. The AVP function can only
be used with the remote sensing differential amplifier.
Float or connect a 1kΩ resistor to DIFFP pin when AVP
function is not used.
SENSE1+, SENSE2+, SENSE3+ (Pins 5, 7, 11/Pins 7, 9,
13): Current Sense Comparator Inputs. The (+) inputs to
the current comparators are normally connected to DCR
sensing networks or current sensing resistors.
SENSE1, SENSE2, SENSE3 (Pins 6, 8, 12/Pins 8, 10,
14): Current Sense Comparator Inputs. The (–) inputs
to the current comparators are connected to the output.
(UHF/FE)
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Current
vs Input Voltage Shutdown Current vs Temperature
Quiescent Current vs Temperature
without EXTVCC
INPUT VOLTAGE (V)
5 10
0
SHUTDOWN CURRENT (µA)
20
50
15 25 30
3829 G20
10
40
30
20 35 40
TEMPERATURE (°C)
–50
40
50
70
25 75
3829 G21
30
20
–25 0 50 100 125
10
0
60
SHUTDOWN CURRENT (µA)
TEMPERATURE (°C)
–50
QUIESCENT CURRENT (mA)
4
5
6
25 75
3829 G22
3
2
–25 0 50 100 125
1
0
TK/SS (Pin 9/Pin 11): Output Voltage Tracking and Soft-
Start Input. When one particular IC is configured to be the
master of two ICs, a capacitor to ground at this pin sets
the ramp rate for the master IC’s output voltage. When the
IC is configured to be the slave of two ICs, the VFB voltage
of the master IC is reproduced by a resistor divider and
applied to this pin. An internal soft-start current of 1.25µA
is charging this pin.
FREQ (Pin 10/Pin 12): There is a precision 10µA current
sourced out of this pin. A resistor to ground sets a voltage
which in turn programs the frequency. Alternatively, this
pin can be driven with a DC voltage to vary the frequency
of the internal oscillator.
VFB (Pin 13/Pin 15): Error Amplifier Feedback Input. This
pin receives the remotely sensed feedback voltage from
an external resistive divider.
ITH (Pin 14/Pin 16): Current Control Threshold and Error
Amplifier Compensation Point. Each associated channels’
current comparator tripping threshold increases with this
ITH control voltage.
LTC3829
9
3829fc
For more information www.linear.com/LTC3829
PIN FUNCTIONS
(UHF/FE)
ISET (Pin 15/Pin 17): Stage Shedding Comparator and
Burst Mode Comparator Programming Pin. A resistor to
ground programs the stage shedding comparator threshold
or Burst Mode comparator threshold and its current limit
depending on MODE pin setting.
ILIM (Pin 16/Pin 18): Current Comparator Sense Voltage
Range Pin. This pin is to be programmed to SGND, FLOAT
or INTVCC to set the maximum current sense threshold to
one of three different levels for each comparator.
PGOOD (Pin 17/Pin 19): Power Good Indicator Output.
Open-drain logic out that is pulled to ground when the
output exceeds ±10% regulation window after the internal
100µs power bad mask timer expires.
PLLIN (Pin 18/Pin 20): External Synchronization Pin. A
clock on the pin synchronizes the internal oscillator with
the clock on this pin.
EXTVCC (Pin 23/Pin 25): External Power Input to an Inter-
nal Switch Connected to INTVCC. This switch closes and
supplies the IC power, bypassing the internal low dropout
regulator, whenever EXTVCC is higher than 4.7V. Do not
exceed 6V on this pin and ensure VIN > VEXTVCC at all times.
INTVCC (Pin 24/Pin 26): Internal 5V Regulator Output. The
control circuits are powered from this voltage. Decouple
this pin to PGND with a minimum of 4.7µF low ESR tan-
talum or ceramic capacitor.
VIN (Pin 25/Pin 27): Main Input Supply. Decouple this pin
to PGND with a capacitor (0.1µF to 1µF).
BG1, BG2, BG3 (Pins 30, 29, 22/Pins 32, 31, 24): Bot-
tom Gate Driver Outputs. These pins drive the gates of the
bottom N-channel MOSFETs between PGND and INTVCC.
SW1, SW2, SW3 (Pins 31, 28, 21/Pins 33, 30, 23):
Switch Node Connections to Inductors. Voltage swing
at these pins is from a Schottky diode (external) voltage
drop below ground to VIN.
TG1, TG2, TG3 (Pins 32, 27, 20/Pins 34, 29, 22): Top Gate
Driver Outputs. These are the outputs of floating drivers
with a voltage swing equal to INTVCC superimposed on
the switch nodes voltages.
BOOST1, BOOST2, BOOST3 (Pins 33, 26, 19/Pins 35,
28, 21): Boosted Floating Driver Supplies. The (+) terminal
of the bootstrap capacitors connect to these pins. These
pins swing from a diode voltage drop below INTVCC up
to VIN + INTVCC.
CLKOUT (Pin 34/Pin 36): Clock Output Pin. CLKOUT is
60° out of phase relative to channel 1 in non-shedding
mode. During stage shedding, CLKOUT is 180° out of
phase with channel 1.
MODE (Pin 35/Pin 37): Forced Continuous Mode, Burst
Mode or Shed Mode Selection Pin. Connect this pin to
SGND to force IC in continuous mode of operation. Con-
nect to INTVCC to enable shed mode operation. Leave the
pin floating to enable Burst Mode operation.
IFAST (Pin 36/Pin 38): Programmable Pin for Nonlinear
Control Trip Threshold. A resistor to ground programs the
tripping threshold for nonlinear control circuit. Connect
this pin to INTVCC to disable this feature. See Applications
Information section for details. Leave this pin floating
when it is not used.
ITEMP (Pin 37/Pin 1): Input of the Temperature Sensing
Comparator. Connect this pin to external NTC resistors
placed near inductors.
DIFFOUT (Pin 38/Pin 2): Output of Remote Sensing
Differential Amplifier. Connect this pin to VFB through a
resistive divider.
SGND/PGND (Exposed Pad Pin 39/Exposed Pad Pin 39):
Combined Signal and Power Ground Pad. Connect this pad
closely to the sources of the bottom N-channel MOSFETs,
the (–) terminal of CVCC and the (–) terminal of CIN. All
small-signal components and compensation components
should also Kelvin-connect to this pad.
LTC3829
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FUNCTIONAL DIAGRAM
+
++
SLEEP
ISET
INTVCC
0.55V
+
+
0.5V
SS
+
1.22V
RUN
ISET
1.25µA
VIN
EA
ITH RC
CC1 CSS
ISET
ISET RUN TK/SS
0.6V
REF
S
RQ
SHED
COMP
5V
REG
IFAST
SLOPE RECOVERY
ACTIVE CLAMP
OSC
MODE/SYNC
DETECT
SLOPE
COMPENSATION
UVLO
1
51k
ITHB
1.0µA
IFAST
CLKOUT
FREQ
MODE PLLIN ITEMP
0.6V
BURSTEN
EXTVCC
ILIM
+
+
ICOMP IREV
F
+
4.7V
F
3k
+
+
OV
UV
+
+
+
+
DIFFAMP
0.54V
VFB
PGOOD
PGND CVCC
CB
M1
M2
VOUT
L1
INTVCC
VIN
COUT
DB
BG
SENSE
SENSE+
SW
TG
BOOST
INTVCC
DIFFOUT
DIFFN
3829 BD
SENSE1+
SENSE1
SENSE2+
SENSE2
SENSE3+
SENSE3
DIFFP
SGND
AVP
0.66V
R1
RPRE-AVP
40k 40k
40k
RAVP
40k
R2
SWITCH
LOGIC
AND
ANTISHOOT-
THROUGH
OV
RUN
ON
FCNT
PLL-SYNC
TEMPSNS
+
CIN
+
VIN
LTC3829
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OPERATION
Main Control Loop
The LTC3829 uses a constant frequency, current mode
step-down architecture. During normal operation, each
top MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the main current
comparator, ICMP
, resets each RS latch. The peak inductor
current at which ICMP resets the RS latch is controlled by
the voltage on the ITH pin, which is the output of the er-
ror amplifier, EA. The remote sense amplifier (DIFFAMP)
produces a signal equal to the differential voltage sensed
across the output capacitor and re-references it to the lo-
cal IC ground reference. The VFB pin receives a portion of
this feedback signal and compares it to the internal 0.6V
reference. When the load current increases, it causes a
slight decrease in the VFB pin voltage relative to the 0.6V
reference, which in turn causes the ITH voltage to increase
until each inductor’s average current equals one-third of
the new load current (assuming all three current sensing
resistors are equal). After each top MOSFET has turned off,
the bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by the reverse cur-
rent comparator, IREV
, or the beginning of the next cycle.
The main control loop is shut down by pulling the RUN
pin low. Releasing RUN allows an internal 1.0µA current
source to pull up the RUN pin. When the RUN pin reaches
1.22V, the main control loop is enabled and the IC is
powered up. When the RUN pin is low, all functions are
kept in a controlled state.
INTVCC/EXTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin.
When the EXTVCC pin is left open or tied to a voltage less
than 4.7V, an internal 5V linear regulator supplies INTVCC
power from VIN. If EXTVCC is taken above 4.7V, the 5V
regulator is turned off and an internal switch is turned on
connecting EXTVCC. Using the EXTVCC pin allows the INTVCC
power to be derived from a high efficiency external source
such as a switching regulator output. Each top MOSFET
driver is biased from the floating bootstrap capacitor, CB,
which normally recharges during each off cycle through
an external diode when the top MOSFET turns off. If the
input voltage, VIN, decreases to a voltage close to VOUT
,
the loop may enter dropout and attempt to turn on the
top MOSFET continuously. The dropout detector detects
this and forces the top MOSFET off for about one-twelfth
of the clock period plus 100ns every third cycle to allow
CB to recharge. However, it is recommended that a load
be present or the IC operates at low frequency during the
dropout transition to ensure CB is recharged.
Shutdown and Start-Up (RUN and TK/SS Pins)
The LTC3829 can be shut down using the RUN pin. Pulling
the RUN pin below 1.22V shuts down the main control loop
for the controller and most internal circuits, including the
INTVCC regulator. Releasing the RUN pin allows an internal
1.0µA current to pull up the pin and enable the controller.
Alternatively, the RUN pin may be externally pulled up or
driven directly by logic. Be careful not to exceed the ab-
solute maximum rating of 6V on this pin. The start-up of
the controller’s output voltage, VOUT
, is controlled by the
voltage on the TK/SS pin. When the voltage on the TK/SS
pin is less than the 0.6V internal reference, the LTC3829
regulates the VFB voltage to the TK/SS pin voltage instead
of the 0.6V reference. This allows the TK/SS pin to be used
to program a soft-start by connecting an external capacitor
from the TK/SS pin to SGND. An internal 1.25µA pull-up
current charges this capacitor, creating a voltage ramp on
the TK/SS pin. As the TK/SS voltage rises linearly from
0V to 0.6V (and beyond), the output voltage, VOUT
, rises
smoothly from zero to its final value. Alternatively, the TK/
SS pin can be used to cause the start-up of VOUT to track
that of another supply. Typically, this requires connect-
ing to the TK/SS pin an external resistor divider from the
other supply to ground (see the Applications Information
section). When the RUN pin is pulled low to disable the
controller, or when INTVCC drops below its undervoltage
lockout threshold of 3.3V, the TK/SS pin is pulled low
by an internal MOSFET. When in undervoltage lockout,
all phases of the controller are disabled and the external
MOSFETs are held off.
(Refer to Functional Diagram)
LTC3829
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Light Load Current Operation (Burst Mode Operation,
Stage Shedding or Continuous Conduction)
The LTC3829 can be enabled to enter high efficiency
Burst Mode operation, Stage Shedding mode or forced
continuous conduction mode. To select forced continuous
operation, tie the MODE pin to a DC voltage below 0.6V
(e.g., SGND). To select Stage Shedding mode of opera-
tion, tie the MODE pin to INTVCC. To select Burst Mode
operation, float the MODE pin.
When the controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-sixth of the maximum sense voltage even though the
voltage on the ITH pin indicates a lower value. The peak
current can be programmed through the ISET pin. If the
average inductor current is higher than the load current,
the error amplifier, EA, will decrease the voltage on the
ITH pin. When the ITH voltage drops below 0.5V (can
also be programmed by the ISET pin), the internal sleep
signal goes high (enabling sleep mode) and the external
MOSFETs are turned off. In sleep mode, the load current
is supplied by the output capacitor. As the output voltage
decreases, the EA’s output begins to rise. When the output
voltage drops enough, the sleep signal goes low, and the
controller resumes normal operation by turning on the top
external MOSFET on the next cycle of the internal oscillator.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator, IREV
, turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus, the
controller operates in discontinuous operation. In forced
continuous operation, the inductor current is allowed to
reverse at light loads or under large transient conditions.
The peak inductor current is determined by the voltage
on the ITH pin. In this mode, the efficiency at light loads is
lower than in Burst Mode operation. However, continuous
mode has the advantages of lower output ripple and less
interference with audio circuitry.
When the MODE pin is connected to INTVCC, the LTC3829
operates in Stage Shedding mode at light loads. The
controller will turn off channels 2 and 3 and increase
the current gain of the first channel to ensure smooth
transition. The threshold where the controller goes into
Stage Shedding mode is when the ITH voltage drops
below 0.5V, but it can be programmed by ISET pin. The
inductor current is not allowed to reverse in this mode
(discontinuous operation). At very light loads, the cur-
rent comparator may remain tripped for several cycles
and force the external top MOSFET to stay off for the
same number of cycles (i.e., skipping pulses). This mode
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
2-Chip Operations (CLKOUT Pin)
The LTC3829’s three channels are 120° out of phase
providing multiphase operation. This configuration can
provide enough power for most high current applications.
However, for even higher power applications, the LTC3829
can be configured for PolyPhase
®
and 2-chip operation.
The LTC3829 features a CLKOUT pin which enables two
LTC3829s to operate out of phase. The CLKOUT signal is
60° out of phase with respect to phase 1 of the controller.
In Stage Shedding mode, however, the CLKOUT signal is
180° out of phase with respect to phase 1 of the controller.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
If the PLLIN pin is not being driven by an external clock
source, the FREQ pin can be used to program the control-
ler’s operating frequency from 250kHz to 770kHz. There
is a precision 10µA current flowing out of the FREQ pin
so that the user can program the controller’s switching
frequency with a single resistor to SGND. A curve is pro-
vided later in the Applications Information section showing
the relationship between the voltage on the FREQ pin and
switching frequency.
OPERATION
(Refer to Functional Diagram)
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OPERATION
(Refer to Functional Diagram)
A phase-locked loop (PLL) is available on the LTC3829
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN pin. The PLL loop
filter network is integrated inside the LTC3829. The phase-
locked loop is capable of locking any frequency within
the range of 250kHz to 770kHz. The frequency setting
resistor should always be present to set the controller’s
initial switching frequency before locking to the external
clock. The controller is operating in forced continuous
mode when it is synchronized.
Sensing the Output Voltage with a
Differential Amplifier
The LTC3829 includes a low offset, unity-gain, high band-
width differential amplifier for applications that require true
remote sensing. Sensing the load across the load capaci-
tors directly greatly benefits regulation in high current, low
voltage applications, where board interconnection losses
can be a significant portion of the total error budget.
The LTC3829 differential amplifier has a typical output slew
rate of 2V/µs. The amplifier is configured for unity gain,
meaning that the difference between DIFFP and DIFFN is
translated to DIFFOUT, relative to SGND.
Care should be taken to route the DIFFP and DIFFN PCB
traces parallel to each other all the way to the terminals
of the output capacitor or remote sensing points on the
board. In addition, avoid routing these sensitive traces
near any high speed switching nodes in the circuit. Ide-
ally, the DIFFP and DIFFN traces should be shielded by a
low impedance ground plane to maintain signal integrity.
The maximum output voltage when using the differential
amplifier is INTVCC – 1.4V (typically 3.6V). Above this
output voltage the differential amplifier should not be used.
Power Good (PGOOD Pin)
The PGOOD pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the VFB pin voltage is not
within ±10% of the 0.6V reference voltage. The PGOOD
pin is also pulled low when the RUN pin is below 1.22V or
when the LTC3829 is in the soft-start or tracking phase.
When the VFB pin voltage is within the ±10% regulation
window, the MOSFET is turned off and the pin is allowed
to be pulled up by an external resistor to a source of up
to 6V. The PGOOD pin will flag power good immediately
when the
VFB pin is within the regulation window. However,
there is an internal 100µs power-bad mask when the VFB
goes out of the window.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In such cases, the
top MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Undervoltage Lockout
The LTC3829 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTVCC voltage
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTVCC is below
3.3V. To prevent oscillation when there is a disturbance
on the INTVCC, the UVLO comparator has 600mV of preci-
sion hysteresis.
Another way to detect an undervoltage condition is to
monitor the VIN supply. Because the RUN pin has a preci-
sion turn-on reference of 1.22V, one can use a resistor
divider to VIN to turn on the IC when VIN is high enough.
An extra 4.5µA of current flows out of the RUN pin once
the RUN pin voltage passes 1.22V. The RUN comparator
itself has about 80mV of hysteresis. One can program
additional hysteresis for the RUN comparator by adjust-
ing the values of the resistive divider. For accurate VIN
undervoltage detection, VIN needs to be higher than 4.5V.
LTC3829
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APPLICATIONS INFORMATION
The Typical Application on the first page of this data sheet
is a basic LTC3829 application circuit. The LTC3829 can be
configured to use either DCR (inductor resistance) sens-
ing or low value resistor sensing. The choice between the
two current sensing schemes is largely a design trade-off
between cost, power consumption and accuracy. DCR
sensing is becoming popular because it saves expensive
current sensing resistors and is more power efficient,
especially in high current applications. However, current
sensing resistors provide the most accurate current limits
for the controller. Other external component selection is
driven by the load requirement, and begins with the se-
lection of RSENSE (if RSENSE is used) and inductor value.
Next, the power MOSFETs are selected. Finally, input and
output capacitors are selected.
Current Limit Programming
The ILIM pin is a tri-level logic input which sets the maxi-
mum current limit of the controller. When ILIM is either
grounded, floated or tied to INTVCC, the typical value for
the maximum current sense threshold will be 30mV, 50mV
or 75mV, respectively.
Which setting should be used? For the best current limit
accuracy, use the 75mV setting. The 30mV setting will allow
for the use of very low DCR inductors or sense resistors,
but at the expense of current limit accuracy. The 50mV
setting is a good balance between the two.
SENSE+ and SENSE Pins
The SENSE+ and SENSE pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 5V. All SENSE+ pins are
high impedance inputs with small currents of less than
1µA. The high impedance inputs to the current compara-
tors allow accurate DCR sensing. All SENSE pins and
DIFFP should be connected to VOUT directly when DCR
sensing is used. Care must be taken not to float these
pins during normal operation. Filter components mutual
to the sense lines should be placed close to the LTC3829,
and the sense lines should run close together to a Kelvin
connection underneath the current sense element (shown
in Figure 1). Sensing current elsewhere can effectively add
parasitic inductance and capacitance to the current sense
element, degrading the information at the sense terminals
and making the programmed current limit unpredictable.
If DCR sensing is used (Figure 2b), sense resistor R1
should be placed close to the switching node, to prevent
noise from coupling into sensitive small-signal nodes.
The capacitor C1 should be placed close to the IC pins.
COUT
TO SENSE FILTER,
NEXT TO THE CONTROLLER
RSENSE
3829 F01
Figure 1. Sense Lines Placement with Sense Resistor
Low Value Resistors Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current. The current comparator has a maximum
threshold VSENSE(MAX) determined by the ILIM setting. The
input common mode range of the current comparator
is 0V to 5V. The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
output current IMAX equal to the peak value less half the
peak-to-peak ripple current, IL. To calculate the sense
resistor value, use the equation:
RSENSE =
V
SENSE(MAX)
IMAX +IL
2
Because of possible PCB noise in the current sensing loop,
the AC current sensing ripple of VSENSE = ILRSENSE
also needs to be checked in the design to get a good
signal-to-noise ratio. In general, for a reasonably good
PCB layout, a 10mV VSENSE voltage is recommended as
a conservative number to start with, either for RSENSE or
DCR sensing applications. For previous generation current
mode controllers, the maximum sense voltage was high
enough (e.g., 75mV for the LTC1628/LTC3728 family)
that the voltage drop across the parasitic inductance of
the sense resistor represented a relatively small error. For
today’s highest current density solutions, however, the
value of the sense resistor can be less than 1and the
LTC3829
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APPLICATIONS INFORMATION
peak sense voltage can be as low as 20mV. In addition,
inductor ripple currents greater than 50% with operation
up to 1MHz are becoming more common. Under these
conditions the voltage drop across the sense resistor’s
parasitic inductance is no longer negligible. A typical sens-
ing circuit using a discrete resistor is shown in Figure 2a.
In previous generations of controllers, a small RC filter
placed near the IC was commonly used to reduce the ef-
fects of capacitive and inductive noise coupled in the sense
traces on the PCB. A typical filter consists of two series
10Ω resistors connected to a parallel 1000pF capacitor,
VIN VIN
INTVCC
BOOST
TG
SW
BG
PGND
FILTER COMPONENTS
PLACED NEAR SENSE PINS
SENSE+
SENSE
SGND
LTC3829 VOUT
3829 F02a
CF • 2 • RF ≤ ESL/RS
POLE-ZERO
CANCELLATION
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
RSESL
CF
RF
RF
VIN VIN
INTVCC
BOOST
TG
SW
BG
PGND
ITEMP
RNTC
*PLACE C1 NEAR SENSE+,
SENSE PINS
**PLACE R1 NEXT TO INDUCTOR
INDUCTOR
OPTIONAL
TEMP COMP
NETWORK DCRL
SENSE+
SENSE
SGND
LTC3829 VOUT
3829 F02b
R1**
R2C1*
RP
RS
R1||R2 × C1 = L
DCR RSENSE(EQ) = DCR R2
R1 + R2
(2a) Using a Resistor to Sense Current
(2b) Using the Inductor DCR to Sense Current
Figure 2. Tw o Different Methods of Sensing Current
resulting in a time constant of 20ns. This same RC filter,
with minor modifications, can be used to extract the resis-
tive component of the current sense signal in the presence
of parasitic inductance. For example, Figure 3 illustrates
the voltage waveform across a 2sense resistor with
a 2010 footprint for the 1.2V/15A converter operating at
100% load. The waveform is the superposition of a purely
resistive component and a purely inductive component.
It was measured using two scope probes and waveform
math to obtain a differential measurement. Based on
additional measurements of the inductor ripple current
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APPLICATIONS INFORMATION
and the on-time and off-time of the top switch, the value
of the parasitic inductance was determined to be 0.5nH
using the equation:
ESL =
V
ESL(STEP)
IL
t
ON
t
OFF
tON
+
tOFF
(1)
If the RC time constant is chosen to be close to the
parasitic inductance divided by the sense resistor (L/R),
the resulting waveform looks resistive again, as shown
in Figure 4. For applications using low maximum sense
voltages, check the sense resistor manufacturer’s data
sheet for information about parasitic inductance. In the
absence of data, measure the voltage drop directly across
the sense resistor to extract the magnitude of the ESL step
and use Equation 1 to determine the ESL. However, do not
overfilter. Keep the RC time constant, less than or equal
to the inductor time constant to maintain a high enough
ripple voltage of VSENSE. The above generally applies to
high density/high current applications where IMAX > 10A
and low values of inductors are used. For applications
500ns/DIV
VSENSE
20mV/DIV
3829 F03
VESL(STEP)
Figure 3. Voltage Waveform Measured
Directly Across the Sense Resistor
500ns/DIV
VSENSE
20mV/DIV
3829 F04
Figure 4. Voltage Waveform Measured After
the Sense Resistor Filter. CF = 1000pF, RF = 100Ω
where IMAX < 10A, set RF to 10Ω and CF to 1000pF. This
will provide a good starting point. The filter components
need to be placed close to the IC. The positive and nega-
tive sense traces need to be routed as a differential pair
and Kelvin connected to the sense resistor.
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3829 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1for today’s low value, high current
inductors. In a high current application requiring such an
inductor, conduction loss through a sense resistor would
cost several points of efficiency compared to DCR sensing.
If the external R1|| R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
RSENSE(EQUIV) =
V
SENSE(MAX)
IMAX +IL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the Maximum Current Sense Threshold
(VSENSE(MAX)) in the Electrical Characteristics table (25mV,
45mV or 68mV, depending on the state of the ILIM pin).
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of resistance, which is approximately 0.4%/°C.
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APPLICATIONS INFORMATION
A conservative value for TL(MAX) is 100°C. To scale the
maximum inductor DCR to the desired sense resistor
value, use the divider ratio:
RD=
R
SENSE(EQUIV)
DCR(MAX) at T
L(MAX)
C1 is usually selected to be in the range of 0.047µF to
0.47µF. This forces R1|| R2 to around 2k, reducing error
that might have been caused by the SENSE+ pins’ ±1µA
current. TL(MAX) is the maximum inductor temperature.
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
R1||R2=
L
(DCR at 20
°
C) C1
The sense resistor values are:
R1=
R1||R2
RD
; R2=
R1R
D
1
RD
The LTC3829 also features a DCR temperature compen-
sation circuit by using a NTC temperature sensor. See
the Inductor DCR Sensing Temperature Compensation
section for details.
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
P
LOSS R1=
V
IN(MAX)
V
OUT
( )
V
OUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduces
conduction losses and provides higher efficiency at heavy
loads. Peak efficiency is about the same with either method.
To maintain a good signal-to-noise ratio for the current
sense signal, use a minimum VSENSE of 10mV for duty
cycles less than 40%. For a DCR sensing application, the
actual ripple voltage will be determined by the equation:
V
SENSE =
V
IN
V
OUT
R1C1
V
OUT
V
IN f
OSC
Inductor DCR Sensing Temperature Compensation
and the ITEMP Pin
Inductor DCR current sensing provides a lossless method
of sensing the instantaneous current. Therefore, it can
provide higher efficiency for applications of high output
currents. However, the DCR of the inductor, which is the
small amount of DC winding resistance of the copper,
typically has a positive temperature coefficient. As the
temperature of the inductor rises, its DCR value increases.
The current limit of the controller is therefore reduced.
The LTC3829 offers a method to counter this inaccuracy
by allowing the user to place an NTC temperature sensing
resistor near the inductor to actively correct this error. The
ITEMP pin, when left floating, is at a voltage around 5V and
DCR temperature compensation is disabled. The ITEMP
pin has a constant 10µA precision current flowing out the
pin. By connecting an NTC resistor from the ITEMP pin
to SGND, the maximum current sense threshold can be
varied over temperature according the following equation:
V
SENSEMAX(ADJ ) =V
SENSE(MAX)
1.8– V
ITEMP
1.3
where:
VSENSEMAX(ADJ) is the maximum adjusted current sense
threshold.
VSENSE(MAX) is the maximum current sense threshold
specified in the Electrical Characteristics table. It is
typically 75mV, 50mV or 30mV depending on the set-
ting ILIM pins.
VITEMP is the voltage of the ITEMP pin.
The valid voltage range for DCR temperature compensa-
tion on the ITEMP pin is between 0.5V to 0.2V, with 0.5V
or above being no DCR temperature correction and 0.2V
the maximum correction. However, if the duty cycle of the
controller is less than 25%, the ITEMP range is extended
from 0.5V to 0V.
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APPLICATIONS INFORMATION
The NTC resistor has a negative temperature coefficient,
meaning its value decreases as temperature rises. The
VITEMP voltage, therefore, decreases as temperature in-
creases and in turn, the VSENSEMAX(ADJ) will increase to
compensate the DCR temperature coefficient. The NTC
resistor, however, is nonlinear and the user can linear-
ize its value by building a resistor network with regular
resistors. Consult the NTC manufacture data sheets for
detailed information.
Another use for the ITEMP pins, in addition to NTC com-
pensated DCR sensing, is adjusting VSENSE(MAX) to values
between the nominal values of 30mV, 50mV and 75mV for
a more precise current limit. This is done by applying a
voltage less than 0.5V to the ITEMP pin. VSENSE(MAX) will
be varied per the previous equation and the same duty cycle
limitations will apply. The current limit can be adjusted using
this method either with a sense resistor or DCR sensing.
NTC Compensated DCR Sensing
For DCR sensing applications where a more accurate
current limit is required, a network consisting of an NTC
thermistor placed from the ITEMP pin to ground will
provide correction of the current limit over temperature.
Figure 2b shows this network. Resistors RS and RP will
linearize the impedance the ITEMP pin sees. To implement
NTC compensated DCR sensing, design the DCR sense
filter network per the same procedure mentioned in the
previous selection, except calculate the divider components
using the room temperature value of the DCR. For a single
output rail operating from one phase:
1. Set the ITEMP pin resistance to 50k at 25°C. With
10µA flowing out of the ITEMP pin, the voltage on the
ITEMP pin will be 0.5V at room temperature. Current
limit correction will occur for inductor temperatures
greater than 25°C.
2. Calculate the ITEMP pin resistance and the maximum
inductor temperature which is typically 100°C. Use the
equations:
RITEMP100C =
V
ITEMP100C
10μA
V
ITEMP100C =0.5V 1.3IMAX DCR(MAX)R2/ R1+R2
( )
100°C– 25°C
( )
0.4/100
V
SENSE(MAX)
Calculate the values for RP and RS. A simple method is to
graph the following RS versus RP equations with RS on
the y-axis and RP on the x-axis.
RS = RITEMP25C – RNTC25C || RP
RS = RITEMP100C – RNTC100C || RP
Next, find the value of RP that satisfies both equations
which will be the point where the curves intersect. Once
RP is known, solve for RS.
The resistance of the NTC thermistor can be obtained
from the vendor’s data sheet either in the form of graphs,
tabulated data or formulas. The approximate value for the
NTC thermistor for a given temperature can be calculated
from the following equation:
R=ROexp B 1
T
+
273
1
T
O
+
273
where:
R = resistance at temperature T, which is in degrees C
RO = resistance at temperature TO, typically 25°C
B = B-constant of the thermistor.
Figure 5 shows a typical resistance curve for a 100k
thermistor and the ITEMP pin network over temperature.
Starting values for the NTC compensation network are
listed below:
NTC RO = 100k
RS = 20k
RP = 50k
But, the final values should be calculated using the above
equations and checked at 25°C and 100°C.
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After determining the components for the temperature
compensation network, check the results by plotting IMAX
versus inductor temperature using the following equations:
I
MAX =
V
SENSEMAX(ADJ )
V
SENSE
/3
DCR(MAX) at 25
°
C 1
+
T
L(MAX) 25
°
C
( )
0.4/100
( )
where:
V
SENSEMAX(ADJ ) =V
SENSE(MAX)
1.8V V
ITEMP
1.3 A
V
ITEMP
=
10μA• RS
+
RP||RNTC
( )
Use typical values for VSENSE(MAX). Subtracting constant
A will provide a minimum value for VSENSE(MAX). These
values are summarized in Table 1.
Table 1
ILIM GND FLOAT INTVCC
VSENSE(MAX) TYP 30mV 50mV 75mV
A 5mV 5mV 7mV
The resulting current limit should be greater than or equal
to IMAX for inductor temperatures between 25°C and 100°C.
These are typical values for the NTC compensation network:
NTC RO = 100k, B-constant = 3000 to 4000
RS ≈ 20k
RP ≈ 50k
Generating the IMAX versus inductor temperature curve plot
first using the above values as a starting point and then
adjusting the RS and RP values as necessary is another
approach. Figure 6 shows a typical curve of IMAX versus
inductor temperature.
The same thermistor network can be used to correct for
temperatures less than 25°C. But make sure VITEMP is
greater than 0.2V for duty cycles of 25% or more, oth-
erwise temperature correction may not occur at elevated
ambients. For the most accurate temperature detection,
place the thermistors next to the inductors as shown in
Figure 7. Take care to keep the ITEMP pin away from the
switch nodes.
INDUCTOR TEMPERATURE (°C)
10
RESISTANCE (kΩ)
100
1000
10000
–40 20 40 60 10080 120
1
–20 0
3829 F05
THERMISTOR RESISTANCE
RO = 100k
TO = 25°C
B = 4334 FOR 25°C/100°C
RITMP
RS = 20k
RP = 43.2k
100k NTC
Figure 5. Resistance Versus Temperature for
the ITEMP Pin Network and the 100k NTC
INDUCTOR TEMPERATURE (°C)
–40
I
MAX
(A)
15
20
25
20 60 120
3829 F06
10
5
0
–20 0 40 80 100
CORRECTED
IMAX
NOMINAL
IMAX
UNCORRECTED
IMAX
RS = 20k
RP = 43.2k
NTC THERMISTOR:
RO = 100k
TO = 25°C
B = 4334
VOUT RNTC
L1
SW1
L2
SW2
L3
SW3
3829 F07
Figure 6. Worst-Case IMAX Versus Inductor Temperature Curve
with and without NTC Temperature Compensation
Figure 7. Thermistor Location. Place Thermistor Next to
Inductor(s) for Accurate Sensing of the Inductor Temperature,
But Keep the ITEMP Pin Away from the Switch Nodes and Gate
Drive Traces
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Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequen-
cy current mode architectures by preventing sub-harmonic
oscillation at high duty cycles. It is accomplished internally
by adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. Normally, this
results in a reduction of maximum inductor peak current
for duty cycles greater than 40%. However, the LTC3829
uses a scheme that counteracts this compensating ramp,
which allows the maximum inductor peak current to remain
unaffected throughout all duty cycles.
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use of
smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET
gate charge and transition losses. In addition to this basic
trade-off, the effect of inductor value on ripple current
and low current operation must also be considered. The
PolyPhase approach reduces both input and output ripple
currents while optimizing individual output stages to run
at a lower fundamental frequency, enhancing efficiency.
The inductor value has a direct effect on ripple current.
The inductor ripple current, IL, per individual sectionN,
decreases with higher inductance or frequency and in-
creases with higher VIN or VOUT
:
IL=
V
OUT
fL
1
V
OUT
V
IN
where f is the individual output stage operating frequency.
In a PolyPhase converter, the net ripple current seen by
the output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.
Figure 8 shows the net ripple current seen by the output
capacitors for the different phase configurations. The
output ripple current is plotted for a fixed output voltage
as the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations. The zero output
ripple current is obtained when:
V
OUT
V
IN
=
k
N
where k=1, 2,...,N–
1
Figure 8. Normalized Peak Output Current
vs Duty Factor [IRMS = 0.3(IOP-P)]
DUTY FACTOR (VOUT/VIN)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3829 F08
DI
O(P-P)
VO/fL
6-PHASE
4-PHASE
12-PHASE
3-PHASE
2-PHASE
1-PHASE
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Power MOSFET and Schottky Diode
(Optional) Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and on-resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an output voltage that
is less than 1/3 of the input voltage. In applications where
VIN >> VOUT
, the top MOSFETs’ on-resistance is normally
less important for overall efficiency than its input capaci-
tance at operating frequencies above 300kHz. MOSFET
manufacturers have designed special purpose devices that
provide reasonably low on-resistance with significantly
reduced input capacitance for the main switch application
in switching regulators.
The peak-to-peak MOSFET gate drive levels are set by the
voltage, VCC, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BVDSS specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less. Selection
criteria for the power MOSFETs include the on-resistance,
RDS(ON), input capacitance, input voltage and maximum
output current. MOSFET input capacitance is a combina-
tion of several components but can be taken from the
typical gate charge curve included on most data sheets
(Figure 9). The curve is generated by forcing a constant
input current into the gate of a common source, current
source loaded stage and then plotting the gate voltage
versus time.
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given VDS drain
voltage, but can be adjusted for different VDS voltages by
multiplying the ratio of the application VDS to the curve
specified VDS values. A way to estimate the CMILLER term
is to take the change in gate charge from points a and b
on a manufacturer’s data sheet and divide by the stated
VDS voltage specified. CMILLER is the most important se-
lection criteria for determining the transition loss term in
the top MOSFET but is not directly specified on MOSFET
data sheets. CRSS and COS are specified sometimes but
definitions of these parameters are not included. When the
controller is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
MainSwitchDuty Cycle=
V
OUT
V
IN
Synchronous SwitchDuty Cycle=V
IN V
OUT
V
IN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
MAIN =V
OUT
V
IN
IMAX
N
2
1+δ
( )
RDS(ON) +
V
IN
( )
2IMAX
2
RDR
( )
C
MILLER
( )
1
V
CC V
TH(IL)
+1
V
TH(IL)
f
PSYNC =V
IN V
OUT
V
IN
IMAX
N
2
1+δ
( )
RDS(ON)
where N is the number of output stages, δ is the tem-
perature dependency of RDS(ON), RDR is the effective top
+
VDS
V
IN
3729 F09
VGS
MILLER EFFECT
QIN
a b
CMILLER = (QB – QA)/VDS
VGS V
+
Figure 9. Gate Charge Characteristic
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APPLICATIONS INFORMATION
driver resistance (approximately 2Ω at VGS = VMILLER), VIN
is the drain potential and the change in drain potential in
the particular application. VTH(IL) is the data sheet speci-
fied typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. CMILLER
is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For VIN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V, the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diodes conduct during the dead
time between the conduction of the two large power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead
time and requiring a reverse-recovery period which could
cost as much as several percent in efficiency. A 2A to 8A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition loss due to
their larger junction capacitance.
CIN and COUT Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle VOUT/
VIN. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a close form
equation can be found in Application Note 77. Figure 10
shows the input capacitor ripple current for different phase
configurations with the output voltage fixed and input volt-
age varied. The input ripple current is normalized against
the DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(VOUT), is approximately equal to the
input voltage VIN or:
V
OUT
V
IN
=
k
N
where k=1, 2,...,N–
1
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages. In
the graph of Figure 10, the local maximum input RMS
capacitor currents are reached when:
V
OUT
V
IN
=
2k1
N
where k=1, 2,...,N
These worst-case conditions are commonly used for design
because even significant deviations do not offer much relief.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
capacitor manufacturer if there is any question.
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The Figure 10 graph shows that the peak RMS input
current is reduced linearly, inversely proportional to the
number N of stages used. It is important to note that the
efficiency loss is proportional to the input RMS current
squared and therefore a 3-stage implementation results
in 90% less power loss when compared to a single-phase
design. Battery/input protection fuse resistance (if used),
PC board trace and connector resistance losses are also
reduced by the reduction of the input ripple current in a
PolyPhase system. The required amount of input capaci-
tance is further reduced by the factor N, due to the effective
increase in the frequency of the current pulses. Ceramic
capacitors are becoming very popular for small designs
but several cautions should be observed. X7R, X5R and
Y5V are examples of a few of the ceramic materials used
as the dielectric layer, and these different dielectrics have
very different effect on the capacitance value due to the
voltage and temperature conditions applied. Physically,
if the capacitance value changes due to applied voltage
change, there is a concommitant piezo effect which results
in radiating sound! A load that draws varying current at an
audible rate may cause an attendant varying input voltage
on a ceramic capacitor, resulting in an audible signal. A
secondary issue relates to the energy flowing back into
a ceramic capacitor whose capacitance value is being
reduced by the increasing charge. The voltage can increase
at a considerably higher rate than the constant current being
supplied because the capacitance value is decreasing as
the voltage is increasing! Nevertheless, ceramic capacitors,
when properly selected and used, can provide the lowest
overall loss due to their extremely low ESR.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The steady-state output ripple (VOUT) is determined by:
V
OUT ILESR+
1
8NfC
OUT
where f = operating frequency of each stage, N is the
number of output stages, COUT = output capacitance and
IL = ripple current in each inductor. The output ripple is
highest at maximum input voltage since IL increases with
input voltage. The output ripple will be less than 50mV at
maximum VIN with IL = 0.4IOUT(MAX) assuming:
COUT required ESR < N • RSENSE
and
C
OUT >
1
8Nf
( )
RSENSE
( )
DUTY FACTOR (VOUT/VIN)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
3829 F10
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
6-PHASE
4-PHASE
12-PHASE
3-PHASE
2-PHASE
1-PHASE
Figure 10. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Output Stages
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The emergence of very low ESR capacitors in small, surface
mount packages makes very small physical implementa-
tions possible. The ability to externally compensate the
switching regulator loop using the ITH pin allows a much
wider selection of output capacitor types. The impedance
characteristic of each capacitor type is significantly differ-
ent than an ideal capacitor and therefore requires accurate
modeling or bench evaluation during design. Manufacturers
such as Nichicon, Nippon Chemi-Con and Sanyo should be
considered for high performance through-hole capacitors.
The OS-CON semiconductor dielectric capacitors available
from Sanyo and the Panasonic SP surface mount types
have a good (ESR)(size) product.
Once the ESR requirement for COUT has been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement. Ceramic capacitors from AVX, Taiyo Yuden,
Murata and Tokin offer high capacitance value and very
low ESR, especially applicable for low output voltage
applications.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum
electrolytic and dry tantalum capacitors are both available
in surface mount configurations. New special polymer
surface mount capacitors offer very low ESR also but
have much lower capacitive density per unit volume. In
the case of tantalum, it is critical that the capacitors are
surge tested for use in switching power supplies. Several
excellent choices are the AVX TPS, AVX TPSV, the KEMET
T510 series of surface mount tantalums or the Panasonic
SP series of surface mount special polymer capacitors
available in case heights ranging from 2mm to 4mm. Other
capacitor types include Sanyo POSCAP, Sanyo OS-CON,
Nichicon PL series and Sprague 595D series. Consult the
manufacturers for other specific recommendations.
Differential Amplifier
The LTC3829 has a true remote voltage sense capability.
The sensing connections should be returned from the
load, back to the differential amplifier’s inputs through a
common, tightly coupled pair of PC traces. The differential
amplifier rejects common mode signals capacitively or
inductively radiated into the feedback PC traces as well as
ground loop disturbances. The differential amplifier output
signal is divided by a pair of resistors and is compared
with the internal, precision 0.6V voltage reference by the
error amplifier.
Active Voltage Positioning (AVP)
In an application, the AVP scheme modifies the regu-
lated output voltage depending its current loading. AVP
can improve overall transient response and save power
consumption.
The LTC3829 senses inductor current information through
monitoring voltage drops on the sense resistor RSENSE or
DCR sensing network of all three channels. The voltage
drops are added together and applied as VPRE-AVP between
the AVP and DIFFP pins, which are connected through
resistor RPRE-AVP
. Then VPRE-AVP is scaled through RAVP
and added to output voltage as the compensation for the
load voltage drop.
Let:
∆V = VSENSE1+ – VSENSE1
∆V = VSENSE2+ – VSENSE2
∆V = VSENSE3+ – VSENSE3
then:
V
DIFFP,VOUT =3•V
R
AVP
RPRE-AVP
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The final load slope is defined by the inductor current sense
resistors and the two external resistors mentioned above.
In summary, the load slope is:
RSENSE
R
AVP
RPRE-AVP
V/A
The recommended value for RAVP is 90Ω to 100Ω. The
maximum output voltage at AVP is 2.5V. Therefore, for
output higher than 2.5V, AVP function is not supported.
The DIFFP pin, however, should always be connected to
the output even when AVP or diffamp functions are not
used. When AVP function is not desired, float the AVP pin
or connect a resistor between the AVP pin and DIFFP pin.
RPRE-AVP on the order of 1kΩ is recommended.
Programmable Shed Mode
When the MODE pin is tied to INTVCC, the LTC3829 enters
shed mode. It means that the second and third channel will
stop switching when ITH is below a certain programmed
threshold. The threshold voltage on ITH when LTC3829
goes into shed mode, is programmed according to the
following formula:
VSHED = 0.5 + (5/3) • (0.5 – VISET)
The valid range of VISET is between 0V to 0.5V and VISET
is the voltage on the ISET pin. There is a precision 7.5µA
flowing out of the ISET pin. Connecting a resistor to SGND
sets the VISET voltage. When left floating, VISET voltage
will be at INTVCC. The shed mode threshold voltage in this
case will be 0.5V. There is a 50mV hysteresis for the shed
mode threshold comparator.
Programmable Burst Mode Operation
When the MODE pin is floating, the LTC3829 enters Burst
Mode operation. This means that all channels will stop
switching when ITH is below a certain threshold.
The Burst Mode clamp, which sets the current limit when
bursting, can be programmed through VISET according to
the following equation:
VCLAMP = 0.7 + 0.62 (0.5 – VISET)
The valid range of VISET is between 0.3V to 0.5V and VISET
is the voltage on the ISET pin. There is a precision 7.5µA
flowing out of ISET. Connecting a resistor to SGND sets
the VISET voltage. When left floating, the VISET voltage will
be at INTVCC. The Burst Mode clamp voltage in this case
will be 0.7V. There is a 50mV hysteresis for the Burst
Mode comparator.
Nonlinear Control Loop
The LTC3829 features a unique control loop that can
speed up transient response dramatically. This feature is
enabled and programmed through the IFAST pin. When
IFAST is tied to INTVCC, the nonlinear control loop is dis-
abled. VIFAST is the voltage that can be programmed on
the IFAST pin. There is a precision 10µA flowing out of the
IFAST pin. Connecting a resistor to SGND sets the VIFAST
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voltage. When VIFAST is set below 0.5V, the difference of
0.5V and VIFAST sets the threshold voltage that triggers
nonlinear control. Nonlinear control is only enabled when
VFB is within the UV and OV window. It should be enabled
only for forced continuous mode of operation.
Once nonlinear control is enabled, the top gate of all chan-
nels will turn on if:
V
FB =V
REF
0.5– V
IFAST
5
1.
2
The top gate of all channels will turn off if:
V
FB =V
REF +
0.5– V
IFAST
5
where VREF is the reference voltage, normally at 0.6V, and
VFB is the feedback voltage.
Soft-Start and Tracking
The LTC3829 has the ability to either soft-start by itself
with a capacitor or track the output of another channel
or external supply. When the controller is configured to
soft-start by itself, a capacitor should be connected to its
TK/SS pin. The controller is in the shutdown state if its
RUN pin voltage is below 1.22V and its TK/SS pin is ac-
tively pulled to ground in this shutdown state. If the RUN
pin voltage is above 1.22V, the controller powers up. A
soft-start current of 1.25µA then starts to charge the TK/
SS soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.6V on the
TK/SS pin. The total soft-start time can be calculated as:
tSOFTSTART =0.6•
C
SS
1.25μA
Regardless of the mode selected by the MODE pin, the
controller always starts in discontinuous mode up to TK/
SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it will oper-
ate in forced continuous mode and revert to the selected
mode once TK/SS > 0.54V. The output ripple is minimized
during the 40mV forced continuous mode window ensuring
a clean PGOOD signal. When the channel is configured
to track another supply, the feedback voltage of the other
supply is duplicated by a resistor divider and applied to
the TK/SS pin. Therefore, the voltage ramp rate on this
pin is determined by the ramp rate of the other supply’s
voltage. Note that the small soft-start capacitor charging
current is always flowing, producing a small offset error.
To minimize this error, select the tracking resistive divider
value to be small enough to make this error negligible.
In order to track down another channel or supply after
the soft-start phase expires, the LTC3829 is forced into
continuous mode of operation as soon as VFB is below
the undervoltage threshold of 0.54V regardless of the
setting on the MODE pin. However, the LTC3829 should
always be set in forced continuous mode tracking down
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APPLICATIONS INFORMATION
when there is no load. After TK/SS drops below 0.1V, the
controller operates in discontinuous mode.
The LTC3829 allows the user to program how its output
ramps up and down by means of the TK/SS pins. Through
these pins, the output can be set up to either coincidentally
or ratiometrically track another supply’s output, as shown
in Figure 11. In the following discussions, VOUT1 refers
to the LTC3829’s output as a master and VOUT2 refers
to another supply output as a slave. To implement the
coincident tracking in Figure 11a, connect an additional
resistive divider to VOUT1 and connect its mid-point to the
TK/SS pin of the slave controller. The ratio of this divider
should be the same as that of the slave controller’s feed-
back divider shown in Figure 12a. In this tracking mode,
VOUT1 must be set higher than VOUT2. To implement the
ratiometric tracking in Figure 11b, the ratio of the VOUT2
divider should be exactly the same as the master control-
ler’s feedback divider shown in Figure 12b . By selecting
different resistors, the LTC3829 can achieve different
modes of tracking including the two in Figure 11.
So which mode should be programmed? While either
mode in Figure 11 satisfies most practical applications,
some trade-offs exist. The ratiometric mode saves a pair
of resistors, but the coincident mode offers better output
regulation. Under ratiometric tracking, when the master
controller’s output experiences dynamic excursion (under
load transient, for example), the slave controller output
Figure 11. Tw o Different Modes of Output Voltage Tracking
Figure 12. Setup and Coincident and Ratiometric Tracking
TIME
(11a) Coincident Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
3829 F11a
VOUT1
VOUT2
TIME 3829 F11b
(11b) Ratiometric Tracking
OUTPUT VOLTAGE
R3 R1
R4 R2
R3
VOUT2
R4
(12a) Coincident Tracking Setup
TO
VFB1
PIN
TO
TK/SS2
PIN
TO
VFB2
PIN
VOUT1
R1
R2
R3
VOUT2
R4
3829 F12
(12b) Ratiometric Tracking Setup
TO
VFB1
PIN
TO
TK/SS2
PIN
TO
VFB2
PIN
VOUT1
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will be affected as well. For better output regulation, use
the coincident tracking mode instead of ratiometric.
INTVCC (LDO) and EXTVCC
The LTC3829 features a true PMOS LDO that supplies power
to INTVCC from the VIN supply. INTVCC powers the gate
drivers and much of the LTC3829’s internal circuitry. The
LDO regulates the voltage at the INTVCC pin to 5V when VIN
is greater than 5.5V. EXTVCC connects to INTVCC through
a P-channel MOSFET and can supply the needed power
when its voltage is higher than 4.7V. Each of these can
supply a peak current of 100mA and must be bypassed
to ground with a minimum of 4.7µF ceramic capacitor or
low ESR electrolytic capacitor. No matter what type of bulk
capacitor is used, an additional 0.1µF ceramic capacitor
placed directly adjacent to the INTVCC and PGND pins is
highly recommended. Good bypassing is needed to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3829 to be
exceeded. The INTVCC current, which is dominated by the
gate charge current, may be supplied by either the 5V LDO
or EXTVCC. When the voltage on the EXTVCC pin is less
than 4.7V, the LDO is enabled. Power dissipation for the
IC in this case is highest and is equal to VINIINTVCC. The
gate charge current is dependent on operating frequency
as discussed in the Efficiency Considerations section.
The junction temperature can be estimated by using the
equations given in Note 3 of the Electrical Characteristics
tables. For example, the LTC3829 INTVCC current is limited
to less than 42mA from a 38V supply in the UHF package
and not using the EXTVCC supply:
TJ = 70°C + (42mA)(38V)(34°C/W) = 125°C
To prevent the maximum junction temperature from be-
ing exceeded, the input supply current must be checked
while operating in continuous conduction mode (MODE
= SGND) at maximum VIN. When the voltage applied to
EXTVCC rises above 4.7V, the INTVCC LDO is turned off
and the EXTVCC is connected to the INTVCC. The EXTVCC
remains on as long as the voltage applied to EXTVCC remains
above 4.5V. Using the EXTVCC allows the MOSFET driver
and control power to be derived from one of switching
regulator outputs during normal operation and from the
INTVCC when the output is out of regulation (e.g., start-
up, short circuit). If more current is required through the
EXTVCC than is specified, an external Schottky diode can
be added between the EXTVCC and INTVCC pins. Do not
apply more than 6V to the EXTVCC pin and make sure that
EXTVCC < VIN.
Significant efficiency and thermal gains can be realized
by powering INTVCC from the output, since the VIN cur-
rent resulting from the driver and control currents will be
scaled by a factor of (duty cycle)/(switcher efficiency).
Tying the EXTVCC pin to a 5V supply reduces the junction
temperature in the previous example from 125°C to:
TJ = 70°C + (42mA)(5V)(34°C/W) = 77°C
However, for low voltage outputs, additional circuitry is
required to derive INTVCC power from the output.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTVCC
to be powered from the internal 5V LDO resulting
in an efficiency penalty of up to 10% at high input
voltages.
2. EXTVCC connected directly to VOUT
. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
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3. EXTVCC connected to an external supply. If a 5V external
supply is available, it may be used to power EXTVCC
providing it is compatible with the MOSFET gate drive
requirements.
4. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.7V.
For applications where the main input power is 5V, tie
the VIN and INTVCC pins together and tie the combined
pins to the 5V input with a 1Ω or 2.2Ω resistor as shown
in Figure 13 to minimize the voltage drop caused by the
gate charge current. This will override the INTVCC linear
regulator and will prevent INTVCC from dropping too low
due to the dropout voltage. Make sure the INTVCC voltage
is at or exceeds the RDS(ON) test voltage for the MOSFET
which is typically 4.5V for logic-level devices
Topside MOSFET Driver Supply (CB, DB)
External bootstrap capacitors, CB, connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor CB in the Functional Diagram is charged though
external diode DB from INTVCC when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the CB voltage across the gate source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
VIN and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply:
VBOOST = VIN + VINTVCC
The value of the boost capacitor, CB, needs to be 100 times
that of the total input capacitance of the topside MOSFET(s).
The reverse breakdown of the external Schottky diode
must be greater than VIN(MAX). When adjusting the gate
drive level, the final arbiter is the total input current for
the regulator. If a change is made and the input current
decreases, then the efficiency has improved. If there is
no change in input current, then there is no change in
efficiency.
Setting Output Voltage
The LTC3829 output voltage is set by an external feed-
back resistive divider carefully placed across the output,
as shown in Figure 14. The regulated output voltage is
determined by:
V
OUT =0.6V 1+
R
B
RA
To improve the frequency response, a feedforward ca-
pacitor, CFF
, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
APPLICATIONS INFORMATION
RVIN
1Ω
CIN
3829 F13
5V
CINTVCC
4.7µF
+
INTVCC
LTC3829
VIN
Figure 13. Setup for a 5V Input Figure 14. Setting Output Voltage
LTC3829
VFB
V
OUT
RBCFF
RA
3829 F14
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If diffamp is used, then the resistor, RB, should connect
to the output of the diffamp, DIFFOUT.
Fault Conditions: Current Limit and Current Foldback
The LTC3829 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximum programmed value to one-third of the maximum
value. Foldback current limiting is disabled during the
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3829 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short
circuit ripple current is determined by the minimum on-
time tON(MIN) of the LTC3829 (≈90ns), the input voltage
and inductor value:
IL(SC) =tON(MIN)
V
IN
L
The resulting short-circuit current is:
ISC =
1/3V
SENSE(MAX)
RSENSE
1
2
IL(SC)
3
Phase-Locked Loop and Frequency Synchronization
The LTC3829 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the PLLIN pin. The turn-on of the
second phases’ top MOSFETs is thus 120° out of phase
with the external clock and so on. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal filter
network. There is a precision 10µA of current flowing out
of FREQ pin. This allows the user to use a single resistor to
SGND to set the switching frequency when no external clock
is applied to the PLLIN pin. The internal switch between
the FREQ pin and the integrated PLL filter network is on,
allowing the filter network to be pre-charged at the same
voltage as of the FREQ pin. The relationship between the
voltage on the FREQ pin and operating frequency is shown
in Figure 15 and specified in the Electrical Characteristics
table. If an external clock is detected on the PLLIN pin, the
internal switch mentioned above turns off and isolates the
influence of the FREQ pin. Note that the LTC3829 can only
be synchronized to an external clock whose frequency is
within range of the LTC3829’s internal VCO. This is guar-
anteed to be between 250kHz and 770kHz. A simplified
block diagram is shown in Figure 16.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor CLP holds the voltage.
Typically, the external clock (on the PLLIN pin) input high
threshold is 1.6V, while the input low threshold is 1V.
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Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC3829 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
V
OUT
V
IN f
( )
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase. The
minimum on-time for the LTC3829 is approximately 90ns,
with reasonably good PCB layout, minimum 30% induc-
tor current ripple and at least 10mV ripple on the current
sense signal. The minimum on-time can be affected by
PCB switching noise in the voltage and current loop. As
the peak sense voltage decreases the minimum on-time
gradually increases to 130ns. This is of particular concern
in forced continuous applications with low ripple current
at light loads. If the duty cycle drops below the minimum
on-time limit in this situation, a significant amount of cycle
skipping can occur with correspondingly larger current
and voltage ripple.
Figure 15. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
Figure 16. Phase-Locked Loop Block Diagram
FREQ PIN VOLTAGE (V)
0
FREQUENCY (kHz)
0.5 1 1.5 2
38501 F15
2.5
0
100
300
400
500
900
800
700
200
600
DIGITAL
PHASE/
FREQUENCY
DETECTOR VCO
2.4V 5V
10µA RSET
3829 F16
FREQ
SYNC
EXTERNAL
OSCILLATOR
PLLIN
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Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3829 circuits: 1) IC VIN current, 2) IN-
TVCC regulator current, 3) I2R losses, 4) topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. VIN current typically results
in a small (<0.1%) loss.
2.
INTVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTVCC to ground. The resulting dQ/dt is a current
out of INTVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges
of the topside and bottom side MOSFETs. Supplying
INTVCC power through EXTVCC from an output-derived
source will scale the VIN current required for the driver
and control circuits by a factor of (duty cycle)/(effi-
ciency). For example, in a 20V to 5V application, 10mA
of INTVCC current results in approximately 2.5mA of
VIN current. This reduces the mid-current loss from
10% or more (if the driver was powered directly from
VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor and current sense re-
sistor. In continuous mode, the average output current
flows through L and RSENSE, but is chopped between
the topside MOSFET and the synchronous MOSFET.
If the two MOSFETs have approximately the same
RDS(ON), then the resistance of one MOSFET can simply
be summed with the resistances of L and RSENSE to
obtain I2R losses. For example, if each RDS(ON) = 10mΩ,
RL = 10mΩ, RSENSE = 5mΩ, then the total resistance is
25mΩ. This results in losses ranging from 2% to 8%
as the output current increases from 3A to 15A for a 5V
output, or a 3% to 12% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) VIN2 • IO(MAX) • CRSS • f
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20µF to 40µF of capacitance
having a maximum of 20to 50of ESR. Other
losses including Schottky conduction losses during
dead time and inductor core losses generally account
for less than 2% total additional loss.
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APPLICATIONS INFORMATION
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ILOAD (ESR), where ESR is the effective
series resistance of COUT
. ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC-coupled and
AC-filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The ITH external components shown
in the Typical Application circuit will provide an adequate
starting point for most applications. The ITH series RC-CC
filter sets the dominant pole-zero loop compensation.
The values can be modified slightly (from 0.5 to 2 times
their suggested values) to optimize transient response
once the final PC layout is done and the particular output
capacitor type and value have been determined. The output
capacitors need to be selected because the various types
and values determine the loop gain and phase. An output
current pulse of 20% to 80% of full-load current having a
rise time ofs to 10µs will produce output voltage and
ITH pin waveforms that will give a sense of the overall
loop stability without breaking the feedback loop. Placing
a power MOSFET directly across the output capacitor and
driving the gate with an appropriate signal generator is a
practical way to produce a realistic load step condition. The
initial output voltage step resulting from the step change
in output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the ITH
pin signal which is in the feedback loop and is the filtered
and compensated control loop response. The gain of the
loop will be increased by increasing RC and the bandwidth
of the loop will be increased by decreasing CC. If RC is
increased by the same factor that CC is decreased, the
zero frequency will be kept the same, thereby keeping the
phase shift the same in the most critical frequency range
of the feedback loop. The output voltage settling behavior
is related to the stability of the closed-loop system and
will demonstrate the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT
, causing a rapid drop in VOUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
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APPLICATIONS INFORMATION
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 17. Check the following in the
PC layout:
1. Keep the SGND at one end of a printed circuit path thus
preventing MOSFET currents from traveling under the
IC. The INTVCC decoupling capacitor should be placed
immediately adjacent to the IC between the INTVCC pin
and PGND plane. AF ceramic capacitor of the X7R or
X5R type is small enough to fit very close to the IC to
minimize the ill effects of the large current pulses drawn
to drive the bottom MOSFETs. An additionalF to 10µF
of ceramic, tantalum or other very low ESR capacitance
is recommended in order to keep the internal IC supply
quiet. The power ground returns to the sources of the
bottom N-channel MOSFETs, anodes of the Schottky
diodes and (–) plates of CIN, which should have as short
lead lengths as possible.
2. Does the IC DIFFP pin connect to the (+) plates of
COUT? A 30pF to 300pF feedforward capacitor between
the DIFFP and VFB pins should be placed as close as
possible to the IC.
3. Are the SENSE and SENSE+ printed circuit traces for
each channel routed together with minimum PC trace
spacing? The filter capacitors between SENSE+ and
SENSE for each channel should be as close as possible
to the pins of the IC. Connect the SENSE and SENSE+
pins to the pads of the sense resistor as illustrated in
Figure 1.
4. Do the (+) plates of CPWR connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the pulsed current to the MOSFETs.
5. Keep the switching nodes, SWn, BOOSTn and TGn away
from sensitive small-signal nodes (SENSE+, SENSE,
DIFFP, DIFFN, VFB). Ideally the SWn, BOOSTn and
TGn printed circuit traces should be routed away and
separated from the IC and especially the quiet side of
the IC. Separate the high dv/dt traces from sensitive
small-signal nodes with ground traces or ground planes.
6. Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
7. The 47pF to 330pF ceramic capacitor between the ITH
pin and signal ground should be placed as close as pos-
sible to the IC. Figure 17 illustrates all branch currents
in a 3-phase switching regulator. It becomes very clear
after studying the current waveforms why it is critical to
keep the high switching current paths to a small physical
size. High electric and magnetic fields will radiate from
these loops just as radio stations transmit signals. The
output capacitor ground should return to the negative
terminal of the input capacitor and not share a common
ground path with any switched current paths. The left
half of the circuit gives rise to the noise generated by
a switching regulator. The ground terminations of the
synchronous MOSFETs and Schottky diodes should
return to the bottom plate(s) of the input capacitor(s)
with a short isolated PC trace since very high switched
currents are present. External OPTI-LOOP
®
compensa-
tion allows overcompensation for PC layouts which are
not optimized but this is not the recommended design
procedure.
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APPLICATIONS INFORMATION
Figure 17. Branch Current Waveform
+
RIN
VIN VOUT
CIN
BOLD LINES INDICATE HIGH,
SWITCHING CURRENTS.
KEEP LINES TO A MINIMUM
LENGTH.
+
COUT
D3
D2
SW2
D1
L1
SW1 RSENSE1
L2
RSENSE2
L3
SW3 RSENSE3
3829 F17
RL
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TYPICAL APPLICATION
D2 CMDSH-3
CLKOUT
VFB
ITH
ISET
DIFFN
DIFFP
DIFFOUT
AVP
EXTVCC
PGOOD
ITEMP
GND
TK/SS
34
13
14
15
1
2
38
4
23
17
37
39
CLKOUT
VOSENSE
VOSENSE+
EXTVCC
PGOOD
ITEMP
SENSE1+
PLLIN
ILIM
FREQ
MODE
RUN
IFAST
SENSE1
SENSE2+
C21
1000pF
SENSE2
SENSE3+
C22
1000pF
SENSE3
C23
1000pF
LTC3829
DIFFOUT
S3N
13.5k
40.2k
1000Ω
TG1
SW1
BG1
TG2
SW2
BG2
TG3
SW3
BG3
D1 CMDSH-3
100k
40.2k
R26 100Ω
R25 100Ω
R24 100Ω
R23 100Ω
R22 100Ω
R21 100Ω
S3P
S2N
S2P
S1N
S1P
9
47pF
DIFFOUT
20.0k
30.1k
100pF
CSS
0.1µF
0.1µF
2.2Ω
0.1µF
1nF
5 6 7 8 11 12
18 16 10 35 36
25
3
PLLIN
VIN 24
INTVCC
33
32
31
30
BOOST1
TG1
SW1
BG1
INTVCC
VIN
RUN
MODE
4.7µF
16V
0.1µF
26
27
28
29
BOOST2
TG2
SW2
BG2 D3 CMDSH-3
0.1µF
19
20
21
22
BOOST3
TG3
SW3
BG3
Q1
VIN
10µF
16V
X5R
L1
0.33µH
RSENSE1
0.001Ω
RSENSE2
0.001Ω
RSENSE3
0.001Ω
Q3 Q4
100µF
6.3V
X5R
VOUT
330µF
2.5V
SANYO
×2
+
Q5
VIN
10µF
16V
X5R
S2P S2N
L2
0.33µH
Q1,Q5,Q9: RJK0305DPB
Q3,Q4,Q7,Q8,Q11,Q12: RJK0330DPB
Q7 Q8
100µF
6.3V
X5R
VOUT
1.5V
60A
GND
VOUT
VOSENSE
VOSENSE+
10Ω
VOUT
3829 TA02
330µF
2.5V
SANYO
×2
+
Q9
VIN
10µF
16V
X5R
L3
0.33µH
Q11 Q12
100µF
6.3V
X5R
330µF
2.5V
SANYO
×2
+
VIN
180µF
16V
VIN
7V TO 14V
GND
+
180µF
16V
+
S3P S3N
S1P S1N
10Ω
1.5V, 60A Converter Using Sense Resistors, fSW = 400kHz
LTC3829
37
3829fc
For more information www.linear.com/LTC3829
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
5.00 ± 0.10
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.50 REF
5.15 ± 0.10
7.00 ± 0.10
0.75 ± 0.05
R = 0.125
TYP
R = 0.10
TYP
0.25 ± 0.05
(UH) QFN REF C 1107
0.50 BSC
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 REF
3.15 ± 0.10
0.40 ±0.10
0.70 ± 0.05
0.50 BSC
5.5 REF
3.00 REF 3.15 ± 0.05
4.10 ± 0.05
5.50 ± 0.05 5.15 ± 0.05
6.10 ± 0.05
7.50 ± 0.05
0.25 ± 0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
LTC3829
38
3829fc
For more information www.linear.com/LTC3829
PACKAGE DESCRIPTION
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev A)
Exposed Pad Variation AA
4.75
(.187) REF
FE38 (AA) TSSOP 0608 REV A
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
119
20
REF
9.60 – 9.80*
(.378 – .386)
38
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.50
(.0196)
BSC 0.17 – 0.27
(.0067 – .0106)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.315 ±0.05
0.50 BSC
4.50 REF
6.60 ±0.10
1.05 ±0.10
4.75 REF
2.74 REF
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LTC3829
39
3829fc
For more information www.linear.com/LTC3829
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 03/13 Note 2 clarification, updated Phase Shedding Transition curves
Updated DIFFP, AVP, ITEMP pin functions and ∆VOUT equation
Updated schematic
5, 6
8, 9, 23
40
B 09/14 Clarification of Pin 37 call out
Last paragraph change from ISET to IFAST
2
25
C 11/14 Updated AVP pin function
Added text
Changed resistor value
8
25
36
LTC3829
40
3829fc
For more information www.linear.com/LTC3829
LINEAR TECHNOLOGY CORPORATION 2010
LT 1114 REV C • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC3829
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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4V ≤ VIN ≤ 30V, 0.8V ≤ VOUT ≤ 5.25V
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Controller, RSENSE or DCR Current Sensing and Tracking
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3mm × 3mm QFN-16, SSOP-16
LTC3775 High Frequency Synchronous Voltage Mode Step-Down
DC/DC Controller
Fast T
ransient Response, tON(MIN) = 30ns, 4V ≤ VIN ≤ 38V,
0.6V ≤ VOUT ≤ 0.8VIN, MSOP-16E, 3mm × 3mm QFN-16
LTC3878 No RSENSE Constant On-Time Synchronous Step-Down DC/DC
Controller, No RSENSE Required
Very Fast Transient Response, tON(MIN) = 43ns, 4V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 0.9VIN, SSOP-16
LTC3879 No RSENSE Constant On-Time Synchronous Step-Down DC/DC
Controller, No RSENSE Required
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0.6V ≤ VOUT ≤ 0.9VIN, MSOP-16E, 3mm × 3mm QFN-16
TYPICAL APPLICATION
1.2V/60A Triple Phase Converter with Active Voltage Positioning, fSW = 400kHz, RDROOP = 1.33mΩ
+
+
INTVCC
EXTVCC
ITEMP
BOOST1
BOOST2
BOOST3
RUN
ILIM
MODE
FREQ
ITH
TK/SS
SENSE1+
SENSE1
PGND
BG1
SW1
TG1
4.7µF
SW3 SW2 SW1
100k
75Ω
100Ω
0.1µF
220pF
10k
20k
20k
22µF
35V
×3
VIN
6V TO 14V
COUT1
330µF
4V
×6
COUT2
100µF
6.3V
×6
VOUT
1.2V
60A
SENSE2+
SENSE2
BG2
SW2
TG2
SENSE3+
SENSE3
BG3
CLKOUT
IFAST
SW3
TG3
SGND
DIFFOUT
AVP
ISET
VFB
DIFFN
DIFFP
PGOOD
0.3µH
VIN
VIN
0.001Ω
0.3µH 0.001Ω
0.3µH
3829 TA03
0.001Ω
VIN
LTC3829