APL5916 0.8V Reference Ultra Low Dropout (0.15V@7A) Linear Regulator Features General Description * The APL5916 is a 7A ultra low dropout linear regulator. This product is specifically designed to provide well sup- Ultra Low Dropout - 0.15V(typical) at 7A Output Current * ply volatage for motherboards and VGA card applications. The IC needs two supply voltages, a control voltage for Low ESR Output Capacitor (Multi-Layer Chip Capacitors (MLCC)) Applicable * 0.8V Reference Voltage * High Output Accuracy the circuitry, and a main supply voltage for power conversion, to reduce power dissipation and provide extremely low dropout. The APL5916 integrates many functions into a single - 1.5% over Line, Load, and Temperature * Fast Transient Response * Adjustable Output Voltage by External package. A Power-On-Reset (POR) circuit monitors both supply voltages to prevent wrong operations. Thermal Resistors * shutdown and current limit functions protect the device against thermal and current over-loads. POK indicates Power-On-Reset Monitoring on both VCNTL and VIN Pins * Internal Soft-Start * Current-Limit Protection * Under-Voltage Protection * Thermal Shutdown with Hysteresis * Power-OK Output with a Delay Time * Shutdown for Standby or Suspend Mode * Simple SOP-8P Package with Exposed Pad * that the output status with time delay which is set internally. It can control other converter for power sequence. The APL5916 can be enabled by other power system. Pulling and holding the EN pin below 0.3V shuts off the output. The APL5916 is available in SOP-8P package which features small size as SOP-8 and an Exposed Pad to reduce the junction-to-case resistance, being applicable in 2~ 2.6W applications. Lead Free and Green Devices Available (RoHS Compliant) Pin Configuration Applications * Note Book PC Applications * Motherboard Applications * VGA Card Applications GND FB VOUT VOUT 1 2 3 4 VIN 8 7 6 5 EN POK VCNTL VIN SOP-8P (Top View) = Exposed Pad (connected to the VIN plane for better heat dissipation) Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 1 www.anpec.com.tw APL5916 Ordering and Marking Information Package Code KA : SOP-8P Operating Ambient Temperature Range I : -40 to 85 oC Handing Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APL5916 Assembly Material Handling Code Temperature Range Package Code APL5916 XXXXX APL5916 KA : XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol VCNTL Parameter VCNTL Supply Voltage (VCNTL to GND) VIN VIN Supply Voltage (VIN to GND) VI/O EN and FB to GND VPOK POK to GND PD TJ TSTG TSDR (Note 1) Power Dissipation Rating Unit -0.3 ~ 7 V -0.3 ~ 3.9 V -0.3 ~ VCNTL+0.3 V -0.3 ~ 7 V 3 Junction Temperature Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds W 150 o -65 ~ 150 o 260 o C C C Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol JA JC Parameter Typical Value Junction-to-Ambient Thermal Resistance in Free Air (Note 2) SOP-8P Junction-to-Case Thermal Resistance (Note 3) SOP-8P Unit 38 o 14 o C/W C/W Note 2 : JA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of SOP-8P is soldered directly on the PCB. Note 3 : The "Thermal Pad Temperature" is measured on the PCB copper area connected to the thermal pad of package. 1 2 3 4 8 VIN 7 6 5 Measured Point PCB Copper Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 2 www.anpec.com.tw APL5916 Recommended Operating Conditions Symbol VCNTL VIN VOUT Parameter VCNTL Supply Voltage VIN Supply Voltage Output Voltage, VCNTL=5.05% Range Unit 4.5 ~ 6 V 1.0 ~ 3.5 V 0.8 ~ VIN-0.2 V IOUT VOUT Output Current 0~7 TJ Junction Temperature -40 ~ 125 A o C Electrical Characteristics Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.25V, VOUT = 1.05V and TA = -40 to 85C, unless otherwise specified. Typical values refer to TA = 25C. Symbol Parameter Test Conditions APL5916 Min. Typ. Max. Unit SUPPLY CURRENT ICNTL ISD VCNTL Supply Current EN = VCNTL, VFB is well regulated 0.4 1 2 mA VCNTL Shuntdown Current EN = GND - 280 380 A VCNTL Rising 2.7 2.9 3.1 V - 0.4 - V 0.8 0.9 1.0 - 0.5 - V - 0.8 - V POWER-ON-RESET VCNTL POR Threshold VCNTL POR Hysteresis VIN POR Threshold VIN Rising VIN POR Hysteresis OUTPUT VOLTAGE VREF Reference Voltage FB =VOUT o Output Voltage Accuracy IOUT=0A ~ 7A, TJ= -40~125 C -1.5 - +1.5 % Line Regulation VCNTL=4.5 ~ 6V -1.5 - +1.5 mV/V Load Regulation IOUT=0A ~ 7A - 0.06 0.15 % IOUT = 7A, VCNTL=5V, TJ= 25oC - 0.11 0.14 V IOUT = 7A, VCNTL=5V, TJ= -40~125oC - - 0.2 V DROPOUT VOLTAGE Dropout Voltage PROTECTION ILIM Current Limit TSD Thermal Shutdown Temperature VCNTL=5V, TJ= 25oC 8 10 12 A 7.2 - - A - 150 - o - 50 - o VFB Falling - 0.4 - VEN Rising 0.3 0.4 0.5 V - 30 - mV - 10 - A - 2 - ms VCNTL=5V, TJ= -40 ~ 125oC TJ Rising Thermal Shutdown Hysteresis Under-Voltage Threshold C C V ENABLE AND SOFT-START EN Logic High Threshold Voltage EN Hysteresis EN Pin Pull-Up Current TSS EN=GND Soft-Start Interval Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 3 www.anpec.com.tw APL5916 Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.25V, VOUT = 1.05V and TA = -40 to 85C, unless otherwise specified. Typical values refer to TA = 25C. Symbol Parameter Test Conditions APL5916 Min. Typ. Max. Unit POWER-OK AND DELAY VPOK POK Threshold Voltage for Power OK VFB Rising 90% 92% 94% VREF VPNOK POK Threshold Voltage for Power Not VFB Falling OK 79% 81% 83% VREF - 0.25 0.4 V 1 3 10 ms POK Low Voltage TDELAY POK sinks 5mA POK Delay Time Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 4 www.anpec.com.tw APL5916 Typical Operating Characteristics Reference Voltage vs. Junction Temperature VCNTL Supply Current vs. Junction Temperature 0.808 0.9 VCNTL = 5V 0.806 Reference Voltage, VREF (mV) VCNTL Supply Current, ICNTL (mA) 1.0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -50 0.804 0.802 0.800 0.798 0.796 0.794 0.792 -25 0 25 50 75 100 Junction Temperature (C) 125 -50 125 140 4.5 VCNTL = 5V, VOUT = 1.05V 4.3 120 VIN Dropout Voltage (mV) 4.1 POK Delay Time (ms) 0 25 50 75 100 Junction Temperature (C) VIN Dropout Voltage vs. Output Current POK Delay Time vs. Junction Temperature 3.9 VCNTL = 5V 3.7 3.5 3.3 3.1 2.9 2.7 100 TJ=125oC TJ=75oC 80 TJ=25oC 60 TJ=0oC 40 TJ=-25oC TTJ=50oC 20 2.5 0 -50 -25 0 25 50 75 100 Junction Temperature (C) 0 125 VIN Dropout Voltage vs. Output Current 2 3 4 5 Output Current, IOUT(A) 6 7 160 VCNTL = 5V, VOUT = 1.5V VCNTL = 5V, VOUT = 2.5V 140 VIN Dropout Voltage (mV) 120 100 TJ=125oC 80 o TJ=75 C TJ=25oC 60 TJ=0oC 40 TJ=-25oC TTJ=50oC 20 0 1 VIN Dropout Voltage vs. Output Current 140 VIN Dropout Voltage (mV) -25 120 TJ=125oC 100 TJ=75oC 80 TJ=25oC 60 TJ=0oC TJ=-25oC 40 TTJ=50oC 20 0 0 1 2 3 4 5 Output Current, IOUT(A) Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 6 0 7 5 1 2 3 4 5 Output Current, IOUT(A) 6 7 www.anpec.com.tw APL5916 Typical Operating Characteristics (Cont.) VIN PSRR vs. Frequency Current-Limit vs. Junction Temperature 10 20 9.9 10 0 VCNTL = 5V 9.7 -10 9.6 VIN PSRR POK Delay Time (ms) 9.8 VINPK-PK = 50mV VCNTL = 5V, VIN = 1.25V VOUT = 1.05V, COUT = 22mF 9.5 9.4 -20 -30 9.3 -40 9.2 -50 9.1 IOUT = 1A IIOUT = 3A IOUT = 5A -60 9 -50 -25 0 25 50 75 100 -70 125 Junction Temperature (C) IIOUT = 7A 1000 10000 100000 1000000 Frequency(Hz) VCNTL PSRR vs. Frequency 0 -10 -20 VCNTL PSRR -30 VCNTL = 5V IOUT = 3A VIN = 1.25V I = 1A OUT VOUT = 1.05V COUT = 22F VCNTLPK-PK = 50mV -40 -50 -60 -70 -80 1000 IOUT = 5A IOUT = 7A 10000 100000 Frequency(Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 1000000 6 www.anpec.com.tw APL5916 Operating Waveforms 1. Load transient Response 1.1 Using an Output Capacitor with ESR18m - COUT = 150F/6.3V (ESR = 25m), CIN = 22F/6.3V - IOUT = 10mA to 7A to 10mA, Rise time = Fall time = 5s IOUT = 10mA -> 7A IOUT = 10mA -> 7A ->10mA IOUT = 7A -> 10mA R1=1k, R2=3.2k, C1=33nF VOUT 1 VOUT 1 1 VOUT IOUT IOUT IOUT 2 2 CH1 : VOUT, 50mV/Div CH2 : IOUT, 2A/Div Time : 5s/Div 2 CH1 : VOUT, 50mV/Div CH2 : IOUT, 2A/Div Time : 100s/Div CH1 : VOUT, 50mV/Div CH2 : IOUT, 2A/Div Time : 5s/Div 1.2 Using an MLCC as the Output Capacitor - COUT = 22F/6.3V (ESR = 3m), CIN = 22F/6.3V - IOUT = 10mA to 7A to 10mA, Rise time = Fall time = 5s IOUT = 10mA -> 7A IOUT = 10mA -> 7A ->10mA IOUT = 7A -> 10mA R1=124k, R2=396.8k, C1=36pF VOUT 1 1 VOUT VOUT 1 IOUT IOUT IOUT 2 2 CH1 : VOUT, 100mV/Div CH2 : IOUT, 2A/Div Time : 5s/Div Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 2 CH1 : VOUT, 100mV/Div CH2 : IOUT, 2A/Div Time : 100s/Div 7 CH1 : VOUT, 100mV/Div CH2 : IOUT, 2A/Div Time : 5s/Div www.anpec.com.tw APL5916 Operating Waveforms (Cont.) 2. Power ON and Power OFF - VIN = 1.25V, VCNTL = 5V,VOUT = 1.05V - COUT = 22F/6.3V (ESR = 3m), CIN = 22F/6.3V Power ON Power OFF VIN VIN 1 1 VOUT VOUT 2 2 VCNTL VCNTL VPOK VPOK VPOK 3 3 4 4 CH1 : VIN, 1V/div CH2 : VOUT, 1V/div CH3 : VPOK, 1V/div CH4 : VCNTL, 2V/div Time: 5ms/div CH1 : VIN, 1V/div CH2 : VOUT, 1V/div CH3 : VPOK, 1V/div CH4 : VCNTL, 2V/div Time: 500ms/div 3. Shutdown and Enable - VIN = 1.25V, VCNTL = 5V,VOUT = 1.05V - COUT = 22F/6.3V (ESR = 3m), CIN = 22F/6.3V Enable 1 2 Shutdown VEN VEN 1 VOUT VOUT 2 VPOK 4 VPOK 3 3 IOUT CH1 : VEN, 5V/div CH2 : VOUT, 1V/div CH3 : VPOK, 1V/div CH4 : IOUT, 2A/div Time: 1ms/div Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 IOUT 4 CH1 : VEN, 5V/div CH2 : VOUT, 1V/div CH3 : VPOK, 1V/div CH4 : IOUT, 2A/div Time: 10s/div 8 www.anpec.com.tw APL5916 Operating Waveforms (Cont.) 4. POK Delay - VIN = 1.25V, VCNTL = 5V,VOUT = 1.05V - COUT = 22F/6.3V (ESR = 3m), CIN = 22F/6.3V 1 VIN VOUT 2 3 VPOK POK Delay CH1 : VIN, 1V/div CH2 : VOUT, 1V/div CH3 : VPOK, 1V/div Time: 2ms/div Block Diagram EN VCNTL VIN Power-OnReset UV Soft-Start and Control Logic Thermal Limit 0.4V VREF 0.8V EAMP VOUT FB Current Limit POK Delay GND 90% VREF POK Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 9 www.anpec.com.tw APL5916 Typical Application Circuit 1. Using an Output Capacitor with ESRl18m VCNTL +5V CCNTL 1F 6 R3 1k VCNTL 7 POK VIN POK VOUT VOUT APL5916 8 EN EN FB 5 3 4 VOUT +1.05V / 7A COUT 150F 2 R1 1k GND Enable VIN +1.25V CIN 22F 1 R2 3.2k C1 33nF (in the range of 12 ~ 48nF) 2. Using an MLCC as the Output Capacitor VCNTL +5V CCNTL 1F 6 R3 1k VCNTL 7 POK VIN POK VOUT VOUT 8 EN APL5916 EN FB 5 3 4 VOUT +1.05V / 7A COUT 22F 2 GND Enable 1 R2 396.8k R1 124k C1 36pF COUT (F) 22 44 VOUT (V) 1.2 1.5 1.8 1.05 1.2 1.5 1.8 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 VIN +1.25V CIN 22F R1 (k) 120 120 105 240 187 180 162 10 R2 (k) 240 137.14 184 768 374 205.71 129.6 22F/ ECJ3YBOJ226M Panasonic GRM21BR60J226M Murata C1 (pF) 36 39 39 39 47 47 47 www.anpec.com.tw APL5916 Typical Application Circuit (Cont.) R4 C2 1F +5V 5 R8 8.2k C8 470pF 7 BOOT Shutdown 6 PHASE U2 APW7057 FB LGATE C4 470F x2 C9 47F 1 OCSET UGATE C3 1F D1 1N4148 VCC Q3 L1 1H 2.2 2 C6 0.1F Q1 APM2014N L2 3.3H VIN +1.25V 8 GND R5 1.125k 3 R7 2k Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 C7 0.1F EN Enable POK 6 VCNTL 5 CIN 22F C5 1000F x2 Q2 APM2014N 4 VCNTL +5V CVCNTL 1F 8 VIN POK 7 3 VOUT 4 VOUT U1 APL5916 2 EN FB GND R2 1 3.2k R3 1k VOUT +1.05V/7A COUT 150F R1 1k C1 33nF R6 0 11 www.anpec.com.tw APL5916 Pin Description GND (Pin 1) EN (Pin 8) Ground pin of the circuitry. All voltage levels are mea- Enable control pin. Pulling and holding this pin below 0. 3V shuts down the output. When re-enabled, the IC un- sured with respect to this pin. FB (Pin 2) dergoes a new soft-start cycle. When leave this pin open, an internal current source 10A pulls this pin up to VCNTL Connecting this pin to an external resistor divider receives voltage, enabling the regulator. the feedback voltage of the regulator. The output voltage set by the resistor divider is determined by: V OUT = 0.8 1 + R1 R2 (V) where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB to GND. A bypass capacitor may be connected with R1 in parallel to improve load transient response. VOUT (Pin 3, 4) Output of the regulator. Please connect Pin 3 and 4 together using wide tracks. It is necessary to connect a output capacitor with this pin for closed-loop compensation and improving transient response. VIN (Pin 5) and Exposed Pad Main supply input pins for power conversions. The Exposed Pad provides a very low impedance input path for the main supply voltage. Please tie the Exposed Pad and VIN Pin (Pin 8) together to reduce the dropout voltage. The voltage at this pins is monitored for Power-On-Reset purpose. VCNTL (Pin 6) Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On-Reset purpose. POK (Pin 7) Power-OK signal output pin. This pin is an open-drain output used to indicate status of output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not above the VPOK threshold or the falling FB voltage is below the VPNOK threshold, indicating the output is not OK. Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 12 www.anpec.com.tw APL5916 Function Description Power-On-Reset A Power-On-Reset (POR) circuit monitors both input volt- after the junction temperature cools by 50C, resulting in ages at VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates that a soft-start pro- a pulsed output during continuous thermal overload conditions. The thermal shutdown is designed with a cess after the two supply voltages exceed their rising POR threshold voltages during powering on. The POR 50oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, ex- function also pulls low the POK pin regardless the output voltage when the VCNTL voltage falls below it's falling tending lifetime of the device. For normal operation, device power dissipation should POR threshold. Internal Soft-Start be externally limited, so junction temperatures will not exceed +125C. An internal soft-start function controls rise rate of the out- Enable Control put voltage to limit the current surge at start-up. The typical soft-start interval is about 2ms. The APL5916 has a dedicated enable pin (EN). A logic low signal (VEN< 0.3V) applied to this pin shuts down the output. Following a shutdown, a logic high signal re-en- Output Voltage Regulation ables the output through initiation of a new soft-start cycle. Left open, this pin is pulled up by an internal current source An error amplifier working with a temperature-compensated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier is designed (10A typical) to enable operation. It's not necessary to use an external transistor to save cost. with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the Power-OK and Delay reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load The APL5916 indicates the status of the output voltage by monitoring the feedback voltage (VFB) on FB pin. As the current from VIN to VOUT. VFB rises and reaches the rising Power-OK threshold (VPOK), an internal delay function starts to perform a de- Current-Limit lay time. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate the output is OK. As The APL5916 monitors the current via the output NMOS and limits the maximum current to prevent load and APL5916 from damages during overload or short-circuit the VFB falls and reaches the falling Power-OK threshold (VPNOK), the IC immediately turns on the NMOS of the conditions. POK to indicate the output is not OK without a delay time. Under-Voltage Protection (UVP) The APL5916 monitors the voltage on FB pin after softstart process is finished. Therefore, the UVP is disable during soft-start. When the voltage on FB pin falls below the under-voltage threshold, the UVP circuit shuts off the output immediately. After a while, the APL5916 starts a new soft-start to regulate output. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5916. When the junction temperature exceeds +150C, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 13 www.anpec.com.tw APL5916 Application Information Power Sequencing The power sequencing of VIN and VCNTL is not necessary to be concerned. But do not apply a voltage to VOUT can all be used as an input capacitor of VIN. For most applications, the recommended input capacitance of VIN for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic diode from is 10F at least. If the drop of the input voltage is not cared, the input capacitance can be less than 10F. More VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. capacitance reduces the variations of the input voltage of VIN pin. Output Capacitor Feedback Network The APL5916 requires a proper output capacitor to Figure 1 shows the feedback network between VOUT, GND, and FB pins. It works with the internal error amplifier maintain stability and improve transient response over temperature and current. The output capacitor selection to provide proper frequency response for the linear regulator. The ESR is the equivalent series resistance of is to select proper ESR (equivalent series resistance) and capacitance of the output capacitor for good stability the output capacitor. The COUT is ideal capacitance in the output capacitor. The VOUT is the setting of the output and load transient response. The APL5916 is designed with a programmable feedback voltage. compensation adjusted by an external feedback network for the use of wide ranges of ESR and capacitance in all applications. Ultra-low-ESR capacitors (such as ceramic chip capacitors), low-ESR bulk capacitors (such as solid VOUT VOUT APL5916 Tantalum, POSCap, and Aluminum electrolytic capacitors) all can be used as an output capacitor. The value of the R1 output capacitors can be increased without limit. During load transients, the output capacitors, depending ESR FB VERR VFB EAMP VREF on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by C1 the APL5916 and help the device to minimize the variations of output voltage for good transient response. For the COUT R2 Figure 1 applications with large stepping load current, the lowESR bulk capacitors are normally recommended. The feedback network selection depends on the values Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the ESR and COUT, which has been classified into three conditions: of the layout must be minimized. * Condition 1 : Large ESR ( 18m ) Input Capacitor The APL5916 requires proper input capacitors to supply - Select the R1 in the range of 400 ~ 2.4k - Calculate the R2 as the following equation : current surge during stepping load transients to prevent the input rail from dropping. Because the parasitic induc- R2(k) = R1(k) tor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents, more - Calculate the C1 as the following equation : parasitic inductance needs more input capacitance. 10 Ultra-low-ESR capacitors (such as ceramic chip 0.8(V) .......... (1) VOUT(V) - 0.8(V) VOUT(V) VOUT(V) C1(nF) 40 ...... (2) R1(k) R1(k ) capacitors), low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 14 www.anpec.com.tw APL5916 Application Information (Cont.) Feedback Network (Cont.) Where R1=R1(calculated) from equation (6) If the C1(calculated) can not meet the equation (8), * Condition 2 : Middle ESR - Calculate the R1 as the following equation : R1(k ) = please use the Condition 2. - Use equation (2) to calculate the R2. 6000 - 37.5 VOUT(V) + 30 ......... (3) ESR(m ) The reason to have three conditions described above is to optimize the load transient responses for all kinds of Select a proper R1(selected) to be a little larger than the calculated R1. the output capacitor. For stability only, the Condition 2, regardless of equation (5), is enough for all kinds of output - Calculate the C1 as the following equation: capacitor. C1(pF) = [ESR(m ) + 200] PCB Layout Consideration (See Figure 2) COUT( F) ........ (4) R1(k ) 1. Please solder the Exposed Pad and VIN together on the PCB. The main current flow is through the exposed Where R1=R1(selected) Select a proper C1(selected) to be a little smaller than the calculated C1. pad. 2. Please place the input capacitors for VIN and VCNTL - The C1 calculated from equation (4) must meet the following equation: pins near pins as close as possible. 3. Ceramic decoupling capacitors for load must be placed 37.5 V OUT(V) 200 C1 (pF) 5 . 1 1 + 1+ .. (5) R1 (k ) ESR (m ) near the load as close as possible. 4. To place APL5916 and output capacitors near the load Where R1=R1(calculated) from equation (3) is good for performance. 5. The negative pins of the input and output capaci-tors If the C1(calculated) can not meet the equation (5), please use the Condition 3. and the GND pin of the APL5916 are connected to the ground plane of the load. - Use equation (2) to calculate the R2. * Condition 3 : Low ESR (eg. Ceramic Capacitors) 6. Please connect PIN 3 and 4 together by a wide track. 7. Large current paths must have wide tracks. - Calculate the R1 as the following equation: 8. See the Typical Application (see next page Figure 2) R1 (k ) = (5.9 ESR (m ) + 1175 ) COUT( F) - 37.5 VOUT(V) .. (6) - Connect the one pin of the R2 to the GND of APL5916 - Connect the one pin of R1 to the Pin 3 of APL5916 Select a proper R1(selected) to be a little larger than the calculated R1. The minimum selected R1 is equal to 1k when the calculated R1 is smaller - Connect the one pin of C1 to the Pin 3 of APL5916 than 1k or negative. - Calculate the C1 as the following equation: V CNTL C CNTL 37.5 VOUT(V) C1(pF) = (0.17 ESR(m ) + 34) COUT( F) 1 + .. (7) R1(k ) C IN VCNTL V IN VIN APL5916 Where R1=R1(selected) Select a proper C1(selected) to be a little smaller V OUT VOUT C OUT VOUT than the calculated C1. - The C1 calculated from equation (7) must meet the C1 FB following equation : R1 Load GND R2 1.25 VOUT(V) C1(pF) 0.033 + ESR(m ) COUT(F) .. (8) R1(k ) Figure 2 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 15 www.anpec.com.tw APL5916 Application Information (Cont.) Thermal Consideration See Figure 3. The SOP-8P is a cost-effective package featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications. The exposed pad must be soldered to the top VIN plane. The copper of the VIN plane on the Top layer conducts heat into the PCB and air. Please enlarge the area to reduce the case-to-ambient resistance (CA). 102 mil 118 mil 1 8 2 7 SOP-8P 3 6 5 4 Top VOUT plane Die Exposed Pad Top VIN plane Ambient Air PCB Figure 3 Recommended Minimum Footprint 8 7 6 5 0.072 0.024 0.118 0.212 0.138 1 2 0.050 3 4 Unit : Inch Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 16 www.anpec.com.tw APL5916 Package Information SOP-8P D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE L VIEW A S Y M B O L SOP-8P MILLIMETERS MIN. MAX. A A1 INCHES MIN. MAX. 1.60 0.063 0.000 0.15 0.00 0.006 0.049 A2 1.25 b 0.31 0.51 c 0.17 0.25 0.007 0.010 0.197 0.012 0.020 D 4.80 5.00 0.189 D1 2.50 3.50 0.098 0.138 E 5.80 6.20 0.228 0.244 0.157 0.118 E1 3.80 4.00 0.150 E2 2.00 3.00 0.079 0.020 e 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 L 0.40 1.27 0.016 0.050 0o C 8oC 0 0oC 8o C Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 17 www.anpec.com.tw APL5916 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-8P A H T1 C d D 330.02.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 2.00.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.400.20 5.200.20 2.100.20 4.00.10 8.00.10 W E1 12.00.30 1.750.10 F 5.50.05 (mm) Devices Per Unit Package Type Unit Quantity SOP-8P Tape & Reel 2500 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 18 www.anpec.com.tw APL5916 Taping Direction Information SOP-8P USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 19 www.anpec.com.tw APL5916 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 C 150 C 60-120 seconds 150 C 200 C 60-120 seconds 3 C/second max. 3C/second max. 183 C 60-150 seconds 217 C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 C/second max. 6 C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm Volume mm <350 235 C 220 C 3 Volume mm 350 220 C 220 C 3 Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C 3 Volume mm 350-2000 260 C 250 C 245 C 3 Volume mm >2000 260 C 245 C 245 C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 20 Description 5 Sec, 245C 1000 Hrs, Bias @ 125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBM2KV VMM200V 10ms, 1tr100mA www.anpec.com.tw APL5916 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Jan., 2010 21 www.anpec.com.tw