LC74986NWF - Sanyo Semiconductor

SANYO Electric Co.,Ltd. Semiconductor Company

TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

Ordering number : ENN7713

40804TN (OT) No.7713-1/15

Overview

The LC74986NWF and LC74986NWV are video signal processing ICs that perform resolution conversion, interlaced

to progressive scan (IP) conversion, and image quality improvement without requiring the use of external field (frame)

memory. These ICs can display a wide variety of video signals and formats on a flat panel display. These ICs also

provide image quality improvement and adjustment functions to create the optimal image quality for the flat panel

display used. They also include an OSD function that displays characters with the sizes optimal for the size of panel

used. A flat panel TV monitor with the necessary video signal processing circuits can be formed easily by combining

one of these ICs with a video decoder, A/D converters, a microcontroller, and an LCD panel.

Features

• Multi-source support

— NTSC, PAL, and DTV (480i and 480p) inputs

— Progressive scan inputs up to XGA (The LC74986NWV supports up to SVGA.)

— Supports both RGB and YCbCr (4:4:4 24 bits, 4:2:2 16 bits or 8 bits) inputs (built-in YCbCr to RGB converter).

• Resolution conversion

— Independent horizontal and vertical expansion and reduction in the horizontal direction

— Interlaced to progressive scan conversion

• Image quality correction

— Sharpness, color, tint, white/black stretch, brightness, contrast, white balance, black balance

— Built-in lookup table based gamma correction circuit (Common characteristics for each 8-bit RGB value can be

programmed.)

• Panel interface

— Single RGB 24-bit or 18-bit, or dual RGB 48-bit or 36-bit signal output (built-in dither processing)

— Horizontal sync signal, vertical sync signal, data enable signal, and pixel clock outputs

• Other features

— No external frame memory required (The input and output have the same frame period.)

— Built-in OSD function (510 characters, 8 colors, built-in 8-character font RAM)

—I

C bus interface (The OSD function can also be controlled over a 3-wire bus.)

— Low-power design

IC Specifications

• Supply voltage: I/O: 3.3V, core: 2.5V (LC74986NWF) or 1.8V (LC74986NWV) dual power supply system

• Maximum operating frequency: 85MHz (LC74986NWF), 40MHz (LC74986NWV)

• Package: 144-pin SQFP

SANYO Semiconductors

DATA SHEET

LC74986NWF

LC74986NWV CMOS IC

LCD TV Scan Converter IC

Any and all SANYO products described or contained herein do not have specifications that can handle

applications that require extremely high levels of reliability, such as life-support systems, aircraft's

control systems, or other applications whose failure can be reasonably expected to result in serious

physical and/or material damage. Consult with your SANYO representative nearest you before using

any SANYO products described or contained herein in such applications.

SANYO assumes no responsibility for equipment failures that result from using products at values that

exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other

parameters) listed in products specifications of any and all SANYO products described or contained

herein.

No.7713-2/15

LC74986NWF, 74986NWV

Applications

• LCD TVs and LCD monitors

• Car TVs and car monitors

• PDP TVs

Specifications

Absolute Maximum Ratings at Ta = 25°C, DVSS = 0V, AVSS = 0V. Values in parentheses apply to the

LC74986NWV. These are provisional specifications for the LC74986NWF.

Parameter Symbol Conditions Ratings Unit

Maximum supply voltage VDD1–0.3 to +3.6 V

VDD2–0.3 to +4.6 V

Input voltage VI–0.3 to VDD2+0.3 V

Output voltage VO–0.3 to VDD2+0.3 V

Allowable power dissipation Pd max TBD (0.6) W

Storage temperature Tstg –55 to +125 °C

Operating temperature Topr –30 to +70 °C

Allowable Operating Ranges at Ta = –30 to +70°C. Values in parentheses apply to the LC74986NWV. These are

provisional specifications for the LC74986NWF.

*: Certain input pins have built-in pull-down resistors. Thus there are cases where, due to the circuit structure, the quiescent current characteristics cannot

be guaranteed.

Parameter Symbol Conditions Ratings Unit

min typ max

Supply voltage VDD1DVDD12.3 (1.7) 2.5 (1.8) 2.7 (1.9) V

VDD2DVDD2, AVDD 3.0 3.3 3.6 V

Input voltage range VIN 0 3.6 V

DC Characteristics at VDD1 = 2.5V (LC74986NWF) or 1.8V (LC74986NWV), VDD2 = 3.3V, Ta = –30 to +70°C.

These are provisional specifications for the LC74986NWF.

Parameter Symbol Conditions Ratings Unit

min typ max

Input high-level voltage VIH CMOS level inputs 0.7VDD2 V

CMOS level Schmitt inputs 0.75VDD2 V

Input low-level voltage VIL CMOS level inputs 0.2VDD2 V

CMOS level Schmitt inputs 0.15VDD2 V

Input high-level current IIH VI=VDD2–10 +10 µA

VI= VDD2, with a pull-down resistor used +10 +100 µA

Input low-level current IIL VI=VSS –10 +10 µA

B4 type, IOH=–2mA VDD2–0.4 V

Output high-level voltage VOH B8 type, IOH=–4mA VDD2–0.4 V

B12 type, IOH=–6mA VDD2–0.4 V

B4 type, IOL=2mA 0.4 V

Output low-level voltage VOL B8 type, IOL=4mA 0.4 V

B12 type, IOL=6mA 0.4 V

Output leakage current IOZ In high-impedance output mode –10 +10 µA

Pull-down resistance RDN 126 kΩ

Quiescent current IDD1Outputs open, VI=VSS or VDD1300 µA

Quiescent current* IDD2Outputs open, VI=VSS or VDD210 µA

No.7713-3/15

LC74986NWF, 74986NWV

20.0

22.0

20.0

22.0

0.145

0.2

0.5

(1.25)

0.5

1 36

73108

109

144

(1.4)

1.6max

0.1

Package Dimensions

unit : mm

3214

SANYO : SQFP144

Input and Output Signals

• Input Signals Items shown in parentheses are alternate functions that can be selected by setting a register.

Signal type Number of pins Symbol Description Notes

• 24-bit RGB

• 24-bit YCbCr, 16-bit or 8-bit 4:2:2

Video signals

8 VPA1 Input port A

• The input polarity is arbitrary. The IC discriminates

the polarity automatically.

• The input polarity is arbitrary. The IC discriminates

the polarity automatically.

• The input polarity is arbitrary. The IC discriminates

the polarity automatically.

•

The pin can be selected by setting an internal register.

Sync signals

HSI

VSI

VPBH

VPBV

(AICS/PDOWN2)

8 VPA2

8 VPA3

8 VPB1 (ROUT_2) Input port B

(External video or dual output)

Port A system horizontal sync signal

Port A system vertical sync signal

Port B system horizontal sync signal

Port B system vertical sync signal

(Three-wire bus chip select, power

down)

8 VPB2 (GOUT_2)

8 VPB3 (BOUT_2)

• The input polarity is arbitrary. It can be inverted

internally.

• DEVI must be held fixed at 1 when a composite

video signal is input.

Data enable signals

DEHI Port A system horizontal data

enable, port A system composite

enable

• The input polarity is arbitrary. It can be inverted

internally.

DEVI Port A system vertical data enable1

• Only H/V composite signals are supported.

• The input polarity is arbitrary. It can be inverted

internally.

VPBDEN

(VPBEN)

Port B system composite data

enable

(External video enable)

Continued on next page.

No.7713-4/15

LC74986NWF, 74986NWV

Continued from preceding page.

Signal type Number of pins Symbol Description Notes

• Max85MHz(LC74986NWF),

Max40MHz(LC74986NWV)

Pixel clock

Clock enable

1 CLKI Port A system clock

• Max85MHz(LC74986NWF),

Max40MHz(LC74986NWV)

1 DCLKI Display clock

• Max85MHz(LC74986NWF),

Max40MHz(LC74986NWV)

1 VPBCK Port B system clock

• Positive logic1 CLKIEN Port A system clock enable

Fixed oscillator • Max85MHz(LC74986NWF),

Max40MHz(LC74986NWV)

1 XTAL Used for the control bus and

various detection functions

System reset • Inverted logic1 RST System reset

External video

• Inputs a video signal synchronized with the output

• Dither processing possible. Image quality

adjustments not possible.

• 6-bit input also possible

• Positive logic

8 VPB1

8 VPB2

8 VPB3

1VPBEN

(VPBDEN)

External video signal

(input port B, dual output)

External video signal enable

(port B system composite data

enable)

• Output Signals

Signal type Number of pins Symbol Description Notes

• Dithered 6-bit output also possible

•

Dual output also possible. (Odd/even inversion possible)

• First data

• Dedicated dual system output. (Odd/even inversion

possible)

• Second data

• The sync signal, position, and polarity can be set.

• The polarity can be set.

Video signals

Sync signals

Data enable signals

Pixel clocks

Clamp pulse

8 ROUT R

8 GOUT G

8 BOUT B

8 ROUT_2 (VPB1)

8 GOUT_2 (VPB2)

8 BOUT_2 (VPB3)

HSO

VSO

DEHO

DEVO

Dual output

(input port B, external video

signal)

Horizontal sync signal

Vertical sync signal, composite signal

Horizontal data enable

Vertical data enable, composite enable

• The polarity can be inverted.1 CLKIO Outputs the input clock

• The polarity can be inverted. Divided-by-two output

possible in dual output mode.

1 DCLKO Display clock

• Output at the clamp position. The position can be

changed. The pulse width can be changed.

1 CLPP Used for A/D conversion

Clamp levels

Divided output

signal for external

PLL circuit

• Clamp level discrimination output

(Too large: low, too small: high, match: high

impedance)

1 CLPVPA1 VP1 clamp level

1 CLPVPA2 VP2 clamp level

1 CLPVPA3 VP3 clamp level

1 PLLHIO For an external PLL circuit

No.7713-5/15

LC74986NWF, 74986NWV

• Control Signals

Signal type Number of pins Symbol Description Notes

• For OSD control (Normally, the I2C bus is used.)

• Used for setting internal registers and for internal

status output.

• The slave address is 0111000 + (R/W)

• OSD control, gamma correction control

• Normally low. 0111000 + (R/W)

• Switches the IC to 0111001 + (R/W) when high.

Three-wire bus

signals

I2C bus signals

1 AICS (VPBV)

1 AIDA

Three-wire bus chip select (port B

system vertical sync signal)

Data bus

1 AICK Bus clock

1 SDA Data bus

1 SCL Bus clock

1I2CSEL Slave switching

• Other Signals

Signal type Number of pins Symbol Description Notes

• The output can be forcibly muted from this pin.

Inverted logic

Forcible mute

signal 1 MUTE Muting

• Low-power mode used when the IC is not operating.

This pin is normally held at the high level.

Power down (low-

power mode) signal 2PDOWN1

PDOWN2 (VPBV)

Low-power mode

(Port B system vertical sync signal)

• Used for test settings. This pin must be held at the

low level during normal operation.

Test signals

1 SCANEN

Test

• Used for test settings. This pin must be held at the

low level during normal operation.

1 SCANMOD

Test

• Used for test settings. This pin must be held at the

low level during normal operation.

5 TEST

Test

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LC74986NWF, 74986NWV

Pin Assignments

DVSS

PLLHIO

CLKIO

CLKIEN

CLKI

AVDD

AVSS

VCOCNT1

VCORNG1

PDO1

DVDD1

DVSS

SDA

SCL

I2CSEL

MUTE

AICS (VPBV)

AIDA

AICK

RST

PDOWN1

PDOWN2 (VPBV)

DVDD1

DVSS

XTAL

DCLKI

DVDD1

DVSS

VPBCK

DVDD1

DVSS

DCLKO

VPBH

DVDD1

DVSS

VPA17

VPA16

VPA15

VPA14

VPA13

VPA12

VPA11

VPA10

VPA27

VPA26

VPA25

VPA24

VPA23

VPA22

VPA21

VPA20

DVDD2

DVSS

VPA37

VPA36

VPA35

VPA34

VPA33

VPA32

VPA31

VPA30

CLPVPA1

CLPVPA2

CLPVPA3

CLPP

VSI

HSI

DEVI

DEHI

DVDD2

BOUT7

BOUT6

BOUT5

BOUT4

BOUT3

BOUT2

BOUT1

BOUT0

DVSS

DVDD2

GOUT7

GOUT6

GOUT5

GOUT4

GOUT3

GOUT2

GOUT1

GOUT0

DVSS

DVDD2

ROUT7

ROUT6

ROUT5

ROUT4

ROUT3

ROUT2

ROUT1

ROUT0

DVSS

DVDD2

VSO

HSO

DEVO

DEHO

DVSS

DVDD1

VPB30 (BOUT0_2)

VPB31 (BOUT1_2)

VPB32 (BOUT2_2)

VPB33 (BOUT3_2)

VPB34 (BOUT4_2)

VPB35 (BOUT5_2)

VPB36 (BOUT6_2)

VPB37 (BOUT7_2)

VPB20 (GOUT0_2)

VPB21 (GOUT1_2)

VPB22 (GOUT2_2)

VPB23 (GOUT3_2)

VPB24 (GOUT4_2)

VPB25 (GOUT5_2)

VPB26 (GOUT6_2)

VPB27 (GOUT7_2)

DVSS

DVDD1

VPB10 (ROUT0_2)

VPB11 (ROUT1_2)

VPB12 (ROUT2_2)

VPB13 (ROUT3_2)

VPB14 (ROUT4_2)

VPB15 (ROUT5_2)

VPB16 (ROUT6_2)

VPB17 (ROUT7_2)

VPBEN (VPBDEN)

TEST4

TEST3

TEST2

TEST1

TEST0

SCANMOD

SCANEN

DVSS

109

110

115

120

125

130

135

140

144

108

105

100

LC74986NWF

LC74986NWV

Top view

No.7713-7/15

LC74986NWF, 74986NWV

Pin Symbol I/O and type Function Notes

number I/O Type

1 DVSS P — Digital system ground

2 PLLHIO O gqcio19 Input or external PLL divided clock output The divider ratio can be set over the I2C bus.

3 CLKIO O gqcio20 Outputs the input clock Has the same period as the input system. The output can be

inverted by a setting controllable over the I2C bus.

4 CLKIEN I gqcio02 Port A system input clock enable This input is normally held fixed at the high level. (Positive

logic.)

5 CLKI I gqcio02 Port A system input clock Input signal pixel clock

6 AVDD P — Analog system power supply: 3.3V Connect to DVDD2 if unused.

7 AVSS P — Analog system ground

8 VCOCNT1 I gqcio10 PLL VCO control voltage input Connect to AVSS if unused.

9 VCORNG1 I gqcio10 PLL range setting resistor connection Connect to AVSS if unused.

10 PDO1 O gqcio09 PLL phase comparator output Leave open if unused.

11 DVDD1 P — Digital system power supply: 2.5V (1.8V)

12 DVSS P — Digital system ground

13 SDA B gqcio22 I2C bus data

Used for setting internal registers and for reading out IC status.

14 SCL I gqcio03 I2C bus clock Also used for OSD control and gamma correction settings.

15 I2CSEL I gqcio18 I2C bus slave address switching Normally left open (slave address: 70h) or connected to

DVSS.

16 MUTE I gqcio02 Muting control Inverted logic

17 AICS (VPBV) I gqcio03 Chip select or port B system vertical sync Three-wire bus: use is optional.

signal Only used for OSD control (Normally, the I2C bus is used.)

18 AIDA I gqcio03 Data The AICS pin uses inverted logic.

19 AICK I gqcio03 Clock VPBP can be used by setting a register.

20 RST I gqcio03 Initial reset Inverted logic

21 PDOWN1 I gqcio02 Power down Normally held fixed at the high level (Used for testing.)

PDOWN2 (VPBV)

I gqcio03 Power down or port B system vertical sync (Used for testing.) VPBV can be used by setting a register.

signal

23 DVDD1 P — Digital system power supply: 2.5V (1.8V)

24 DVSS P — Digital system ground

25 XTAL I gqcio02 Clock input for the detection functions Connection for the fixed-frequency oscillator

26 DCLKI I gqcio02 Display clock input Display processing pixel clock

27 DVDD1 P — Digital system power supply: 2.5V (1.8V)

28 DVSS P — Digital system ground

29 DVSS P — Digital system ground

30 DVSS P — Digital system ground

31 VPBCK I gqcio02 Port B system input clock Port B system input signal pixel clock

32 DVDD1 P — Digital system power supply: 2.5V (1.8V)

33 DVSS P — Digital system ground

34 DCLK0 O gqcio20 LCD panel module clock output Has the same period as DCLKI.

Alternatively, may have 1/2 the period.

35 VPBH I gqcio03 Port B system horizontal sync signal Port B system input horizontal sync signal

36 DVDD1 P — Digital system power supply: 2.5V (1.8V)

37 DVSS P — Digital system ground

38 DEHO O gqcio19 FPD module horizontal enable The polarity can be selected over the I2C bus.

39 DEVO O gqcio19 FPD module vertical enable A composite signal can be output from DEVO.

40 HSO O gqcio19 FPD module horizontal sync signal The polarity and pulse width can be set over the I2C bus.

41 VSO O gqcio19 FPD module vertical sync signal A composite sync signal can be output from VSO.

42 DVDD2 P — Digital system power supply: 3.3V

43 DVSS P — Digital system ground

44 ROUT0 O gqcio19 FPD module R output LSB

45 ROUT1 O gqcio19 (The ROUT5:0 pins are used for 6-bit output.)

46 ROUT2 O gqcio19 When 2-phase output is used, the first byte is data.

47 ROUT3 O gqcio19 (MSB when 6-bit output is selected)

48 ROUT4 O gqcio19

49 ROUT5 O gqcio19

50 ROUT6 O gqcio19

51 ROUT7 O gqcio19 MSB

52 DVDD2 P — Digital system power supply: 3.3V

53 DVSS P — Digital system ground

Pin Functions Items in parentheses apply to the LC74986NWV.

Continued on next page.

No.7713-8/15

LC74986NWF, 74986NWV

Continued from preceding page.

Pin Symbol I/O and type Function Notes

number I/O Type

54 GOUT0 O gqcio19 FPD module G output LSB

55 GOUT1 O gqcio19 (The ROUT5:0 pins are used for 6-bit output.)

56 GOUT2 O gqcio19 When 2-phase output is used, the first byte is data.

57 GOUT3 O gqcio19 (MSB when 6-bit output is selected)

58 GOUT4 O gqcio19

59 GOUT5 O gqcio19

60 GOUT6 O gqcio19

61 GOUT7 O gqcio19 MSB

62 DVDD2 P — Digital system power supply: 3.3V

63 DVSS P — Digital system ground

64 BOUT0 O gqcio19 FPD module B output LSB

65 BOUT1 O gqcio19 (The ROUT5:0 pins are used for 6-bit output.)

66 BOUT2 O gqcio19 When 2-phase output is used, the first byte is data.

67 BOUT3 O gqcio19 (MSB when 6-bit output is selected)

68 BOUT4 O gqcio19

69 GOUT5 O gqcio19

70 GOUT6 O gqcio19

71 GOUT7 O gqcio19 MSB

72 DVDD2 P — Digital system power supply: 3.3V

73 DVSS P — Digital system ground

74 SCANEN I gqcio18 Test settings Normally left open or connected to DVSS

75 SCANMOD I gqcio18

76 TEST0 I gqcio18

77 TEST1 I gqcio18

78 TEST2 I gqcio18

79 TEST3 I gqcio18

80 TEST4 I gqcio18

VPBEN (VPBDEN)

I gqcio03 External video input enable or port B system Enable: positive logic. Connect to DVSS if unused.

enable

VPB17 (ROUT7_2)

I/O gqcio35 Video data input (R) or port B system input MSB

VPB16 (ROUT6_2)

I/O gqcio35 or 2-phase output (MSB when 6-bit input or output mode selected)

VPB15 (ROUT5_2)

I/O gqcio35 (Data is input to VPB15 to VPB10 in 6-bit input mode.)

VPB14 (ROUT4_2)

I/O gqcio35 Second data in 2-phase output mode

VPB13 (ROUT3_2)

I/O gqcio35 Connect to DVSS if unused.

VPB12 (ROUT2_2)

I/O gqcio35

VPB11 (ROUT1_2)

I/O gqcio35

VPB10 (ROUT0_2)

I/O gqcio35 LSB

90 DVDD1 P — Digital system power supply: 2.5V (1.8V)

91 DVSS P — Digital system ground

VPB27 (GOUT7_2)

I/O gqcio35 Video data input (G) or port B system input MSB

VPB26 (GOUT6_2)

I/O gqcio35 or 2-phase output (MSB when 6-bit input or output mode selected)

VPB25 (GOUT5_2)

I/O gqcio35 (Data is input to VPB25 to VPB20 in 6-bit input mode.)

VPB24 (GOUT4_2)

I/O gqcio35 Second data in 2-phase output mode

VPB23 (GOUT3_2)

I/O gqcio35 Connect to DVSS if unused.

VPB22 (GOUT2_2)

I/O gqcio35

VPB21 (GOUT1_2)

I/O gqcio35

VPB20 (GOUT0_2)

I/O gqcio35 LSB

100

VPB37 (BOUT7_2)

I/O gqcio35 Video data input (B) or port B system input MSB

101

VPB36 (BOUT6_2)

I/O gqcio35 or 2-phase output (MSB when 6-bit input or output mode selected)

102

VPB35 (BOUT5_2)

I/O gqcio35 (Data is input to VPB35 to VPB30 in 6-bit input mode.)

103

VPB34 (BOUT4_2)

I/O gqcio35 Second data in 2-phase output mode

104

VPB33 (BOUT3_2)

I/O gqcio35 Connect to DVSS if unused.

105

VPB32 (BOUT2_2)

I/O gqcio35

106

VPB31 (BOUT1_2)

I/O gqcio35

107

VPB30 (BOUT0_2)

I/O gqcio35 LSB

108 DVDD1 P — Digital system power supply: 2.5V (1.8V)

109 DVSS P — Digital system ground

Continued on next page.

No.7713-9/15

LC74986NWF, 74986NWV

Continued from preceding page.

Pin Symbol I/O and type Function Notes

number I/O Type

110 VPA17 I gqcio02 Port A system input MSB

111 VPA16 I gqcio02 Y/R/YCbCr multiplexed

112 VPA15 I gqcio02 Connect to DVSS if unused.

113 VPA14 I gqcio02

114 VPA13 I gqcio02

115 VPA12 I gqcio02

116 VPA11 I gqcio02

117 VPA10 I gqcio02 LSB

118 VPA27 I gqcio02 Port A system input MSB

119 VPA26 I gqcio02 Cb/G/CbCr multiplexed or YCbCr multiplexed

120 VPA25 I gqcio02 Connect to DVSS if unused.

121 VPA24 I gqcio02

122 VPA23 I gqcio02

123 VPA22 I gqcio02

124 VPA21 I gqcio02

125 VPA20 I gqcio02 LSB

126 DVDD2 P — Digital system power supply: 3.3V

127 DVSS P — Digital system ground

128 VPA37 I gqcio02 Port A system input MSB

129 VPA36 I gqcio02 Cr/B/YCbCr multiplexed

130 VPA35 I gqcio02 Connect to DVSS if unused.

131 VPA34 I gqcio02

132 VPA33 I gqcio02

133 VPA32 I gqcio02

134 VPA31 I gqcio02

135 VPA30 I gqcio02 LSB

136 CLPVPA1 O gqcio21 VPA1 clamp level detection output The clamp level can be set over the I2C bus.

137 CLPVPA2 O gqcio21 VPA2 clamp level detection output

138 CLPVPA3 O gqcio21 VPA3 clamp level detection output

139 CLPP O gqcio05 Clamp pulse output The clamp position and width can be set over the I2C bus.

140 VSI I gqcio03 Vertical sync signal input Arbitrary polarity. The IC discriminates the polarity

141 HSI I gqcio03 Horizontal sync signal input automatically.

142 DEVI I gqcio03 Vertical data enable input Arbitrary polarity. A composite signal can be input to DEHI.

143 DEHI I gqcio03 Horizontal data enable input

Hold DEVI fixed at the high level if a composite signal is used.

144 DVDD2 P — Digital system power supply: 3.3V

No.7713-10/15

LC74986NWF, 74986NWV

Pin Type

Input or output Function Equivalent circuit Applicable pins

circuit type

gqcio02 Input CLKIEN, CLKI, XTAL, DCLKI, PDOWN1, VPA10 to

VPA17, VPA20 to VPA27, VPA30 to VPA37, MUTE,

VPBCK

gqcio03 Schmitt trigger input SCL, AICS, AIDA, AICK, RST, VPBEN, VSI, HSI,

DEVI, DEHI, PDOWN2, VPBH

gqcio18 Input with built-in pull-

down resistor I2CSEL, SCANEN, SCAMOD, TEST0 to TEST4*

gqcio05

gqcio19

gqcio20

4mA drive output

8mA drive output

12mA drive output

CLPP*

PLLHIO, DEHO, DEVO, HSO, VSO, ROUT0 to

ROUT7, GOUT0 to GOUT7, BOUT0 to BOUT7*

CLKIO, DCLKO*

gqcio21 4mA 3-state drive output CLPVPA1, CLPVPA2, CLPVPA3*

gqcio22 Open-drain I/O SDA

gqcio10 Analog through VCOCNT1, VCORNG1

gqcio09 Analog through PDO1*

gqcio35 8mA drive bidirectional VPB10 to VPB17, VPB20 to VPB27, VPB30 to VPB37

Notes:

• Pins marked with an asterisk (*) must be left open if unused.

• If noise or other problems due to external factors can be expected, input pins with built-in pull-down resistors must be connected to DVSS.

• All of the DVDD*and DVSS pins must be connected to the corresponding power supply system. These pins must not be left open.

• All of the AVDD and AVSS pins must be connected to the corresponding power supply system. These pins must not be left open.

No.7713-11/15

LC74986NWF, 74986NWV

Input and Output Data Timing

• Input Data Timing 1

tHI

tLO

tCK

tSU tHD

CLKI

Input data

VDD/2

Pin Name Parameter Symbol min max unit

Clock low level time tLO 5.5 (12.5) — ns

CLKI Clock high level time tHI 5.5 (12.5) — ns

Clock period tCK 11.0 (25.0) — ns

VPA1 [7:0], VPA2 [7:0] Input data setup time tSU 3.0 — ns

VPA3 [7:0], VSI, HSI, Input data hold time tHD 3.0 — ns

DEVI, DEHI, CLKIEN

Items in parentheses refer to the LC74986NWV.

*: An input clock duty of 50% is recommended.

• Input Data Timing 2

tHI

tLO

tCK

tSU tHD

DCLKI

Input data

VDD/2

Pin Name Parameter Symbol min max unit

Clock low level time tLO 5.5 (12.5) — ns

DCLKI Clock high level time tHI 5.5 (12.5) — ns

Clock period tCK 11.0 (25.0) — ns

VPBEN, VPB1 [7:0], Input data setup time tSU 3.0 — ns

VPB2 [7:0], VPB3 [7:0] Input data hold time tHD 3.0 — ns

Items in parentheses refer to the LC74986NWV.

*: An input clock duty of 50% is recommended.

No.7713-12/15

LC74986NWF, 74986NWV

• Output Data Timing 1

tHI

tLO

tCK

tSU tHD

CLKIO

Output data

VDD/2

• Output Data Timing 2

tHI

tLO

tCK

tSU

DCLKO

Output data

VDD/2

tHD

Pin Name Parameter Symbol min max unit

Clock low level time tLO 5.5 (12.5) — ns

CLKIO Clock high level time tHI 5.5 (12.5) — ns

Clock period tCK 11.0 (25.0) — ns

CLPVPA1, CLPVPA2, Output data setup time tSU 2.0 — ns

CLPVPA3, CLPP, PLLHIO

Output data hold time tHD 2.0 — ns

Items in parentheses refer to the LC74986NWV.

Pin Name Parameter Symbol min max unit

Clock low level time tLO 5.5 (12.5) — ns

DCLKO Clock high level time tHI 5.5 (12.5) — ns

Clock period tCK 11.0 (25.0) — ns

DEHO, DEVO, HSO, Output data setup time tSU 2.0 — ns

VSO, ROUT [7:0], Output data hold time tHD 2.0 — ns

GOUT [7:0], BOUT [7:0]

Items in parentheses refer to the LC74986NWV.

No.7713-13/15

LC74986NWF, 74986NWV

Input and Output Clock Timing

• Input System Clock Timing

Input CLKI

Output CLKIO

tHI tCK

tLO

tOUT

VDD/2

Pin Name Parameter Symbol min max unit

Clock low level time tLO 5.5 (12.5) — ns

CLKI Clock high level time tHI 5.5 (12.5) — ns

Clock period tCK 11.0 (25.0) — ns

CLKIO CLKIO delay time tOUT 017 ns

Items in parentheses refer to the LC74986NWV.

Pin Name Parameter Symbol min max unit

Clock low level time tLO 5.5 (12.5) — ns

DCLKI Clock high level time tHI 5.5 (12.5) — ns

Clock period tCK 11.0 (25.0) — ns

DCLKO DCLKO delay time tOUT 020 ns

Items in parentheses refer to the LC74986NWV.

• Output System Clock Timing

Input DCLKI

Output DCLKO

tHI tCK

tLO

tOUT1

VDD/2

No.7713-14/15

LC74986NWF, 74986NWV

Internal Block Diagram

Input Processing

VPA1[7:0]

VPA2[7:0]

VPA3[7:0]

110 117

118 125

128 135

YCbCr RGB

Sharpness

Color Tint

Scaling Processing

Horizontal reduction Horizontal and vertical

enlargement

ROUT[7:0]

GOUT[7:0]

BOUT[7:0]

Output Processing

44 51

54 61

64 71

MIX OSD

VSI 140

Input

timing

HSI 141

DEVI 142

DEHI 143

CLKI 5

CLKIEN

*1, *2: Register selection

Output

timing

VSO 41

HSO 40

DEVO 39

DEHO

DCLKO

DCLKI

AICS*2/AIDA/AICK

17 18 1913 14

SDA/SCL

VPB1[7:0]*1

VPB2[7:0]*1

VPB3[7:0]*1

82 89

92 99

100 107

VPBEN 81

XTAL

RGB YCbCr

Data

Select

White/black

expansion

White balance

Contrast

Black balance

Brightness

Gamma correction

Dithering

CCD

Select

External

video

ROUT_2[7:0]*1

GUOT_2[7:0]*1

BOUT_2[7:0]*1

82 89

92 99

100 107

VPBH 35

VPBV*2 17

Select

VPBCK 31

PS No.7713-15/15

LC74986NWF, 74986NWV

Specifications of any and all SANYO products described or contained herein stipulate the performance,

characteristics, and functions of the described products in the independent state, and are not guarantees

of the performance, characteristics, and functions of the described products as mounted in the customer's

products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,

the customer should always evaluate and test devices mounted in the customer's products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all

semiconductor products fail with some probability. It is possible that these probabilistic failures could

give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,

or that could cause damage to other property. When designing equipment, adopt safety measures so

that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective

circuits and error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products(including technical data,services) described or

contained herein are controlled under any of applicable local export control laws and regulations,

such products must not be exported without obtaining the export license from the authorities

concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or

mechanical, including photocopying and recording, or any information storage or retrieval system,

or otherwise, without the prior written permission of SANYO Electric Co. , Ltd.

Any and all information described or contained herein are subject to change without notice due to

product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"

for the SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not

guaranteed for volume production. SANYO believes information herein is accurate and reliable, but

no guarantees are made or implied regarding its use or any infringements of intellectual property rights

or other rights of third parties.

This catalog provides information as of April, 2004. Specifications and information herein are subject to

change without notice.