ICS950810 Integrated Circuit Systems, Inc. Frequency Generator with 200MHz Differential CPU Clocks Recommended Application: CK-408 clock for BANIAS processor/ ODEM and MONTARA-G chipsets. VDDREF X1 X2 GND PCICLK_F0 PCICLK_F1 PCICLK_F2 VDDPCI GND PCICLK0 PCICLK1 PCICLK2 PCICLK3 VDDPCI GND PCICLK4 PCICLK5 PCICLK6 VDD3V66 GND 3V66_2 3V66_3 3V66_4 3V66_5 *PD# VDDA GND Vtt_PWRGD# Output Features: * 3 Differential CPU Clock Pairs @ 3.3V * 7 PCI (3.3V) @ 33.3MHz * 3 PCI_F (3.3V) @ 33.3MHz * 1 USB (3.3V) @ 48MHz * 1 DOT (3.3V) @ 48MHz * 1 REF (3.3V) @ 14.318MHz * 5 3V66 (3.3V) @ 66.6MHz * 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz Features: * Supports spread spectrum modulation, down spread 0 to -0.5%. (CPU, 3V66, PCI) * Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * CPU Output Skew <100ps 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ICS950810 Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF FS1 FS0 CPU_STOP#* CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND VDDCPU CPUCLKT2 CPUCLKC2 MULTSEL0* IREF GND FS2 48MHz_USB 48MHz_DOT VDD48 GND 3V66_1/VCH_CLK PCI_STOP#* 3V66_0 VDD3V66 GND SCLK SDATA 56-Pin 300mil SSOP 6.10 mm. Body, 0.50 mm. pitch TSSOP * These inputs have 150K internal pull-up resistor to VDD. Block Diagram Functionality 48MHz_USB PLL2 FS2 FS1 FS0 48MHz_DOT X1 X2 XTAL OSC PLL1 Spread Spectrum CPU DIVDER Stop 3 3 PD# CPU_STOP# PCI_STOP# MULTSEL0 FS (2:0) SDATA SCLK 0472E--07/03/02 PCI DIVDER Stop 7 Control Logic 3V66 DIVDER 3 Reg. PCI_F PCI (MHz) 166.66 66.66 33.33 X 0 X 0 1 100.00 66.66 33.33 3V66_3 X 1 0 200.00 66.66 33.33 X 1 1 133.33 66.66 33.33 REF Mid 0 0 Tristate Tristate Tristate CPUCLKT (2:0) CPUCLKC (2:0) Mid 0 1 TCLK/2 TCLK/4 TCLK/8 Mid 1 0 Reserved Reserved Reserved Mid 1 1 Reserved Reserved Reserved PCICLK (6:0) PCICLK_F (2:0) 3V66_0 Config. 3V66(5:0) (MHz) 3V66_5 3V66_(4,2) 0 CPU (MHz) 3V66_1/VCH_CLK I REF ICS950810 Pin Configuration PIN NUMBER PIN NAME TYPE 1 VDDREF PWR 2 X1 IN DESCRIPTION Ref, XTAL power supply, nominal 3.3V Cr ystal input,nominally 14.318MHz. 3 X2 OUT Cr ystal output, nominally 14.318MHz. 4 GND PWR Ground pin for 3V outputs. 5 PCICLK_F0 OUT Free running PCI clock not affected by PCI_STOP# . 6 PCICLK_F1 OUT Free running PCI clock not affected by PCI_STOP# . 7 PCICLK_F2 OUT Free running PCI clock not affected by PCI_STOP# . 8 VDDPCI PWR Power supply for PCICLK_F and PCICLK, nominal 3.3V 9 GND PWR Ground pin for 3V outputs. 10 PCICLK0 OUT PCI clock outputs. 11 PCICLK1 OUT PCI clock outputs. 12 PCICLK2 OUT PCI clock outputs. 13 PCICLK3 OUT PCI clock outputs. 14 VDDPCI PWR Power supply for PCICLK_F and PCICLK, nominal 3.3V 15 GND PWR Ground pin for 3V outputs. 16 PCICLK4 OUT PCI clock outputs. 17 PCICLK5 OUT PCI clock outputs. 18 PCICLK6 OUT PCI clock outputs. 19 VDD3V66 PWR Power pin for the 3V66 clocks. 20 GND PWR Ground pin for 3V outputs. 21 3V66_2 OUT 66MHz outputs at 3.3V. 22 3V66_3 OUT 66MHz outputs at 3.3V. 23 3V66_4 OUT 66MHz outputs at 3.3V. 24 3V66_5 OUT 66MHz input/output at 3.3V. 25 PD# IN 26 VDDA PWR 3.3V power for the PLL core. 27 GND PWR Ground pin for 3V outputs. Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the cr ystal are stopped. The latency of the power down will not be greater than 3ms. 0472E--07/03/02 2 ICS950810 Pin Configuration (Continued) PIN NUMBER PIN NAME TYPE 28 Vtt_PWRGD# IN This 3.3V LVTTL input is a level sensitive strobe used to deter mine when FS[2:0] and MULTISEL0 inputs are valid and are ready to be sampled. (active low) 29 SDATA I/O Data pin for I2C circuitr y 5V tolerant 30 SCLK IN 31 GND PWR Ground pin for 3V outputs. 32 VDD3V66 PWR Power pin for the 3V66 clocks. 33 3V66_0 OUT 34 PCI_STOP# IN DESCRIPTION Clock pin of I2C circuitr y 5V tolerant 66MHz outputs at 3.3V. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when i n p u t l ow 35 3V66_1/VCH_CLK OUT 36 GND PWR Selectable 48MHz non-SSC or 66MHz SSC clock output Ground pin for 3V outputs. 37 VDD48 PWR Power for 48MHz output buffers and fixed PLL core. 38 48MHz_DOT OUT 48MHz output clock 39 48MHz_USB OUT 40 FS2 IN 48MHz output clock 41 GND PWR Ground pin for 3V outputs. 42 IREF OUT This pin festablishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropr iate current. 43 MULTSEL0 IN Frequency select pin. 3.3V LVTTL input for selection the current multiplier for CPU outputs 44 CPUCLKC2 OUT "Complementar y" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. 45 CPUCLKT2 OUT "Tr ue" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. 46 VDDCPU PWR Supply for CPU clocks,3.3V nominal 47 GND PWR Ground pin for 3V outputs. 48 CPUCLKC1 OUT "Complementar y" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. 49 CPUCLKT1 OUT "Tr ue" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. 50 VDDCPU PWR Supply for CPU clocks,3.3V nominal 51 CPUCLKC0 OUT "Complementar y" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. 52 CPUCLKT0 OUT "Tr ue" clocks of differential pair CPU outputs. These are current mode outputs. Exter nal resistors are required for voltage bias. 53 CPU_STOP# IN This asynchronous input halts to active low level when dr iven low. 54 FS0 IN Frequency select pin. 55 FS1 IN 56 REF OUT Frequency select pin. 14.318 MHz reference clock. 0472E--07/03/02 3 ICS950810 Power Groups (Analog) VDDA = PLL1 VDD48 = 48MHz, PLL VDDREF = VDD for Xtal, POR (Digital) VDDPCI VDD3V66 VDDCPU Truth Table FS2 FS1 FS0 CPU (MHz) 3V66 (5:0) (MHz) PCI_F PCI (MHz) REF0 (MHz) USB/DOT (MHz) X 0 0 166.66 66.66 33.33 14.318 48.00 X 0 1 100.00 66.66 33.33 14.318 48.00 X 1 0 200.00 66.66 33.33 14.318 48.00 X 1 1 133.33 66.66 33.33 14.318 48.00 Mid 0 0 Tristate Tristate Tristate Tristate Tristate Mid 0 1 TCLK/2 TCLK/4 TCLK/8 TCLK TCLK/2 Mid 1 0 Reserved Reserved Reserved Reserved Reserved Mid 1 1 Reserved Reserved Reserved Reserved Reserved Maximum Allowed Current Condition Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND Powerdown Mode (PWRDWN# = 0) 25mA Full Active 360mA Host Swing Select Functions MULTISEL0 Board Target Trace/Term Z Reference R, Iref = VDD/(3*Rr) Output Current Voh @ Z 0 - - - - 1 50 ohms Rr = 475 1%, Iref = 2.32mA Ioh = 6* I REF 0.7V @ 50 NOTE: MULTSEL0 = 0 not supported in ICS950810. Refer to ICS950805 for Buffered Mode support. 0472E--07/03/02 4 ICS950810 Power Management PD# CPU_STOP# PCI_STOP# VCO CPU CPU# PCICLK 3v66 48MHz REF 0 1 1 1 1 X 1 0 1 1 X 1 1 0 1 STOP RUN RUN RUN RUN Iref*2 RUN Iref*2 RUN RUN FLOAT RUN FLOAT RUN RUN LOW RUN RUN LOW RUN LOW RUN RUN RUN RUN LOW RUN RUN RUN RUN LOW RUN RUN RUN RUN Note: PCI_F is not affected by PCI_STOP# and CPU_STOP# Tri-State Control of CPU Outputs State 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Byte0 bit6 Byte1bit6 PD# Cpu_stop# 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 Pin PD# 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 Pin Stoppable Cpu_Stop# CPU outputs 1 Running 0 Irefx6 1 Irefx2 0 Irefx2 1 Running 0 Hi-Z 1 Hi-Z 0 Hi-Z 1 Running 0 Irefx6 1 Hi-Z 0 Hi-Z 1 Running 0 Hi-Z 1 Hi-Z 0 Hi-Z 0472E--07/03/02 5 Free-Running CPU outputs Running Running Irefx2 Irefx2 Running Running Irefx2 Irefx2 Running Running Hi-Z Hi-Z Running Running Hi-Z Hi-Z ICS950810 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +85C Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN 2 Input High Voltage VIH Input Low Voltage VIL VSS -0.3 Input High Current IIH VIN = VDD -5 VIN = 0 V; Inputs with no pull-up -5 IIL1 resistors Input Low Current VIN = 0 V; Inputs with pull-up IIL2 -200 resistors IDD3.3OP Operating Supply Current IDD3.3OP Powerdown Current Input Frequency Pin Inductance 1 Input Capacitance Clk Stabilization1,2 IDD3.3PD Fi Lpin CIN COUT CINX CL = Full load; Select @ 100 MHz CL =Full load; Select @ 133 MHz IREF=2.32 mA VDD = 3.3 V TYP MAX VDD +0.3 0.8 5 UNITS V V A 229 230 360 mA 220 233 360 mA 22 14.32 25 36 7 5 6 45 mA MHz nH pF pF pF 1 1.8 ms Logic Inputs Output pin capacitance X1 & X2 pins From PowerUp or deassertion of PowerDown to 1st clock. 27 tPZH,tPZL Output enable delay (all outputs) 1 10 ns tPHZ,tPLZ Output disable delay (all outputs) 1 10 ns TSTAB Delay1 1 Guaranteed by design, not 100% tested in production. See timing diagrams for buffered and un-buffered timing requirements. 2 0472E--07/03/02 6 ICS950810 Electrical Characteristics - CPU (0.7V Select) TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Current Source Output VO = Vx Zo1 Impedance IOH = -1 mA Output High Voltage VOH3 IOL = 1 mA Output Low Voltage VOL3 Statistical measurement on Voltage High VHigh single ended signal using Voltage Low VLow Measurement on single ended Max Voltage Vovs signal using absolute value. Min Voltage Vuds Crossing Voltage (abs) Vcross(abs) Variation of crossing over all Crossing Voltage (var) d-Vcross edges VOL = 0.175V, VOH = 0.525V Rise Time tr VOH = 0.525V VOL = 0.175V Fall Time tf Rise Time Variation d-tr Fall Time Variation d-tf Measurement from differential Duty Cycle dt3 wavefrom VT = 50% Skew tsk3 Jitter, Cycle to cycle tjcyc-cyc 1 MIN TYP MAX UNITS 3000 2.4 V 660 -150 -450 250 812 31 838 29 388 0.4 850 150 1150 mV 550 mV 140 mV mV 175 175 407 465 700 700 125 125 ps ps ps ps 45 49.5 55 % 48.8 100 ps 53 150 ps VT = 50% 1 Guaranteed by design, not 100% tested in production. I OWT can be varied and is selectable thru the MULTSEL pin. 2 Electrical Characteristics - PCICLK TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance V O = V DD*(0.5) RDSP1 Output High Voltage IOH = -1 mA VOH1 1 Output Low Voltage V OL Output High Current IOH1 Output Low Current IOL1 Rise Time tr11 tf11 dt11 tsk11 Fall Time Duty Cycle Skew Jitter,cycle to cyc tjcyc-cyc MIN 12 TYP 33 2.4 3.28 IOL = 1 mA V UNITS W V 0.55 V -33 -110 V OH@MAX = 3.135 V VOL @MIN = 1.95 V -20 110 -33 mA 30 V OL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 0.5 37 1.28 38 2 mA ns VOH = 2.4 V, VOL = 0.4 V 0.5 1.37 2 ns VT = 1.5 V 45 51.1 55 % VT = 1.5 V 127 500 ps VT = 1.5 V 164 250 ps OH@MIN 1 1 Guaranteed by design, not 100% tested in production. 0472E--07/03/02 7 = 1.0 V 0.08 MAX 55 ICS950810 Electrical Characteristics - 3V66 Mode: 3V66 [5:0] TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 V O = V DD*(0.5) Output Impedance RDSP1 1 Output High Voltage IOH = -1 mA VOH 1 Output Low Voltage V OL Output High Current IOH1 Output Low Current IOL1 Rise Time tr11 tf11 dt11 tsk11 Fall Time Duty Cycle Skew Jitter tjcyc-cyc MIN 12 TYP 33 2.4 3.28 IOL = 1 mA V V 0.55 V -110 -20 110 -33 mA 30 V OL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 0.5 37 1.15 38 2 mA ns VOH = 2.4 V, VOL = 0.4 V 0.5 1.53 2 ns VT = 1.5 V 45 51.3 55 % VT = 1.5 V 67 250 ps VT = 1.5 V 3V66 175 250 ps MIN 20 TYP 48 MAX 60 UNITS 2.4 3.27 V OH@MAX = 3.135 V VOL @MIN = 1.95 V 1 UNITS -33 OH@MIN = 1.0 V 0.08 MAX 55 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance V O = V DD*(0.5) RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 Output Low Voltage V OL Output High Current IOH1 Output Low Current IOL1 48DOT Rise Time tr11 tf11 tr11 tf11 dt11 dt11 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time 48 DOT Duty Cycle VCH 48 USB Duty Cycle IOL = 1 mA V OH@MIN = 1.0 V 0.08 -29 V 0.4 V -12 -23 mA -61 V OH@MAX = 3.135 V VOL @MIN = 1.95 V 29 V OL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 0.5 0.69 27 1 mA ns VOH = 2.4 V, VOL = 0.4 V 0.5 0.81 1 ns VOL = 0.4 V, VOH = 2.4 V 1 1.37 2 ns VOH = 2.4 V, VOL = 0.4 V 1 1.47 2 ns VT = 1.5 V 45 51.2 55 % VT = 1.5 V 45 53.5 55 % 48 DOT Jitter tjcyc-cyc 1 VT = 1.5 V 111 350 ps 48 USB Jitter tjcyc-cyc 1 VT = 1.5 V 99 350 ps USB to DOT Skew tsk11 VT = 1.5 V (0 OR 180 degrees) 1 ns 350 ps VCH Jitter tjcyc-cyc 1 VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0472E--07/03/02 8 147 ICS950810 Electrical Characteristics - REF TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance V RDSP1 O = V DD*(0.5) 1 Output High Voltage IOH = -1 mA VOH 1 Output Low Voltage V OL Output High Current IOH1 Output Low Current IOL1 Rise Time MIN 20 TYP 48 2.4 3.28 IOL = 1 mA V UNITS V 0.4 V -33 -110 V OH@MAX = 3.135 V VOL @MIN = 1.95 V -33 mA 30 -20 110 tr11 V OL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 1 37 1.69 38 2 mA ns Fall Time tf11 VOH = 2.4 V, VOL = 0.4 V 1 1.56 2 ns Duty Cycle dt11 VT = 1.5 V 45 53 55 % 152 1000 ps Jitter tjcyc-cyc OH@MIN 1 = 1.0 V 0.08 MAX 60 VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0472E--07/03/02 9 ICS950810 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: * * * * * * * * * * * * * * * * Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ICS (Slave/Receiver) ACK Byte Count ACK Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0472E--07/03/02 10 ICS950810 I2C Tables Affected Pin Name Spread Enabled BYTE 0 Bit 7 Pin # - Bit 6 - CPU_T(2:0) Bit 5 Bit 4 35 53 3V66_1/VCH_CLK CPU_STOP#* Bit 3 34 PCI_STOP#* Bit 2 Bit 1 Bit 0 40 55 54 FS2 FS1 FS0 BYTE 1 Bit 7 Pin # 43 Bit 6 - Bit 5 45, 44 Bit 4 49, 48 Bit 3 52, 51 Bit 2 45, 44 Bit 1 49, 48 Bit 0 52, 51 Affected Pin Name MULTSEL0* CPU_T(2:0) CPUCLKT2 CPUCLKC2 CPUCLKT1 CPUCLKC1 CPUCLKT0 CPUCLKC0 CPUCLKT2 CPUCLKC2 CPUCLKT1 CPUCLKC1 CPUCLKT2 CPUCLKC2 Control Function Type RW Spread Spectrum Control Power down mode output level 0= CPU driven in power RW down 1= undriven VCH/66.66 Select RW Reflects value of pin R Reflects value of pin at R/RW power up. Also can be set. Frequency Selection RW Frequency Selection RW Frequency Selection RW Control Function Type Reflects value of pin R CPU_Stop mode output level 0= CPU driven when stopped RW 1 = undriven Allow control of output with assertion of CPU_STOP#. Allow control of output with assertion of CPU_STOP#. Allow control of output with assertion of CPU_STOP#. RW RW RW Bit Control 0 1 OFF ON PWD 0 HIGH LOW 0 66.66 Stop 48.00 Active 0 X Stop Active 1 - - X X X Bit Control 0 1 - HIGH LOW Not Freerun Freerun Not Freerun Freerun Not Freerun Freerun PWD x 0 0 0 0 Output control RW Disable Enable 1 Output control RW Disable Enable 1 Output control RW Disable Enable 1 0472E--07/03/02 11 ICS950810 BYTE 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BYTE 3 Pin # 18 17 16 13 12 11 10 Affected Pin Name PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Affected Pin Bit Control 0 1 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Control Function Type (Reserved) Output control Output control Output control Output control Output control Output control Output control RW RW RW RW RW RW RW Control Function Type Output control Output control RW RW 0 1 Disable Enable Disable Enable PWD 0 1 1 1 1 1 1 1 Bit Control Bit 7 Bit 6 Pin # 38 39 Name 48MHz_DOT 48MHz_USB Bit 5 7 PCICLK_F2 Allow control of output with assertion of PCI_STOP#. RW Freerun Not Freerun 0 Bit 4 6 PCICLK_F1 Allow control of output with assertion of PCI_STOP#. RW Freerun Not Freerun 0 Bit 3 5 PCICLK_F0 Allow control of output with assertion of PCI_STOP#. RW Freerun Not Freerun 0 Bit 2 Bit 1 Bit 0 7 6 5 PCICLK_F2 PCICLK_F1 PCICLK_F0 Output control Output control Output control RW RW RW Disable Enable Disable Enable Disable Enable 1 1 1 BYTE 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 33 35 24 23 22 21 Affected Pin Name 3V66_0 3V66_1/VCH_CLK 3V66_5 3V66_4 3V66_3 3V66_2 Control Function Type (Reserved) (Reserved) Output control Output control Output control Output control Output control Output control RW RW RW RW RW RW RW RW Bit Control 0 1 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable PWD 0 0 1 1 1 1 1 1 0472E--07/03/02 12 PWD 1 1 ICS950810 BYTE 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # X X X X X X X X Affected Pin Name - BYTE 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # X X X X X X X X Affected Pin Name Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Control Function Type (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) - Control Function Type (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) R R R R R R R R 0472E--07/03/02 13 Bit Control 0 1 - PWD 0 0 0 0 0 0 0 0 Bit Control 0 1 - PWD 1 1 1 1 1 1 1 1 ICS950810 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. 3V66 (1:0) 3V66 (4:2) 3V66_5 PCICLK_F (2:0) PCICLK (6:0) Tpci Skews at Common Transition Edges GROUP PCI SYMBOL PCI tsk 1 CONDITIONS VT = 1.5 V 3V66 3V66 tsk 1 VT = 1.5 V 3V66 to PCI S3V66-PCI 3V66 (5:0) leads 33MHz PCI 1 Guarenteed by design, not 100% tested in production. 0472E--07/03/02 14 MIN 1.5 TYP 127 MAX 500 UNITS ps 67 250 ps 3.5 ns ICS950810 CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition. When the I2C Bit 6 of Byte 1 is programmed to '0' the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not be driven . When the I2C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU and CPU# outputs will not be driven. Assertion of CPU_STOP# Waveforms CPU_STOP# CPUT CPUC CPU_STOP# Functionality CPU_STOP# CPUT CPUC 1 Normal Normal 0 iref * Mult Float CPU_STOP# - De-assertion (transition from logic "0" to logic "1") All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the de-assertion to active outputs is to be defined to be tetween 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit 6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 3 nS of CPU_Stop# de-assertion. De-assertion of CPU_STOP# Waveforms 0472E--07/03/02 15 ICS950810 PD# - Assertion (transition from logic "1" to logic "0") When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must be held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both CPU and CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200 MHz. Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Power Down Assertion of Waveforms 0ns 25ns 50ns PD # CPUT 100MHz CPUC 100MHz 3V66MHz PCI 33MHz USB 48MHz REF 14.318MHz Power Down De-Assertion Mode The power-up latency needs to be less than 1.8mS. this is the time from the de-asseration of the powerdown of the ramping of the power supply until the time that stable clocks are output from the clock chip. If the I2C Bit 6 of Byte 0 is programmed to "1" then the stopped CPU outputs will be driven high within 3 nS of PD# de-asseration. 0472E--07/03/02 16 ICS950810 PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms PCI_S TOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz tsu 0472E--07/03/02 17 ICS950810 c N SYMBOL L E1 E INDEX AREA 1 2 h x 45 D A A A1 b c D E E1 e h L N A1 -Ce SEATING PLANE b .10 (.004) C N 56 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8 D (inch) MIN .720 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS950810yFT Example: ICS XXXX y F - T Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0472E--07/03/02 18 MAX .730 ICS950810 c N L E1 INDEX AREA E 1 2 D A A2 In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 A1 -Ce b VARIATIONS N SEATING PLANE aaa C 56 D mm. MIN 13.90 D (inch) MAX 14.10 MIN .547 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 6.10 mm. Body, 0.50 mm. pitch TSSOP (20 mil) (240 mil) Ordering Information ICS950810yGT Example: ICS XXXX y G - T Designation for tape and reel packaging Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0472E--07/03/02 19 MAX .555 Page 1 of 2 Global Sites Search Entire Site Contact IDT | Investors | Press Email | Print Document Search | Package Search | Parametric Search | Cross Reference Search | Green & RoHS | Calculators | Thermal Data | Reliability & Quality | Military Home > Products > Timing Solutions > PC-Notebook-Server Clocks > Clock Synthesizer by Chipset Vendor > Notebook Chipsets > 950810 You may also like... Add to myIDT [?] 950810 (Notebook Chipsets) Description CK-408 clock for BANIAS processor/ ODEM and MONTARA-G chipsets. Market Group PC CLOCK Additional Info * 3 Differential CPU Clock Pairs @ 3.3V * 7 PCI (3.3V) @ 33.3MHz * 3 PCI_F (3.3V) @ 33.3MHz * 1 USB (3.3V) @ 48MHz * 1 DOT (3.3V) @ 48MHz * 1 REF (3.3V) @ 14.318MHz * 5 3V66 (3.3V) @ 66.6MHz * 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz Related Orderable Parts Attributes 950810CFLF 950810CFLFT 950810CGLF 950810CGLFT Voltage 3.3 V (PVG56) 3.3 V (PVG56) 3.3 V (PAG56) 3.3 V (PAG56) Package SSOP 56 SSOP 56 TSSOP 56 TSSOP 56 NA NA NA NA C C C C Status Active Active Active Active Sample Yes No Yes No Minimum Order Quantity 104 1000 102 1000 Factory Order Increment 26 1000 34 1000 Speed Temperature Related Documents Type Title Datasheet 950810 Datasheet Size 167 KB Revision Date 11/08/2006 Product Change Notice PCN#: TB-0510-05 New Shipping Tube for TSSOP/TVSOP/TSSOP Exposed 202 KB 12/13/2005 Home | Site Map | About IDT | Press Room | Investor Relations | Trademark | Privacy Policy | Careers | Register | Contact Us Use of this website signifies your agreement to the acceptable use and privacy policy. Copyright 1997-2007 Integrated Device Technology, Inc. All Rights Reserved. mhtml:file://C:\950810.mht 08-Jun-2007 Page 2 of 2 Node: www.idt.com mhtml:file://C:\950810.mht 08-Jun-2007