ISL706BRHF/PROTO - Intersil Corporation

Rad-Hard, 5.0V/3.3V µ-Processor Supervisory Circuits

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

This family of devices are radiation hardened 5.0V/3.3V

supervisory circuits that reduce the complexity required to

monitor supply voltages in microprocessor systems. These

devices significantly improve accuracy and reliability relative to

discrete solutions. Each IC provides four key functions.

1. A reset output during power-up, power-down, and brownout

conditions.

2. An independent watchdog output that goes low if the

watchdog input has not been toggled within 1.6s.

3. A precision threshold detector for monitoring a power

supply other than VDD.

4. An active-low manual-reset input.

Specifications for Rad Hard QML devices are controlled by the

Defense Logistics Agency Land and Maritime (DLA). The SMD

numbers listed in the “Ordering Information” table on page 3

must be used when ordering.

Detailed Electrical Specifications for the ISL705ARH,

ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH and

ISL706CRH are contained in SMD 5962-11213. A “hot-link” is

provided on our website for downloading.

Applications

• Supervisor for µ-Processors, µ-Controllers, FPGAs and DSPs

• Critical Power Supply Monitoring

• Reliable Replacement of Discrete Solutions

Features

• Electrically Screened to SMD 5962-11213

• QML Qualified per MIL-PRF-38535 Requirements

•Radiation Hardness

- High Dose Rate. . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)

- SEL/SEB LETTH. . . . . . . . . . . . . . . . . . . . . . 86MeV/mg/cm2

• Precision Supply Voltage Monitor

- 4.65V Threshold in the ISL705ARH/BRH/CRH

- 3.08V Threshold in the ISL706ARH/BRH/CRH

• 200ms (Typ) Reset Pulse Width

- Active High, Active Low and Open Drain Options

• Independent Watchdog Timer with 1.6s (Typ) Timeout

• Precision Threshold Detector

- 1.25V Threshold in the ISL705ARH/BRH/CRH

- 0.6V Threshold in the ISL706ARH/BRH/CRH

• Debounced TTL/CMOS Compatible Manual-Reset Input

• Reset Output Valid at VDD = 1.2V

Related Literature

• ISL705RH Voltage Supervisory Circuit Evaluation Board

User’s Guide

• ISL706RH Voltage Supervisory Circuit Evaluation Board

User’s Guide

FIGURE 1. TYPICAL APPLICATION

VDD

GND

PFI

WDO

RST

WDI

PFO

µP

165k

49.9k ISL705ARH

5V SUPERVISOR APPLICATION WITH OVERVOLTAGE PROTECTION

NMI

RST

I/O

VCC

5V POWER SUPPLY

FIGURE 2. PRECISION THRESHOLD DETECTOR TEMPERATURE

CHARACTERISTICS CURVE

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-80 -60 -40 -20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

VPFI (V)

ISL705xRH

ISL706xRH

December 1, 2011

FN7662.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

2FN7662.1

December 1, 2011

Pin Configurations

ISL705ARH, ISL706ARH

(8 LD FLATPACK)

TOP VIEW

ISL705BRH, ISL706BRH

(8 LD FLATPACK)

TOP VIEW

ISL705CRH, ISL706CRH

(8 LD FLATPACK)

TOP VIEW

VDD

GND

PFI

WDO

RST

WDI

PFO

MR 1

VDD

GND

PFI

WDO

RST

WDI

PFO

MR 1

VDD

GND

PFI

WDO

RST_OD

WDI

PFO

Pin Descriptions

ISL705ARH

ISL706ARH

ISL705BRH

ISL706BRH

ISL705CRH

ISL706CRH NAME DESCRIPTION

111MR

Manual Reset. MR is an active-low, debounced, TTL/CMOS compatible input that may

be used to trigger a reset pulse.

222V

DD Power Supply. VDD is a supply voltage input that provides power to all internal circuitry.

This input is also monitored and used to trigger a reset pulse. Reset is guaranteed

operable after VDD rises above 1.2V.

333GNDGround. GND is a supply voltage return for all internal circuitry. This return establishes

the reference level for voltage detection and should be connected to signal ground.

444PFIPower Fail Input. PFI is an input to a threshold detector, which may be used to monitor

another supply voltage level. The threshold of the detector (VPFI) is 1.25V in the

ISL705ARH/BRH/CRH and 0.6V in the ISL706ARH/BRH/CRH.

555PFO

Power Fail Output. PFO is an active-low, push-pull output of a threshold detector that

indicates the voltage at the PFI pin is less than VPFI.

666WDIWatchdog Input. WDI is a tri-state input that monitors microprocessor activity. If the

microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated, WDO goes

low. As long as reset is asserted or WDI is tri-stated, the watchdog timer will stay cleared

and will not count. As soon as reset is released and WDI is driven high or low, the timer

will start counting. Floating WDI or connecting WDI to a high impedance tri-state buffer

disables the watchdog feature.

7--RST

Reset. RST is an active-low, push-pull output that is guaranteed to be low once VDD

reaches 1.2V. As VDD rises, RST stays low. When VDD rises above a 4.65V

(ISL705ARH/BRH/CRH) or 3.08V (ISL706ARH/BRH/CRH) reset threshold, an internal

timer releases RST after about 200ms. RST pulses low whenever VDD goes below the

reset threshold. If a brownout condition occurs in the middle of a previously initiated

reset pulse, the pulse will continue for at least 140ms. On power-down, once VDD falls

below the reset threshold, RST goes low and is guaranteed low until VDD drops below

1.2V.

-7-RSTReset. RST is an active-high, push-pull output. RST is the inverse of RST.

--7RST_OD

Reset. RST_OD is an active-low, open-drain output that goes low when reset is asserted.

This pin may be pulled up to VDD with a resistor consistent with the sink and leakage

current specifications of the output. Behavior is otherwise identical to the RST pin.

888WDO

Watchdog Output. WDO is an active-low, push-pull output that goes low if the

microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated. WDO is

usually connected to the non-maskable interrupt input of a microprocessor. When VDD

drops below the reset threshold, WDO will go low whether or not the watchdog timer

has timed out. Reset is simultaneously asserted, thus preventing an interrupt. Since

floating WDI disables the internal timer, WDO goes low only when VDD drops below the

reset threshold, thus functioning as a low line output.

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

3FN7662.1

December 1, 2011

Ordering Information

ORDERING NUMBER PART NUMBER

TEMP RANGE

(°C)

PACKAGE

(RoHs Compliant) PKG. DWG. #

5962R1121301QXC ISL705ARHQF (Note 1) -55 to +125 8 Ld Flatpack K8.A

5962R1121301VXC ISL705ARHVF (Note 1) -55 to +125 8 Ld Flatpack K8.A

5962R1121301V9A ISL705ARHVX -55 to +125 Die

ISL705ARHF/PROTO ISL705ARHF/PROTO (Note 1) -55 to +125 8 Ld Flatpack K8.A

ISL705ARHX/SAMPLE ISL705ARHX/SAMPLE -55 to +125 Die

5962R1121302QXC ISL705BRHQF (Note 1) -55 to +125 8 Ld Flatpack K8.A

5962R1121302VXC ISL705BRHVF (Note 1) -55 to +125 8 Ld Flatpack K8.A

5962R1121302V9A ISL705BRHVX -55 to +125 Die

ISL705BRHF/PROTO ISL705BRHF/PROTO (Note 1) -55 to +125 8 Ld Flatpack K8.A

ISL705BRHX/SAMPLE ISL705BRHX/SAMPLE -55 to +125 Die

5962R1121303QXC ISL705CRHQF (Note 1) -55 to +125 8 Ld Flapack K8.A

5962R1121303VXC ISL705CRHVF (Note 1) -55 to +125 8 Ld Flatpack K8.A

5962R1121303V9A ISL705CRHVX -55 to +125 Die

ISL705CRHF/PROTO ISL705CRHF/PROTO (Note 1) -55 to +125 8 Ld Flatpack K8.A

ISL705CRHX/SAMPLE ISL705CRHX/SAMPLE -55 to +125 Die

5962R1121304QXC ISL706ARHQF (Note 1) -55 to +125 8 Ld Flapack K8.A

5962R1121304VXC ISL706ARHVF (Note 1) -55 to +125 8 Ld Flatpack K8.A

5962R1121304V9A ISL706ARHVX -55 to +125 Die

ISL706ARHF/PROTO ISL706ARHF/PROTO (Note 1) -55 to +125 8 Ld Flatpack K8.A

ISL706ARHX/SAMPLE ISL706ARHX/SAMPLE -55 to +125 Die

5962R1121305QXC ISL706BRHQF (Note 1) -55 to +125 8 Ld Flatpack K8.A

5962R1121305VXC ISL706BRHVF (Note 1) -55 to +125 8 Ld Flatpack K8.A

5962R1121305V9A ISL706BRHVX -55 to +125 Die

ISL706BRHF/PROTO ISL706BRHF/PROTO (Note 1) -55 to +125 8 Ld Flatpack K8.A

ISL706BRHX/SAMPLE ISL706BRHX/SAMPLE -55 to +125 Die

5962R1121306QXC ISL706CRHQF (Note 1) -55 to +125 8 Ld Flatpack K8.A

5962R1121306VXC ISL706CRHVF (Note 1) -55 to +125 8 Ld Flatpack K8.A

5962R1121306V9A ISL706CRHVX -55 to +125 Die

ISL706CRHF/PROTO ISL706CRHF/PROTO (Note 1) -55 to +125 8 Ld Flatpack K8.A

ISL706CRHX/SAMPLE ISL706CRHX/SAMPLE -55 to +125 Die

ISL705XRHEVAL1Z ISL705XRH Evaluation Board

ISL706XRHEVAL1Z ISL706XRH Evaluation Board

NOTE:

1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with

both SnPb and Pb-free soldering operations.

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

4FN7662.1

December 1, 2011

Functional Block Diagrams

Timing Diagrams

+VREF

VDD

POR

GND

WDT

VREF

PFI

WDI

WDO

PF PFO

RST

ISL705ARH, ISL706ARH

VREF

VDD

POR

GND

WDT

VREF

PFI

WDI

WDO

PF PFO

RST

ISL705BRH, ISL706BRH ISL705CRH, ISL706CRH

VREF

VDD

POR

GND

WDT

VREF

PFI

WDI

WDO

PF PFO

RST_OD

FIGURE 3. RST, RST, MR AND WDO TIMING DIAGRAM

FIGURE 4. WATCHDOG TIMING DIAGRAM

VDD

RST

tRST

VRST

1.2V

tRST tRST

>tMR

RST

<tMD

VDD

WDI

WDO

VRST

1.2V

tWD

>tWP

< tWD

< tWD < tWD

tRST

RST

tRST

tWD

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

5FN7662.1

December 1, 2011

Absolute Maximum Ratings Thermal Information

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V

Voltage on All Other Inputs . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD + 0.3V

ESD Rating

Human Body Model (Tested per MIL-PRF-883 3015.7). . . . . . . . . .3.0kV

Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 300V

Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . .1.0kV

Latch Up (Tested per JESD-78C) . . . . . . . . . . . . . . . . . . . . . . Class 2, Level A

Recommended Operating Conditions

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage

ISL705ARH/BRH/CRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.5V

ISL706ARH/BRH/CRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15V to 3.6V

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

8 Ld Flatpack Package (Notes 2, 3). . . . . . 140 15

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

2. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

3. For θJC, the “case temp” location is the center of the package underside.

Electrical Specifications Unless otherwise specified VDD = 4.75V to 5.5V for the ISL705ARH/BRH/CRH, VDD = 3.15V to 3.6V for the

ISL706ARH/BRH/CRH TA= -55°C to +125°C. Boldface limits apply over the ambient operating temperature range, -55°C to +125°C.

SYMBOL PARAMETER CONDITIONS

MIN

(Note 4)

TYP

(Note 5)

MAX

(Note 4) UNITS

POWER SUPPLY SECTION

VDD Operating Supply Voltage (Note 6) ISL705ARH/BRH/CRH 1.2 55.5 V

ISL706ARH/BRH/CRH 1.2 3.3 3.6 V

IDD Operating Supply Current ISL705ARH/BRH/CRH 530 µA

ISL706ARH/BRH/CRH 400 µA

RESET SECTION

VRST Reset Threshold Voltage ISL705ARH/BRH/CRH 4.50 4.65 4.75 V

ISL706ARH/BRH/CRH 3.00 3.08 3.15 V

VHYS Reset Threshold Voltage Hysteresis ISL705ARH/BRH/CRH 20 40 mV

ISL706ARH/BRH/CRH 20 30 mV

tRST Reset Pulse Width 140 200 280 ms

VOUT Reset Output Voltage ISL705ARH/BRH, ISOURCE = 800µA VDD - 1.5 V

ISL705ARH/BRH/CRH, ISINK = 3.2mA 0.4 V

ISL706ARH/BRH, ISOURCE = 500µA 0.8 x VDD V

ISL706ARH/BRH/CRH, ISINK = 1.2mA 0.3 V

ISL70XARH/CRH, VDD = 1.2V, ISINK = 100µA 0.3 V

ISL70XBRH, VDD = 1.2V, ISOURCE = 4µA 0.9 V

ILEAK Reset Output Leakage Current ISL705CRH, VOUT = VDD 1µA

ISL706CRH, VOUT = VDD 1µA

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

6FN7662.1

December 1, 2011

WATCHDOG SECTION

tWD Watchdog Time-Out Period 1.00 1.60 2.25 s

tWP Watchdog Input (WDI) Pulse Width ISL705ARH/BRH/CRH, VIL =0.4V, V

IH = 0.8 x VDD 50 ns

ISL706ARH/BRH/CRH, VIL =0.4V, V

IH = 0.8 x VDD 100 ns

VIL Watchdog Input (WDI) Threshold Voltage ISL705ARH/BRH/CRH 0.8 V

VIH ISL705ARH/BRH/CRH 3.5 V

VIL ISL706ARH/BRH/CRH 0.6 V

VIH ISL706ARH/BRH/CRH 0.7 x VDD V

IWDI Watchdog Input (WDI) Current ISL705ARH/BRH/CRH, WDI = VDD 100 µA

ISL705ARH/BRH/CRH, WDI = 0V -100 µA

ISL706ARH/BRH/CRH, WDI = VDD 5µA

ISL706ARH/BRH/CRH, WDI = 0V -5 µA

VWDO Watchdog Output (WDO) Voltage ISL705ARH/BRH/CRH, ISOURCE = 800µA VDD - 1.5 V

ISL705ARH/BRH/CRH, ISINK = 1.2mA 0.4 V

ISL706ARH/BRH/CRH, ISOURCE = 500µA 0.8 x VDD V

ISL706ARH/BRH/CRH, ISINK = 500µA 0.3 V

MANUAL RESET SECTION

IMR Manual Reset (MR) Pull-up Current ISL705ARH/BRH/CRH, MR =0V -500 -100 µA

ISL706ARH/BRH/CRH, MR =0V -250 -25 µA

tMR Manual Reset (MR) Pulse Width ISL705ARH/BRH/CRH 150 ns

ISL706ARH/BRH/CRH 150 ns

VIL Manual Reset (MR) Input Threshold Voltage ISL705ARH/BRH/CRH 0.8 V

VIH 2.0 V

VIL ISL706ARH/BRH/CRH 0.6 V

VIH 0.7 x VDD V

tMD Manual Reset (MR) to Reset Out Delay ISL705ARH/BRH/CRH 100 ns

ISL706ARH/BRH/CRH 100 ns

THRESHOLD DETECTOR SECTION

VPFI Power Fail Input (PFI) Input Threshold

Voltage

ISL705ARH/BRH/CRH 1.20 1.25 1.30 V

ISL706ARH/BRH/CRH 0.576 0.6 0.624 V

IPFI Power Fail Input (PFI) Input Current -10 10 nA

VPFO Power Fail Output (PFO) Output Voltage ISL705ARH/BRH/CRH, ISOURCE = 800µA VDD - 1.5 V

ISL705ARH/BRH/CRH, ISINK = 3.2mA 0.4 V

ISL706ARH/BRH/CRH, ISOURCE = 500µA 0.8 x VDD V

ISL706ARH/BRH/CRH, ISINK = 1.2mA 0.3 V

tRPFI PFI Rising Threshold Crossing to PFO Delay ISL705ARH/BRH/CRH 7 15 µs

ISL706ARH/BRH/CRH 11 20 µs

Electrical Specifications Unless otherwise specified VDD = 4.75V to 5.5V for the ISL705ARH/BRH/CRH, VDD = 3.15V to 3.6V for the

ISL706ARH/BRH/CRH TA= -55°C to +125°C. Boldface limits apply over the ambient operating temperature range, -55°C to +125°C. (Continued)

SYMBOL PARAMETER CONDITIONS

MIN

(Note 4)

TYP

(Note 5)

MAX

(Note 4) UNITS

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

7FN7662.1

December 1, 2011

tFPFI PFI Falling Threshold Crossing to PFO Delay ISL705ARH/BRH/CRH 20 35 µs

ISL706ARH/BRH/CRH 25 40 µs

NOTES:

4. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

5. Typical values shown reflect TA = TJ = +25°C operation and are not guaranteed.

6. Reset is the only parameter operable within 1.2V and the minimum recommended operating supply voltage.

Typical Performance Curves

FIGURE 5. IDD vs TEMPERATURE FIGURE 6. VRST vs TEMPERATURE

FIGURE 7. VPFI vs TEMPERATURE FIGURE 8. ISL705xRH RESET and RESET ASSERTION

Electrical Specifications Unless otherwise specified VDD = 4.75V to 5.5V for the ISL705ARH/BRH/CRH, VDD = 3.15V to 3.6V for the

ISL706ARH/BRH/CRH TA= -55°C to +125°C. Boldface limits apply over the ambient operating temperature range, -55°C to +125°C. (Continued)

SYMBOL PARAMETER CONDITIONS

MIN

(Note 4)

TYP

(Note 5)

MAX

(Note 4) UNITS

200

250

300

350

400

450

500

550

-80-60-40-200 20406080100120140

TEMPERATURE (°C)

IDD (µA)

ISL705xRH

ISL706xRH

2.0

2.5

3.0

3.5

4.0

4.5

5.0

-80 -60 -40 -20 0 20 40 60 80 100 120 140

VRST (V)

TEMPERATURE (°C)

ISL705xRH

ISL706xRH

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-80 -60 -40 -20 0 20 40 60 80 100 120 140

TEMPERATURE (°C)

VPFI (V)

ISL705xRH

ISL706xRH

VDD

RST

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

8FN7662.1

December 1, 2011

FIGURE 9. ISL706xRH RESET AND RESET ASSERTION FIGURE 10. ISL705xRH RESET AND RESET DEASSERTION

FIGURE 11. ISL706xRH RESET AND RESET DEASSERTION FIGURE 12. ISL705xRH PFI TO PFO RESPONSE

FIGURE 13. ISL706xRH PFI TO PFO RESPONSE

Typical Performance Curves (Continued)

VDD

RST

VDD

RST

VDD

RST

PFO

PFI

PFO

PFI

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

9FN7662.1

December 1, 2011

Post Radiation Characteristics Unless otherwise specified, VDD = 4.75V to 5.5V for the ISL705ARH/BRH/CRH, VDD = 3.15V to 3.6V

for the ISL706ARH/BRH/CRH TA= +25°C. This data is parameter deltas post radiation exposure at a rate of 50 to 300rad(Si)/s. This data is intended to

show typical parameter shifts due to high dose radiation. These are not limits nor are they guaranteed.

SYMBOL PARAMETER CONDITIONS 0 - 25kRad 0 - 50kRad 0 - 75kRad 0 - 100kRad UNITS

POWER SUPPLY SECTION

IDD Operating Supply Current ISL705ARH/BRH/CRH -2 -2.44 -3.86 -4.88 µA

ISL706ARH/BRH/CRH -4.79 -7.47 -6.93 -8.88 µA

RESET SECTION

VRST Reset Threshold Voltage ISL705ARH/BRH/CRH -8.1 -13.1 -17.5 -18.1 mV

ISL706ARH/BRH/CRH -1 -3.25 -5.38 -7.25 mV

VHYS Reset Threshold Voltage

Hysteresis

ISL705ARH/BRH/CRH -3.75 -1.9 -5 -3.12 mV

ISL706ARH/BRH/CRH 0.375 0.25 0.625 0.625 mV

tRST Reset Pulse Width -2.13 -2.18 -2.39 -2.35 ms

WATCHDOG SECTION

tWD Watchdog Time-Out Period -56 -72 -81 -80 ms

MANUAL RESET SECTION

tMD Manual Reset (MR) to Reset

Out Delay

ISL705ARH/BRH/CRH 0.028 0.146 0.274 0.368 ns

ISL706ARH/BRH/CRH 0.305 0.605 0.793 0.956 ns

THRESHOLD DETECTOR SECTION

VPFI Power Fail Input (PFI) Input

Threshold Voltage

ISL705ARH/BRH/CRH 0.94 0.31 0 -0.62 mV

ISL706ARH/BRH/CRH -1.56 -2.5 -2.5 -2.5 mV

tRPFI PFI Rising Threshold

Crossing to PFO Delay

ISL705ARH/BRH/CRH -0.026 -0.047 -0.085 -0.068 µs

ISL706ARH/BRH/CRH 0.028 -0.058 0.11 -0.11 µs

tFPFI PFI Falling Threshold

Crossing to PFO Delay

ISL705ARH/BRH/CRH -0.397 -0.77 -1.17 -2.88 µs

ISL706ARH/BRH/CRH -0.35 -0.782 -1.516 -2.087 µs

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

10 FN7662.1

December 1, 2011

Functional Overview

The ISL705xRH and ISL706xRH provide the functions needed for

monitoring critical voltages in high reliability applications such as

microprocessor systems. Functions of the these supervisors include

power-on reset control; supply voltage supervisions; power-fail

detection; manual-reset assertion and a watch dog timer. The

integration of all these functions along with their high threshold

accuracy, low power consumption, and radiation tolerance make

these devices ideal for critical supply monitoring.

Reset Output

Reset control has long been a critical aspect of embedded

control design. Microprocessors require a reset signal during

power up to ensure that the system environment is stable before

initialization.

The reset signal provides several benefits:

• It prevents the system microprocessor from starting to operate

with insufficient voltage.

• It prevents the processor from operating prior to stabilization

of the oscillator.

• It ensures that the monitored device is held out of operation

until internal registers are initialized.

• It allows time for an FPGA to perform its self configuration

prior to initialization of the circuit.

On power-up, once VDD reaches 1.2V, RST is guaranteed logic

low. As VDD rises, RST stays low. When VDD rises above the reset

threshold (VRST), an internal timer releases RST after 200ms

(typ). RST pulses low whenever VDD degrades to below VRST (see

Figure 3). If a brownout condition occurs in the middle of a

previously initiated reset pulse, the pulse is lengthened 200ms

(typ).

On power-down, once VDD falls below the reset threshold, RST

stays low and is guaranteed to be low until VDD drops below 1.2V.

The ISL705BRH and ISL706BRH active-high RST output is simply

the complement of the RST output, and is guaranteed to be valid

with VDD down to 1.2V. The ISL705CRH and ISL706CRH

active-low open-drain reset output is functionally identical to RST.

Power Failure Monitor

Besides monitoring VDD for reset control, these devices have a

Power-Failure Monitor feature that supervises an additional

critical voltage on the Power-Fail Input (PFI) pin. For example, the

PFI pin could be used to provide an early power-fail warning,

overvoltage detection or monitor a power supply other than VDD.

PFO goes low whenever PFI is less than VPFI.

The threshold detector can be adjusted using an external resistor

divider network to provide custom voltage monitoring for

voltages greater than VPFI, according to Equation 1 (see

Figure 14).

Manual Reset

The manual reset input (MR) allows designers to add manual

system reset capability via a push button switch (see Figure 15).

The MR input is an active low debounced input which asserts

reset if the MR pin is pulled low to less than VIL for at least

150ns. After MR is released, the reset output remains asserted

for tRST and then released. MR is a TTL/CMOS logic compatible,

so it can be driven by external logic. By connecting WDO to MR,

one can force a watchdog time out to generate a reset pulse.

Watch Dog Timer

The watchdog time circuit checks for coherent program

execution by monitoring the WDI pin. If the processor does not

toggle the watchdog input within tWD (1.0s min), WDO will go

low. As long as reset is asserted or the WDI pin is tri-stated, the

watchdog timer will stay cleared and not count. As soon as reset

is released and WDI is driven high or low, the timer will start

counting. Pulses as short as 50ns can be detected on the

ISL705xRH, on ISL706xRH pulses as short as 100ns can be

detected.

Whenever there is a low-voltage VDD condition, WDO goes low.

Unlike the reset outputs, however, WDO goes high as soon as

VDD rises above its voltage trip point (see Figure 4). With WDI

open or connected to a tri-stated high impedance input, the

Watchdog Timer is disabled and only pulls low when VDD < VRST.

Applications Information

Negative Voltage Sensing

This family of devices can be used to sense and monitor the

presence of both a positive and negative rail. VDD is used to

monitors the positive supply while PFI monitors the negative rail.

PFO is high when the negative rail degrades below a VTRIP value

and remains low when the negative rail is above the Vtrip value.

As the differential voltage across the R1, R2 divider is increased,

the resistor values must be chosen such that the PFI node is

<1.25V when the -V supply is satisfactory and the positive supply

VIN VPFI

R1 R2+

----------------------

⎝⎠

⎛⎞

=(EQ. 1)

FIGURE 14. CUSTOM VTH WITH RESISTOR DIVIDER ON PFI

VIN

PFI

ISL705xRH/ISL706xRH

20k

FIGURE 15. CONNECTING A MANUAL RESET PUSH-BUTTON

ISL705xRH/ISL706xRH

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

11 FN7662.1

December 1, 2011

is at its maximum specified value. This allows the positive supply

to fluctuate within its acceptable range without signaling a reset

when configured as shown in Figure 16.

In Figure 16, the ISL705ARH is monitoring +5V through VDD and

-5V through PFI. In this example, the trip point (VTRIP) for the

negative supply rail is set for -4.5V. Equation 2 can be used to

select the appropriate resistor values. R1 is selected arbitrarily as

100kΩ, VDD = 5V, VPFI = 1.25V, and VTRIP = (-4.5V). By plugging

the values into Equation 2 as shown in Equation 3 it can be seen

a resistor of 153.3kΩ is needed. The closest 1% resistor value is

154kΩ.

Figure 4 also has a general purpose NPN transistor in which the

base is connected to the PFO pin through a 100kΩ resistor. The

emitter is tied to ground and the collector is tied to MR signal.

This configuration allows the negative voltage sense circuit to

initiate a reset if it is not within its regulation window. A pull-up

on the MR ensures no false reset triggering when the negative

voltage is within its regulation window.

Assuring a Valid RST Output

When VDD falls below 1.2V, the RST output can no longer sink

current and is essentially an open circuit. As a result, this pin can

drift to undetermined voltages if left undriven. By adding a pull-down

resistor to the RST pin as shown in Figure 17, any stray charge or

leakage currents will be drained to ground and keep RST low when

VDD falls below 1.2V. The resistor value (R1) is not critical however, it

should be large enough not to load RST and small enough to pull

RST to ground. A 100kΩ resistor would suffice, assuming there is no

load on the RST pin during that time.

Assuring a Valid RST Output

On the ISL705BRH and ISL706BRH, when VDD falls below 1.2V, the

RST output can no longer source enough current to track VDD. As a

result, this pin can drift to undetermined voltages if left undriven. By

adding a pull-up resistor to the RST pin as shown in Figure 18, RST

will track VDD below 1.2V. The resistor value (R1) is not critical

however, it should be large enough not to exceed the sink capability

of RST pin at 1.2V. A 300kΩ resistor would suffice, assuming there

is no load on the RST pin during that time.

Selecting Pull-Up Resistor Values

The ISL705CRH and ISL706CRH have open drain active low reset

outputs (RST_OD). A pull-up resistor is needed to ensure RST_OD

is high when VDD is in a valid state (Figure 19). The resistor value

must be chosen in order not to exceed the sink capability of the

RST_OD pin. The ISL705ARH has a sink capability of 3.2mA and

the ISL706CRH has a sink capability of 1.2mA. Equation 4 may

be used to select resistor RPULL based on the pull-up voltage

VPULL. It is also important that the pull-up voltage does not

exceed VDD.

FIGURE 16. ±5V MONITORING

R2 R1 VPFI Vtrip–()

VDD VPFI–

---------------------------------------------

=(EQ. 2)

R2 100k 1.25 4.5–()–()

51.25–

------------------------------------------------------153.3kΩ== (EQ. 3)

+5V

ISL705ARH

-5V

100k

100k 2N3904

RST

PFO

PFI

VDD

FIGURE 17. RST VALID TO GROUND CIRCUIT

FIGURE 18. RST VALID TO GROUND CIRCUIT

FIGURE 19. RST_OD PULL-UP CONNECTION

ISL705ARH, ISL706ARH

100kΩ

RST

VDD

ISL705BRH, ISL706BRH

300kΩ

RST

VDD R1

ISL706CRH, ISL705CRH

RPULL

RST_OD

VDD

VPULL

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

12 FN7662.1

December 1, 2011

Adding Hysteresis to the PFI Comparator

The PFI comparator has no built in hysteresis, however the

designer may add hysteresis by connecting a resistor from the

PFO pin to the PFI pin, essentially adding positive feedback to the

comparator (see Figure 20).

The following procedure allows the system designer to calculate

the components based on the requirements and on given data,

such as supply rail voltages, hysteresis band voltage (VHB), and

reference voltage (VPFI).

The comparator only has two states of operation. When it is low,

the current through R3 is IR3 = VPFI/R3. When the output is high,

IR3 = (VDD - VPFI)/R3. The feedback current needs to be very

small so it does not induce oscillations; 200nA is a good starting

point. Now two values of R3 can be calculated with VDD = 5V and

VPFI = 1.25V; R3 = 6.25MΩ or 11.25MΩ, select the lowest value

of the two.

With R3 selected as 6.2MΩ (closest standard 1% resistor), R1

can be calculated as:

with VHB selected at 100mV. The closest standard value for R1 is

124kΩ. Then next step is select the rising trip voltage (VTR) such

that:

The rising threshold voltage is selected at 3.0V and R2 is

calculated by Equation 7.

Plugging in all the variables R2 in this example is 90.9kΩ again

this is choosing the closest 1% resistor. The final step is verify the

trip voltages.

The rising voltage, VTR is calculated as 2.98V and the falling

voltage VTF is calculated as 2.88V so 100mV hysteresis is

achieved.

An additional item to consider is that the output voltage is equal

to VDD, however according to the “Electrical Specifications” on

page 6, the output of the PFI comparator is guaranteed to be at

least (VDD-1.5) volts. When you take this worst case into account,

the hysteresis can be as low at 70mV.

Special Application Considerations

Using good decoupling practices will prevent transients (i.e., due

to switching noises and short duration droops in the supply

voltage) from causing unwanted resets and reduce the power-fail

circuit’s sensitivity to high-frequency noise on the line being

monitored.

When the WDI input is left unconnected, it is recommended to

place a 10µF capacitor to ground to reduce single event

transients from arising in the WDO pin.

As described in the “Electrical Specifications” Table on page 7,

there is a delay on the PFO pin whenever PFI crosses the

threshold. This delay is due to internal filters on the PFI

comparator circuitry which were added to mitigate single event

transients. If the PFI input transitions below or above the

threshold and the duration of the transition is less than the delay,

the PFO pin will not change states.

FIGURE 20. POSITIVE FEEDBACK FOR HYSTERISIS

RPULL

VPULL

ISINK

----------------

=(EQ. 4)

ISL705ARH

RST

PFO

PFI

VDD

R1 R3 VHB

VDD

-----------

⎝⎠

⎛⎞

124kΩ== (EQ. 5)

VTR VPFI 1VHB

VDD

-----------

⎝⎠

⎛⎞

>(EQ. 6)

R2 1 VTR

VPFI R1×()

------------------------------

⎝⎠

⎛⎞

-------

⎝⎠

⎛⎞

–1

-------

⎝⎠

⎛⎞

–⁄=(EQ. 7)

VTR VPFI

()R1×1

-------

⎝⎠

⎛⎞ 1

-------

⎝⎠

⎛⎞ 1

-------

⎝⎠

⎛⎞

++=(EQ. 8)

VTF VTR R1 VDD×

--------------------------

⎝⎠

⎛⎞

–= (EQ. 9)

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

13 FN7662.1

December 1, 2011

Weight Characteristics

Weight of Packaged Device

0.31 Grams typical

Die Characteristics

Die Dimensions

2030µm x 2030µm (79.9 mils x 79.9 mils)

Thickness: 483µm ± 25.4µm (19.0 mils ± 1 mil)

Interface Materials

GLASSIVATION

Type: Silicon Oxide and Silicon Nitride

Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm

TOP METALLIZATION

Type: AlCu (99.5%/0.5%)

Thickness: 2.7µm ±0.4µm

TOP METALLIZATION

Type: Silicon

BACKSIDE FINISH

Silicon

PROCESS

0.6µM BiCMOS Junction Isolated

ASSEMBLY RELATED INFORMATION

Substrate Potential

Unbiased

ADDITIONAL INFORMATION

Worst Case Current Density

< 2 x 105 A/cm2

Transistor Count

1400

Layout Characteristics

Step and Repeat

2030µm x 2030µm

Metallization Mask Layout

WDO

VDD

GND

PFI PFO

WDI

RST, RST, RST_OD

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7662.1

December 1, 2011

For additional products, see www.intersil.com/product_tree

Products

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Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE REVISION CHANGE

11/1/11 FN7662.1 Page 13: Updated the transistor count to 1400 from 25000.

Pages7, 9: Removed erroneous overline bars in Figures 8-11.

9/15/11 FN7662.0 Initial release

ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH

15 FN7662.1

December 1, 2011

Package Outline Drawing

K8.A

8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

Rev 2, 12/10

LEAD FINISH

SIDE VIEW

TOP VIEW

-D-

-C-

0.265 (6.75)

0.115 (2.92)

0.026 (0.66)

0.265 (6.73)

SEATING AND

0.180 (4.57)

0.03 (0.76) MIN

BASE PLANE

-H-

0.09 (0.23)

0.005 (0.13)

PIN NO. 1

ID AREA

0.050 (1.27 BSC)

0.022 (0.56)

0.015 (0.38)

MIN 0.245 (6.22)

0.070 (1.18)

0.170 (4.32) 0.370 (9.40)

0.250 (6.35)

0.04 (0.10)

0.245 (6.22)

1. adjacent to pin one and shall be located within the shaded area shown.

The manufacturer’s identification shall not be used as a pin one

identification mark. Alternately, a tab may be used to identify pin one.

2. of the tab dimension do not apply.

3. The maximum limits of lead dimensions (section A-A) shall be

measured at the centroid of the finished lead surfaces, when solder

dip or tin plate lead finish is applied.

5. shall be molded to the bottom of the package to cover the leads.

6. meniscus) of the lead from the body. Dimension minimum shall

be reduced by 0.0015 inch (0.038mm) maximum when solder dip

lead finish is applied.

NOTES:

0.015 (0.38)

0.008 (0.20)

PIN NO. 1

ID OPTIONAL

1 2

Dimensioning and tolerancing per ANSI Y14.5M - 1982.

Controlling dimension: INCH.

Index area: A notch or a pin one identification mark shall be located

If a pin one identification mark is used in addition to a tab, the limits

Measure dimension at all four corners.

For bottom-brazed lead packages, no organic or polymeric materials

Dimension shall be measured at the point of exit (beyond the

SECTION A-A

BASE

METAL

0.007 (0.18)

0.004 (0.10)

0.009 (0.23)

0.004 (0.10)

0.019 (0.48)

0.015 (0.38) 0.0015 (0.04)

MAX

0.022 (0.56)

0.015 (0.38)

0.045 (1.14)