KAI-29052-QXA-JD-B1 - ON SEMICONDUCTOR

May, 2017 − Rev. 0

1Publication Order Number:

KAI−29052/D

KAI-29052

6576 (H) x 4384 (V)

Interline CCD Image Sensor

Description

The KAI−29052 Image Sensor is a 29 Megapixel CCD in a 35 mm

optical format that provides increased Quantum Efficiency (particularly

for NIR wavelengths) compared to members of the standard 5.5 mm

family.

The sensor shares the same broad dynamic range, excellent imaging

performance, and flexible readout architecture as other members of the

5.5 mm pixel family. However, QE at 820 nm has been approximately

doubled compared to existing devices, enabling enhanced sensitivity

without a corresponding decrease in the Modulation Transfer Function

(MTF) of the device.

The sensor is available with the Sparse Color Filter Pattern, which

provides a 2× improvement in light sensitivity compared to a standard

color Bayer part.

The KAI−29052 is drop-in compatible with the KAI−29050 Image

Sensor, simplifying adoption by camera manufacturers currently

working with the KAI−29050.

Table 1. GENERAL SPECIFICATIONS

Parameter Typical Value

Architecture Interline CCD; Progressive Scan

Total Number of Pixels 6644 (H) × 4452 (V)

Number of Effective Pixels 6600 (H) × 4408 (V)

Number of Active Pixels 6576 (H) × 4384 (V)

Pixel Size 5.5 mm (H) × 5.5 mm (V)

Active Image Size 36.17 mm (H) × 24.11 mm (V)

43.47 mm (diag.), 35 mm Optical Format

Aspect Ratio 3:2

Number of Outputs 1, 2, or 4

Charge Capacity 20,000 electrons

Output Sensitivity 35 mV/e*

Quantum Efficiency

Pan (−AXA, −QXA, −PXA)

R, G, B (−FXA, −QXA)

43%, 12%, 5% (540, 850, 920 nm)

39%, 40%, 37% (620, 540, 480 nm)

Read Noise (f = 40 MHz) 10 electrons rms

Dark Current

Photodiode

VCCD

7 electrons/s

140 electrons/s

Dark Current Doubling Temp.

Photodiode

VCCD

7°C

9°C

Dynamic Range 66 dB

Charge Transfer Efficiency 0.999999

Blooming Suppression > 300 X

Smear Estimated –100 dB

Image Lag < 10 electrons

Maximum Pixel Clock Speed 40 MHz

Maximum Frame Rates

Quad Output

Dual Output

Single Output

4 fps

2 fps

1 fps

Package 72 pin PGA

Cover Glass AR Coated, 2 Sides

NOTE: All Parameters are specified at T = 40°C unless otherwise noted.

Features

•Increased QE, with 2× Improvement at

820 nm

•Bayer Color Pattern, Sparse Color Pattern,

and Monochrome Configurations

•Progressive Scan Readout

•Flexible Readout Architecture

•High Frame Rate

•Low Noise Architecture

•Excellent Smear Performance

•Package Pin Reserved for Device

Identification

Applications

•Industrial Imaging and Inspection

•Medical Imaging

•Security and Surveillance

www.onsemi.com

Figure 1. KAI−29052 CCD Image Sensor

See detailed ordering and shipping information on page 2 of

this data sheet.

ORDERING INFORMATION

KAI−29052

www.onsemi.com

ORDERING INFORMATION

Table 2. ORDERING INFORMATION

Part Number Description Marking Code

KAI−29052−AXA−JD−B1 Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass

with AR Coating (Both Sides), Grade 1

KAI−29052−AXA

Serial Number

KAI−29052−AXA−JD−B2 Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass

with AR Coating (Both Sides), Grade 1

KAI−29052−AXA−JD−AE Monochrome, Special Microlens, PGA Package, Sealed Clear Cover Glass

with AR Coating (Both Sides), Engineering Grade

KAI−29052−FXA−JD−B1 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear

Cover Glass with AR Coating (Both Sides), Grade 1

KAI−29052−FXA

Serial Number

KAI−29052−FXA−JD−B2 Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear

Cover Glass with AR Coating (Both Sides), Grade 2

KAI−29052−FXA−JD−AE Gen2 Color (Bayer RGB), Special Microlens, PGA Package, Sealed Clear

Cover Glass with AR Coating (Both Sides), Engineering Grade

KAI−29050−QXA−JD−B1 Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear

Cover Glass with AR Coating (Both Sides), Grade 1

KAI−29052−QXA

Serial Number

KAI−29050−QXA−JD−AE Gen2 Color (Sparse CFA), Special Microlens, PGA Package, Sealed Clear

Cover Glass with AR Coating (Both Sides), Engineering Grade

Table 3. EVALUATION SUPPORT

Part Number Description

G2−FPGA−BD−14−40−A−GEVK FPGA Board for IT−CCD Evaluation Hardware

KAI−72PIN−HEAD−BD−A−GEVB 72 Pin Imager Board for IT−CCD Evaluation Hardware

LENS−MOUNT−KIT−C−GEVK Lens Mount Kit for IT−CCD Evaluation Hardware

See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention

used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at

www.onsemi.com.

KAI−29052

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DEVICE DESCRIPTION

Architecture

Figure 2. Block Diagram

22 Dark

V1B

12 Buffer

ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ

FLD

ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ

FLD

3288 3288

(Last VCCD Phase = V1 à H1S)

V2B

V3B

V4B

V1T

V2T

V3T

V4T

H1Sa

H1Ba

H2Sa

H2Ba

RDa

VDDa

VOUTa

GND

H1Sb

H1Bb

H2Sb

H2Bb

RDc

VDDc

VOUTc

GND

RDd

VDDd

VOUTd

GND

RDb

VDDb

VOUTb

GND

V1B

V2B

V3B

V4B

V1T

V2T

V3T

V4T

H1Sd

H1Bd

H2Sd

H2Bd

H1Sc

H1Bc

H2Sc

H2Bc

H2SLa

OGa

H2SLc

OGc

H2SLd

OGd

H2SLb

OGb

ESD ESD

SUBSUB

82210112822101 12

822101 12 82210112

22 12

DevID

6576 (H) y 4384 (V)

5.5 mm y 5.5 mm Pixels

FDGcd

FDGab

Dark Reference Pixels

There are 22 dark reference rows at the top and 22 dark

rows at the bottom of the image sensor. The dark rows are not

entirely dark and so should not be used for a dark reference

level. Use the 22 dark columns on the left or right side of the

image sensor as a dark reference. Under normal

circumstances use only the center 20 columns of the 22

column dark reference due to potential light leakage.

Dummy Pixels

Within each horizontal shift register there are 11 leading

additional shift phases. These pixels are designated as

dummy pixels and should not be used to determine a dark

reference level. In addition, there is one dummy row of

pixels at the top and bottom of the image.

Active Buffer Pixels

12 unshielded pixels adjacent to any leading or trailing

dark reference regions are classified as active buffer pixels.

These pixels are light sensitive but are not tested for defects

and non-uniformities.

Image Acquisition

An electronic representation of an image is formed when

incident photons falling on the sensor plane create

electron-hole pairs within the individual silicon

photodiodes. These photoelectrons are collected locally by

the formation of potential wells at each photo-site. Below

photodiode saturation, the number of photoelectrons

collected at each pixel is linearly dependent upon light level

and exposure time and non-linearly dependent on

wavelength. When the photodiodes charge capacity is

reached, excess electrons are discharged into the substrate to

prevent blooming.

ESD Protection

Adherence to the power-up and power-down sequence is

critical. Failure to follow the proper power-up and

power-down sequences may cause damage to the sensor. See

Power-Up and Power-Down Sequence section.

KAI−29052

www.onsemi.com

Bayer Color Filter Pattern

Figure 3. Bayer Color Filter Pattern

22 Dark

V1B

12 Buffer

ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ

FLD

ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ

FLD

3288 3288

(Last VCCD Phase = V1 à H1S)

V2B

V3B

V4B

V1T

V2T

V3T

V4T

H1Sa

H1Ba

H2Sa

H2Ba

RDa

VDDa

VOUTa

GND

H1Sb

H1Bb

H2Sb

H2Bb

RDc

VDDc

VOUTc

GND

RDd

VDDd

VOUTd

GND

RDb

VDDb

VOUTb

GND

V1B

V2B

V3B

V4B

V1T

V2T

V3T

V4T

H1Sd

H1Bd

H2Sd

H2Bd

H1Sc

H1Bc

H2Sc

H2Bc

H2SLa

OGa

H2SLc

OGc

H2 SLd

OGd

H2SLb

OGb

ESD ESD

SUBSUB

82210112822101 12

822101 12 82210112

22 12

DevID

6576 (H) y 4384 (V)

5.5 mm y 5.5 mm Pixels

FDGcd FDGab

FDGab

FDGcd

Sparse Color Filter Pattern

Figure 4. Sparse Color Filter Pattern

22 Dark

V1B

12 Buffer

ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ

FLD

ÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ

FLD

3288 3288

(Last VCCD Phase = V1 à H1S)

V2B

V3B

V4B

V1T

V2T

V3T

V4T

H1Sa

H1Ba

H2Sa

H2Ba

RDa

VDDa

VOUTa

GND

H1Sb

H1Bb

H2Sb

H2Bb

RDc

VDDc

VOUTc

GND

RDd

VDDd

VOUTd

GND

RDb

VDDb

VOUTb

GND

V1B

V2B

V3B

V4B

V1T

V2T

V3T

V4T

H1Sd

H1Bd

H2Sd

H2Bd

H1Sc

H1Bc

H2Sc

H2Bc

H2 SLa

OGa

H 2 SLc

OGc

H 2 SLd

OGd

H 2 SLb

OGb

ESD ESD

SUBSUB

82210112822101 12

822101 12 82210112

22 12

DevID

P B G

B P

P R P

P B G

B P

P R P

P B G

B P

P R P

P B G

B P

P R P

6576 (H) y 4384 (V)

5.5 mm y 5.5 mm Pixels

FDGcd FDGab

FDGab

FDGcd

KAI−29052

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PHYSICAL DESCRIPTION

Pin Description and Device Orientation

Figure 5. Package Pin Description (Top View)

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36

72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38

71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37

V3B

Pixel

(1,1)

V3B

V1B

VDDa

VDDb

GND

H2SLa

H2SLb

H1Ba

H1Bb

H2Sa

H2Sb

SUB

N/C

V3T

V1T

VDDc

VDDd

GND

H2SLc

H2SLd

H1Bc

H1Bd

H2Sc

H2Sd

N/C

SUB

V4B

ESD

V4B

V2B

VOUTa

VOUTb

RDa

RDb

OGa

OGb

H2Ba

H2Bb

H1Sa

H1Sb

FDGab

V4T

DevID

V4T

V2T

VOUTc

VOUTd

RDc

RDd

OGc

OGd

H2Bc

H2Bd

H1Sc

H1Sd

FDGcd

ESD

KAI−29052

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Table 4. PIN DESCRIPTION

Pin Name Description

1 V3B Vertical CCD Clock, Phase 3, Bottom

3 V1B Vertical CCD Clock, Phase 1, Bottom

4 V4B Vertical CCD Clock, Phase 4, Bottom

5 VDDa Output Amplifier Supply, Quadrant a

6 V2B Vertical CCD Clock, Phase 2, Bottom

7 GND Ground

8 VOUTa Video Output, Quadrant a

9 Ra Reset Gate, Quadrant a

10 RDa Reset Drain, Quadrant a

11 H2SLa Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant a

12 OGa Output Gate, Quadrant a

13 H1Ba Horizontal CCD Clock, Phase 1, Barrier,

Quadrant a

14 H2Ba Horizontal CCD Clock, Phase 2, Barrier,

Quadrant a

15 H2Sa Horizontal CCD Clock, Phase 2,

Storage, Quadrant a

16 H1Sa Horizontal CCD Clock, Phase 1,

Storage, Quadrant a

17 SUB Substrate

18 FDGab Fast Line Dump Gate, Bottom

19 N/C No Connect

20 FDGab Fast Line Dump Gate, Bottom

21 H2Sb Horizontal CCD Clock, Phase 2,

Storage, Quadrant b

22 H1Sb Horizontal CCD Clock, Phase 1,

Storage, Quadrant b

23 H1Bb Horizontal CCD Clock, Phase 1, Barrier,

Quadrant b

24 H2Bb Horizontal CCD Clock, Phase 2, Barrier,

Quadrant b

25 H2SLb Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant b

26 OGb Output Gate, Quadrant b

27 Rb Reset Gate, Quadrant b

28 RDb Reset Drain, Quadrant b

29 GND Ground

30 VOUTb Video Output, Quadrant b

31 VDDb Output Amplifier Supply, Quadrant b

32 V2B Vertical CCD Clock, Phase 2, Bottom

33 V1B Vertical CCD Clock, Phase 1, Bottom

34 V4B Vertical CCD Clock, Phase 4, Bottom

35 V3B Vertical CCD Clock, Phase 3, Bottom

36 ESD ESD Protection Disable

Pin Name Description

72 ESD ESD Protection Disable

71 V3T Vertical CCD Clock, Phase 3, Top

70 V4T Vertical CCD Clock, Phase 4, Top

69 V1T Vertical CCD Clock, Phase 1, Top

68 V2T Vertical CCD Clock, Phase 2, Top

67 VDDc Output Amplifier Supply, Quadrant c

66 VOUTc Video Output, Quadrant c

65 GND Ground

64 RDc Reset Drain, Quadrant c

63 Rc Reset Gate, Quadrant c

62 OGc Output Gate, Quadrant c

61 H2SLc Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant c

60 H2Bc Horizontal CCD Clock, Phase 2, Barrier,

Quadrant c

59 H1Bc Horizontal CCD Clock, Phase 1, Barrier,

Quadrant c

58 H1Sc Horizontal CCD Clock, Phase 1,

Storage, Quadrant c

57 H2Sc Horizontal CCD Clock, Phase 2,

Storage, Quadrant c

56 FDGcd Fast Line Dump Gate, Top

55 N/C No Connect

54 FDGcd Fast Line Dump Gate, Top

53 SUB Substrate

52 H1Sd Horizontal CCD Clock, Phase 1,

Storage, Quadrant d

51 H2Sd Horizontal CCD Clock, Phase 2,

Storage, Quadrant d

50 H2Bd Horizontal CCD Clock, Phase 2, Barrier,

Quadrant d

49 H1Bd Horizontal CCD Clock, Phase 1, Barrier,

Quadrant d

48 OGd Output Gate, Quadrant b

47 H2SLd Horizontal CCD Clock, Phase 2,

Storage, Last Phase, Quadrant d

46 RDd Reset Drain, Quadrant d

45 Rd Reset Gate, Quadrant d

44 VOUTd Video Output, Quadrant d

43 GND Ground

42 V2T Vertical CCD Clock, Phase 2, Top

41 VDDd Output Amplifier Supply, Quadrant d

40 V4T Vertical CCD Clock, Phase 4, Top

39 V1T Vertical CCD Clock, Phase 1, Top

38 DevID Device Identification

37 V3T Vertical CCD Clock, Phase 3, Top

1. Like named pins are internally connected and should have a common drive signal.

2. N/C pins (19, 55) should be left floating.

KAI−29052

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IMAGING PERFORMANCE

Table 5. TYPICAL OPERATION CONDITIONS

(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)

Description Condition

Light Source (Note 1) Continuous Red, Green and Blue LED Illumination

Operation Nominal Operating Voltages and Timing

1. For monochrome sensor, only green LED used.

Table 6. SPECIFICATIONS

Description Symbol Min. Nom. Max. Unit

Sampling

Plan

Temperature

Tested at (5C)

ALL CONFIGURATIONS

Dark Field Global Non-uniformity DSNU − − 5 mVpp Die 27, 40

Bright Field Global Non-uniformity

(Note 1)

−2 5 %rms Die 27, 40

Bright Field Global Peak to Peak

Non-uniformity (Note 1)

PRNU −10 30 %pp Die 27, 40

Maximum Photo-response

Non-linearity (Note 2)

NL −2−% Design

Maximum Gain Difference

Between Outputs (Note 2)

DG−10 −% Design

Maximum Signal Error due to

Non-linearity Differences (Note 2)

DNL −1−% Design

Horizontal CCD Charge Capacity HNe −50 −ke−Design

Vertical CCD Charge Capacity VNe −40 −ke−Design

Photodiode Charge Capacity

(Note 3)

PNe −20 −ke−Die 27, 40

Horizontal CCD Charge Transfer

Efficiency

HCTE 0.999995 0.999999 −Die

Vertical CCD Charge Transfer

Efficiency

VCTE 0.999995 0.999999 −Die

Photodiode Dark Current IPD −7 70 e/p/s Die 40

Vertical CCD Dark Current IVD −140 400 e/p/s Die 40

Image Lag Lag − − 10 e−Design

Anti-blooming Factor XAB 300 − − Design

Vertical Smear Smr − −100 −dB Design

Read Noise (Note 4) ne−T−10 −e−rms Design

Dynamic Range (Notes 4, 5) DR −66 −dB Design

Output Amplifier DC Offset VODC −9.4 −V Die 27, 40

Output Amplifier Bandwidth

(Note 6)

f−3db −250 −MHz Die

Output Amplifier Impedance ROUT −127 −WDie 27, 40

Output Amplifier Sensitivity DV/DN−35 −mV/e−Design

KAI−29052

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Table 6. SPECIFICATIONS

Description Symbol Min. Nom. Max. Unit

Sampling

Plan

Temperature

Tested at (5C)

KAI−29052−AXA AND KAI−29052−QXA CONFIGURATIONS

Peak Quantum Efficiency QEMAX −43 −% Design

Peak Quantum Efficiency

Wavelength

lQE −540 −nm Design

Quantum Efficiency (850 nm) QEMAX −12 −nm Design

Peak Quantum Efficiency

(920 nm)

QEMAX −5−nm Design

KAI−29052−FBA AND KAI−29052−QBA GEN2 COLOR CONFIGURATIONS

Peak Quantum Efficiency

Blue

Green

Red

QEMAX −

−

% Design

Peak Quantum Efficiency

Wavelength

Blue

Green

Red

lQE

−

480

540

620

−

nm Design

1. Per color

2. Value is over the range of 10% to 90% of photodiode saturation.

3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such

that the photodiode charge capacity is 700 mV.

4. At 40 MHz.

5. Uses 20 LOG (PNe / ne−T).

6. Assumes 5 pF load.

KAI−29052

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TYPICAL PERFORMANCE CURVES

Quantum Efficiency

Monochrome with Microlens

Figure 6. Monochrome with Microlens Quantum Efficiency

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100

Absolute Quantum Efficiency

Wavelength (nm)

KAI−29052 KAI−29050

Measured with AR

coated cover glass

KAI−29052

www.onsemi.com

Color (Bayer RGB) with Microlens

Figure 7. Color (Bayer RGB) with Microlens Quantum Efficiency

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100

Absolute Quantum Efficiency

Wavelength (nm)

KAI−29052 Red KAI−29052 Green KAI−29052 Blue

KAI−29050 Red KAI−29050 Green KAI−29050 Blue

Measured with AR

coated cover glass

Color (Sparse FCA) with Microlens

Figure 8. Color (Sparse CFA) with Microlens Quantum Efficiency

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100

Absolute Quantum Efficiency

Wavelength (nm)

Pan Red Green Blue

Measured with AR

coated cover glass

KAI−29052

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Angular Quantum Efficiency

For the curves marked “Horizontal”, the incident light angle is varied in a plane parallel to the HCCD.

For the curves marked “Vertical”, the incident light angle is varied in a plane parallel to the VCCD.

Monochrome with Microlens

Figure 9. Monochrome with Microlens Angular Quantum Efficiency

−40

Angle (Degrees)

Relative Quantum Efficiency (%)

100

Vertical

Horizontal

−30 −20 −10 0 10 20 30 40

Dark Current vs. Temperature

Figure 10. Dark Current vs. Temperature

2.9

Dark Current (e/s/pixel)

100

Photodiode

VCCD

0.1

1000

10000

3.1

3.2

3.3

3.4

1000/T (K)

T (5C)

KAI−29052

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Power − Estimated

Figure 11. Power

0.0

0.5

1.0

1.5

2.0

2.5

10 15 20 25 30 35 40

HCCD Frequency (MHz)

Power (W)

Single Dual Quad

Frame Rates

Figure 12. Frame Rates

10 15 20 25 30 35 40

HCCD Frequency (MHz)

Frame Rate (fps)

0.5 0.5

1.0 1.0

1.5 1.5

2.0 2.0

2.5 2.5

3.0 3.0

3.5 3.5

4.0 4.0

4.5 4.5

5.0 5.0

Single Dual (Left/Right) Quad

KAI−29052

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DEFECT DEFINITIONS

Table 7. OPERATION CONDITIONS FOR DEFECT TESTING AT 405C

Description Condition

Operational Mode Two Outputs, using VOUTa and VOUTc, Continuous Readout

HCCD Clock Frequency 10 MHz

Pixels Per Line (Note 1) 6800

Lines Per Frame (Note 2) 2320

Line Time 715.7 ms

Frame Time 1660.5 ms

Photodiode Integration Time (PD_Tint) Mode A: PD_Tint = Frame Time = 1660.5 ms, No Electronic Shutter Used

VCCD Integration Time (Note 3) 1593.1 ms

Temperature 40°C

Light Source (Note 4) Continuous Red, Green and Blue LED Illumination

Operation Nominal Operating Voltages and Timing

1. Horizontal overclocking used.

2. Vertical overclocking used.

3. VCCD Integration Time = 2226 lines × Line Time, which is the total time a pixel will spend in the VCCD registers.

4. For monochrome sensor, only the green LED is used.

Table 8. DEFECT DEFINITIONS FOR TESTING AT 405C

Description Definition Grade 1

Grade 2

Mono

Grade 2

Color

Major Dark Field Defective Bright Pixel

(Note 1)

PD_Tint = Mode A ³ Defect ≥ 565 mV 270 540 540

Major Bright Field Defective Dark Pixel

(Note 1)

Defect ≥ 12%

Minor Dark Field Defective Bright Pixel PD_Tint = Mode A ³ Defect ≥ 282 mV 2700 5400 5400

Cluster Defect (Note 2) A group of 2 to 19 contiguous major defective

pixels, but no more than 4 adjacent defects

horizontally

20 N/A N/A

Cluster Defect (Note 2) A group of 2 to 38 contiguous major defective

pixels, but no more than 5 adjacent defects

horizontally

N/A 50 50

Column Defect (Note 2) A group of more than 10 contiguous major

defective pixels along a single column

0 7 27

1. For the color devices (KAI−29052−CXA and KAI−29052−QXA), a bright field defective pixel deviates by 12% with respect to pixels of the

same color.

2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).

KAI−29052

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Table 9. OPERATION CONDITIONS FOR DEFECT TESTING AT 275C

Description Condition

Operational Mode Two Outputs, using VOUTa and VOUTc, Continuous Readout

HCCD Clock Frequency 10 MHz

Pixels Per Line (Note 1) 6800

Lines Per Frame (Note 2) 2320

Line Time 715.7 ms

Frame Time 1660.5 ms

Photodiode Integration Time (PD_Tint) Mode A: PD_Tint = Frame Time = 1660.5 ms, No Electronic Shutter Used

VCCD Integration Time (Note 3) 1593.1 ms

Temperature 27°C

Light Source (Note 4) Continuous Red, Green and Blue LED Illumination

Operation Nominal Operating Voltages and Timing

1. Horizontal overclocking used.

2. Vertical overclocking used.

3. VCCD Integration Time = 2226 lines × Line Time, which is the total time a pixel will spend in the VCCD registers.

4. For monochrome sensor, only the green LED is used.

Table 10. DEFECT DEFINITIONS FOR TESTING AT 275C

Description Definition Grade 1

Grade 2

Mono

Grade 2

Color

Major Dark Field Defective Bright Pixel

(Note 1)

PD_Tint = Mode A ³ Defect ≥ 565 mV 270 540 540

Major Bright Field Defective Dark Pixel

(Note 1)

Defect ≥ 12%

Cluster Defect (Note 2) A group of 2 to 19 contiguous major defective

pixels, but no more than 4 adjacent defects

horizontally

20 N/A N/A

Cluster Defect (Note 2) A group of 2 to 38 contiguous major defective

pixels, but no more than 5 adjacent defects

horizontally

N/A 50 50

Column Defect (Note 2) A group of more than 10 contiguous major

defective pixels along a single column

0 7 27

1. For the color devices (KAI−29052−CXA and KAI−29052−QXA), a bright field defective pixel deviates by 12% with respect to pixels of the

same color.

2. Column and cluster defects are separated by no less than two (2) good pixels in any direction (excluding single pixel defects).

Defect Map

The defect map supplied with each sensor is based upon

testing at an ambient (27_C) temperature. Minor point

defects are not included in the defect map. All defective

pixels are reference to pixel 1, 1 in the defect maps. See

Figure 13: Regions of interest for the location of pixel 1, 1.

KAI−29052

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TEST DEFINITIONS

Test Regions of Interest

Image Area ROI: Pixel (1, 1) to Pixel (6600, 4408)

Active Area ROI: Pixel (13, 13) to Pixel (6588, 4396)

Center ROI: Pixel (3251, 2155) to Pixel (3350, 2254)

Only the Active Area ROI pixels are used for performance

and defect tests.

Overclocking

The test system timing is configured such that the sensor

is overclocked in both the vertical and horizontal directions.

See Figure 13 for a pictorial representation of the regions of

interest.

Figure 13. Regions of Interest

VOUTa

1, 1

13,

Pixel

UTc

22 Dark Columns

12 Buffer Columns

Horizontal Overclock

22 Dark Columns

12 Buffer Columns

22 Dark Rows

12 Buffer Rows

22 Dark Rows

6576 x 4384

Active Pixels

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Tests

Dark Field Global Non-Uniformity

This test is performed under dark field conditions. The

sensor is partitioned into 1536 sub regions of interest, each

of which is 137 by 137 pixels in size. The average signal

level of each of the 1536 sub regions of interest is calculated.

The signal level of each of the sub regions of interest is

calculated using the following formula:

(eq. 1)

Signal of ROI[i] +(ROI Average in Counts *Horizontal Overclock Average in Counts) @mV per Count [mV]

Where i = 1 to 1536. During this calculation on the 1536 sub

regions of interest, the maximum and minimum signal levels

are found. The dark field global uniformity is then calculated

as the maximum signal found minus the minimum signal

level found.

(eq. 2)

Dark Field Global Non−Uniformity = Maximum Signal − Minimum Signal [mVpp]

Global Non-Uniformity

This test is performed with the imager illuminated to

a level such that the output is at 70% of saturation

(approximately 490 V). Prior to this test being performed

the substrate voltage has been set such that the charge

capacity of the sensor is 700 mV. Global non-uniformity is

defined as:

(eq. 3)

Global Non−Uniformity +100 @ǒActive Area Standard Deviation

Active Area Signal Ǔ[%rms]

Global Peak to Peak Non-Uniformity

This test is performed with the imager illuminated to

a level such that the output is at 70% of saturation

(approximately 490 mV). Prior to this test being performed

the substrate voltage has been set such that the charge

capacity of the sensor is 700 mV. The sensor is partitioned

into 1536 sub regions of interest, each of which is 137 by 137

pixels in size. The average signal level of each of the 1536

sub regions of interest (ROI) is calculated. The signal level

of each of the sub regions of interest is calculated using the

following formula:

(eq. 4)

Signal of ROI[i] +(ROI Average in Counts *Horizontal Overclock Average in Counts) @mV per Count [mV]

Where i = 1 to 1536. During this calculation on the 1536 sub

regions of interest, the maximum and minimum signal levels

are found. The global peak to peak uniformity is then

calculated as:

(eq. 5)

Global Peak to Peak Non−Uniformity +100 @ǒMaximum Signal *Minimum Signal

Active Area Signal Ǔ[%pp]

Dark Field Defect Test

This test is performed under dark field conditions. The

sensor is partitioned into 1536 sub regions of interest, each

of which is 137 by 137 pixels in size. In each region of

interest, the median value of all pixels is found. For each

region of interest, a pixel is marked defective if it is greater

than or equal to the median value of that region of interest

plus the defect threshold specified in the “Defect

Definitions” section.

Bright Field Defect Test

This test is performed with the imager illuminated to

a level such that the output is at approximately 490 mV.

Prior to this test being performed the substrate voltage has

been set such that the charge capacity of the sensor is

700 mV. The average signal level of all active pixels is

found. The dark threshold is set as:

(eq. 6)

Dark Defect Threshold = Active Area Signal @Threshold

The sensor is then partitioned into 1536 sub regions of

interest, each of which is 137 by 137 pixels in size. In each

region of interest, the average value of all pixels is found.

For each region of interest, a pixel is marked defective if it

is greater than or equal to the median value of that region of

interest plus the bright threshold specified or if it is less than

or equal to the median value of that region of interest minus

the dark threshold specified.

Example for major bright field defective pixels:

•Average value of all active pixels is found to be 490 mV

•Dark defect threshold: 490 mV ⋅ 12% = 59 mV

•Region of interest #1 selected. This region of interest is

pixels 13, 13 to pixels 149, 149.

♦Median of this region of interest is found to be

495 mV.

♦Any pixel in this region of interest that is

≤ (495 − 59 mV) 436 mV in intensity will be marked

defective.

•All remaining 1536 sub regions of interest are analyzed

for defective pixels in the same manner.

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OPERATION

Table 11. ABSOLUTE MAXIMUM RATINGS

Description Symbol Minimum Maximum Unit

Operating Temperature (Note 1) TOP −50 70 °C

Humidity (Note 2) RH 5 90 %

Output Bias Current (Note 3) IOUT −60 mA

Off-Chip Load CL−10 pF

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. Noise performance will degrade at higher temperatures.

2. T = 25°C. Excessive humidity will degrade MTTF.

3. Total for all outputs. Maximum current is −15 mA for each output. Avoid shorting output pins to ground or any low impedance source during

operation. Amplifier bandwidth increases at higher current and lower load capacitance at the expense of reduced gain (sensitivity).

Table 12. ABSOLUTE MAXIMUM VOLTAGE RATINGS BETWEEN PINS AND GROUND

Description Minimum Maximum Unit

VDDa, VOUTa (Note 1) −0.4 17.5 V

RDa (Note 1) −0.4 15.5 V

V1B, V1T ESD − 0.4 ESD + 24.0 V

V2B, V2T, V3B, V3T, V4B, V4T ESD − 0.4 ESD + 14.0 V

FDGab, FDGcd ESD − 0.4 ESD + 15.0 V

H1Sa, H1Ba, H2Sa, H2Ba, H2SLa, Ra OGa (Note 1) ESD − 0.4 ESD + 14.0 V

ESD −10.0 0.0 V

SUB (Note 2) −0.4 40.0 V

1. a denotes a, b, c or d.

2. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions − AND9183/D.

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Power-Up and Power-Down Sequence

Adherence to the power-up and power-down sequence is

critical. Failure to follow the proper power-up and

power-down sequences may cause damage to the sensor.

Figure 14. Power-Up and Power-Down Sequence

VDD

SUB

ESD VCCD

and FDG

HCCD

Low

Time

V+

V−

Do Not Pulse the Electronic Shutter until ESD is Stable

Activate All Other Biases when ESD is Stable and Sub is above 3 V

Low

Warnings Regarding Power-Up and Power-Down

1. Activate all other biases when ESD is stable and

SUB is above 3 V.

2. Do not pulse the electronic shutter until ESD is

stable.

3. VDD cannot be +15 V when SUB is 0 V.

4. The VCCD clock waveform must not have

a negative overshoot more than 0.4 V below the

ESD voltage.

5. The image sensor can be protected from an

accidental improper ESD voltage by current

limiting the SUB current to less than 10 mA. SUB

and VDD must always be greater than GND. ESD

must always be less than GND. Placing diodes

between SUB, VDD, ESD and ground will protect

the sensor from accidental overshoots of SUB,

VDD, and ESD during power-up and power-down.

See figures shown below.

Figure 15. VCCD Overshoots

All VCCD and FDG Clocks Absolute

Maximum Overshoot of 0.4 V

0.0 V

ESD

ESD − 0.4 V

Figure 16. External Diode Protection

ESD

GND

VDDaSUB

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DC Bias Operating Conditions

Table 13. DC BIAS OPERATING CONDITIONS

Description Pins Symbol Min. Nom. Max. Unit

Max. DC

Current

Reset Drain (Note 1) RDaRD 11.8 12.0 12.2 V 10 mA

Output Gate (Note 1) OGaOG −2.2 −2.0 −1.8 V10 mA

Output Amplifier Supply (Notes 1, 2) VDDaVDD 14.5 15.0 15.5 V 11.0 mA

Ground GND GND 0.0 0.0 0.0 V −1.0 mA

Substrate (Notes 3, 8) SUB VSUB 5.0 VAB VDD V50 mA

ESD Protection Disable (Notes 6, 7) ESD ESD −9.2 −9.0 −8.8 V50 mA

Output Bias Current (Notes 1, 4, 5) VOUTaIOUT −3.0 −7.0 −10.0 mA −

1. a denotes a, b, c or d.

2. The maximum DC current is for one output. IDD = IOUT + ISS. See Figure 17.

3. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set such

that the photodiode charge capacity is the nominal PNe (see Specifications).

4. An output load sink must be applied to each VOUT pin to activate each output amplifier.

5. Nominal value required for 40 MHz operation per output. May be reduced for slower data rates and lower noise.

6. Adherence to the power-up and power-down sequence is critical. See Power-Up and Power-Down Sequence section.

7. ESD maximum value must be less than or equal to V1_L + 0.4 V and V2_L + 0.4 V.

8. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions − AND9183/D.

Figure 17. Output Amplifier

Source

Follower

Source

Follower

Source

Follower

Floating

Diffusion

ISS

IDD

IOUT

VOUTa

VDDa

RDa

HCCD

OGa

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AC Operating Conditions

Table 14. CLOCK LEVELS

Description

Pins

(Note 1) Symbol Level Min. Nom. Max. Unit

Capacitance

(Note 2)

Vertical CCD Clock,

Phase 1

V1B, V1T V1_L Low −9.2 −9.0 −8.8 V180 nF

(Note 6)

V1_M Mid −0.2 0.0 0.2

V1_H High 12.8 13.0 14.0

Vertical CCD Clock,

Phase 2

V2B, V2T V2_L Low −9.2 −9.0 −8.8 V180 nF

(Note 6)

V2_H High −0.2 0.0 0.2

Vertical CCD Clock,

Phase 3

V3B, V3T V3_L Low −9.2 −9.0 −8.8 V180 nF

(Note 6)

V3_H High −0.2 0.0 0.2

Vertical CCD Clock,

Phase 4

V4B, V4T V4_L Low −9.2 −9.0 −8.8 V180 nF

(Note 6)

V4_H High −0.2 0.0 0.2

Horizontal CCD Clock,

Phase 1 Storage

H1SaH1S_L Low −5.0

(Note 7)

−4.4 −4.2 V600 pF

(Note 6)

H1S_A Amplitude 4.2 4.4 5.0

(Note 7)

Horizontal CCD Clock,

Phase 1 Barrier

H1BaH1B_L Low −5.0

(Note 7)

−4.4 −4.2 V400 pF

(Note 6)

H1B_A Amplitude 4.2 4.4 5.0

(Note 7)

Horizontal CCD Clock,

Phase 2 Storage

H2SaH2S_L Low −5.0

(Note 7)

−4.4 −4.2 V580 pF

(Note 6)

H2S_A Amplitude 4.2 4.4 5.0

(Note 7)

Horizontal CCD Clock,

Phase 2 Barrier

H2BaH2B_L Low −5.0

(Note 7)

−4.4 −4.2 V400 pF

(Note 6)

H2B_A Amplitude 4.2 4.4 5.0

(Note 7)

Horizontal CCD Clock,

Last Phase (Note 3)

H2SLaH2SL_L Low −5.2 −5.0 −4.8 V20 pF

(Note 6)

H2SL_A Amplitude 4.8 5.0 5.2

Reset Gate RaR_L

(Note 4)

Low −3.5 −2.0 −1.5 V16 pF

(Note 6)

R_H High 2.5 3.0 4.0

Electronic Shutter

(Notes 5, 8)

SUB VES High 29.0 30.0 40.0 V 12 pF

(Note 6)

Fast Line Dump Gate FDGaFDG_L Low −9.2 −9.0 −8.8 V50 pF

(Note 6)

FDG_H High 4.5 5.0 5.5

1. a denotes a, b, c or d.

2. Capacitance is total for all like named pins.

3. Use separate clock driver for improved speed performance.

4. Reset low should be set to –3 volts for signal levels greater than 40,000 electrons.

5. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions − AND9183/D.

6. Capacitance values are estimated.

7. If the minimum horizontal clock low level is used (–5.0 V), then the maximum horizontal clock amplitude should be used (5 V amplitude) to

create a –5.0 V to 0.0 V clock.

8. Figure 18 shown below shows the DC bias (VSUB) and AC clock (VES) applied to the SUB pin. Both the DC bias and AC clock are referenced

to ground.

Figure 18. Substrate and Electron Shutter Reference to Ground

VSUB

VES

GND GND

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Device Identification

The device identification pin (DevID) may be used to determine which ON Semiconductor 5.5 micron pixel interline CCD

sensor is being used.

Table 15. DEVICE IDENTIFICATION

Description Pins Symbol Min. Nom. Max. Unit

Max. DC

Current

Device Identification (Notes 1, 2) DevID DevID 200,000 300,000 400,000 W50 mA

1. If the Device Identification is not used, it may be left disconnected.

2. After Device Identification resistance has been read during camera initialization, it is recommended that the circuit be disabled to prevent

localized heating of the sensor due to current flow through the R_DeviceID resistor.

Recommended Circuit

Note that V1 must be a different value than V2.

Figure 19. Device Identification Recommended Circuit

ADC

R_external

V1 V2

DevID

GND

KAI−29052

R_DeviceID

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TIMING

Table 16. REQUIREMENTS AND CHARACTERISTICS

Description Symbol Min. Nom. Max. Unit Notes

Photodiode Transfer tPD 6− − ms

VCCD Leading Pedestal t3P 16 − − ms

VCCD Trailing Pedestal t3D 16 − − ms

VCCD Transfer Delay tD4− − ms

VCCD Transfer tV8− − ms

VCCD Clock Cross-Over VVCR 75 −100 % 1

VCCD Rise, Fall Times tVR, tVF 5−10 %1, 2

FDG Delay tFDG 2− − ms

HCCD Delay tHS 1− − ms

HCCD Transfer te25.0 29.4 −ns

Shutter Transfer tSUB 1− − ms

Shutter Delay tHD 1− − ms

Reset Pulse tR2.5 − − ns

Reset − Video Delay tRV −2.2 −ns

H2SL − Video Delay tHV −3.1 −ns

Line Time tLINE 96.3 110.0 −msDual HCCD Readout

179.4 208.7 −Single HCCD Readout

Frame Time tFRAME 213.5 246.1 −ms Quad HCCD Readout

427.0 492.2 −Dual HCCD Readout

795.1 925.2 −Single HCCD Readout

1. Refer to Figure 24: VCCD Clock Rise Time, Fall Time, and Edge Alignment.

2. Relative to the pulse width.

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Timing Diagrams

The timing sequence for the clocked device pins may be

represented as one of seven patterns (P1−P7) as shown in the

table below. The patterns are defined in Figure 20 and

Figure 21. Contact ON Semiconductor Application

Engineering for other readout modes.

Table 17. TIMING DIAGRAMS

Device Pin Quad Readout

Dual Readout

VOUTa, VOUTb

Dual Readout

VOUTa, VOUTc

Single Readout

VOUTa

V1T P1T P1B P1T P1B

V2T P2T P4B P2T P4B

V3T P3T P3B P3T P3B

V4T P4T P2B P4T P2B

V1B P1B

V2B P2B

V3B P3B

V4B P4B

H1Sa P5

H1Ba

H2Sa (Note 2) P6

H2Ba

Ra P7

H1Sb P5 P5

H1Bb P6

H2Sb (Note 2) P6 P6

H2Bb P5

Rb P7 P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3)

H1Sc P5 P5 (Note 1) or Off (Note 3) P5 P5 (Note 1) or Off (Note 3)

H1Bc

H2Sc (Note 2) P6 P6 (Note 1) or Off (Note 3) P6 P6 (Note 1) or Off (Note 3)

H2Bc

Rc P7 P7 (Note 1) or Off (Note 3) P7 P7 (Note 1) or Off (Note 3)

H1Sd P5 P5 (Note 1) or Off (Note 3) P5 P5 (Note 1) or Off (Note 3)

H1Bd P6

H2Sd (Note 2) P6 P6 (Note 1) or Off (Note 3) P6 P6 (Note 1) or Off (Note 3)

H2Bd P5

Rd P7 P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3) P7 (Note 1) or Off (Note 3)

#Lines/Frame

(Minimum)

2226 4452 2226 4452

#Pixels/Line

(Minimum)

3333 6666

1. For optimal performance of the sensor. May be clocked at a lower frequency. If clocked at a lower frequency, the frequency selected should

be a multiple of the frequency used on the a and b register.

2. H2SLx follows the same pattern as H2Sx. For optimal speed performance, use a separate clock driver.

3. Off = +5 V. Note that there may be operating conditions (high temperature and/or very bright light sources) that will cause blooming from the

unused c/d register into the image area.

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Photodiode Transfer Timing

A row of charge is transferred to the HCCD on the falling

edge of V1 as indicated in the P1 pattern below. Using this

timing sequence, the leading dummy row or line is

combined with the first dark row in the HCCD. The “Last

Line” is dependent on readout mode – either 2226 or 4452

minimum counts required. It is important to note that, in

general, the rising edge of a vertical clock (patterns P1−P4)

should be coincident or slightly leading a falling edge at the

same time interval. This is particularly true at the point

where P1 returns from the high (3rd level) state to the

mid-state when P4 transitions from the low state to the high

state.

Figure 20. Photodiode Transfer Timing

Last Line L1 + Dummy Line

P1B

P2B

P3B

P4B

Pattern

P1T

P2T

P3T

P4T

1 2 3 4 5 6

tV/2

tHS

t3P tPD t3D

tV/2

tHS

tV/2

Line and Pixel Timing

Each row of charge is transferred to the output, as

illustrated below, on the falling edge of H2SL (indicated as

P6 pattern). The number of pixels in a row is dependent on

readout mode – either 3333 or 6666 minimum counts

required.

Figure 21. Line and Pixel Timing

P1T

Pixel

VOUT

Pattern

P1B

te/2

tHS

tLINE

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Pixel Timing Detail

Figure 22. Pixel Timing Detail

VOUT

tHV tRV

Frame/Electronic Shutter Timing

The SUB pin may be optionally clocked to provide

electronic shuttering capability as shown below. The

resulting photodiode integration time is defined from the

falling edge of SUB to the falling edge of V1 (P1 pattern).

Figure 23. Electronic Shutter Timing

P1T/B

SUB

Pattern

tHD

tSUB

tINT

tFRAME

VCCD Clock Edge Alignment

Figure 24. VCCD Clock Rise Time, Fall Time, and Edge Alignment

VVCR

90%

10%

tVF

tVR

tVF tVR

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Line and Pixel Timing − Vertical Binning by 2

P1T

P2T

P3T

P4T

P1B

P2B

P3B

P4B

VOUT

Pixel

tHS

Figure 25. Line and Pixel Timing − Vertical Binning by 2

Fast Line Dump Timing

The FDG pins may be optionally clocked to efficiently

remove unwanted lines in the image resulting for increased

frame rates at the expense of resolution. Below is an example

of a 2 line dump sequence followed by a normal readout line.

Figure 26. Fast Line Dump Timing

tFDG

Clock

V1B

V2B

FDGab

H1S

V1T

V2T

FDGcd

H1S

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STORAGE AND HANDLING

Table 18. STORAGE CONDITIONS

Description Symbol Minimum Maximum Unit

Storage Temperature (Note 1) TST −55 80 °C

Humidity (Note 2) RH 5 90 %

1. Long-term exposure toward the maximum temperature will accelerate color filter degradation.

2. T = 25°C. Excessive humidity will degrade MTTF.

For information on ESD and cover glass care and

cleanliness, please download the Image Sensor Handling

and Best Practices Application Note (AN52561/D) from

www.onsemi.com.

For information on environmental exposure, please

download the Using Interline CCD Image Sensors in High

Intensity Lighting Conditions Application Note

(AND9183/D) from www.onsemi.com.

For information on soldering recommendations, please

download the Soldering and Mounting Techniques

Reference Manual (SOLDERRM/D) from

www.onsemi.com.

For quality and reliability information, please download

the Quality & Reliability Handbook (HBD851/D) from

www.onsemi.com.

For information on device numbering and ordering codes,

please download the Device Nomenclature technical note

(TND310/D) from www.onsemi.com.

For information on Standard terms and Conditions of

Sale, please download Terms and Conditions from

www.onsemi.com.

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MECHANICAL INFORMATION

Completed Assembly

Figure 27. Completed Assembly (1 of 2)

Notes:

1. See Ordering Information for marking code.

2. Cover glass not to overhang package holes or outer ceramic edges.

3. Glass epoxy not to extend over image array.

4. No materials to interfere with clearance through package holes.

5. Units: IN [MM].

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Figure 28. Completed Assembly (2 of 2)

Notes:

1. Units: IN [MM].

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Cover Glass

Figure 29. Cover Glass

Notes:

1. Substrate = Schott D263T eco

2. Dust, Scratch, Inclusion Specification:

a. 20_m Max size in Zone A

b. Zone A = 1.474 × 1.000 [16.43 × 10.08] Centered

3. MAR coated both sides

4. Spectral Transmission

a. 350−365 nm: T ≥ 88%

b. 365−405 nm: T ≥ 94%

c. 405−450 nm: T ≥ 98%

d. 450−650 nm: T ≥ 99%

e. 650−690 nm: T ≥ 98%

f. 690−770 nm: T ≥ 94%

g. 770−870 nm: T ≥ 88%

5. Units: IN [MM]

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Cover Glass Transmission

Figure 30. Cover Glass Transmission

100

200 300 400 500 600 700 800 900

Wavelength (nm)

Transmission (%)

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