© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 2
1Publication Order Number:
SA572/D
SA572
Programmable Analog
Compandor
The SA572 is a dual-channel, high-performance gain control
circuit in which either channel may be used for dynamic range
compression or expansion. Each channel has a full-wave rectifier to
detect the average value of input signal, a linearized, temperature-
compensated variable gain cell (G) and a dynamic time constant
buffer. The buffer permits independent control of dynamic attack and
recovery time with minimum external components and improved low
frequency gain control ripple distortion over previous compandors.
The SA572 is intended for noise reduction in high-performance
audio systems. It can also be used in a wide range of communication
systems and video recording applications.
Features
•Independent Control of Attack and Recovery Time
•Improved Low Frequency Gain Control Ripple
•Complementary Gain Compression and Expansion with
External Op Amp
•Wide Dynamic Range − Greater than 110 dB
•Temperature-Compensated Gain Control
•Low Distortion Gain Cell
•Low Noise − 6.0 V Typical
•Wide Supply Voltage Range − 6.0 V-22 V
•System Level Adjustable with External Components
•Pb−Free Packages are Available*
Applications
•Dynamic Noise Reduction System
•Voltage Control Amplifier
•Stereo Expandor
•Automatic Level Control
•High-Level Limiter
•Low-Level Noise Gate
•State Variable Filter
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
PIN CONNECTIONS
1
2
3
4
5
6
7
89
10
11
12
13
14
16
15
D, N, DTB Packages*
TRACK TRIM A
RECOV. CAP A
RECT. IN A
ATTACK CAP A
THD TRIM A
GND
G OUT A
G IN A
TRACK TRIM B
RECOV. CAP B
RECT. IN B
ATTACK CAP B
THD TRIM B
G OUT B
G IN B
VCC
*D package released in large SO (SOL) package only.
PDIP−16
N SUFFIX
CASE 648
16
1
16
SOIC−16 WB
D SUFFIX
CASE 751G
1
MARKING DIAGRAMS
16
1
SA572D
AWLYYWWG
16
1
SA572N
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G= Pb−Free Package
16
1
SA
572
ALYW G
G
TSSOP−16
DTB SUFFIX
CASE 948F
16
1
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(Note: Microdot may be in either location)
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2
(7,9)
(6,10)
(3,13)
(16)
(8) (4,12) (2,14)
(1,15)
(5,11)
GAIN CELL
RECTIFIER
P.S.
BUFFER
270
500
Ω
Ω
G
−
+
−
+
Figure 1. Block Diagram
6.8k
10k10k
R1
PIN FUNCTION DESCRIPTION
Pin Symbol Description
1TRACK TRIM A Tracking Trim A
2RECOV. CAP A Recovery Capacitor A
3RECT. IN A Rectifier A Input
4ATTACK CAP A Attack Capacitor A
5G OUT A Variable Gain Cell A Output
6THD TRIM A Total Harmonic Distortion Trim A
7G IN A Variable Gain Cell A Input
8 GND Ground
9G IN B Variable Gain Cell B Input
10 THD TRIM B Total Harmonic Distortion Trim B
11 G OUT B Variable Gain Cell B Output
12 ATTACK CAP B Attack Capacitor B
13 RECT. IN B Rectifier B Input
14 RECOV. CAP B Recovery Capacitor B
15 TRACK TRIM B Tracking Trim B
16 VCC Positive Power Supply
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3
MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC 22 VDC
Operating Temperature Range TA−40 to +85 °C
Operating Junction Temperature TJ150 °C
Power Dissipation PD500 mW
Thermal Resistance, Junction−to−Ambient N Package
D Package
DTB Package
RJA 75
105
133
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
DC ELECTRICAL CHARACTERISTICS Standard test conditions, VCC = 15 V, TA = 25°C; Expandor mode (see Test Circuit). Input
signals at unity gain level (0 dB) = 100 mVRMS at 1.0 kHz; V1 = V2; R2 = 3.3 k; R3 = 17.3 k unless otherwise noted.
Characteristic Symbol Test Conditions Min Typ Max Unit
Supply Voltage VCC −6.0 −22 VDC
Supply Current ICC No Signal − − 6.3 mA
Internal Voltage Reference VR−2.3 2.5 2.7 VDC
Total Harmonic Distortion (Untrimmed)
Total Harmonic Distortion (Trimmed)
Total Harmonic Distortion (Trimmed)
THD
THD
THD
1.0 kHz, CA = 1.0 F
1.0 kHz, CR = 10 F
100 Hz
−
−
−
0.2
0.05
0.25
1.0
−
−
%
%
%
No Signal Output Noise Input to V1 and V2
grounded (20−20 kHz)
−6.0 25 V
DC Level Shift (Untrimmed) Input change from no
signal to 100 mVRMS
−"20 "50 mV
Unity Gain Level − −1.5 0 +1.5 dB
Large-Signal Distortion V1 = V2 = 400 mV −0.7 3.0 %
Tracking Error
(Measured relative to value at unity gain) =
[VO−VO (unity gain)] dB−V2dB
Rectifier Input
V2 = +6.0 dB, V1 = 0 dB
V2 = −30 dB, V1 = 0 dB
−
−"0.2
"0.5 −2.5, +1.6
dB
dB
Channel Crosstalk 200 mVRMS into
channel A, measured
output on channel B
60 − − dB
Power Supply Rejection Ratio PSRR 120 Hz −70 −dB
Figure 2. Test Circuit
BUFFER
RECTIFIER
NE5234
+15V
−15V
(7,9)
(2,14)
(4,12)
(5,11)
(6,10)
(8)
(1,15)
(16)
(3,13)
G
V1
V2
V0
270pF
2.2k
1%
2.2F
22F
2.2F
22F
0.1F
1F
2.2F
5
CR = 10F
R3
1%
R2
100
+
+
+
+
−
6.8k
3.3k
82k
1k
17.3k
CA = 1F
SA572
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4
Audio Signal Processing IC Combines VCA and
Fast Attack/Slow Recovery Level Sensor
In high-performance audio gain control applications, it
is desirable to independently control the attack and
recovery time of the gain control signal. This is true, for
example, in compandor applications for noise reduction. In
high end systems the input signal is usually split into two
or more frequency bands to optimize the dynamic behavior
for each band. This reduces low frequency distortion due
to control signal ripple, phase distortion, high frequency
channel overload and noise modulation. Because of the
expense in hardware, multiple band signal processing up to
now was limited to professional audio applications.
With the introduction of the SA572 this high-
performance noise reduction concept becomes feasible for
consumer hi fi applications. The SA572 is a dual channel
gain control IC. Each channel has a linearized,
temperature-compensated gain cell and an improved level
sensor. In conjunction with an external low noise op amp
for current-to-voltage conversion, the VCA features low
distortion, low noise and wide dynamic range.
The novel level sensor which provides gain control
current for the VCA gives lower gain control ripple and
independent control of fast attack, slow recovery dynamic
response. An attack capacitor CA with an internal 10 k
resistor RA defines the attack time A. The recovery time
R of a tone burst is defined by a recovery capacitor CR and
an internal 10 k resistor RR. Typical attack time of 4.0 ms
for the high-frequency spectrum and 40 ms for the low
frequency band can be obtained with 0.1 F and 1.0 F
attack capacitors, respectively. Recovery time of 200 ms
can be obtained with a 4.7 F recovery capacitor for a
100 Hz signal, the third harmonic distortion is improved by
more than 10 dB over the simple RC ripple filter with a
single 1.0 F attack and recovery capacitor, while the
attack time remains the same.
The SA572 is assembled in a standard 16-pin dual in-line
plastic package and in oversized SOL package. It operates
over a wide supply range from 6.0 V to 22 V. Supply
current is less than 6.0 mA. The SA572 is designed for
applications from −40°C to +85°C.
BASIC APPLICATIONS
Description
The SA572 consists of two linearized, temperature-
compensated gain cells (G), each with a full-wave
rectifier and a buffer amplifier as shown in the block
diagram. The two channels share a 2.5 V common bias
reference derived from the power supply but otherwise
operate independently. Because of inherent low distortion,
low noise and the capability to linearize large signals, a
wide dynamic range can be obtained. The buffer amplifiers
are provided to permit control of attack time and recovery
time independent of each other. Partitioned as shown in the
block diagram, the IC allows flexibility in the design of
system levels that optimize DC shift, ripple distortion,
tracking accuracy and noise floor for a wide range of
application requirements.
Gain Cell
Figure 3 shows the circuit configuration of the gain cell.
Bases of the differential pairs Q1-Q2 and Q3-Q4 are both
tied to the output and inputs of OPA A1. The negative
feedback through Q1 holds the VBE of Q1-Q2 and the VBE
of Q3-Q4 equal. The following relationship can be derived
from the transistor model equation in the forward active
region.
VBEQ3Q4 +BEQ1Q2
(VBE = VT IIN IC/IS)
VTInǒ1
2IG)1
2IO
ISǓ*VTInǒ1
2IG*1
2IO
ISǓ
+VTInǒI1)IIN
ISǓ*VTInǒI2*I1*IIN
ISǓ
(eq. 1)
where IIN +VIN
R1
R1 = 6.8 k
I1 = 140 A
I2 = 280 A
IO is the differential output current of the gain cell and IG
is the gain control current of the gain cell.
If all transistors Q1 through Q4 are of the same size,
equation 1 can be simplified to:
IO+2
I2@IIN @IG*1
I2
ǒI2*2I1Ǔ@IG(eq. 2)
The first term of equation 2 shows the multiplier
relationship of a linearized two quadrant transconductance
amplifier. The second term is the gain control feedthrough
due to the mismatch of devices. In the design, this has been
minimized by large matched devices and careful layout.
Offset voltage is caused by the device mismatch and it leads
to even harmonic distortion. The offset voltage can be
trimmed out by feeding a current source within "25 A
into the THD trim pin.
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5
The residual distortion is third harmonic distortion and
is caused by gain control ripple. In a compandor system,
available control of fast attack and slow recovery improve
ripple distortion significantly. At the unity gain level of
100 mV, the gain cell gives THD (total harmonic
distortion) of 0.17% typ. Output noise with no input signals
is only 6.0 V in the audio spectrum (10 Hz-20 kHz). The
output current IO must feed the virtual ground input of an
operational amplifier with a resistor from output to
inverting input. The non-inverting input of the operational
amplifier has to be biased at VREF if the output current IO
is DC coupled.
VREF
THD
TRIM
V+
1
2IG)1
2IOI1
140A
280A
I2
IG
IO
Q4Q3Q1Q2
VIN
+−
A1
Figure 3. Basic Gain Cell Schematic
R1
6.8k
Rectifier
The rectifier is a full-wave design as shown in Figure 4.
The input voltage is converted to current through the input
resistor R2 and turns on either Q5 or Q6 depending on the
signal polarity. Deadband of the voltage to current
converter is reduced by the loop gain of the gain block A2.
If AC coupling is used, the rectifier error comes only from
input bias current of gain block A2. The input bias current
is typically about 70 nA. Frequency response of the gain
block A2 also causes second-order error at high frequency.
The collector current of Q6 is mirrored and summed at the
collector of Q5 to form the full wave rectified output
current IR. The rectifier transfer function is:
IR+VIN *VREF
R2
(eq. 3)
If VIN is AC-coupled, then the equation will be reduced
to:
IRAC +VIN(AVG)
R2
The internal bias scheme limits the maximum output
current IR to be around 300 A. Within a "1.0 dB error
band the input range of the rectifier is about 52 dB.
VIN
VREF
V+
A2
+
−
IR+
VIN *VREF
R2
Figure 4. Simplified Rectifier Schematic
Q5
Q6
R2
D7
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Buffer Amplifier
In audio systems, it is desirable to have fast attack time
and slow recovery time for a tone burst input. The fast
attack time reduces transient channel overload but also
causes low-frequency ripple distortion. The low-frequency
ripple distortion can be improved with the slow recovery
time. If different attack times are implemented in
corresponding frequency spectrums in a split band audio
system, high quality performance can be achieved. The
buffer amplifier is designed to make this feature available
with minimum external components. Referring to
Figure 5, the rectifier output current is mirrored into the
input and output of the unipolar buffer amplifier A3 through
Q8, Q9 and Q10. Diodes D11 and D12 improve tracking
accuracy and provide common-mode bias for A3. For a
positive-going input signal, the buffer amplifier acts like a
voltage-follower. Therefore, the output impedance of A3
makes the contribution of capacitor CR to attack time
insignificant. Neglecting diode impedance, the gain Ga(t)
for G can be expressed as follows:
Ga(t) +(GaINT *GaFNL)e
*t
A)GaFNL
GaINT = Initial Gain
GaFNL = Final Gain
A = RA • CA = 10 k • CA
where A is the attack time constant and RA is a 10 k
internal resistor. Diode D15 opens the feedback loop of A3
for a negative-going signal if the value of capacitor CR is
larger than capacitor CA. The recovery time depends only
on CR • RR. If the diode impedance is assumed negligible,
the dynamic gain GR (t) for G is expressed as follows:
GR(t) +(GRINT *GRFNL)e
*t
R)GRFNL
GR(t) +(GRINT *GRFNL)e
*t
R)GRFNL
R = RR • CR = 10 k • CR
where R is the recovery time constant and RR is a 10 k
internal resistor. The gain control current is mirrored to the
gain cell through Q14. The low level gain errors due to input
bias current of A2 and A3 can be trimmed through the
tracking trim pin into A3 with a current source of "3.0 A.
X2
X2
A3
TRACKING
TRIM
IR1
IR2
IQ = 2IR2
V+
IR+
VIN
R
−
+
Figure 5. Buffer Amplifier Schematic
10k
10k
Q8Q9Q10
Q16
D13
D15
Q14 Q18
D11
D12
CACR
Q17
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7
Basic Expandor
Figure 6 shows an application of the circuit as a simple
expandor. The gain expression of the system is given by:
VOUT
VIN +ǒ2
I1@R3@VIN(AVG)
R2@R1Ǔ2(eq. 4)
(I1 = 140 A)
Both the resistors R1 and R2 are tied to internal summing
nodes. R1 is a 6.8 k internal resistor. The maximum input
current into the gain cell can be as large as 140 A. This
corresponds to a voltage level of 140 A•6.8 k = 952 mV
peak. The input peak current into the rectifier is limited to
300 A by the internal bias system. Note that the value of
R1 can be increased to accommodate higher input level. R2
and R3 are external resistors. It is easy to adjust the ratio of
R3/R2 for desirable system voltage and current levels. A
small R2 results in higher gain control current and smaller
static and dynamic tracking error. However, an impedance
buffer A1 may be necessary if the input is voltage driven
with large source impedance.
The gain cell output current feeds the summing node of
the external OPA A2. R3 and A2 convert the gain cell output
current to the output voltage. In high-performance
applications, A2 has to be low-noise, high-speed and wide
band so that the high-performance output of the gain cell
will not be degraded. The non-inverting input of A2 can be
biased at the low noise internal reference Pin 6 or 10.
Resistor R4 is used to bias up the output DC level of A2 for
maximum swing. The output DC level of A2 is given by:
VOUT DC +VREFǒ1)R3
R4Ǔ*VB
R3
R4
(eq. 5)
VB can be tied to a regulated power supply for a dual
supply system and be grounded for a single supply system.
CA sets the attack time constant and CR sets the recovery
time constant.
−
+
A1 (7,9)
(3,13)
(8) (16)
(4,12)
(2,14)
(6,10)
(5,11)
BUFFER
A2 VOUT
VIN
CIN1
CIN2
CIN3
VREF
+VB
+VCC
G
10F1F
2.2F
2.2F
2.2F
Figure 6. Basic Expandor Schematic
R5
100k
R2
3.3k
6.8k
17.3k
1k
R4R3
R1
R6
C1
CR
CA
2.2F
Basic Compressor
Figure 7 shows the hook-up of the circuit as a
compressor. The IC is put in the feedback loop of the OPA
A1. The system gain expression is as follows:
VOUT
VIN +ǒI1
2@R2@R1
R3@VIN(AVG)Ǔ
1
2(eq. 6)
(I1 = 140 A)
RDC1, RDC2, and CDC form a DC feedback for A1. The
output DC level of A1 is given by:
VOUT DC +VREFǒ1)RDC1 )RDC2
R4Ǔ
*VB@ǒRDC1 )RDC2
R4Ǔ
(eq. 7)
The zener diodes D1 and D2 are used for channel
overload protection.
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8
(7,9)
BUFFER
VREF
G
A1
(6,10)
(5,11)
(2,14)
(4,12)
(8)
(3,13)
(16)
CIN3
VCC
10F
.1F
2.2F
CIN1
VIN
10F1F
2.2F
CIN2
2.2F
VOUT
−
+
Figure 7. Basic Compressor Schematic
R3
17.3k
1k
9.1k9.1k
6.8k
3.3k
RDC1
R4RDC2
CDC
C2
D1D2
C1
R5
R1
CA
CR
R2
Basic Compandor System
The above basic compressor and expandor can be
applied to systems such as tape/disc noise reduction, digital
audio, bucket brigade delay lines. Additional system
design techniques such as bandlimiting, band splitting,
pre-emphasis, de-emphasis and equalization are easy to
incorporate. The IC is a versatile functional block to
achieve a high performance audio system. Figure 8 shows
the system level diagram for reference.
COMPRESSION
IN EXPANDOR
OUT
REL LEVEL ABS LEVEL
dB dBM
3.0 V
547.6 mV
400 mV
100 mV
10 mV
1 mV
+29.54
+14.77
+12.0
0.0
−20
−40
−60
−80
+11.76
−3.00
−5.78
−17.78
−37.78
−57.78
−77.78
−97.78
VRMS
100 V
10 V
2
1
2
Figure 8. SA572 System Level
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9
BUFFER
G
10 F
2.2 F
C3
VIN
VOUT
Figure 9. Automatic Level Control
R3
17.3k
9.1k 9.1k
RDC1
R4RDC2
CDC
C5
R55532
−
+
VOUT
100k
+22 F
CA
+1 FCR
+10 F
+
2.2 F
C2+
2.2 F
+
2.2 F
C1+R1
3.3k
RX
6.8k
ATTACK
CAP
RECOVERY
CAP
V+
V−
TO THD
TRIM PIN
OF 572
PINS 6, 10
1k
+
3, 13
4, 12
5, 11
2, 14
7, 9
DC
1
2
3
R2
Automatic Level Control (ALC)
In the ALC configuration, the variable gain cell is placed
in the feedback loop of the operational amplifier and the
rectifier is connected to the input. As the input amplitude
increases above the crossover point, the overall system
gain decreases proportionally, holding the output
amplitude constant. As the input amplitude decreases
below the crossover point, the overall system gain
increases proportionally, holding the output amplitude at
the same constant level.
Gain +R1R2I1
2R
3VIN(avg)
where: R1 = 6.8 k (Internal)
R2 = 3.3 k
R3 = 17.3 k
I1 = 140 A
The output DC level can be set using the following
equation:
VOUT DC +ǒ1)RDC1 )RDC2
R4ǓVREF
where: R4 = 100 k
RDC1 = RDC2 = 9.1 k
VREF = 2.5 V
The output level is calculated using the following
equation:
VOUT_LEVEL +R1R2I1
2R
3ǒVIN
VIN (avg)Ǔ
where: R1 = 6.8 k (Internal)
R2 = 3.3 k
R3 = 17.3 k
I1 = 140 A
VIN
VIN (avg) +
22
Ǹ+1.11 (for sine waves)
Note that for very low input levels, ALC may not be
desired and to limit the maximum gain, resistor RX has
been added.
Gain max. +ǒR1)Rx
VREF Ǔ·R
2·I
B
2R
3
Rx^((desired max gain) 26 k)*10 k
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ORDERING INFORMATION
Device Description Package Temperature Range Shipping†
SA572D 16−Pin Plastic Small Outline Package SO−16 WB −40 to +85°C47 Units / Rail
SA572DG 16−Pin Plastic Small Outline Package
(Pb−Free)
SO−16 WB −40 to +85°C47 Units / Rail
SA572DR2 16−Pin Plastic Small Outline Package SO−16 WB −40 to +85°C1000 / Tape & Reel
SA572DR2G 16−Pin Plastic Small Outline Package
(Pb−Free)
SO−16 WB −40 to +85°C1000 / Tape & Reel
SA572DTB 16−Pin Thin Shrink Small Outline Package TSSOP−16* −40 to +85°C96 Units / Rail
SA572DTBG 16−Pin Thin Shrink Small Outline Package TSSOP−16* −40 to +85°C96 Units / Tube
SA572DTBR2 16−Pin Thin Shrink Small Outline Package TSSOP−16* −40 to +85°C2500 / Tape & Reel
SA572DTBR2G 16−Pin Thin Shrink Small Outline Package TSSOP−16* −40 to +85°C2500 / Tape & Reel
SA572NG 16−Pin Plastic Dual In−Line Package PDIP−16 −40 to +85°C25 Units / Rail
SA572NG 16−Pin Plastic Dual In−Line Package
(Pb−Free)
PDIP−16 −40 to +85°C25 Units / Rail
†For information on / Tape and reel specifications, including part orientation and / Tape sizes, please refer to our / Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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11
PACKAGE DIMENSIONS
SOIC−16 WB
D SUFFIX
CASE 751G−03
ISSUE C
D
14X
B16X
SEATING
PLANE
S
A
M
0.25 B S
T
16 9
81
hX 45_
M
B
M
0.25
H8X
E
B
A
e
T
A1
A
L
C
qNOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
DIM MIN MAX
MILLIMETERS
A2.35 2.65
A1 0.10 0.25
B0.35 0.49
C0.23 0.32
D10.15 10.45
E7.40 7.60
e1.27 BSC
H10.05 10.55
h0.25 0.75
L0.50 0.90
q0 7
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
−T−
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
PDIP−16
CASE 648−08
ISSUE T
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12
PACKAGE DIMENSIONS
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
SECTION N−N
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉ
ÉÉ
DETAIL E
F
M
L
2X L/2
−U−
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
−T−
−V−
−W−
0.25 (0.010)
16X REFK
N
N
TSSOP−16
CASE 948F−01
ISSUE A
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