Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
4A, Ultra Low Dropout (0.30V Typical) Linear Regulator
Features
• Compatible with APL5913
• Ultra Low Dropout
- 0.30V(typical) at 4A Output Current
• Low ESR Output Capacitor (Multi-Layer Chip Ca
pacitors (MLCC)) Applicable
• 0.8V Reference Voltage
• High Output Accuracy
- ±1.5% over Line, Load, and Temperature Range
• Fast Transient Response
• Adjustable Output Voltage
• Power-On-Reset Monitoring on Both VCNTL and
VIN Pins
• Inernal Soft-Start
• Current-Limit and Short Current-Limit Protections
• Thermal Shutdown with Hysteresis
• Open-Drain VOUT Voltage Indicator (POK)
• Low Shutdown Quiescent Current (<30 µA)
• Shutdown/Enable Control Function
• Simple SOP-8P Package with Exposed Pad
• Lead Free and Green Devices Available
(RoHS Compliant)
Applications
General Description
The APL5940 is a 4A ultra low dropout linear regulator.
The IC needs two supply voltages, one is a control voltage
(VCNTL) for the control circuitry, the other is a main supply
voltage (VIN) for power conversion, to reduce power dissi-
pation and provide extremely low dropout voltage.
The APL5940 integrates many functions. A Power-On-
Reset (POR) circuit monitors both supply voltages on
VCNTL and VIN pins to prevent erroneous operations.
The functions of thermal shutdown and current-limit pro-
tect the device against thermal and current over-loads. A
POK indicates the output voltage status with a delay time
set internally. It can control other converter for power
sequence. The APL5940 can be enabled by other power
systems. Pulling and holding the EN voltage below 0.4V
shuts off the output.
The APL5940 is available in a SOP-8P package which
features small size as SOP-8 and an Exposed Pad to
reduce the junction-to-case resistance to extend power
range of applications.
• Front Side Bus VTT
• NoteBook PC Applications
• Motherboard Applications
Simplified Application CircuitPin Configuration
= Exposed Pad
(connected to VIN plane for better heat dissipation)
GND
FB
VOUT
1
2
3
4
EN
POK
VCNTL
VIN
8
7
6
5
SOP-8P (Top View)
VOUT
VCNTL
VOUT
VIN
GND
VOUT
VCNTL
POK VIN
EN
Enable EN
POK
APL5940
FB
Optional
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw2
Ordering and Marking Information
Symbol Parameter Rating Unit
VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 4.0 V
VCNTL VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 7 V
VOUT VOUT to GND Voltage -0.3 ~ VIN +0.3 V
POK to GND Voltage -0.3 ~ 7 V
EN, FB to GND Voltage -0.3 ~ VCNTL +0.3 V
PD Power Dissipation 3 W
TJ Maximum Junction Temperature 150 oC
TSTG Storage Temperature -65 ~ 150 oC
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 oC
Absolute Maximum Ratings (Note 1)
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA Junction-to-Ambient Resistance in Free Air (Note 2)
SOP-8P
42 oC/W
θJC Junction-to-Case Resistance in Free Air (Note 3)
SOP-8P
18 oC/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of SOP-8P is soldered directly on the PCB.
Note 3: The “Thermal Pad Temperature” is measured on the PCB copper area connected to the thermal pad of package.
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
1
2
3
4
8
7
6
5
VIN
Measured Point
PCB Copper
APL5940
Handling Code
Temperature Range
Package Code
Package Code
KA : SOP-8P
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
APL5940 KA : APL5940
XXXXX XXXXX - Date Code
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw3
Recommended Operating Conditions
Symbol Parameter Range Unit
VCNTL VCNTL Supply Voltage 3.0 ~ 5.5 V
VIN VIN Supply Voltage 1.2 ~ 3.65 V
VOUT VOUT Output Voltage (when VCNTL-VOUT>1.9V) 0.8 ~ VIN – VDROP V
Continuous Current 0 ~ 4
IOUT VOUT Output Current Peak Current 0 ~ 4.5 A
IOUT = 4A at 25% nominal VOUT 8 ~ 600
IOUT = 3A at 25% nominal VOUT 8 ~ 1100
IOUT = 2A at 25% nominal VOUT 8 ~ 1700
COUT VOUT Output Capacitance
IOUT = 1A at 25% nominal VOUT 8 ~ 2400
µF
ESRCOUT ESR of VOUT Output Capacitor 0 ~ 200 mΩ
TA Ambient Temperature -40 ~ 85 oC
TJ Junction Temperature -40 ~ 125 oC
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=1.8V, VOUT= 1.2V and TA= -40 ~ 85 oC. Typical values are
at TA=25oC.
APL5940
Symbol Parameter Test Conditions Min.
Typ.
Max.
Unit
SUPPLY CURRENT
IVCNTL VCNTL Supply Current EN = VCNTL, IOUT=0A - 1.0 1.5 mA
ISD VCNTL Supply Current at Shutdown EN = GND - 15 30 µA
VIN Supply Current at Shutdown EN = GND, VIN=3.65V - - 1 µA
POWER-ON-RESET (POR)
Rising VCNTL POR Threshold 2.5 2.7 2.9 V
VCNTL POR Hysteresis - 0.4 - V
Rising VIN POR Threshold 0.8 0.9 1.0 V
VIN POR Hysteresis - 0.5 - V
OUTPUT VOLTAGE
VREF Reference Voltage FB=VOUT - 0.8 - V
Output Voltage Accuracy VCNTL=3.0 ~ 5.5V, IOUT= 0~4A,
TJ= -40~125oC -1.5
- +1.5
%
Load Regulation IOUT=0 ~4A - 0.06
0.25
%
Line Regulation IOUT=10mA, VCNTL= 3.0 ~ 5.5V - 0.15
- + 0.15
%/V
VOUT Pull-low Resistance VCNTL=3.3V, VEN=0V, VOUT<0.8V - 85 - Ω
FB Input Current VFB=0.8V -100
- 100
nA
DROPOUT VOLTAGE
T
J=25oC - 0.33
0.38
V
OUT=2.5V
T
J=-40~125oC
- - 0.49
T
J=25oC - 0.31
0.36
VDROP VIN-to-VOUT Dropout Voltage
VCNTL=5.0V
, IOUT=4A
V
OUT=1.8V
T
J=-40~125oC
- - 0.47
V
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw4
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=1.8V, VOUT= 1.2V and TA= -40 ~ 85 oC. Typical values
are at TA=25oC.
APL5940
Symbol
Parameter Test Conditions Min.
Typ.
Max.
Unit
DROPOUT VOLTAGE (CONT.)
T
J=25oC - 0.30
0.35
VDROP
VIN-to-VOUT Dropout Voltage VCNTL=5.0V,
IOUT=4A V
OUT=1.2V T
J=-40~125oC
- - 0.45
V
TJ=25oC 4.7 5.7 6.7
ILIM Current-Limit Level TJ= -40 ~ 125oC 4.2 - - A
PROTECTIONS
ISHORT
Short Current-Limit Level VFB<0.2V - 1.1 - A
Short Current-Limit Blanking
Time From beginning of soft-start 0.6 1.5 - ms
TSD Thermal Shutdown Temperature
TJ rising - 170 - oC
Thermal Shutdown Hysteresis - 50 - oC
ENABLE AND SOFT-START
EN Logic High Threshold Voltage
VEN rising 0.5 0.8 1.1 V
EN Hysteresis - 0.1 - V
EN Pull-High Current EN=GND - 5 - µA
TSS Soft-Start Interval 0.3 0.6 1.2 ms
POWER-OK AND DELAY
VTHPOK
Rising POK Threshold Voltage VFB rising 90 92 94 %
POK Threshold Hysteresis - 8 - %
POK Pull-low Voltage POK sinks 5mA - 0.25
0.4 V
POK Debounce Interval VFB<falling POK voltage threshold - 10 - µs
POK Delay Time From VFB =VTHPOK to rising edge of the VPOK
1 2 4 ms
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw5
Typical Operating Characteristics
Current-Limit, ILIM (A)
Current-Limit vs. Junction
Temperature
Junction Temperature ( )
oC
-50 -25 0 25 50 75 100 125
VOUT = 1.2V
VCNTL = 5V
VCNTL = 3.3V
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Short Current-Limit, ISHORT (mA)
Junction Temperature ( )
oC
Short Current-Limit vs. Junction
Temperature
VCNTL = 5V
VCNTL = 3.3V
-50 -25 025 50 75 100 125
1.00
1.02
1.04
1.06
1.08
1.10
1.12
1.14
1.16
1.18
1.20
VCNTL = 5V
VOUT = 1.2V
TJ = 25°C
TJ = 0°C
TJ = 75°C
TJ = 125°C
TJ = - 40°C
0
50
100
150
200
250
300
350
400
450
Dropout Voltage, VDROP (mV)
Output Current, IOUT (A)
Dropout Voltage vs. Output Current
00.5 11.5 22.5 33.5 4
Dropout Voltage, VDROP (mV)
Output Current, IOUT (A)
Dropout Voltage vs. Output Current
TJ = 25°C
TJ = 0°C
TJ = 75°C
TJ = 125°C
TJ = - 40°C
VCNTL = 3.3V
VOUT = 1.2V
0
50
100
150
200
250
300
350
400
450
00.5 11.5 22.5 33.5 4
Dropout Voltage, VDROP (mV)
Output Current, IOUT (A)
Dropout Voltage vs. Output Current
TJ = 25°C
TJ = 0°C
TJ = 75°C
TJ = 125°C
TJ = - 40°C
VCNTL = 5V
VOUT = 1.5V
0
50
100
150
200
250
300
350
400
00.5 11.5 22.5 33.5 4
Dropout Voltage, VDROP (mV)
Output Current, IOUT (A)
Dropout Voltage vs. Output Current
00.5 11.5 22.5 33.5 4
0
50
100
150
200
250
300
350
400
TJ = 25°C
TJ = 0°C
TJ = 75°C
TJ = 125°C
TJ = - 40°C
VCNTL = 5V
VOUT = 1.8V
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw6
Typical Operating Characteristics (Cont.)
Power Supply Rejection Ratio (dB)
Frequency (Hz)
VIN Power Supply Rejection Ratio
(PSRR)
VCNTL=5V
VIN=1.8V
VINPK-PK=100mV
VOUT=1.2V
IOUT=3A
CIN=10µF
COUT=10µF
-60
-50
-40
-30
-20
-10
0
1000 10000 100000 1000000
Power Supply Rejection Ratio (dB)
Frequency (Hz)
VCNTL Power Supply Rejection Ratio
(PSRR)
VCNTL=4.6~5.4V
VIN=1.8V
VOUT=1.2V
IOUT=3A
CIN=COUT=10µF
-70
-60
-50
-40
-30
-20
-10
0
1000 10000 100000 1000000
Dropout Voltage, VDROP (mV)
Output Current, IOUT (A)
Dropout Voltage vs. Output Current
VCNTL = 5V
VOUT = 2.5V
TJ = 25°C
TJ = 0°C
TJ = 75°C
TJ = 125°C
TJ = - 40°C
00.5 11.5 22.5 33.5 4
0
50
100
150
200
250
300
350
400
450
Reference Voltage, VREF (V)
Junction Temperature (°C)
Reference Voltage vs. Junction
Temperature
0.792
0.794
0.796
0.798
0.800
0.802
0.804
0.806
0.808
-50 -25 025 50 75 100 125
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw7
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=1.8V, VCNTL=5V, VOUT=1.2V, TA= 25oC, unless other-
wise specified.
Power On
VCNTL
VIN
VOUT
VPOK
1
4
2
3
CH1: VCNTL, 5V/Div, DC
CH2: VIN, 1V/Div, DC
TIME: 2ms/Div
COUT=10µF, CIN=10µF, RL=0.4Ω
CH3: VOUT, 1V/Div, DC
CH4: VPOK, 5V/Div, DC
Over Current Protection
IOUT
VOUT
1
4
CH1: VOUT, 0.5V/Div, DC
CH4: IOUT, 2A/Div, DC
TIME: 0.2ms/Div
COUT=10µF, CIN=10µF, IOUT= 2A to 5.6A
Power Off
VCNTL
VIN
VOUT
VPOK
1
4
2
3
CH1: VCNTL, 5V/Div, DC
CH2: VIN, 1V/Div, DC
TIME: 2ms/Div
COUT=10µF, CIN=10µF, RL=0.4Ω
CH3: VOUT, 1V/Div, DC
CH4: VPOK, 5V/Div, DC
CH1: VOUT, 50mV/Div, AC
CH2: IOUT, 2A/Div, DC
TIME: 50µs/Div
COUT=10µF, CIN=10µF
IOUT=10mA to 4A to 10mA (rise / fall time = 1µs)
IOUT
VOUT
1
2
Load Transient Response
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw8
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=1.8V, VCNTL=5V, VOUT=1.2V, TA= 25oC, unless other-
wise specified.
CH1: VEN, 5V/Div, DC
CH2: VOUT, 1V/Div, DC
TIME: 2µs/Div
COUT=10µF, CIN=10µF, RL=0.4Ω
Shutdown
IOUT
VEN
1
4
2
3
VOUT
VPOK
CH3: VPOK, 5V/Div, DC
CH4: IOUT, 2A/Div, DC
CH1: VEN, 5V/Div, DC
CH2: VOUT, 0.5V/Div, DC
TIME: 0.5ms/Div
COUT=10µF, CIN=10µF, RL=0.4Ω
Enable
1
4
2
3
IOUT
VEN
VOUT
VPOK
CH3: VPOK, 5V/Div, DC
CH4: IOUT, 2A/Div, DC
Pin Description
PIN
NO. NAME FUNCTION
1 GND Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
2 FB Voltage Feedback Pin. Connecting this pin to an external resistor divider receives the feedback voltage
of the regulator.
3，4 VOUT Output pin of the regulator. Connecting this pin to load and output capacitors (10µF at least) is required
for stability and improving transient response. The output voltage is programmed by the resistor-divider
connected to FB pin. The VOUT can provide 4A (max.) load current to loads. During shutdown, the
output voltage is quickly discharged by an internal pull-low MOSFET.
5 VIN Main supply input pin for voltage conversions. A decoupling capacitor (≥10µF recommended) is usually
connected near this pin to filter the voltage noise and improve transient response. The voltage on this
pin is monitored for Power-On-Reset purpose.
6 VCNTL Bias voltage input pin for internal control circuitry. Connect this pin to a voltage source (+5V
recommended). A decoupling capacitor (1µF typical) is usually connected near this pin to filter the
voltage noise. The voltage at this pin is monitored for Power-On-Reset purpose.
7 POK Power-OK signal output pin. This pin is an open-drain output used to indicate the status of output
voltage by sensing FB voltage. This pin is pulled low when output voltage is not within the Power-OK
voltage window.
8 EN
Active-high enable control pin. Applying and holding the voltage on this pin below the enable voltage
threshold shuts down the output. When re-enabled, the IC undergoes a new soft-start process. When
leave this pin open, an internal pull-up current (5µA typical) pulls the EN voltage and enables the
regulator.
Exposed
Pad - Connect this pad to system VIN plane for good thermal conductivity.
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw9
Block Diagram
Typical Application Circuit
VOUT
+1.2V / 4A
CCNTL
1µFVIN
+1.8V
GND
VOUT
VCNTL
POK VIN
CIN
10µF
COUT
10µF
EN
Enable EN
POK
R3
5.1kΩ5
3,4
61
8
7
APL5940
R1
12kΩ
C1
Optional
FB 2
R2
24kΩ
(X5R/X7R Recommended)
(X5R/X7R Recommended)
10µF: GRM31MR60J106KE19 Murata
VCNTL
(+5V is preferred)
Thermal
Shutdown
GND
VOUT
VIN
EN
VCNTL
POK
90%
VREF
FB
Delay
0.8V
5µA
Enable
POR
POR
Error Amplifier
Power-
On-Reset
(POR)
VREF
0.8V
ISEN
Control Logic
and
Soft-Start
Current-Limit
and
Short Current-
Limit
Soft-Start
Enable
PWOK
VCNTL
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw10
Function Description
Power-On-Reset
Internal Soft-Start
Output Voltage Regulation
Current-Limit Protection
Short Current-Limit Protection
Thermal Shutdown
Enable Control
Power-OK and Delay
A Power-On-Reset (POR) circuit monitors both of supply
voltages on VCNTL and VIN pins to prevent wrong logic
controls. The POR function initiates a soft-start process
after both of the supply voltages exceed their rising POR
voltage thresholds during powering on. The POR func-
tion also pulls low the POK voltage regardless the output
status when one of the supply voltages falls below its
falling POR voltage threshold.
An internal soft-start function controls rise rate of the out-
put voltage to limit the current surge during start-up. The
typical soft-start interval is about 0.6 ms.
An error amplifier works with a temperature-com-
pensated 0.8V reference and an output NMOS regulates
output to the preset voltage. The error amplifier is de-
signed with high bandwidth and DC gain provides very
fast transient response and less load regulation. It com-
pares the reference with the feedback voltage and ampli-
fies the difference to drive the output NMOS which pro-
vides load current from VIN to VOUT.
The APL5940 monitors the current flowing through the
output NMOS and limits the maximum current to prevent
load and APL5940 from damages during current over-
load conditions.
The short current-limit function reduces the current-limit
level down to 1.1A (typical) when the voltage on FB pin
falls below 0.2V (typical) during current overload or short-
circuit conditions.
The short current-limit function is disabled for success-
ful start-up during soft-start interval.
A thermal shutdown circuit limits the junction tempera-
ture of APL5940. When the junction temperature exceeds
+170oC, a thermal sensor turns off the output NMOS, al-
lowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start pro-
cess after the junction temperature cools by 50oC, result-
ing in a pulsed output during continuous thermal over-
load conditions. The thermal shutdown is designed with
a 50oC hysteresis to lower the average junction tempera-
ture during continuous thermal overload conditions, ex-
tending lifetime of the device.
For normal operation, the device power dissipation should
be externally limited so that junction temperatures will
not exceed +125oC.
The APL5940 has a dedicated enable pin (EN). A logic
low signal applied to this pin shuts down the output. Fol-
lowing a shutdown, a logic high signal re-enables the
output through initiation of a new soft-start cycle. When
left open, this pin is pulled up by an internal current source
(5µA typical) to enable normal operation. It’s not neces-
sary to use an external transistor to save cost.
The APL5940 indicates the status of the output voltage by
monitoring the feedback voltage (VFB) on FB pin. As the
VFB rises and reaches the rising Power-OK voltage thresh-
old (VTHPOK), an internal delay function starts to work. At
the end of the delay time, the IC turns off the internal
NMOS of the POK to indicate that the output is ok. As the
VFB falls and reaches the falling Power-OK voltage
threshold, the IC turns on the NMOS of the POK (after a
debounce time of 10µs typical).
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw11
Application Information
........... (V)
Power Sequencing
Output Capacitor
Input Capacitor
Setting Output Voltage
+⋅=R2
R1
10.8 VOUT
The power sequencing of VIN and VCNTL is not neces-
sary to be concerned. However, do not apply a voltage to
VOUT for a long time when the main voltage applied at
VIN is not present. The reason is the internal parasitic
diode from VOUT to VIN conducts and dissipates power
without protections due to the forward-voltage.
The APL5940 requires a proper output capacitor to main-
tain stability and improve transient response. The output
capacitor selection is dependent upon ESR (equivalent
series resistance) and capacitance of the output capaci-
tor over the operating temperature.
Ultra-low-ESR capacitors (such as ceramic chip
capacitors) and low-ESR bulk capacitors (such as solid
tantalum, POSCap, and Aluminum electrolytic capacitors)
can all be used as output capacitors.
During load transients, the output capacitors, depending
on the stepping amplitude and slew rate of load current,
are used to reduce the slew rate of the current seen by
the APL5940 and help the device to minimize the varia-
tions of output voltage for good transient response. For
the applications with large stepping load current, the low-
ESR bulk capacitors are normally recommended.
Decoupling ceramic capacitors must be placed at the
load and ground pins as close as possible and the im-
pedance of the layout must be minimized.
The APL5940 requires proper input capacitors to supply
current surge during stepping load transients to prevent
the input voltage rail from dropping. Because the para-
sitic inductor from the voltage sources or other bulk ca-
pacitors to the VIN pin limit the slew rate of the surge
currents, more parasitic inductance needs more input
capacitance.
Ultra-low-ESR capacitors (such as ceramic chip capaci-
tors) and low-ESR bulk capacitors (such as solid
tantalum, POSCap, and Aluminum electrolytic capacitors)
can all be used as an input capacitor of VIN. For most
applications, the recommended input capacitance of VIN
is 10µF at least. However, if the drop of the input voltage
is not cared, the input capacitance can be less than 10µF.
More capacitance reduces the variations of the supply
voltage on VIN pin.
The output voltage is programmed by the resistor divider
connected to FB pin. The preset output voltage is calcu-
lated by the following equation :
Where R1 is the resistor connected from VOUT to FB with
Kelvin sensing connection and R2 is the risistor con-
nected from FB to GND. A bypass capacitor(C1) may be
connected with R1 in parallel to improve load transient
response and stability.
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw12
Layout Consideration
Figure 2
Thermal Consideration1. Please solder the Exposed Pad on the VIN pad on
the top-layer of PCBs. The VIN pad must have wide
size to conduct heat into the ambient air through the
VIN plane and PCB as a heat sink.
2. Please place the input capacitors for VIN and VCNTL
pins near the pins as close as possible for
decoupling high-frequency ripples.
3. Ceramic decoupling capacitors for load must be
placed near the load as close as possible for
decoupling high-frequency ripples.
4. To place APL5940 and output capacitors near the
load reduces parasitic resistance and inductance
for excellent load transient response.
5. The negative pins of the input and output capacitors
and the GND pin must be connected to the ground
plane of the load.
6. Large current paths, shown by bold lines on the fig-
ure 1, must have wide tracks.
7. Place the R1, R2, and C1 near the APL5940 as close
as possible to avoid noise coupling.
8. Connect the ground of the R2 to the GND pin by us-
ing a dedicated track.
9. Connect the one pin of the R1 to the load for Kelvin
sensing.
10. Connect one pin of the C1 to the VOUT pin for reli-
able feedback compensation.
Refer to the figure 2, the SOP-8P is a cost-effective pack-
age featuring a small size like a standard SOP-8 and a
bottom exposed pad to minimize the thermal resistance
of the package, being applicable to high current applica-
tions. The exposed pad must be soldered to the top-layer
VIN plane. The copper of the VIN plane on the Top layer
conducts heat into the PCB and ambient air. Please en-
large the area of the top-layer pad and the VIN plane to
reduce the case-to-ambient resistance (θCA).
Exposed
Pad
Die Top
VIN
plane
PCB
Ambient
Air
118 mil
102 mil
SOP-8P
5
6
7
8
1
2
3
4
Top
VOUT
plane
Recommended Minimum Footprint
0.212
0.072
0.050
0.024
1 2 3 4
8 7 6 5
0.118
0.138
Unit : Inch
VCNTL
VOUT
CCNTL
VIN
GND
VOUT
VCNTLVIN
CIN
COUT
APL5940
R1
C1
FB
R2
Load
Figure 1
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw13
Package Information
SOP-8P
THERMAL
PAD
D
D1
E2
E1
E
eb
h X 45o
c
SEE VIEW A
A2
A
A1
VIEW AL
0.25
GAUGE PLANE
SEATING PLANE
θ
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
0.020
0.010
0.020
0.050
0.006
0.063
MAX.
0.40
L
00oC
E
e
h
E1
0.25
D
c
b
0.17
0.31
0.016
1.27
8oC0oC8oC
0.50
1.27 BSC
0.51
0.25
0.050 BSC
0.010
0.012
0.007
MILLIMETERS
MIN.
S
Y
M
B
O
L
A1
A2
A
0.00
1.25
SOP-8P
MAX.
0.15
1.60
MIN.
0.000
0.049
INCHES
D1 2.50 0.098
2.00 0.079E2
3.50
3.00
0.138
0.118
4.80 5.00 0.189 0.197
3.80 4.00 0.150 0.157
5.80 6.20 0.228 0.244
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw14
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Carrier Tape & Reel Dimensions
Package Type Unit Quantity
SOP- 8P Tape & Reel 2500
Devices Per Unit
Application
A H T1 C d D W E1 F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0 P1 P2 D0 D1 T A0 B0 K0
SOP-8P
4.0±0.10
8.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±0.20
5.20±0.20
2.10±0.20
(mm)
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw15
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
Classification Profile
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw16
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
Copyright ANPEC Electronics Corp.
Rev. A.1 - Jul., 2009
APL5940
www.anpec.com.tw17
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
