E PRELIMINARY SMART 3 ADVANCED BOOT BLOCK BYTE-WIDE 8-MBIT (1024K x 8), 16-MBIT (2056K x 8) FLASH MEMORY FAMILY 28F008B3, 28F016B3 n n n n n n n n n Flexible SmartVoltage Technology 2.7V-3.6V Program/Erase 2.7V-3.6V Read Operation 12V VPP Fast Production Programming 2.7V or 1.8V I/O Option Reduces Overall System Power Optimized Block Sizes Eight 8-Kbyte Blocks for Data, Top or Bottom Locations Up to Thirty-One 64-Kbyte Blocks for Code High Performance 2.7V-3.6V: 120 ns Max Access Time Block Locking VCC-Level Control through WP# Low Power Consumption 20 mA Maximum Read Current Absolute Hardware-Protection VPP = GND Option VCC Lockout Voltage Extended Temperature Operation -40C to +85C n n n n n n n n n Extended Cycling Capability 10,000 Block Erase Cycles Automated Byte Program and Block Erase Command User Interface Status Registers SRAM-Compatible Write Interface Automatic Power Savings Feature Reset/Deep Power-Down 1 A ICCTypical Spurious Write Lockout Standard Surface Mount Packaging 48-Ball BGA* Package 40-Lead TSOP Package Footprint Upgradeable Upgradeable from 2-, 4- and 8-Mbit Boot Block ETOXTM V (0.4 ) Flash Technology x8-Only Input/Output Architecture For Space-Constrained 8-bit Applications Supports Code plus Data Storage Optimized for FDI, Flash Data Integrator Software Fast Program Suspend Capability Fast Erase Suspend Capability The new Smart 3 Advanced Boot Block, manufactured on Intel's latest 0.4 technology, represents a featurerich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability (2.7V read, program and erase) with high-speed, low-power operation. Several new features have been added, including the ability to drive the I/O at 1.8V, which significantly reduces system active power and interfaces to 1.8V controllers. A new blocking scheme enables code and data storage within a single device. Add to this the Intel-developed Flash Data Integrator (FDI) software and you have the most cost-effective, monolithic code plus data storage solution on the market today. Smart 3 Advanced Boot Block Byte-Wide products will be available in 40-lead TSOP and 48-ball BGA* packages. Additional information on this product family can be obtained by accessing Intel's WWW page: http://www.intel.com/design/flcomp May 1997 Order Number: 290605-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F008B3 and 28F016B3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel's website at http:\\www.intel.com COPYRIGHT (c) INTEL CORPORATION 1996, 1997 *Third-party brands and names are the property of their respective owners. CG-041493 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE CONTENTS PAGE 1.0 INTRODUCTION .............................................5 1.1 Smart 3 Advanced Boot Block Flash Memory Enhancements ..............................5 1.2 Product Overview.........................................6 2.0 PRODUCT DESCRIPTION..............................6 2.1 Package Pinouts ..........................................7 2.2 Block Organization .....................................11 2.2.1 Parameter Blocks ................................11 2.2.2 Main Blocks .........................................11 3.0 PRINCIPLES OF OPERATION .....................14 3.1 Bus Operation ............................................14 3.1.1 Read....................................................15 3.1.2 Output Disable.....................................15 3.1.3 Standby ...............................................15 3.1.4 Deep Power-Down/Reset ....................15 3.1.5 Write....................................................15 3.2 Modes of Operation....................................15 3.2.1 Read Array ..........................................16 3.2.2 Read Intelligent Identifier .....................17 3.2.3 Read Status Register ..........................17 3.2.4 Program Mode.....................................18 3.2.5 Erase Mode .........................................19 3.3 Block Locking.............................................26 3.3.1 VPP = VIL for Complete Protection .......26 3.3.2 WP# = VIL for Block Locking................26 3.3.3 WP# = VIH for Block Unlocking ............26 3.4 VPP Program and Erase Voltages ..............26 PAGE 3.5 Power Consumption ...................................26 3.5.1 Active Power .......................................26 3.5.2 Automatic Power Savings (APS) .........27 3.5.3 Standby Power ....................................27 3.5.4 Deep Power-Down Mode.....................27 3.6 Power-Up/Down Operation.........................27 3.6.1 RP# Connected to System Reset ........27 3.6.2 VCC, VPP and RP# Transitions .............27 3.7 Power Supply Decoupling ..........................28 3.7.1 VPP Trace on Printed Circuit Boards ....28 4.0 ABSOLUTE MAXIMUM RATINGS ................29 5.0 OPERATING CONDITIONS (VCCQ = 2.7V-3.6V).......................................29 5.1 DC Characteristics: VCCQ = 2.7V-3.6V.......30 6.0 OPERATING CONDITIONS (VCCQ = 1.8V-2.2V).......................................34 6.1 DC Characteristics: VCCQ = 1.8V-2.2V.......34 7.0 AC CHARACTERISTICS...............................39 7.1 Reset Operations .......................................43 APPENDIX A: Ordering Information .................45 APPENDIX B: Write State Machine Current/ Next States ..................................................46 APPENDIX C: Access Time vs. Capacitive Load...........................................47 APPENDIX D: Architecture Block Diagram ......48 APPENDIX E: Additional Information ...............49 PRELIMINARY 3 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE E REVISION HISTORY Number -001 4 Description Original version PRELIMINARY E 1.0 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE INTRODUCTION 1.1 This preliminary datasheet contains the specifications for the Advanced Boot Block flash memory family, which is optimized for low power, portable systems. This family of products features 1.8V-2.2V or 2.V-3.6V I/Os and a low VCC/VPP operating range of 2.7V-3.6V for read and program/erase operations. In addition this family is capable of fast programming at 12V. Throughout this document, the term "2.7V" refers to the full voltage range 2.7V-3.6V (except where noted otherwise) and "VPP = 12V" refers to 12V 5%. Section 1 and 2 provides an overview of the flash memory family including applications, pinouts and pin descriptions. Section 3 describes the memory organization and operation for these products. Finally, Sections 4, 5, 6 and 7 contain the operating specifications. Smart 3 Advanced Boot Block Flash Memory Enhancements The new 8-Mbit and 16-Mbit Smart 3 Advanced Boot Block flash memory provides a convenient upgrade from and/or compatibility to previous 4Mbit and 8-Mbit Boot Block products. The Smart 3 product functions are similar to lower density products in both command sets and operation, providing similar pinouts to ease density upgrades. The Smart 3 Advanced Boot Block flash memory features * Enhanced blocking for easy segmentation of code and data or additional design flexibility * Program Suspend command which permits program suspend to read * WP# pin to lock and unlock the upper two (or lower two, depending on location) 8-Kbyte blocks * VCCQ input for 1.8V-2.2V on all I/Os. See Figures 1-3 for pinout diagrams and VCCQ location * Maximum program time improved data storage. specification for Table 1. Smart 3 Advanced Boot Block Feature Summary Feature 28F016B3/28F008B3/28F004B3 Reference VCC Read Voltage 2.7V- 3.6V Table 9, Table 12 VCCQ I/O Voltage 1.8V-2.2V or 2.7V- 3.6V Table 9, Table 12 VPP Program/Erase Voltage 2.7V- 3.6V or 11.4V- 12.6V Table 9, Table 12 Bus Width 8 bits Table 2 Speed 120 ns Table 15 Memory Arrangement 1 Mbit x 8 (8 Mbit), 2 Mbit x 8 (16 Mbit) Blocking (top or bottom) Eight 8-Kbyte parameter blocks (8/16 Mbit) & Fifteen 64-Kbyte blocks (8 Mbit) Thirty-one 64-Kbyte main blocks (16 Mbit) Section 2.2 Figures 4 and 5 Locking WP# locks/unlocks parameter blocks All other blocks protected using V PP switch Section 3.3 Table 8 Operating Temperature Extended: -40C to +85C Table 9, Table 12 Program/Erase Cycling 10,000 cycles Table 9, Table 12 Packages 40-Lead TSOP, 48-Ball BGA* CSP Figures 1, 2, and 3 PRELIMINARY 5 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE 1.2 Product Overview Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: VCC for read operation, VCCQ for output swing, and VPP for program and erase operation. Discrete supply pins allow system designers to use the optimal voltage levels for their design. All Smart 3 Advanced Boot Block flash memory products provide program/erase capability at 2.7V or 12V and read with VCC at 2.7V. Since many designs read from the flash memory a large percentage of the time, 2.7V VCC operation can provide substantial power savings. The 12V VPP option maximizes program and erase performance during production programming. The Smart 3 Advanced Boot Block flash memory products are high-performance devices with low power operation. The available densities for the byte-wide devices (x8) are a. 8-Mbit (8,388,608-bit) flash memory organized as 1 Mbyte of 8 bits each b. 16-Mbit (16,777,216-bit) flash memory organized as 2 Mbytes of 8 bits each. For word-wide devices (x16) see the Smart 3 Advanced Boot Block Word-Wide Flash Memory Family datasheet. The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by WP# (see Section 3.3 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or byte program completion and status. 6 E Program and erase automation allows program and erase operations to be executed using an industrystandard two-write command sequence to the CUI. Data writes are performed in byte increments. Each byte in the flash memory can be programmed independently of other memory locations; every erase operation erases all locations within a block simultaneously. Program suspend allows system software to suspend the program command in order to read from any other block. Erase suspend allows system software to suspend the block erase command in order to read from or program data to any other block. The Smart 3 Advanced Boot Block flash memory is also designed with an Automatic Power Savings (APS) feature which minimizes system current drain, allowing for very low power designs. This mode is entered immediately following the completion of a read cycle. When the CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. A deep powerdown mode is enabled when the RP# pin is at GND, minimizing power consumption and providing write protection. ICC current in deep power-down is 1 A typical (2.7V VCC). A minimum reset time of tPHQV is required from RP# switching high until outputs are valid to read attempts. With RP# at GND, the WSM is reset and Status Register is cleared. Section 3.5 contains additional information on using the deep power-down feature, along with other power consumption issues. The RP# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions (see Section 3.6). Refer to the DC Characteristics Table, Sections 5.1 and 6.1, for complete current and voltage specifications. Refer to the AC Characteristics Table, Section 7.0, for read, program and erase performance specifications. 2.0 PRODUCT DESCRIPTION This section explains device pin description and package pinouts. PRELIMINARY E 2.1 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Package Pinouts The Smart 3 Advanced Boot Block flash memory is available in 40-lead TSOP (see Figure 1) and 48ball BGA packages (see Figures 2 and 3). In Figure 1, pin changes from one density to the next are circled. Both packages, 40-lead TSOP and 48ball BGA package, are 8-bits wide and fully upgradeable across product densities (from 8 Mb to 16 Mb). 28F016 28F008 28F008 28F016 A16 A15 A14 A13 A12 A11 A9 A8 WE# RP# VPP WP# A18 A7 A6 A5 A4 A3 A2 A1 A16 A15 A14 A13 A12 A11 A9 A8 WE# RP# VPP WP# A18 A7 A6 A5 A4 A3 A2 A1 A17 GND NC A19 A10 DQ7 DQ6 DQ5 DQ4 VCCQ VCC NC DQ3 DQ2 DQ1 DQ0 OE# GND CE# A0 A17 GND A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCCQ VCC NC DQ3 DQ2 DQ1 DQ0 OE# GND CE# A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Advanced Boot Block 40-Lead TSOP 10 mm x 20 mm TOP VIEW 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 0605-01 Figure 1. 40-Lead TSOP Package PRELIMINARY 7 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE 1 2 A14 A12 A15 C D A B E F 3 4 5 6 7 8 A8 VPP WP# NC A7 A4 A10 WE# RP# A19 A18 A5 A2 A16 A13 A9 A6 A3 A1 A17 NC D5 NC D2 NC CE# A0 VCCQ A11 D6 NC D3 NC D0 GND GND D7 NC D4 VCC NC D1 OE# 0605-03 NOTE: Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area. Figure 2. 8-Mbit 48-Ball BGA* Chip Size Package 8 PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE 1 2 A14 A12 A15 C D A B E F 3 4 5 6 7 8 A8 VPP WP# A20 A7 A4 A10 WE# RP# A19 A18 A5 A2 A16 A13 A9 A6 A3 A1 A17 NC D5 NC D2 NC CE# A0 VCCQ A11 D6 NC D3 NC D0 GND GND D7 NC D4 VCC NC D1 OE# 0605-02 NOTE: Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area. Figure 3. 16-Mbit 48-Ball BGA* Chip Size Package PRELIMINARY 9 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE The pin descriptions table details the usage of each device pin. Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions Symbol A0-A20 DQ0-DQ7 Type INPUT Name and Function ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. 28F008B3: A[0-19], 28F016B3: A[0-20] INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. CE# INPUT CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. If CE# and RP# are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE# and RP# inputs. OE# INPUT OUTPUT ENABLE: Enables the device's outputs through the data buffers during an array or status register read. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. RP# INPUT RESET/DEEP POWER-DOWN: Uses two voltage levels (V IL, VIH) to control reset/deep power-down mode. When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and draws minimum current. When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to logic-high, the device defaults to the read array mode. WP# INPUT WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks. When WP# is at logic low, the lockable blocks are locked, preventing program and erase operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed. When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased. See Section 3.3 for details on write protection. 10 PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued) Symbol VCCQ Type Name and Function INPUT OUTPUT VCC: Enables all outputs to be driven to 2.0V 10% while the VCC is at 2.7V. When this mode is used, the V CC should be regulated to 2.7V-2.85V to achieve lowest power operation (see Section 6.1: DC Characteristics: VCCQ = 1.8V-2.2V). This input may be tied directly to V CC (2.7V-3.6V). See the DC Characteristics for further details. VCC DEVICE POWER SUPPLY: 2.7V-3.6V VPP PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block, a voltage of either 2.7V-3.6V or 12V 5% must be applied to this pin. When V PP < VPPLK all blocks are locked and protected against Program and Erase commands. Applying 11.4V-12.6V to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum (see Section 3.4 for details). GND GROUND: For all internal circuitry. All ground inputs must be connected. NC NO CONNECT: Pin may be driven or left floating. 2.2 Block Organization The Smart 3 Advanced Boot Block is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. Each block can be erased independently of the others up to 10,000 times. For the address locations of each block, see the memory maps in Figure 4 (top boot blocking) and Figure 5 (bottom boot blocking). 2.2.1 PARAMETER BLOCKS The Smart 3 Advanced Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters (e.g., data that would normally be stored in an EEPROM. By using software techniques, the byterewrite functionality of EEPROMs can be emulated. Each 8-/16-Mbit device contains eight parameter blocks of 8 Kbytes (8,192-bytes) each. 2.2.2 MAIN BLOCKS After the parameter blocks, the remainder of the array is divided into equal size main blocks for data or code storage. Each 16-Mbit device contains thirty-one 64-Kbyte (65,536-byte) blocks. Each 8-Mbit device contains fifteen 64-Kbyte blocks. PRELIMINARY 11 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE 16-Mbit Advanced Boot Block 1FFFFF 1FE000 1FDFFF 1FC000 1FBFFF 1FA000 1F9FFF 1F8000 1F7FFF 1F6000 1F5FFF 1F4000 1F3FFF 1F2000 1F1FFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000 8-Mbit Advanced Boot Block FFFFF FE000 FDFFF FC000 FBFFF 8-Kbyte Block 38 8-Kbyte Block 37 8-Kbyte Block 36 8-Kbyte Block 35 8-Kbyte Block 34 8-Kbyte Block 33 8-Kbyte Block 32 8-Kbyte Block 31 64-Kbyte Block 30 64-Kbyte Block E0000 DFFFF 29 64-Kbyte Block 28 64-Kbyte Block D0000 CFFFF C0000 BFFFF 27 64-Kbyte Block 26 64-Kbyte Block 25 64-Kbyte Block 24 64-Kbyte Block 23 64-Kbyte Block 22 64-Kbyte Block 21 64-Kbyte Block 50000 4FFFF 20 64-Kbyte Block 19 40000 3FFFF 64-Kbyte Block 18 64-Kbyte Block 17 64-Kbyte Block 16 64-Kbyte Block 15 64-Kbyte Block 14 64-Kbyte Block 13 64-Kbyte Block 12 64-Kbyte Block 11 64-Kbyte Block 10 64-Kbyte Block 9 64-Kbyte Block 8 64-Kbyte Block 7 64-Kbyte Block 6 64-Kbyte Block 5 64-Kbyte Block 4 64-Kbyte Block 3 64-Kbyte Block 2 64-Kbyte Block 1 0 64-Kbyte Block FA000 F9FFF F8000 F7FFF F6000 F5FFF F4000 F3FFF F2000 F1FFF F0000 EFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000 8-Kbyte Block 22 8-Kbyte Block 21 8-Kbyte Block 20 8-Kbyte Block 19 8-Kbyte Block 18 8-Kbyte Block 17 8-Kbyte Block 16 8-Kbyte Block 15 64-Kbyte Block 14 64-Kbyte Block 13 64-Kbyte Block 12 64-Kbyte Block 11 64-Kbyte Block 10 64-Kbyte Block 9 64-Kbyte Block 8 64-Kbyte Block 7 64-Kbyte Block 6 64-Kbyte Block 5 64-Kbyte Block 4 64-Kbyte Block 3 64-Kbyte Block 2 64-Kbyte Block 0 1 64-Kbyte Block 0 0 0605-05 Figure 4. 8-/16-Mbit Advanced Boot Block Byte-Wide Top Boot Memory Maps 12 PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE 16-Mbit Advanced Boot Block 1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 0EFFFF 0E0000 0DFFFF 0D0000 0CFFFF 0C0000 0BFFFF 0B0000 0AFFFF 0A0000 09FFFF 090000 08FFFF 080000 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 00E000 00DFFF 00C000 00BFFF 00A000 009FFF 008000 007FFF 006000 005FFF 004000 003FFF 002000 001FFF 000000 64-Kbyte Block 38 64-Kbyte Block 37 64-Kbyte Block 36 64-Kbyte Block 35 64-Kbyte Block 34 64-Kbyte Block 33 64-Kbyte Block 32 64-Kbyte Block 31 64-Kbyte Block 30 64-Kbyte Block 29 64-Kbyte Block 28 64-Kbyte Block 27 64-Kbyte Block 26 64-Kbyte Block 25 64-Kbyte Block 24 64-Kbyte Block 23 64-Kbyte Block 22 64-Kbyte Block 21 64-Kbyte Block 20 64-Kbyte Block 19 64-Kbyte Block 18 64-Kbyte Block 17 64-Kbyte Block 16 64-Kbyte Block 15 64-Kbyte Block 14 64-Kbyte Block 13 64-Kbyte Block 12 64-Kbyte Block 11 64-Kbyte Block 10 64-Kbyte Block 64-Kbyte Block 8-Kbyte Block 9 8 7 8-Kbyte Block 6 8-Kbyte Block 5 8-Mbit Advanced Boot Block FFFFF F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 0E000 0DFFF 0C000 0BFFF 0A000 09FFF 8-Kbyte Block 4 8-Kbyte Block 3 08000 07FFF 8-Kbyte Block 2 06000 05FFF 8-Kbyte Block 0 1 8-Kbyte Block 0 04000 03FFF 02000 01FFF 00000 64-Kbyte Block 22 64-Kbyte Block 21 64-Kbyte Block 20 64-Kbyte Block 19 64-Kbyte Block 18 64-Kbyte Block 17 64-Kbyte Block 16 64-Kbyte Block 15 64-Kbyte Block 14 64-Kbyte Block 13 64-Kbyte Block 12 64-Kbyte Block 11 64-Kbyte Block 10 64-Kbyte Block 9 64-Kbyte Block 8 8-Kbyte Block 7 8-Kbyte Block 6 8-Kbyte Block 5 8-Kbyte Block 4 8-Kbyte Block 3 8-Kbyte Block 2 8-Kbyte Block 1 0 8-Kbyte Block 0 0605-06 Figure 5. 8-/16-Mbit Advanced Boot Block Byte-Wide Bottom Boot Memory Maps PRELIMINARY 13 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE 3.0 PRINCIPLES OF OPERATION Flash memory combines EEPROM functionality with in-circuit electrical program and erase capability. The Smart 3 Advanced Boot Block flash memory family utilizes a Command User Interface (CUI) and automated algorithms to simplify program and erase operations. The CUI allows for 100% CMOS-level control inputs, fixed power supplies during erasure and programming, and maximum EEPROM compatibility. When VPP < VPPLK, the device will only execute the following commands successfully: Read Array, Read Status Register, Clear Status Register and Read Intelligent Identifier. The device provides standard EEPROM read, standby and output disable operations. Manufacturer identification and device identification data can be accessed through the CUI. In addition, 2.7V or 12V on VPP allows program and erase of the device. All functions associated with altering memory contents, namely program and erase, are accessible via the CUI. The internal Write State Machine (WSM) completely automates program and erase operations while the CUI signals the start of an operation and the status register reports status. The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation. 3.1 Bus Operation Smart 3 Advanced Boot Block flash memory devices read, program and erase in-system via the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#, WE# and RP#. These bus operations are summarized in Table 3. Table 3. Bus Operations for Byte-Wide Mode Mode Notes RP# CE# OE# WE# WP# A0 VPP DQ0-7 1,2,3 VIH VIL VIL VIH X X X DOUT Output Disable 2 VIH VIL VIH VIH X X X High Z Standby 2 VIH VIH X X X X X High Z Deep Power-Down 2,9 VIL X X X X X X High Z Intelligent Identifier (Mfr.) 2,4 VIH VIL VIL VIH X VIL X 89 H Intelligent Identifier (Dvc.) 2,4,5 VIH VIL VIL VIH X VIH X See Table 5 2,6,7, 8 VIH VIL VIH VIL X X VPPH DIN Read Write NOTES: 1. Refer to DC Characteristics. 2. X must be VIL, VIH for control pins and addresses, VPPLK , VPPH1 or VPPH2 for VPP. 3. See DC Characteristics for VPPLK, VPPH1, VPPH2 voltages. 4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1-A20 = X 5. See Table 5 for device IDs. 6. Refer to Table 6 for valid DIN during a write operation. 7. Command writes for block erase or byte program are only executed when VPP = VPPH1 or VPPH2. 8. To program or erase the lockable blocks, hold WP# at VIH. See Section 3.3. 9. RP# must be at GND 0.2V to meet the maximum deep power-down current specified. 14 PRELIMINARY E 3.1.1 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE READ The flash memory has three read modes available: read array, read identifier, and read status. These modes are accessible independent of the VPP voltage. The appropriate read mode command must be issued to the CUI to enter the corresponding mode. Upon initial device power-up or after exit from deep power-down mode, the device automatically defaults to read array mode. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control; when active it enables the flash memory device. OE# is the data output (DQ0-DQ7) control and it drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at VIH. Figure 14 illustrates a read cycle. 3.1.2 OUTPUT DISABLE With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0-DQ7 are placed in a high-impedance state. 3.1.3 STANDBY Deselecting the device by bringing CE# to a logichigh level (VIH) places the device in standby mode, which substantially reduces device power consumption. In standby, outputs DQ0-DQ7 are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete. 3.1.4 DEEP POWER-DOWN/RESET RP# at VIL initiates the deep power-down mode, sometimes referred to as reset mode. From read mode, RP# going low for time tPLPH accomplishes the following: 1. deselects the memory 2. places output drivers in a high-impedance state After return from power-down, a time tPHQV is required until the initial memory access outputs are PRELIMINARY valid. A delay (tPHWL or tPHEL) is required after return from power-down before a write sequence can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H (ready). If RP# is taken low for time tPLPH during a program or erase operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. After returning from an aborted operation, time tPHQV or tPHWL/tPHEL must be met before a read or write operation is initiated respectively. 3.1.5 WRITE A write is any command that alters the contents of the memory array. There are two write commands: Program (40H) and Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internallytimed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to VIL for of tPLRH or an appropriate suspend command). The Command User Interface does not occupy an addressable memory location. Instead, commands are written into the CUI using standard microprocessor write timings when WE# and CE# are low, OE# = VIH, and the proper address and data (command) are presented. The command is latched on the rising edge of the first WE# or CE# pulse, whichever occurs first. Figure 15 illustrates a write operation. Device operations are selected by writing specific commands into the CUI. Table 4 defines the available commands. Appendix B provides detailed information on moving between the different modes of operation. 3.2 Modes of Operation The flash memory has three read modes and two write modes. The read modes are read array, read identifier, and read status. The write modes are program and block erase. Three additional mode (erase suspend to program, erase suspend to read and program suspend to read) are available only during suspended operations. These modes are 15 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE reached using the commands summarized in Table 4. A comprehensive chart showing the state transitions is in Appendix B. When the device is in the read array mode, four control signals must be controlled to obtain data at the outputs. 3.2.1 * READ ARRAY When RP# transitions from VIL (reset) to VIH, the device will be in the read array mode and will respond to the read control inputs (CE#, address inputs, and OE#) without any commands being written to the CUI. WE# must be logic high (VIH) * CE# must be logic low (VIL) * OE# must be logic low (VIL) * RP# must be logic high (VIH) In addition, the address of the desired location must be applied to the address pins. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Array command (FFH) must be written to the CUI before array reads can take place. Table 4. Command Codes and Descriptions Code Device Mode 00 Invalid/ Reserved FF Read Array Places the device in read array mode, such that array data will be output on the data pins. 40 Program Set-Up This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second cycle latches addresses and data information and initiates the WSM to execute the Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 3.2.4. 10 Description Unassigned commands that should not be used. Intel reserves the right to redefine these codes for future functions. Alternate (See 40H/Program Set-Up) Program Set-Up 20 Erase Set-Up Prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a "1," (b) place the device into the read status register mode, and (c) wait for another command. See Section 3.2.5. D0 Program Resume If the previous command was an Erase Set-Up command, then the CUI will close the address and data latches, and begin erasing the block indicated on the address pins. If a program or erase operation was previously suspended, this command will resume that operation. Erase Resume/ Erase Confirm During program/erase, the device will respond only to the Read Status Register, Program Suspend/Erase Suspend commands and will output status register data when CE# or OE# is toggled. 16 PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 4. Command Codes and Descriptions (Continued) Code Device Mode Description B0 Program Suspend Issuing this command will begin to suspend the currently executing program/erase operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM Status bit (SR.7) to a "1" (ready). The WSM will continue to idle in the SUSPEND state, regardless of the state of all input control pins except RP#, which will immediately shut down the WSM and the remainder of the chip if it is driven to V IL. See Sections 3.2.4.1 and 3.2.5.1. Erase Suspend 70 Read Status Register This command places the device into read status register mode. Reading the device will output the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a program or erase operation has been initiated. See Section 3.2.3. 50 Clear Status Register The WSM can set the Block Lock Status (SR.1) , V PP Status (SR.3), Program Status (SR.4), and Erase Status (SR.5) bits in the status register to "1," but it cannot clear them to "0." Issuing this command clears those bits to "0." 90 Intelligent Identifier Puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes (A 0 = 0 for manufacturer, A0 = 1 for device, all other address inputs are ignored). See Section 3.2.2. NOTE: See Appendix B for mode transition information. 3.2.2 READ INTELLIGENT IDENTIFIER To read the manufacturer and device codes, the device must be in read intelligent identifier mode, which can be reached by writing the Intelligent Identifier command (90H). Once in intelligent identifier mode, A0 = 0 outputs the manufacturer's identification code and A0 = 1 outputs the device code. See Table 5 for product signatures. To return to read array mode, write the Read Array command (FFH). Table 5. Intelligent Identifier Table 3.2.3 READ STATUS REGISTER The device status register indicates when a program or erase operation is complete, and the success or failure of that operation. To read the status register issue the Read Status Register (70H) command to the CUI. This causes all subsequent read operations to output data from the status register until another command is written to the CUI. To return to reading from the array, issue the Read Array (FFH) command. The status register bits are output on DQ0-DQ7. Size Mfr. ID Device ID -T -B (Top Boot) (Bottom Boot) 8-Mbit 89H D2H D3H 16-Mbit 89H D0H D1H PRELIMINARY The contents of the status register are latched on the falling edge of OE# or CE#. This prevents possible bus errors which might occur if status register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the status register will not indicate completion of a program or erase operation. 17 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE When the WSM is active, bit 7 (SR.7) of the status register will indicate the status of the WSM; the remaining bits in the status register indicate whether or not the WSM was successful in performing the desired operation (see Table 7). 3.2.3.1 Clearing the Status Register The WSM sets status bits 1 through 7 to "1," and clears bits 2, 6 and 7 to "0," but cannot clear status bits 1 or 3 through 5 to "0." Because bits 1, 3, 4, and 5 indicate various error conditions, these bits can only be cleared by the controlling CPU through the use of the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the Status Register before beginning another command or sequence. Note, again, that the Read Array command must be issued before data can be read from the memory array. 3.2.4 PROGRAM MODE Programming is executed using a two-write sequence. The Program Setup command (40H) is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute the following sequence of internally timed events: 1. Program the desired bits of the addressed memory. 2. Verify that the desired bits are sufficiently programmed. Programming of the memory results in specific bits within an address location being changed to a "0." If the user attempts to program "1"s, there will be no change of the memory cell contents and no error occurs. The status register indicates programming status: while the program sequence is executing, bit 7 of the status register is a "0." The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. 18 E When programming is complete, the Program Status bits should be checked. If the programming operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If SR.3 is set then VPP was not within acceptable limits, and the WSM did not execute the program command. If SR.1 is set, a program operation was attempted to a locked block and the operation was aborted. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the CUI to read array mode. 3.2.4.1 Suspending and Resuming Program The Program Suspend command allows program suspension in order to read data in other locations of memory. Once the programming process starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). The device continues to output status register data after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will determine when the program operation has been suspended (both will be set to "1"). tWHRH1/tEHRH1 specify the program suspend latency. A Read Array command can now be written to the CUI to read data from blocks other than that which is suspended. The only other valid commands, while program is suspended, are Read Status Register and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the program process and status register bits SR.2 and SR.7 will automatically be cleared. After the Program Resume command is written, the device automatically outputs status register data when read (see Figure 7, Program Suspend/Resume Flowchart). VPP must remain at the same VPP level used for program while in program suspend mode. RP# must also remain at V IH. 3.2.4.2 VPP Supply Voltage during Program VPP supply voltage considerations are outlined in Section 3.4. PRELIMINARY E 3.2.5 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE ERASE MODE To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to "1." Only one block can be erased at a time. The WSM will execute the following sequence of internally timed events to: 1. Program all bits within the block to "0." 2. Verify that all bits within the block are sufficiently programmed to "0." 3. Erase all bits within the block to "1." 4. Verify that all bits within the block are sufficiently erased. While the erase sequence is executing, bit 7 of the status register is a "0." When the status register indicates that erasure is complete, check the Erase Status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status register will be set to a "1," indicating an erase error. If VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a "1" to identify that VPP supply voltage was not within acceptable limits. 3.2.5.1 Suspending and Resuming Erase Since an erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from or program data to another block in memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the erase operation has been suspended. A Read Array/Program command can now be written to the CUI in order to read/write data from/to blocks other than that which is suspended. The Program command can subsequently be suspended to read yet another array location. The only valid commands while erase is suspended are Erase Resume, Program, Program Resume, Read Array, or Read Status Register. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking CE# to VIH. This reduces active current consumption. Erase Resume continues the erase sequence when CE# = VIL. As with the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued. 3.2.5.2 VPP Supply Voltage during Erase VPP supply voltage considerations are outlined in Section 3.4. After an erase operation, clear the Status Register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to reset the flash to read array after the erase is complete. PRELIMINARY 19 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 6. Command Bus Definitions First Bus Cycle Command Second Bus Cycle Notes Oper Addr Data Oper Addr Data 5 Write X FFH 2,3,5 Write X 90H Read IA ID Read Status Register 5 Write X 70H Read X SRD Clear Status Register 5 Write X 50H Write (Program) 4,5 Write X 40H Write PA PD Alternate Write (Program) 4,5 Write X 10H Write PA PD Block Erase/Confirm 5 Write X 20H Write BA D0H Program/Erase Suspend 5 Write X B0H Program/Erase Resume 5 Write X D0H Read Array Intelligent Identifier ADDRESS DATA BA = Block Address IA = Identifier Address PA = Program Address X = Don't Care SRD = Status Register Data ID = Identifier Data PD = Program Data NOTES: 1. Bus operations are defined in Table 3. 2. A0 = 0 for manufacturer code, A0 = 1 for device code. 3. Following the Intelligent Identifier command, two read operations access manufacturer and device codes. 4. Either 40H or 10H command is valid. 20 PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 7. Status Register Bit Definition WSMS ESS ES PS VPPS PSS BLS R 7 6 5 4 3 2 1 0 NOTES: SR.7 WRITE STATE MACHINE STATUS 1 = Ready (WSMS) 0 = Busy Check Write State Machine bit first to determine Byte Program or Block Erase completion, before checking Program or Erase Status bits. SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an Erase Resume command is issued. SR.5 = ERASE STATUS (ES) 1 = Error In Block Erasure 0 = Successful Block Erase When this bit is set to "1," WSM has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure. SR.4 = PROGRAM STATUS (PS) 1 = Error in Byte Program 0 = Successful Byte Program When this bit is set to "1," WSM has attempted but failed to program a byte. SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK The VPP Status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered, and informs the system if V PP has not been switched on. The VPP is also checked before the operation is verified by the WSM. The VPP Status bit is not guaranteed to report accurate feedback between VPPLK and VPPH. SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to "1." PSS bit remains set to "1" until a Program Resume command is issued. SR.1 = Block Lock Status 1 = Program/Erase attempted on locked block; Operation aborted 0 = No operation to locked blocks If a program or erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) These bits are reserved for future use and should be masked out when polling the Status Register. PRELIMINARY 21 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Start Write 40H Bus Operation Command Write Program Setup Write Program Program Address/Data Data = 40H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Read Read Status Register Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Repeat for subsequent programming operations. No SR.7 = 1? Comments SR Full Status Check can be done after each program or after a sequence of program operations. Yes Write FFH after the last program operation to reset device to read array mode. Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) Bus Operation 1 SR.3 = 0 VPP Range Error Programming Error 0 1 Comments Standby Check SR.3 1 = VPP Low Detect Standby Check SR.4 1 = VPP Program Error Standby Check SR.1 1 = Attempted Program to Locked Block - Program Aborted 1 SR.4 = SR.1 = Command SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. Attempted Program to Locked Block - Aborted SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked. 0 Program Successful If an error is detected, clear the status register before attempting retry or other error recovery. 0605-07 Figure 6. Automated Byte Programming Flowchart 22 PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Start Bus Operation Command Write Program Suspend Write B0H Read Status Register Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.2 1 = Program Suspended 0 = Program Completed 0 1 0 SR.2 = Program Completed 1 Data = B0H Addr = X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Read SR.7 = Comments Write Read Array Data = FFH Addr = X Read array data from block other than the one being programmed. Read Write FFH Write Program Resume Data = D0H Addr = X Read Array Data No Done Reading Yes Write D0H Write FFH Program Resumed Read Array Data 0605-08 Figure 7. Program Suspend/Resume Flowchart PRELIMINARY 23 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Start Bus Operation Write 20H Write D0H and Block Address Command Write Erase Setup Write Erase Confirm Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Data Read Read Status Register Suspend Erase Loop 0 SR.7 = No Suspend Erase Comments Data = 20H Addr = Within Block to Be Erased Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Yes Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures. 1 Full Status Check if Desired Write FFH after the last write operation to reset device to read array mode. Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) Bus Operation 1 SR.3 = 0 Command Standby Check SR.3 1 = VPP Low Detect Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error Standby Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted VPP Range Error 1 SR.4,5 = Command Sequence Error 0 1 SR.5 = Block Erase Error Comments SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. 0 1 SR.1 = 0 Attempted Erase of Locked Block - Aborted SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Block Erase Successful 0605-09 Figure 8. Automated Block Erase Flowchart 24 PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Start Bus Operation Command Write Erase Suspend Write B0H Read Status Register Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.6 1 = Erase Suspended 0 = Erase Completed 0 1 0 SR.6 = Erase Completed 1 Data = B0H Addr = X Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Read SR.7 = Comments Write Read Array Data = FFH Addr = X Read Read array data from block other than the one being erased. Program Program data to block other than the one being erased. Write FFH/40H Read Array Data/ Program Array Done Reading and/or Programming Write Erase Resume Data = D0H Addr = X No Yes Write D0H Write FFH Erase Resumed Read Array Data 0605-010 Figure 9. Erase Suspend/Resume Flowchart PRELIMINARY 25 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE 3.3 Block Locking The Smart 3 Advanced Boot Block flash memory architecture features two hardware-lockable parameter blocks so that the kernel code for the system can be kept secure while other parameter blocks are programmed or erased as necessary. 3.3.1 VPP = VIL FOR COMPLETE PROTECTION The VPP programming voltage can be held low for complete write protection of all blocks in the flash device. When VPP is below VPPLK, any program or erase operation will result in a error, prompting the corresponding Status Register bit (SR.3) to be set. 3.3.2 WP# = VIH FOR BLOCK UNLOCKING WP# = VIH unlocks all lockable blocks. These blocks can now be programmed or erased. Note that RP# does not override WP# locking as in previous Boot Block devices. WP# controls all block locking and VPP provides protection against spurious writes. Table 8 defines the write protection methods. 3.4 VPP Program and Erase Voltages Intel's Smart 3 products provide in-system programming and erase at 2.7V-3.6V VPP. For customers requiring fast programming in their manufacturing environment, Smart 3 Advanced Boot Block includes an additional low-cost, backward-compatible 12V programming feature. 26 Table 8. Write Protection Truth Table for Advanced Boot Block Flash Memory Family VPP WP# RP# Write Protection Provided X X VIL All Blocks Locked VIL X VIH All Blocks Locked VPPLK VIL VIH Lockable Blocks Locked VPPLK VIH VIH All Blocks Unlocked WP# = VIL FOR BLOCK LOCKING The lockable blocks are locked when WP# = VIL; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two parameter blocks (blocks #37 and #38 for the 16-Mbit, and blocks #21 and #22 for the 8-Mbit) are lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0 and #1 for 8-/16Mbit) are lockable. Unlocked blocks can be programmed or erased normally (unless VPP is below VPPLK). 3.3.3 The 12V VPP mode enhances programming performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12V may be applied to VPP during program and erase operations for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum. Stressing the device beyond these limits may cause permanent damage. 3.5 Power Consumption While in operation, the flash device consumes active power. However, Intel flash devices have a three-tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is idle. If the CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. If RP# = VIL the flash enters a deep power-down mode, where current is at a minimum. The combination of these features can minimize overall memory power consumption, and therefore, overall system power consumption. 3.5.1 ACTIVE POWER With CE# at a logic-low level and RP# at a logichigh level, the device is in the active mode. Refer to the DC Characteristics tables for ICC current values. Active power is the largest contributor to overall system power consumption. Minimizing the active current could have a profound effect on system power consumption, especially for battery-operated devices. PRELIMINARY E 3.5.2 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE AUTOMATIC POWER SAVINGS (APS) Automatic Power Savings provides low-power operation during active mode. Power Reduction Control (PRC) circuitry allows the flash to put itself into a low current state when not being accessed. After data is read from the memory array, PRC logic controls the device's power consumption by entering the APS mode where typical ICC current is comparable to ICCS. The flash stays in this static state with outputs valid until a new location is read. APS reduces active current to standby current levels for 2.7V-3.6V CMOS input levels. 3.5.3 STANDBY POWER With CE# at a logic-high level (VIH) and the CUI in read mode, the flash memory is in standby mode, which disables much of the device's circuitry and substantially reduces power consumption. Outputs (DQ0-DQ7) are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application-specific power and energy requirements. 3.5.4 DEEP POWER-DOWN MODE The deep power-down mode of the Smart 3 Advanced Boot Block products switches the device into a low power savings mode, which is especially important for battery-based devices. This mode is activated when RP# = VIL. (GND 0.2V). During read modes, RP# going low de-selects the memory and places the output drivers in a high impedance state. Recovery from the deep powerdown state, requires a minimum time equal to tPHQV (see AC Characteristics table). During program or erase modes, RP# transitioning low will abort the operation, but the memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. PRELIMINARY During deep power-down, all internal circuits are switched to a low power savings mode (RP# transitioning to VIL or turning off power to the device clears the status register). 3.6 Power-Up/Down Operation The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, VPP or VCC, powers-up first. 3.6.1 RP# CONNECTED TO SYSTEM RESET The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when VCC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.6.2 VCC, VPP AND RP# TRANSITIONS The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode or after VCC transitions above VLKO (Lockout voltage), is read array mode. 27 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE E Refer to AP-617 Additional Flash Data Protection Using VPP, RP#, and WP# for a circuit-level description of how to implement the protection schemes discussed in Section 3.5. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 F ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These highfrequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7 3.7.1 After any program or block erase operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired. Power Supply Decoupling Flash memory's power switching characteristics require careful device decoupling. System designers should consider three supply current issues: 1. Standby current levels (ICCS) 2. Active current levels (I CCR) 3. Transient peaks produced by falling and rising edges of CE#. 28 VPP TRACE ON PRINTED CIRCUIT BOARDS Designing for in-system writes to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. The VPP pin supplies the flash memory cells current for programming and erasing. VPP trace widths and layout should be similar to that of VCC. Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. PRELIMINARY E 4.0 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE ABSOLUTE MAXIMUM RATINGS* Extended Operating Temperature During Read ............................ -40C to +85C During Block Erase and Program............................ -40C to +85C Temperature Under Bias ......... -40C to +85C Storage Temperature................... -65C to +125C Voltage on Any Pin (except VCC, VCCQ and VPP) with Respect to GND ............... -0.5V to +5.0V1 NOTICE: This datasheet contains preliminary information on products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability. NOTES: 1. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods < 20 ns. Maximum DC voltage on input/output pins is VCC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for periods < 20 ns. Maximum DC voltage on VPP may overshoot to +14.0V for periods < 20 ns. Output shorted for no more than one second. No more than one output shorted at a time. VPP Program voltage is normally 2.7V-3.6V. Connection to supply of 11.4V-12.6V can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. VPP may be connected to 12V for a total of 80 hours maximum. See Section 3.4 for details. VPP Voltage (for Block Erase and Program) with Respect to GND .........-0.5V to +13.5V1,2,4 VCC and VCCQ Supply Voltage with Respect to GND ............... -0.2V to +5.0V1 Output Short Circuit Current...................... 100 mA3 2. 3. 4. 5.0 OPERATING CONDITIONS (VCCQ = 2.7V-3.6V) Table 9. Temperature and Voltage Operating Conditions4 Symbol Parameter Notes Min Max Units -40 +85 C TA Operating Temperature VCC 2.7V-3.6V VCC Supply Voltage 1,4 2.7 3.6 Volts VCCQ 2.7V-3.6V I/O Supply Voltage 1,2,4 2.7 3.6 Volts VPP1 Program and Erase Voltage 4 2.7 3.6 Volts 3 11.4 12.6 Volts 5 10,000 VPP2 Cycling Block Erase Cycling Cycles NOTES: 1. See DC Characteristics tables for voltage range-specific specifications. 2. The voltage swing on the inputs, VIN is required to match VCCQ. 3. Applying VPP = 11.4V-12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum. See section 3.4 for details. 4. VCC, VCCQ and VPP1 must share the same supply when all three are between 2.7V and 3.6V. 5. For operating temperatures of -25C- +85C the device is projected to have a minimum block erase cycling of 10,000 to 30,000 cycles. PRELIMINARY 29 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE 5.1 DC Characteristics: VCCQ = 2.7V-3.6V Table 10. DC Characteristics Sym Parameter Notes VCC = 2.7V-3.6V Typ Unit Test Conditions Max ILI Input Load Current 1 1.0 A VCC = VCCMax = VCCQMax VIN = VCCQ or GND ILO Output Leakage Current 1 10 A VCC = VCCMax = VCCQMax VIN = VCCQ or GND ICCS VCC Standby Current 50 A CMOS INPUTS VCC = VCCMax = VCCQMax 1,7 20 CE# = RP# = VCCQ ICCD VCC Deep Power-Down Current ICCR VCC Read Current 1,7 1 10 A CMOS INPUTS VCC = VCCMax = VCCQMax VIN = VCCQ or GND RP# = GND 0.2V 1,5,7 10 20 mA CMOS INPUTS VCC = VCCMax = VCCQMax OE# = VIH , CE# =VIL f = 5 MHz, IOUT = 0 mA Inputs = VIL or VIH ICCW ICCE VCC Program Current VCC Erase Current 1,4,7 1,4,7 8 20 mA VPP = VPPH1 (3V) Program in Progress 8 20 mA VPP = VPPH2 (12V) Program in Progress 8 20 mA VPP = VPPH1 (3V) Erase in Progress 8 20 mA VPP = VPPH2 (12V) Erase in Progress ICCES VCC Erase Suspend Current 1,2,4,7 20 50 A CE# = VIH Erase Suspend in Progress ICCWS VCC Program Suspend Current 1,2,4,7 20 50 A CE# = VIH Program Suspend in Progress IPPD VPP Deep Power-Down Current 1 0.2 5 A RP# = GND 0.2V IPPR VPP Read Current 1 2 50 A VPP VCC 30 PRELIMINARY E Sym IPPW SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 10. DC Characteristics (Continued) Parameter VPP Program Current Notes 1,4 VCC = 2.7V-3.6V Typ Max 15 40 Unit mA Test Conditions VPP = VPPH1 (3V) Program in Progress 10 25 mA VPP = VPPH2 (12V) Program in Progress IPPE VPP Erase Current 1,4 13 25 mA VPP = VPPH1 (3V) Erase in Progress 8 25 mA VPP = VPPH2 (12V) Erase in Progress IPPES VPP Erase Suspend Current 1,4 50 200 A VPP = VPPH1 or VPPH2 Erase Suspend in Progress IPPWS VPP Program Suspend Current 1,4 50 200 A VPP = VPPH1 or VPPH2 Program Suspend in Progress PRELIMINARY 31 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 10. DC Characteristics (Continued) Sym Parameter Notes VCC = 2.7V-3.6V Min Max Input Low Voltage -0.4 0.4 VIH Input High Voltage VCCQ - 0.4V VOL Output Low Voltage VOH Output High Voltage VPPLK VPP Lock-Out Voltage VPPH1 VPP during Prog/Erase Operations VIL Test Conditions V V 0.10 VPPH2 Unit V VCC = VCCMin = VCCQMin IOL = 100 A VCCQ - 0.1V V VCC = VCCMin = VCCQMin IOH = -100 A 3 1.5 V Complete Write Protection 3 2.7 3.6 V 3,6 11.4 12.6 V VLKO VCC Program/Erase Lock Voltage 1.5 V VLKO2 VCCQ Program/Erase Lock Voltage 1.2 V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25C. 2. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is ICCR. If the device is read while in program suspend, current draw is ICCR. 3. Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPPH1 and VPPH2. 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 6. Applying VPP = 11.4V-12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum. See Section 3.4 for details. 7. Includes the sum of VCC and VCCQ current. Table 11. Capacitance (TA = 25C, f = 1 MHz) Sym Parameter Notes Typ Max Units Conditions CIN Input Capacitance 1 6 8 pF VIN = 0V COUT Output Capacitance 1 10 12 pF VOUT = 0V NOTE: 1. Sampled, not 100% tested. 32 PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE VCCQ VCCQ INPUT TEST POINTS 2 VCCQ 2 OUTPUT 0.0 0605-011 NOTE: AC test inputs are driven at VCCQ for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10%-90%) <10 ns. Worst case speed conditions are when VCCQ=2.7V. Figure 10. 2.7V-3.6V Input Range and Measurement Points Test Configuration Component Values for Worst Case Speed Conditions VCCQ Test Configuration R 2.7V Standard Test 1 Device under Test CL (pF) R1 () R2 () 50 25K 25K Out CL R 2 0605-012 NOTE: See table for component values. Figure 11. Test Configuration PRELIMINARY 33 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE 6.0 OPERATING CONDITIONS (VCCQ = 1.8V-2.2V) Table 12. Temperature and VCC Operating Conditions Symbol Parameter Notes Min Max Units -40 +85 C TA Operating Temperature VCC1 2.7V-2.85V VCC Supply Voltage 1 2.7 2.85 Volts VCC2 2.7V-3.3V VCC Supply Voltage 1 2.7 3.3 Volts VCCQ 1.8V-2.2V I/O Supply Voltage 1,4 1.8 2.2 Volts VPP1 Program and Erase Voltage 1 2.7 2.85 Volts VPP2 1 2.7 3.3 Volts VPP3 1,2 11.4 12.6 Volts 3 10,000 Cycling Block Erase Cycling Cycles NOTES: 1. See DC Characteristics tables for voltage range-specific specifications. 2. Applying VPP = 11.4V-12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter. VPP may be connected to 12V for a total of 80 hours maximum. See Section 3.4 for details. 3. For operating temperatures of -25C- +85C the device is projected to have a minimum block erase cycling of 10,000 to 30,000 cycles. 4. The voltage swing on the inputs, VIN is required to match VCCQ. 6.1 DC Characteristics: VCCQ = 1.8V-2.2V These tables are valid for the following power supply combinations only: 1. VCC1 and VCCQ and (VPP1 or VPP3) 2. VCC2 and VCCQ and (VPP2 or VPP3) Wherever the input voltage VIN is mentioned, it is required that V IN matches the chosen V CCQ. 34 PRELIMINARY E Sym SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 13. DC Characteristics: VCCQ = 1.8V-2.2V Parameter Notes VCC1: 2.7V-2.85V VCC2: 2.7V-3.3V Typ Unit Test Conditions Max ILI Input Load Current 1 1.0 A VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND ILO Output Leakage Current 1 10 A VCC = VCC Max VCCQ = VCCQMax VIN = VCCQ or GND ICCS VCC Standby Current 50 A CMOS INPUTS VCC = VCC1 Max (2.7V-2.85V) VCCQ = VCCQMax 1,7 20 CE# = RP# = VCCQ 150 250 A CMOS INPUTS VCC = VCC2 Max (2.7V-3.3V) VCCQ = VCCQMax CMOS INPUTS VCC = VCCMax (VCC1 or VCC2) VCCQ = VCCQMax VIN = VCCQ or GND RP# = GND 0.2V CMOS INPUTS VCC = VCC1Max (2.7V-2.85V) VCCQ = VCCQMax OE# = VIH , CE# = VIL f = 5 MHz, I OUT = 0 mA CE# = RP# = VCCQ ICCD VCC Deep Power-Down Current ICCR VCC Read Current 1,7 1 10 A 1,5,7 8 18 mA Inputs = VIL or VIH 12 23 mA CMOS INPUTS VCC = VCC2Max (2.7V-3.3V) VCCQ = VCCQMax OE# = VIH , CE# = VIL f = 5 MHz, I OUT = 0 mA Inputs = GND 0.2V or VCCQ PRELIMINARY 35 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 13. DC Characteristics: VCCQ = 1.8V-2.2V (Continued) Sym ICCW ICCE Parameter VCC Program Current VCC Erase Current Notes 1,4,7 1,4,7 VCC1: 2.7V-2.85V VCC2: 2.7V-3.3V Unit E Test Conditions Typ Max 8 20 mA VPP = VPPH1 or VPPH2 Program in Progress 8 20 mA VPP = VPPH3 (12V) Program in Progress 8 20 mA VPP = VPPH1 or VPPH2 Erase in Progress 8 20 mA VPP = VPPH3 (12V) Erase in Progress ICCES VCC Erase Suspend Current 1,2,4,7 20 50 A CE# = VIH Erase Suspend in Progress ICCWS VCC Program Suspend Current 1,2,4,7 20 50 A CE# = VIH Program Suspend in Progress IPPD VPP Deep Power-Down Current 1 0.2 5 A RP# = GND 0.2V IPPR VPP Read and Standby Current 1 2 50 A VPP VCC IPPW VPP Program Current 1,4 15 40 mA VPP = VPPH1 or VPPH2 Program in Progress 10 25 mA VPP = VPPH3 (12V) Program in Progress 13 25 mA VPP = VPPH1 or VPPH2 IPPE VPP Erase Current 1,4 Erase in Progress 8 25 mA VPP = VPPH3 (12V) Erase in Progress IPPES VPP Erase Suspend Current 1 50 200 A VPP = VPPH1 , VPPH2 , or VPPH3 Erase Suspend in Progress IPPWS VPP Program Suspend Current 1 50 200 A VPP = VPPH1 , VPPH2 , or VPPH3 Program Suspend in Progress 36 PRELIMINARY E Sym SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 13. DC Characteristics: VCCQ = 1.8V-2.2V (Continued) Parameter Notes VCC1: 2.7V-2.85V VCC2: 2.7V-3.3V Typ Max Input Low Voltage -0.2 0.2 VIH Input High Voltage VCCQ - 0.2V VOL Output Low Voltage -0.10 VIL Unit Test Conditions V V 0.10 V VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VOH Output High Voltage VPPLK VPP Lock-Out Voltage VPPH1 VPP during Prog./Erase Operations VPPH2 VPPH3 VLKO1 VLKO2 VCCQ - 0.1V V VCC = VCCMin VCCQ = VCCQMin IOH = -100 A 3 1.5 V Complete Write Protection 3 2.7 2.85 V 3 2.7 3.3 V 3,6 11.4 12.6 V VCC Program/Erase Lock Voltage VCCQ Program/Erase Lock Voltage 1.5 V 1.2 V NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25C. 2. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is ICCR. If the device is read while in program suspend, current draw is ICCR. 3. Erases and Writes inhibited when VPP < VPPLK, and not guaranteed outside the valid VPP ranges of VPPH1,VPPH2. or VPPH3. 4. Sampled, not 100% tested. 5. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 6. Applying VPP = 11.4V-12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum. See Section 3.4 for details. 7 Includes the sum of VCC and VCCQ current Table 14. Capacitance (TA = 25C, f = 1 MHz) Sym Parameter Notes Typ Max Units Conditions CIN Input Capacitance 1 6 8 pF VIN = 0V COUT Output Capacitance 1 10 12 pF VOUT = 0V NOTE: 1. Sampled, not 100% tested. PRELIMINARY 37 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE VCCQ VCCQ INPUT TEST POINTS 2 VCCQ 2 OUTPUT 0.0 0605-011 NOTE: AC test inputs are driven at VCCQ for a logic "1" and 0.0V for a logic "0." Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10%-90%) <10 ns. For worst case speed conditions VCCQ=1.8V. Figure 12. 1.8V--2.2V Input Range and Measurement Points Test Configuration Component Values for Worst Case Speed Conditions VCCQ Test Configuration R 1.8V Standard Test 1 Device under Test Out CL (pF) R1 () R2 () 50 16.7K 16.7K NOTE: CL includes jig capacitance. CL R 2 0605-012 NOTE: See table for component values. Figure 13. Test Configuration 38 PRELIMINARY E 7.0 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE AC CHARACTERISTICS AC Characteristics are applicable to both VCCQ ranges. Table 15. AC Characteristics: Read Operations (Extended Temperature) # Symbol Parameter Load CL = 50 pF VCC 2.7V-3.6V4 Prod Notes 120 ns Min Max 120 Units 150 ns Min Max R1 tAVAV Read Cycle Time R2 tAVQV Address to Output Delay R3 tELQV CE# to Output Delay 2 R4 tGLQV OE# to Output Delay 2 R5 tPHQV RP# to Output Delay R6 tELQX CE# to Output in Low Z 3 0 0 ns R7 tGLQX OE# to Output in Low Z 3 0 0 ns R8 tEHQZ CE# to Output in High Z 3 40 40 ns R9 tGHQZ OE# to Output in High Z 3 40 40 ns R10 tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 3 0 150 ns 120 150 ns 120 150 ns 65 65 ns 600 600 ns 0 ns NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. 3. Sampled, but not 100% tested. 4. See Test Configuration (Figures 11 and 13), 2.7V-3.6V and 1.8V-2.2V Standard Test component values. PRELIMINARY 39 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE CE# (E) Data Valid Device and Address Selection VIH ADDRESSES (A) VIL Standby Address Stable R1 VIH VIL OE# (G) R8 VIH VIL R9 VIH WE# (W) VIL VOH DATA (D/Q) VOL RP#(P) R7 High Z R10 R3 R6 Valid Output High Z R2 VIH VIL R4 R5 0605-015 Figure 14. AC Waveform: Read Operations 40 PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 16. AC Characteristics: Write Operations (Extended Temperature)1 Load # Symbol Parameter 50 pF VCC 2.7V-3.6V5 2.7V-3.6V5 Prod 120 ns 150 ns Notes Min Max Min Units Max W1 tPHWL tPHEL RP# High Recovery to WE# (CE#) Going Low 600 600 ns W2 tELWL tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 0 0 ns W3 tWLWH tELEH WE# (CE#) Pulse Width 90 90 ns W4 tDVWH tDVEH Data Setup to WE# (CE#) Going High 3 70 70 ns W5 tAVWH tAVEH Address Setup to WE# (CE#) Going High 2 90 90 ns W6 tWHEH tEHWH CE# (WE#) Hold Time from WE# (CE#) High 0 0 ns W7 tWHDX tEHDX Data Hold Time from WE# (CE#) High 3 0 0 ns W8 tWHAX tEHAX Address Hold Time from WE# (CE#) High 2 0 0 ns W9 tWHWL tEHEL WE# (CE#) Pulse Width High 30 30 ns W10 tVPWH tVPEH VPP Setup to WE# (CE#) Going High 4 200 200 ns W11 tQVVL VPP Hold from Valid SRD 4 0 0 ns tLOCK Block Unlock / Lock Delay 4, 6 200 200 ns NOTES: 1. Read timing characteristics during program suspend and erase suspend are the same as during read-only operations. Refer to AC Characteristics during read mode. 2. Refer to command definition table for valid AIN (Table6). 3. Refer to command definition table for valid DIN (Table 6). 4. Sampled, but not 100% tested. 5. See Test Configuration (Figure 11 and 13), 2.7V-3.6V and 1.8V-2.2V Standard Test component values. 6. Time tLOCK is required for successful locking and unlocking of all lockable blocks. PRELIMINARY 41 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE VIH A B C AIN ADDRESSES [A] VIL VIH D E F AIN W8 W5 (Note 1) CE#(WE#) [E(W)] VIL W6 VIH W2 OE# [G] VIL W9 (Note 1) VIH WE#(CE#) [W(E)] VIL W3 W4 VIH DATA [D/Q] High Z VIL RP# [P] W7 DIN DIN W1 Valid SRD DIN VIH VIL VIH WP# V [V] PP VIL W10 W11 VPPH 2 VPPH1 VPPLK VIL 0605-016 NOTES: 1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register Data. A. B. C. D. E. F. VCC Power-Up and Standby. Write Program or Erase Setup Command. Write Valid Address and Data (for Program) or Erase Confirm Command. Automated Program or Erase Delay. Read Status Register Data (SRD): reflects completed program/erase operation. Write Read Array Command. Figure 15. AC Waveform: Program and Erase Operations 42 PRELIMINARY E 7.1 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Reset Operations RP# (P) VIH VIL t PLPH (A) Reset during Read Mode t PHQV t PHWL t PHEL Abort Complete t PLRH RP# (P) VIH t PHQV t PHWL t PHEL VIL t PLPH (B) Reset during Program or Block Erase, t PLPH < t PLRH Abort Deep Complete PowerDown RP# (P) VIH V IL t PLRH t PHQV t PHWL t PHEL t PLPH (C) Reset Program or Block Erase, t PLPH > t PLRH 0605-17 Figure 16. AC Waveform: Deep Power-Down/Reset Operation Reset Specifications VCC = 2.7-3.6V Notes Min tPLPH Symbol RP# Low to Reset during Read (If RP# is tied to VCC, this specification is not applicable) Parameter 1,3 100 tPLRH RP# Low to Reset during Block Erase or Program 2,3 Max Unit ns 22 s NOTES: 1. If tPLPH is < 100 ns the device may still RESET but this is not guaranteed. 2. If RP# is asserted while a block erase or byte program operation is not executing, the reset will complete within 100 ns. 3. Sampled but not 100% tested. PRELIMINARY 43 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE Table 17. Erase and Program Timings VPP = 2.7V Sym Parameter VPP = 12V Notes Typ1 Max3 Typ1 Max3 Unit tBWPB Block Program Time (Parameter) 2 .16 .48 .08 .24 sec tBWMB Block Program Time (Main) 2 1.23 3.69 .58 1.74 sec tWHQV1 tEHQV1 Program Time 2 17 165 8 185 s tWHQV2 tEHQV2 Block Erase Time (Parameter) 2 1 5.0 0.8 4.8 sec tWHQV3 tEHQV3 Block Erase Time (Main) 2 1.8 8.0 1.1 7.0 sec tWHRH1 tEHRH1 Program Suspend Latency 3 5 10 5 10 s tWHRH2 tEHRH2 Erase Suspend Latency 3 5 20 6 12 s NOTES: 1. Typical values measured at TA = +25C and nominal voltages. 2. Excludes external system-level overhead. 3. Sampled but not 100% tested. 44 PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE APPENDIX A ORDERING INFORMATION T E2 8 F 1 6 0 B3 T 1 2 0 Package TE = 40-Lead TSOP GT = 48-Ball BGA* CSP Access Speed (ns) (120, 150) Product line designator for all Intel Flash products T = Top Blocking B = Bottom Blocking Device Density 016 = x8 (16-Mbit) 008 = x8 (8-Mbit) Product Family B3 = Smart 3 Advanced Boot Block VCC = 2.7V - 3.6V VPP = 2.7V - 3.6V or 11.4V - 12.6V VALID COMBINATIONS Extended Extended PRELIMINARY 16M 8M 40-Lead TSOP TE28F016B3T120 TE28F016B3B120 48-Ball BGA* CSP GT28F016B3T120 GT28F016B3B120 TE28F016B3T150 TE28F016B3B150 GT28F016B3T150 GT28F016B3B150 TE28F008B3T120 TE28F008B3B120 GT28F008B3T120 GT28F008B3B120 TE28F008B3T150 TE28F008B3B150 GT28F008B3T150 GT28F008B3B150 45 E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE APPENDIX B WRITE STATE MACHINE CURRENT/NEXT STATES Command Input (and Next State) Current State SR.7 Data When Read Read Array (FFH) Program Setup (40/10H) Erase Setup (20H) Read Array "1" Array Read Array Program Setup Erase Setup Program Setup "1" Status Pgm. Program (Not Comp.) "0" Status Program (Complete) "1" Status Read Array Program Suspend to Status "1" Status Prog. Susp. to Array Program Suspend Program Suspend to Array "1" Array Prog. Susp. to Array Program Suspend to Array Erase Setup "1" Status Erase Cmd. Error "1" Status Erase (Not Comp) "0" Status Erase (Complete) "1" Status Read Array Program Setup Erase Setup Erase Suspend to Status "1" Status Erase Susp. to Array Program Setup Erase Susp. to Array Erase Erase Susp. to Array Erase Erase Susp. to Status Erase Suspend to Array Erase. Susp. to Array "1" Array Erase Susp. to Array Program Setup Erase Susp. to Array Erase Erase Susp. to Array Erase Erase Susp. to Status Erase Suspend to Array Read Status "1" Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Identifier Read Identifier "1" ID Read Array Program Setup Erase Setup Read Array Read Status Read Read Identifier 1. 46 1 Erase Confirm (D0H) Program / Erase Resume (D0) Read Array Read Status (70H) Clear Status (50H) Read ID (90H) Read Status Read Array Read Identifier Program (Command input = Data to be programmed) Program Program Setup Pgm Susp. to Status Erase Setup Program Setup Program Read Array Read Status Read Array Read Identifier Program Program Susp. to Array Program Prog. Susp. to Status Program Suspend to Array Program Program Susp. to Array Program Prog. Susp. to Status Prog. Susp. to Array Erase Erase Cmd. Err. Erase to Array Erase Command Error Read Array Program / Erase Susp. (B0H) Erase Setup Read Array Erase Erase Command Error Read Status Ers. Susp. to Status Prog. Susp. to Array Read Array Read Identifier Erase Read Array Read Status Read Array Array Read Identifier You cannot program "1"s to the flash. Writing FFH following the Program Setup will initiate the internal program algorithm of the WSM. Although the algorithm will execute, array data is not changed. The WSM returns to read status mode without reporting any error. Assuming VPP > VPPLK writing a second FFH while in read status mode will return the flash to read array mode. PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE APPENDIX C ACCESS TIME VS. CAPACITIVE LOAD (tAVQV vs. CL) Access Time vs. Load Capacitance Derating Curve 124 123 Access Time(ns) 122 121 120 Smart 3 Advanced Boot Block 119 118 117 116 115 30 50 70 100 Load Capacitance(pF) NOTE: VCCQ = 2.7V This chart shows a derating curve for device access time with respect to capacitive load. The value in the DC characteristics section of the specification corresponds to C L = 50 pF. NOTE: 1. Sampled, but not 100% tested PRELIMINARY 47 SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE APPENDIX D ARCHITECTURE BLOCK DIAGRAM E DQ0-DQ7 VCCQ Power Reduction Control Input Buffer Identifier Register Status Register Data Register Output Multiplexer Output Buffer I/O Logic CE# WE# OE# RP# Command User Interface Data Comparator WP# A0-A20 Y-Decoder Y-Gating/Sensing Write State Machine Address Counter 48 64-Kbyte Main Block X-Decoder 8-Kbyte Parameter Block 64-Kbyte Main Block Address Latch 8-Kbyte Parameter Block Input Buffer Program/Erase Voltage Switch VPP VCC GND PRELIMINARY E SMART 3 ADVANCED BOOT BLOCK-BYTE-WIDE APPENDIX E ADDITIONAL INFORMATION(1,2) Order Number Document/Tool 210830 1997 Flash Memory Databook 290580 Smart 3 Advanced Boot Block Word-Wide 4-Mbit (256K x 16), 8-Mbit (512K x16), 16-Mbit (1024K x16) Flash Memory Family Datasheet 292172 AP-617 Additional Flash Data Protection Using VPP, RP# and WP# NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com for technical documentation and tools. PRELIMINARY 49