E PRELIMINARY
Ma
y
1997 Order Number: 290605-001
n
Flexible SmartVoltage Technology
2.7V–3.6V Program/Erase
2.7V–3.6V Read Operation
12V VPP Fast Production
Programming
n
2.7V or 1.8V I/O Option
Reduces Overall System Power
n
Optimized Block Sizes
Eight 8-Kbyte Blocks for Data,
Top or Bottom Locations
Up to Thirty-One 64-Kbyte Blocks
for Code
n
High Performance
2.7V–3.6V: 120 ns Max Access Time
n
Block Locking
VCC-Level Control through WP#
n
Low Power Consumption
20 mA Maximum Read Current
n
Absolute Hardware-Protection
VPP = GND Option
VCC Lockout Voltage
n
Extended Temperature Operation
–40°C to +85°C
n
Supports Code plus Data Storage
Optimized for FDI, Flash Data
Integrator Software
Fast Program Suspend Capability
Fast Erase Suspend Capability
n
Extended Cycling Capability
10,000 Block Erase Cycles
n
Automated Byte Program and Block
Erase
Command User Interface
Status Registers
n
SRAM-Compatible Write Interface
n
Automatic Power Savings Feature
n
Reset/Deep Power-Down
1 µA ICCTypical
Spurious Write Lockout
n
Standard Surface Mount Packaging
48-Ball µBGA* Package
40-Lead TSOP Package
n
Footprint Upgradeable
Upgradeable from 2-, 4- and 8-Mbit
Boot Block
n
ETOX™ V (0.4 µ) Flash Technology
n
x8-Only Input/Output Architecture
For Space-Constrained 8-bit
Applications
The new Smart 3 A dvanc ed Boot Bloc k, manuf act ured on Int el’s lates t 0. 4µ tec hnology , repres ents a f eature-
rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I/O at 1.8V, which significantly reduces system active power and
interfac es to 1.8V cont rollers. A new bloc king schem e enables code and data s torage within a si ngle device.
Add to this the Intel-developed Flash Data Integrator (FDI) software and you have the most cost-effective,
monolithic code plus data storage solution on the market today. Smart 3 Advanced Boot Block Byte-Wide
products will be available in 40-lead TSOP and 48-ball µBGA* packages. Additional information on this
product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp
SMART 3 ADVANCED BOOT BLOCK
BYTE-WIDE
8-MBIT (1024K x 8), 16-MBIT (2056K x 8)
FLASH MEMORY FAMILY
28F008B3, 28F016B3
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property ri ghts is granted by this document. Except as provided in Intel’s Terms and Conditi ons of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property ri ght. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F008B3 and 28F016B3 may contain design defects or errors known as errata which may cause the product to devi ate
from published specifications. Current characterized errata are available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
or visit Intel’s website at http:\\www.intel.com
COPYRIGHT © INTEL CORPORATION 1996, 1997 CG-041493
*Third-party brands and names are the property of their respective owners.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
3
PRELIMINARY
CONTENTS
PAGE PAGE
1.0 INTRODUCTION .............................................5
1.1 Smart 3 Advanced Boot Block Flash
Memory Enhancements ..............................5
1.2 Product Overview.........................................6
2.0 PRODUCT DESCRIPTION..............................6
2.1 Package Pinouts..........................................7
2.2 Block Organization.....................................11
2.2.1 Parameter Blocks................................11
2.2.2 Main Blocks.........................................11
3.0 PRINCIPLES OF OPERATION .....................14
3.1 Bus Operation............................................14
3.1.1 Read....................................................15
3.1.2 Output Disable.....................................15
3.1.3 Standby...............................................15
3.1.4 Deep Power-Down/Reset....................15
3.1.5 Write....................................................15
3.2 Modes of Operation....................................15
3.2.1 Read Array..........................................16
3.2.2 Read Intelligent Identifier.....................17
3.2.3 Read Status Register ..........................17
3.2.4 Program Mode.....................................18
3.2.5 Erase Mode.........................................19
3.3 Block Locking.............................................26
3.3.1 VPP = VIL for Complete Protection .......26
3.3.2 WP# = VIL for Block Locking................26
3.3.3 WP# = VIH for Block Unlocking............26
3.4 VPP Program and Erase Voltages ..............26
3.5 Power Consumption...................................26
3.5.1 Active Power .......................................26
3.5.2 Automatic Power Savings (APS) .........27
3.5.3 Standby Power....................................27
3.5.4 Deep Power-Down Mode.....................27
3.6 Power-Up/Down Operation.........................27
3.6.1 RP# Connected to System Reset ........27
3.6.2 VCC, VPP and RP# Transitions.............27
3.7 Power Supply Decoupling ..........................28
3.7.1 VPP Trace on Printed Circuit Boards....28
4.0 ABSOLUTE MAXIMUM RATINGS................29
5.0 OPERATING CONDITIONS
(VCCQ = 2.7V–3.6V).......................................29
5.1 DC Characteristics: VCCQ = 2.7V–3.6V.......30
6.0 OPERATING CONDITIONS
(VCCQ = 1.8V–2.2V).......................................34
6.1 DC Characteristics: VCCQ = 1.8V–2.2V.......34
7.0 AC CHARACTERISTICS...............................39
7.1 Reset Operations .......................................43
APPENDIX A: Ordering Information .................45
APPENDIX B: Write State Machine Current/
Next States ..................................................46
APPENDIX C: Access Time vs.
Capacitive Load...........................................47
APPENDIX D: Architecture Block Diagram ......48
APPENDIX E: Additional Information ...............49
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
4PRELIMINARY
REVISION HISTORY
Number Description
-001 Original version
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
5
PRELIMINARY
1.0 INTRODUCTION
This preliminary datasheet contains the
specifications for the Advanced Boot Block flash
memory family, which is optimized for low power,
portable systems. This family of products features
1.8V–2.2V or 2.V–3.6V I/Os and a low VCC/VPP
operating range of 2.7V–3.6V for read and
program/erase operat ions . I n additi on t his f amil y is
capable of fast programming at 12V. Throughout
this document, the term “2.7V” refers to the full
voltage range 2.7V–3.6V (except where noted
otherwise) and “VPP = 12V” refers to 12V ±5%.
Section 1 and 2 provides an overview of the flash
memory family including applications, pinouts and
pin descriptions. Section 3 describes the memory
organization and operation for these products.
Finally, Sections 4, 5, 6 and 7 contain the
operating specifications.
1.1 Smart 3 Advanced Boot Block
Flash Memory Enhancements
The new 8-Mbit and 16-Mbit Smart 3 Advanced
Boot Block flash memory provides a convenient
upgrade from and/or compatibility to previous 4-
Mbit and 8-Mbit Boot Block produc ts. The Smart 3
product functions are similar to lower density
products in both command sets and operation,
providing similar pinouts to ease density upgrades.
The Smart 3 Advanced Boot Block flash memory
features
•Enhanced blocking for easy segmentation of
code and data or additional design flexibility
•Program Suspend command which permits
program suspend to read
•WP# pin to lock and unlock the upper two (or
lower two, depending on location) 8-Kbyte
blocks
•VCCQ input for 1.8V–2.2V on all I/Os. See
Figures 1–3 for pinout diagrams and VCCQ
location
•Maximum program time specification for
improved data storage.
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature 28F016B3/28F008B3/28F004B3 Reference
VCC Read Voltage 2.7V– 3.6V Table 9, Table 12
VCCQ I/O Voltage 1.8V–2.2V or 2.7V– 3.6V Table 9, Table 12
VPP Program/Erase Voltage 2.7V– 3.6V or 11.4V– 12.6V Table 9, Table 12
Bus Width 8 bits Table 2
Speed 120 ns Table 15
Memory Arrangement 1 Mbit x 8 (8 Mbit), 2 Mbit x 8 (16 Mbit)
Blocking (top or bottom) Eight 8-Kbyte parameter blocks (8/16 Mbit) &
Fifteen 64-Kbyte blocks (8 Mbit)
Thirty-one 64-Kbyte main blocks (16 Mbit)
Section 2.2
Figures 4 and 5
Locking WP# locks/unlocks parameter blocks
All other blocks protected using VPP switch Section 3.3
Table 8
Operating Temperature Extended: –40°C to +85°C Table 9, Table 12
Program/Erase Cycling 10,000 cycles Table 9, Table 12
Packages 40-Lead TSOP, 48-Ball µBGA* CSP Figures 1, 2, and 3
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
6PRELIMINARY
1.2 Product Overview
Intel provides the most flexible voltage solution in
the flash industry, providing three discrete voltage
supply pi ns: VCC f or read operation, VCCQ f or output
swing, and VPP for program and erase operation.
Discret e supply pins allow system designers to use
the optim al voltage l evels f or their des ign. All Smart
3 Advanced Boot Block flash memory products
provide program/erase capability at 2.7V or 12V
and read with VCC at 2.7V. Since many designs
read from the flash memory a large percentage of
the time, 2.7V VCC operation can provide
substantial power savings. The 12V VPP option
maximizes program and erase performance during
production programming.
The Smart 3 Advanced Boot Block flash memory
products are high-performance devices with low
power operation. The available densities for the
byte-wide devices (x8) are
a. 8-Mbit (8,388,608-bit) flash memory
organized as 1 Mbyte of 8 bits each
b. 16-Mbit (16,777,216-bit) flash memory
organized as 2 Mbytes of 8 bits each.
For word-wide devices (x16) see the
Smart 3
Advanced Boot Block Word-Wide Flash Memory
Family
datasheet.
The parameter blocks are located at either the top
(denoted by -T s uf fix) or the bottom (-B suf f i x) of the
address map in order to accommodate different
microprocessor protocols for kernel code location.
The upper two (or lower two) paramet er blocks can
be locked to provide complete code security for
system initialization code. Locking and unlocking is
controlled by WP# (see Section 3.3 for details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or
microcontroller and the internal operation of the
flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for program and erase
operations, including verification, thereby un-
burdening the microprocessor or microcontroller.
The status regist er indicates the status of the WSM
by signifying block erase or byte program
completion and status.
Program and erase aut omation allows program and
erase operations to be executed using an industry-
standard two-write command sequence to the CUI.
Data writes are performed in by te increm ents. Each
byte in the flash memory can be programmed
independently of other memory locations; every
erase operation erases all locations within a block
simultaneously. Program suspend allows system
software to s uspend t he program c ommand in order
to read from any other block . Eras e sus pend allows
system software to suspend the block erase
command in order to read from or program data to
any other block.
The Smart 3 A dvanced Boot B lock flas h memory is
also designed with an Automatic Power Savings
(APS) feature which minimizes system current
drain, allowing for very low power designs. This
mode is entered immediately following the
completion of a read cycle.
When the CE# and RP# pins are at VCC, the ICC
CMOS standby mode is enabled. A deep power-
down mode is enabled when the RP# pin is at
GND, minim izing power consumption and providing
write protection. ICC current in deep power-down is
1 µA typical (2.7V VCC). A minimum reset time of
tPHQV is required from RP# switching high until
outputs are valid to read attempts. With RP# at
GND, the WSM is reset and Status Register is
cleared. Section 3.5 contains additional information
on using the deep power-down feature, along with
other power consumption issues.
The RP# pin provides additional protection against
unwanted command writes that may occur during
system reset and power-up/down sequences due to
invalid system bus conditions (see Section 3.6).
Refer to the DC Charac teristi cs Table, Sec tions 5.1
and 6.1, for complete current and voltage
specifications. Refer to the AC Characteristics
Table, Section 7.0, for read, program and erase
performance specifications.
2.0 PRODUCT DESCRIPTION
This section explains device pin description and
package pinouts.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
7
PRELIMINARY
2.1 Package Pinouts
The Smart 3 A dvanced Boot B lock flas h memory is
available in 40-lead TSOP (see Figure 1) and 48-
ball µBGA packages (see Figures 2 and 3). In
Figure 1, pin changes from one density to the next
are circled. Both packages, 40-lead TSOP and 48-
ball µBGA package, are 8-bits wide and fully
upgradeable across product densities (from 8 Mb t o
16 Mb).
Advan c ed Boot Bloc k
40-Lead TSOP
10 mm x 20 mm
TOP VIEW
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
20
19
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
21
22
23
24
28F00828F016
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
WP#
A7
A6
A5
A4
A3
A2
A1
VPP
A18
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
WP#
A7
A6
A5
A4
A3
A2
A1
VPP
A18
28F008 28F016
A17
GND
A10
DQ7
DQ6
DQ5
DQ4
VCCQ
VCC
NC
DQ3
DQ2
DQ1
OE#
GND
CE#
A0
NC
A17
GND
A10
DQ7
DQ6
DQ5
DQ4
VCCQ
VCC
NC
DQ3
DQ2
DQ1
OE#
GND
CE#
A0
A19 A19
A20
DQ0DQ0
0605-01
Figure 1. 40-Lead TSOP Package
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
8PRELIMINARY
A
14
A
12
A
8
V
PP
WP# NC A
7
A
4
A
15
A
10
WE# RP# A
19
A
18
A
5
A
2
A
16
A
13
A
9
A
6
A
3
A
1
A
17
NC D
5
NC D
2
NC CE# A
0
V
CCQ
A
11
D
6
NC D
3
NC D
0
GND
GND D
7
NC D
4
V
CC
NC D
1
OE#
A
B
C
D
E
F
1234 567 8
0605-03
NOTE:
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.
Routing is not recommended in this area.
Figure 2. 8-Mbit 48-Ball µBGA* Chip Size Package
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
9
PRELIMINARY
A
14
A
12
A
8
V
PP
WP# A
20
A
7
A
4
A
15
A
10
WE# RP# A
19
A
18
A
5
A
2
A
16
A
13
A
9
A
6
A
3
A
1
A
17
NC D
5
NC D
2
NC CE# A
0
V
CCQ
A
11
D
6
NC D
3
NC D
0
GND
GND D
7
NC D
4
V
CC
NC D
1
OE#
A
B
C
D
E
F
1234 567 8
0605-02
NOTE:
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.
Routing is not recommended in this area.
Figure 3. 16-Mbit 48-Ball µBGA* Chip Size Package
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
10 PRELIMINARY
The pin descriptions table details the usage of each device pin.
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions
Symbol Type Name and Function
A0–A20 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a program or erase cycle.
28F008B3: A[0-19], 28F016B3: A[0-20]
DQ0–DQ7INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, Intelligent Identifier and Status Register
data. The data pins float to tri-state when the chip is de-selected or the
outputs are disabled.
CE# INPUT CHIP ENABLE: Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels. If
CE# and RP# are high, but not at a CMOS high level, the standby
current will increase due to current flow through the CE# and RP# inputs.
OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data
buffers during an array or status register read. OE# is active low.
WE# INPUT WRITE ENABLE: Controls writes to the Command Register and memory
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
RP# INPUT RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode, which drives the outputs to High-Z, resets the Write State
Machine, and draws minimum current.
When RP# is at logic high, the device is in standard operation.
When RP# transitions from logic-low to logic-high, the device defaults to
the read array mode.
WP# INPUT WRITE PROTECT: Provides a method for locking and unlocking the two
lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked,
preventing program and erase operations to those blocks. If a program
or erase operation is attempted on a locked block, SR.1 and either SR.4
[program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and
can be programmed or erased.
See Section 3.3 for details on write protection.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
11
PRELIMINARY
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued)
Symbol Type Name and Function
VCCQ INPUT OUTPUT VCC: Enables all outputs to be driven to 2.0V ±10% while the
VCC is at 2.7V. When this mode is used, the VCC should be regulated to
2.7V–2.85V to achieve lowest power operation (see Section 6.1: DC
Characteristics: VCCQ = 1.8V–2.2V).
This input may be tied directly to VCC (2.7V–3.6V).
See the DC Characteristics for further details.
VCC DEVICE POWER SUPPLY: 2.7V–3.6V
VPP PROGRAM/ERASE POWER SUPPLY: For erasing memory array
blocks or programming data in each block, a voltage of either 2.7V–3.6V
or 12V ± 5% must be applied to this pin. When VPP < VPPL
K
all blocks
are locked and protected against Program and Erase commands.
Applying 11.4V–12.6V to VPP can only be done for a maximum of 1000
cycles on the main blocks and 2500 cycles on the parameter blocks.
VPP may be connected to 12V for a total of 80 hours maximum (see
Section 3.4 for details).
GND GROUND: For all internal circuitry. All ground inputs must be
connected.
NC NO CONNECT: Pin may be driven or left floating.
2.2 Block Organization
The Smart 3 Advanced Boot Block is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. Each block can be erased
independently of the others up t o 10,000 tim es. For
the address locations of each block, see the
memory maps in Figure 4 (top boot blocking) and
Figure 5 (bottom boot blocking).
2.2.1 PARAMETER BLOCKS
The Smart 3 Advanced Boot Block flash memory
architecture includes parameter blocks to facilitate
storage of frequently updated small parameters
(e.g., data that would normally be stored in an
EEPROM. By using software techniques, the byte-
rewrite functionality of EEPROMs can be emulated.
Each 8-/16-Mbit device contains eight parameter
blocks of 8 Kbytes (8,192-bytes) each.
2.2.2 MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into equal s ize main blocks for data
or code storage. Each 16-Mbit device contains
thirty-one 64-Kbyte (65,536-byte) blocks. Each
8-Mbit device contains fifteen 64-Kbyte blocks.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
12 PRELIMINARY
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
FFFFF
FE000
FDFFF
FC000
FBFFF
F9FFF
FA000
F7FFF
70000
6FFFF
F8000
F6000
F5FFF
F4000
F2000
F1FFF
F0000
EFFFF
64-Kbyte Block
64-Kbyte Block
3FFFF
30000
2FFFF
20000
3
0
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
20
21
22
18
19
17
16
15
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
10
8
9
7
6
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
14
13
12
11
8-Mbit Advanced Boot
Block
64-Kbyte Block
64-Kbyte Block
50000
4FFFF
40000
64-Kbyte Block
64-Kbyte Block
1FFFF
10000
0FFFF
00000 0
1
2
4
5
F3FFF
5FFFF
60000
1E0000
1BFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
1FFFFF
1FE000
1FDFFF
1FC000
1FBFFF
1F9FFF
1FA000
1F7FFF
070000
06FFFF
1F8000
1F6000
1F5FFF
1F4000
1F2000
1F1FFF
1F0000
1EFFFF
64-Kbyte Block
64-Kbyte Block
03FFFF
030000
02FFFF
020000
3
0
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
36
37
38
34
35
33
32
31
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
10
8
9
7
6
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
30
29
12
11
16-Mbit Advanced Boot
Block
64-Kbyte Block
64-Kbyte Block
050000
04FFFF
040000
64-Kbyte Block
64-Kbyte Block
01FFFF
010000
00FFFF
000000 0
1
2
4
5
1F3FFF
05FFFF
060000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
19
17
18
16
15
64-Kbyte Block
64-Kbyte Block
21
20
64-Kbyte Block
64-Kbyte Block
0E0000
0DFFFF 13
14
0EFFFF
0F0000
1B0000
1A0000
19FFFF
1AFFFF
64-Kbyte Block
64-Kbyte Block
28
27
190000
180000
17FFFF
18FFFF
64-Kbyte Block
64-Kbyte Block
26
25
170000
64-Kbyte Block
160000
16FFFF
64-Kbyte Block
64-Kbyte Block
22
23
24
1DFFFF
1D0000
1CFFFF
1C0000
0605-05
Figure 4. 8-/16-Mbit Advanced Boot Block Byte-Wide Top Boot Memory Maps
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
13
PRELIMINARY
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
FFFFF
F0000
EFFFF
E0000
DFFFF
CFFFF
D0000
BFFFF
0E000
0DFFF
C0000
B0000
AFFFF
A0000
90000
8FFFF
80000
7FFFF
8-Kbyte Block
8-Kbyte Block
07FFF
06000
05FFF
04000
3
0
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
20
21
22
18
19
17
16
15
64-Kbyte Block
8-Kbyte Block
64-Kbyte Block
8-Kbyte Block
64-Kbyte Block
10
8
9
7
6
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
14
13
12
11
8-Mbit Advanced Boot
Block
8-Kbyte Block
8-Kbyte Block
0A000
09FFF
08000
8-Kbyte Block
8-Kbyte Block
03FFF
02000
01FFF
00000 0
1
2
4
5
9FFFF
0BFFF
0C000
170000
14FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1CFFFF
1D0000
1BFFFF
00E000
00DFFF
1C0000
1B0000
1AFFFF
1A0000
190000
18FFFF
180000
17FFFF
8-Kbyte Block
8-Kbyte Block
007FFF
006000
005FFF
004000
3
0
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
36
37
38
34
35
33
32
31
64-Kbyte Block
8-Kbyte Block
64-Kbyte Block
8-Kbyte Block
64-Kbyte Block
10
8
9
7
6
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
30
29
12
11
16-Mbit Advanced Boot
Block
8-Kbyte Block
8-Kbyte Block
00A000
009FFF
008000
8-Kbyte Block
8-Kbyte Block
003FFF
002000
001FFF
000000 0
1
2
4
5
19FFFF
00BFFF
00C000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
19
17
18
16
15
64-Kbyte Block
64-Kbyte Block
21
20
64-Kbyte Block
64-Kbyte Block
070000
06FFFF 13
14
07FFFF
080000
140000
130000
12FFFF
13FFFF
64-Kbyte Block
64-Kbyte Block
28
27
120000
110000
10FFFF
11FFFF
64-Kbyte Block
64-Kbyte Block
26
25
100000
64-Kbyte Block
0F0000
0FFFFF
64-Kbyte Block
64-Kbyte Block
22
23
24
16FFFF
160000
15FFFF
150000
0605-06
Figure 5. 8-/16-Mbit Advanced Boot Block Byte-Wide Bottom Boot Memory Maps
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
14 PRELIMINARY
3.0 PRINCIPLES OF OPERATION
Flash memory combines EEPROM functionality
with in-circuit electrical program and erase
capability. The Smart 3 Advanced Boot Block flash
memory family utilizes a Command User Interface
(CUI) and automated algori thms to s im plif y program
and erase operations. The CUI allows for 100%
CMOS-level control inputs, fixed power supplies
during erasure and programming, and maximum
EEPROM compatibility.
When VPP < VPPLK, the device will only execute the
following commands successfully: Read Array,
Read Status Register, Clear Status Register and
Read Intelligent Identifier. The device provides
standard EEPROM read, standby and output
disable operations. Manufacturer identification and
device identification data can be accessed through
the CUI. In addition, 2.7V or 12V on VPP allows
program and erase of the device. All functions
associated with altering memory contents, namely
program and erase, are accessible via the CUI.
The internal Write State Machine (WSM) com pl etely
automates program and erase operations while the
CUI signals the start of an operation and the status
register reports status. The CUI handles the WE#
interface to the data and address latches, as well
as system status requests during WSM operation.
3.1 Bus Operation
Smart 3 Advanced Boot Block flash memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations
are summarized in Table 3.
Table 3. Bus Operations for Byte-Wide Mode
Mode Notes RP# CE# OE# WE# WP# A0VPP DQ0–7
Read 1,2,3 VIH VIL VIL VIH XXXD
OUT
Output Disable 2 VIH VIL VIH VIH X X X High Z
Standby 2 VIH VIH X X X X X High Z
Deep Power-Down 2,9 VIL X X X X X X High Z
Intelligent Identifier (Mfr.) 2,4 VIH VIL VIL VIH XV
IL X 89 H
Intelligent Identifier (Dvc.) 2,4,5 VIH VIL VIL VIH XV
IH XSee Table 5
Write 2,6,7,
8VIH VIL VIH VIL XXV
PPH DIN
NOTES:
1. Refer to DC Characteristics.
2. X must be VIL, VIH for control pins and addresses, VPPLK , VPPH1 or VPPH2 for VPP.
3. See DC Characteristics for VPPLK, VPPH1, VPPH2 voltages.
4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1–A20 = X
5. See Table 5 for device IDs.
6. Refer to Table 6 for valid DIN during a write operation.
7. Command writes for block erase or byte program are only executed when VPP = VPPH1 or VPPH2.
8. To program or erase the lockable blocks, hold WP# at VIH. See Section 3.3.
9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
15
PRELIMINARY
3.1.1 READ
The flash memory has three read modes available:
read array, read identifier, and read status. These
modes are accessible independent of the VPP
voltage. The appropri ate read mode com m and must
be issued to the CUI to enter the corresponding
mode. Upon initial device power-up or after exit
from deep power-down mode, the device
automatically defaults to read array mode.
CE# and OE# must be driven active to obtain data
at the outputs. CE# is the device selection control;
when active it enables the flash memory device.
OE# is the data output (DQ0–DQ7) control and it
drives the selected memory data onto the I/O bus.
For all read modes, WE# and RP# must be at VIH.
Figure 14 illustrates a read cycle.
3.1.2 OUTPUT DISABLE
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0–DQ7 are
placed in a high-impedance state.
3.1.3 STANDBY
Deselecting the device by bringing CE# to a logic-
high level (V IH) places the devic e in standby mode,
which substantially reduces device power
consumption. In standby, outputs DQ0–DQ7 are
placed in a high-impedance state independent of
OE#. If deselected during program or erase
operation, the device continues to consume active
power until the program or erase operation is
complete.
3.1.4 DEEP POWER-DOWN/RESET
RP# at VIL initiates the deep power-down mode,
sometimes referred to as reset mode.
From read mode, RP# going low for time tPLPH
accomplishes the following:
1. deselects the memory
2. places output drivers in a high-impedance
state
After return from power-down, a time tPHQV is
required until t he initial memory access out puts are
valid. A delay (tPHWL or tPHEL) is required after
return from power-down before a write sequence
can be initiated. After this wake-up interval, normal
operation is restored. The CUI resets to read array
mode, and the status register is set to 80H (ready).
If RP# is taken low for time tPLPH during a program
or erase operation, the operation will be aborted
and the memory contents at the aborted location
are no longer valid. After returning from an aborted
operation, time tPHQV or tPHWL/tPHEL must be met
before a read or write operation is initiated
respectively.
3.1.5 WRITE
A write is any command that alters the contents of
the memory array. There are two write commands:
Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User
Interface (CUI) initiates a sequence of internally-
timed functions that culminate in the completion of
the requested t ask (unl ess that operation is aborted
by either RP# being driven to VIL for of tPLRH or an
appropriate suspend command).
The Command User Interface does not occupy an
addressable memory location. Instead, commands
are written into the CUI using standard
microprocessor write timings when WE# and CE#
are low, OE# = VIH, and the proper address and
data (command) are presented. The command is
latched on the rising edge of the first WE# or CE#
pulse, whichever occurs first. Figure 15 illustrates a
write operation.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the
available commands. Appendix B provides detailed
informat ion on moving between t he different modes
of operation.
3.2 Modes of Operation
The flash memory has three read modes and two
write modes. The read modes are read array, read
identifier, and read status. The write modes are
program and block erase. Three additional mode
(erase suspend to program, erase suspend to read
and program suspend to read) are available only
during suspended operations. These modes are
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
16 PRELIMINARY
reached using the c ommands summariz ed in Table
4. A comprehensive chart showing the state
transitions is in Appendix B.
3.2.1 READ ARRAY
When RP# transitions from VIL (reset) to VIH, the
device will be in the read array mode and will
respond to the read control inputs (CE#, address
inputs, and OE#) without any commands being
written to the CUI.
When the device is in the read array mode, four
control signals must be controlled to obtain data at
the outputs.
•WE# must be logic high (VIH)
•CE# must be logic low (VIL)
•OE# must be logic low (VIL)
•RP# must be logic high (VIH)
In addition, the addres s of the des ired loc ation m ust
be applied to the address pins.
If the dev ice is not in read array mode, as would be
the case after a program or erase operation, the
Read Array command (FFH) must be written to the
CUI before array reads can take place.
Table 4. Command Codes and Descriptions
Code Device Mode Description
00 Invalid/
Reserved Unassigned commands that should not be used. Intel reserves the right to
redefine these codes for future functions.
FF Read Array Places the device in read array mode, such that array data will be output on the
data pins.
40 Program
Set-Up This is a two-cycle command. The first cycle prepares the CUI for a program
operation. The second cycle latches addresses and data information and
initiates the WSM to execute the Program algorithm. The flash outputs status
register data when CE# or OE# is toggled. A Read Array command is required
after programming to read array data. See Section 3.2.4.
10 Alternate
Program Set-Up (See 40H/Program Set-Up)
20 Erase
Set-Up Prepares the CUI for the Erase Confirm command. If the next command is not
an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the
status register to a “1,” (b) place the device into the read status register mode,
and (c) wait for another command. See Section 3.2.5.
D0 Program
Resume
Erase Resume/
Erase Confirm
If the previous command was an Erase Set-Up command, then the CUI will
close the address and data latches, and begin erasing the block indicated on the
address pins. If a program or erase operation was previously suspended, this
command will resume that operation.
During program/erase, the device will respond only to the Read Status Register,
Program Suspend/Erase Suspend commands and will output status register
data when CE# or OE# is toggled.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
17
PRELIMINARY
Table 4. Command Codes and Descriptions (Continued)
Code Device Mode Description
B0 Program
Suspend
Erase
Suspend
Issuing this command will begin to suspend the currently executing
program/erase operation. The status register will indicate when the operation
has been successfully suspended by setting either the program suspend (SR.2)
or erase suspend (SR.6) and the WSM Status bit (SR.7) to a “1” (ready). The
WSM will continue to idle in the SUSPEND state, regardless of the state of all
input control pins except RP#, which will immediately shut down the WSM and
the remainder of the chip if it is driven to VIL. See Sections 3.2.4.1 and 3.2.5.1.
70 Read Status
Register This command places the device into read status register mode. Reading the
device will output the contents of the status register, regardless of the address
presented to the device. The device automatically enters this mode after a
program or erase operation has been initiated. See Section 3.2.3.
50 Clear Status
Register The WSM can set the Block Lock Status (SR.1) , VPP Status (SR.3), Program
Status (SR.4), and Erase Status (SR.5) bits in the status register to “1,” but it
cannot clear them to “0.” Issuing this command clears those bits to “0.”
90 Intelligent
Identifier Puts the device into the intelligent identifier read mode, so that reading the
device will output the manufacturer and device codes (A0 = 0 for manufacturer,
A0 = 1 for device, all other address inputs are ignored). See Section 3.2.2.
NOTE:
See Appendix B for mode transition information.
3.2.2 READ INTELLIGENT IDENTIFIER
To read the manufacturer and device codes, the
device must be in read intelligent identifier mode,
which can be reached by writing the Intelligent
Identifier command (90H). Once in intelligent
identifier mode, A0 = 0 outputs the manufacturer’s
identification code and A0 = 1 outputs the device
code. See Tabl e 5 f or product signat ures. To return
to read array mode, write the Read A rray c ommand
(FFH). Table 5. Intelligent Identifier Table
Device ID
Size Mfr. ID -T
(Top Boot) -B
(
Bottom
Boot)
8-Mbit 89H D2H D3H
16-Mbit 89H D0H D1H
3.2.3 READ STATUS REGISTER
The device status register indicates when a
program or erase operation is complete, and the
success or failure of that operation. To read the
status register issue the Read Status Register
(70H) command to the CUI. This causes all
subsequent read operations t o output data from the
status register until another command is written to
the CUI. To return to reading from the array, issue
the Read Array (FFH) command.
The status register bits are output on DQ0–DQ7.
The contents of the status register are latched on
the falling edge of OE# or CE#. This prevents
possible bus errors which might occur if status
register contents change while being read. CE# or
OE# must be toggled with each subsequent status
read, or the status register will not indicate
completion of a program or erase operation.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
18 PRELIMINARY
When the WSM is active, bit 7 (SR.7) of the status
register will indicate the status of the WSM; the
remaining bits in the status register indicate
whether or not the WSM was successful in
performing the desired operation (see Table 7).
3.2.3.1 Clearing the Status Register
The WSM sets status bits 1 through 7 to “1,” and
clears bi ts 2, 6 and 7 to “0,” but cannot clear status
bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4,
and 5 indicate various error conditions, these bits
can only be cleared by the controlling CP U through
the use of the Clear Status Register (50H)
command. By allowing the system software to
control the resetting of these bits, several
operations m ay be perf ormed (suc h as c umulat iv ely
programming sev eral addresses or erasing multiple
blocks in sequence) before reading the status
register t o determ ine if an error occ urred duri ng t hat
series. Clear the Status Register before beginning
another command or sequence. Note, again, that
the Read Array command must be issued before
data can be read from the memory array.
3.2.4 PROGRAM MODE
Programming is executed using a two-write
sequence. The Program Setup command (40H) is
written t o the CUI fol lowed by a sec ond write which
specifies the address and data to be programmed.
The WSM will execute the following sequence of
internally timed events:
1. Program the desired bits of the addressed
memory.
2. Verify that the desired bits are sufficiently
programmed.
Programming of the memory results in specific bits
within an address l ocat ion being c hanged to a “0. ” If
the user attempts to program “1”s, there will be no
change of the memory cell contents and no error
occurs.
The status register indicates programming status:
while the program sequence is executing, bit 7 of
the status register is a “0.” The status register can
be polled by toggling either CE# or OE#. While
programming, the only valid commands are Read
Status Register, Program Suspend, and Program
Resume.
When programming is complete, the Program
Status bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status
register is set to indicate a program failure. If SR.3
is set then VPP was not wi thin accept abl e l i m i t s, and
the WSM di d not execute t he program command. If
SR.1 is set, a program operation was attempted to
a locked block and the operation was aborted.
The status register should be cleared before
attempting the next operation. Any CUI instruction
can follow after programming is completed;
however, to prevent inadvertent status register
reads, be sure to reset the CUI to read array mode.
3.2.4.1 Suspending and Resuming
Program
The Program Suspend command allows program
suspension in order to read data in other locations
of memory. Once the programming process starts,
writing the Program Suspend command to the CUI
requests that the WSM suspend the program
sequence (at predetermined points in the program
algorithm). The device continues to output status
register data after the Program Suspend command
is writ ten. Poll ing st atus regis ter bit s S R.7 and S R.2
will determine when the program operation has
been suspended (both will be set to “1”).
tWHRH1/tEHRH1 specify the program suspend latency.
A Read Array command can now be written to the
CUI to read data from blocks other than that which
is suspended. The only other valid commands,
while program is suspended, are Read Status
Register and Program Resume. After the Program
Resume command is written to the flash memory,
the WSM will continue with the program process
and status register bits SR.2 and SR.7 will
automatically be cleared. After the Program
Resume command is written, the device
automatically outputs status register data when
read (see Figure 7, Program Suspend/Resume
Flowchart). V PP must remain at the same VPP level
used for program while in program suspend mode.
RP# must also remain at VIH.
3.2.4.2 VPP Supply Voltage during
Program
VPP supply voltage considerations are outlined in
Section 3.4.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
19
PRELIMINARY
3.2.5 ERASE MODE
To erase a block , write t he Eras e Set -up and Erase
Confirm commands to the CUI, along with an
address identifying the block to be erased. This
address is latched internally when the Erase
Confirm command is issued. Block erasure results
in all bits withi n the block being s et to “1.” Only one
block can be erased at a time.
The WSM will execute the following sequence of
internally timed events to:
1. Program all bits within the block to “0.”
2. Verify that all bits within the block are
sufficiently programmed to “0.”
3. Erase all bits within the block to “1.”
4. Verify that all bits within the block are
sufficiently erased.
While the erase sequence is executing, bit 7 of the
status register is a “0.”
When the status register indicates that erasure is
complete, check the Erase Status bit to verify that
the erase operation was successful. If the Erase
operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase
error. If VPP was not within acceptable limits after
the Erase Confirm command was issued, the WS M
will not execute the erase sequence; instead, SR.5
of the status register is set to indicate an erase
error, and SR.3 is set to a “1” to identify that VPP
supply voltage was not within acceptable limits.
After an erase operation, clear the Status Register
(50H) before attempting the next operation. Any
CUI instruction can follow after erasure is
completed; however, to prevent inadvertent status
register reads, it is advisable to reset the flash to
read array after the erase is complete.
3.2.5.1 Suspending and Resuming Erase
Since an erase operation requires on the order of
seconds to complete, an Erase Sus pend command
is provided to allow erase-sequence interruption in
order to read data from or program data to another
block in memory. Once the erase sequence is
started, writing the Erase Suspend com mand to the
CUI requests that the WSM pause the erase
sequence at a predetermined point in the erase
algorithm. The status register will indicate if/when
the erase operation has been suspended.
A Read Array/Program command can now be
written to the CUI i n order to read/writ e data from/ to
blocks other than that which is suspended. The
Program command can subsequently be
suspended to read yet another array location. The
only val id commands while eras e is suspended are
Erase Resume, Program, Program Resume, Read
Array, or Read Status Register.
During erase suspend mode, the chip can be
placed in a ps eudo-standby mode by taking CE # to
VIH. This reduces active current consumption.
Erase Resum e cont inues the erase sequenc e when
CE# = VIL. As with the end of a standard erase
operation, the status register must be read and
cleared before the next instruction is issued.
3.2.5.2 VPP Supply Voltage during Erase
VPP supply voltage considerations are outlined in
Section 3.4.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
20 PRELIMINARY
Table 6. Command Bus Definitions
First Bus Cycle Second Bus Cycle
Command Notes Oper Addr Data Oper Addr Data
Read Array 5 Write X FFH
Intelligent Identifier 2,3,5 Write X 90H Read IA ID
Read Status Register 5 Write X 70H Read X SRD
Clear Status Register 5 Write X 50H
Write (Program) 4,5 Write X 40H Write PA PD
Alternate Write (Program) 4,5 Write X 10H Write PA PD
Block Erase/Confirm 5 Write X 20H Write BA D0H
Program/Erase Suspend 5 Write X B0H
Program/Erase Resume 5 Write X D0H
ADDRESS DATA
BA = Block Address SRD = Status Register Data
IA = Identifier Address ID = Identifier Data
PA = Program Address PD = Program Data
X = Don’t Care
NOTES:
1. Bus operations are defined in Table 3.
2. A0 = 0 for manufacturer code, A0 = 1 for device code.
3. Following the Intelligent Identifier command, two read operations access manufacturer and device codes.
4. Either 40H or 10H command is valid.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
21
PRELIMINARY
Table 7. Status Register Bit Definition
WSMS ESS ES PS VPPS PSS BLS R
76543210
NOTES:
SR.7 WRITE STATE MACHINE STATUS
1 = Ready (WSMS)
0 = Busy
Check Write State Machine bit first to determine
Byte Program or Block Erase completion, before
checking Program or Erase Status bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts
execution and sets both WSMS and ESS bits to
“1.” ESS bit remains set to “1” until an Erase
Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the
max. number of erase pulses to the block and is
still unable to verify successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Byte Program
0 = Successful Byte Program
When this bit is set to “1,” WSM has attempted
but failed to program a byte.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP Status bit does not provide continuous
indication of V
PP
level. The WSM interrogates V
PP
level only after the Program or Erase command
sequences have been entered, and informs the
system if VPP
has not been switched on. The V
PP
is also checked before the operation is verified by
the WSM. The V
PP
Status bit is not guaranteed to
report accurate feedback between VPPL
K
and
VPPH.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts
execution and sets both WSMS and PSS bits to
“1.” PSS bit remains set to “1” until a Program
Resume command is issued.
SR.1 = Block Lock Status
1 = Program/Erase attempted on locked
block; Operation aborted
0 = No operation to locked blocks
If a program or erase operation is attempted to
one of the locked blocks, this bit is set by the
WSM. The operation specified is aborted and the
device is returned to read status mode.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R) These bits are reserved for future use and should
be masked out when polling the Status Register.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
22 PRELIMINARY
Start
Write 40H
Program Address/Data
Read Status Register
SR.7 = 1?
Full Status
Check if Desired
Program Complete
Read Status Register
Data (See Above)
V
PP
Range Error
Programming Error
Attempted Program to
Locked Block - Aborted
Program Successful
SR.3 =
SR.4 =
SR.1 =
FULL STATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program or after a sequence of
program operations.
Write FFH after the last program operation to reset device to read array mode.
Bus Operation
Standby
Standby
SR.3 MUST be cleared, if set during a program attempt, before further
attempts are allowed by the Write State Machine.
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command,
in cases where multiple bytes are programmed before full status is checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
No
Yes
1
0
1
0
1
0
Command
Program Setup
Program
Comments
Data = 40H
Data = Data to Program
Addr = Location to Program
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command Comments
Check SR.3
1 = V
PP
Low Detect
Check SR.1
1 = Attempted Program to
Locked Block - Program
Aborted
Read Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Standby Check SR.4
1 = V
PP
Program Error
0605-07
Figure 6. Automated Byte Programming Flowchart
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
23
PRELIMINARY
Start
Write B0H
Read Status Register
Bus Operation
Write
Write
No
Command
Program Suspend
Read Array
Comments
Data = B0H
Addr = X
Data = FFH
Addr = X
SR.7 =
SR.2 =
1
Write FFH
Read Array Data
Program Completed
Done
Reading
Yes
Write FFHWrite D0H
Program Resumed Read Array Data
0
1
0
Read Read array data from block
other than the one being
programmed.
Read
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Standby Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby Check SR.2
1 = Program Suspended
0 = Program Completed
Write Program Resume Data = D0H
Addr = X
0605-08
Figure 7. Program Suspend/Resume Flowchart
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
24 PRELIMINARY
Start
Write 20H
Write D0H and
Block Address
Read Status Register
SR.7 =
Full Status
Check if Desired
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Bus Operation
Write
Write
Standby
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase or after a sequence of
block erasures.
Write FFH after the last write operation to reset device to read array mode.
Bus Operation
Standby
SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases
where multiple bytes are erased before full status is checked.
If an error is detected, clear the status register before attempting retry or other
error recovery.
No Yes
Suspend Erase
Suspend
Erase Loop
1
0
Standby
Command
Erase Setup
Erase Confirm
Comments
Data = 20H
Addr = Within Block to Be
Erased
Data = D0H
Addr = Within Block to Be
Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command Comments
Check SR.3
1 = V
PP
Low Detect
Check SR.4,5
Both 1 = Command Sequence
Error
Read Status Register
Data (See Above)
V
PP
Range Error
Command Sequence
Error
Block Erase
Successful
SR.3 =
SR.4,5 =
1
0
1
0
Block Erase ErrorSR.5 = 1
0
Attempted Erase of
Locked Block - Aborted
SR.1 = 1
0
Read Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Standby Check SR.5
1 = Block Erase Error
Standby Check SR.1
1 = Attempted Erase of
Locked Block - Erase Aborted
0605-09
Figure 8. Automated Block Erase Flowchart
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
25
PRELIMINARY
Start
Write B0H
Read Status Register
Bus Operation
Write
Write
No
Command
Erase Suspend
Read Array
Comments
Data = B0H
Addr = X
Data = FFH
Addr = X
SR.7 =
SR.6 =
1
Write FFH/40H
Read Array Data/
Program Array
Erase Completed
Done
Reading and/or
Programming
Yes
Write FFHWrite D0H
Erase Resumed Read Array Data
0
1
0
Read Read array data from block
other than the one being
erased.
Read
Status Register Data Toggle
CE# or OE# to Update Status
Register Data
Addr = X
Standby Check SR.7
1 = WSM Ready
0 = WSM Busy
Standby Check SR.6
1 = Erase Suspended
0 = Erase Completed
Write Erase Resume Data = D0H
Addr = X
Program Program data to block other
than the one being erased.
0605-010
Figure 9. Erase Suspend/Resume Flowchart
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
26 PRELIMINARY
3.3 Block Locking
The Smart 3 Advanced Boot Block flash memory
architecture features two hardware-lockable
parameter blocks so that the kernel code for the
system can be kept secure while other parameter
blocks are programmed or erased as necessary.
3.3.1 VPP = VIL FOR COMPLETE
PROTECTION
The VPP programming voltage can be held low for
complete write protection of all blocks in the flash
device. When VPP is below VPPLK, any program or
erase operation will result in a error, prompting the
corresponding Status Register bit (SR.3) to be set.
3.3.2 WP# = VIL FOR BLOCK LOCKING
The lockable blocks are locked when WP# = VIL;
any program or erase operation to a locked block
will result in an error, which will be reflected in the
status register. For top configuration, the top two
parameter blocks (blocks #37 and #38 for the
16-Mbit, and blocks #21 and #22 for the 8-M bit) are
lockable. For the bottom configuration, the bottom
two parameter blocks (blocks #0 and #1 for 8-/16-
Mbit) are lockable. Unlocked blocks can be
programmed or erased normally (unless VPP is
below VPPLK).
3.3.3 WP# = VIH FOR BLOCK UNLOCKING
WP# = VIH unlocks all lockable blocks.
These blocks can now be programmed or erased.
Note that RP# does not override WP# locking as in
previous B oot Block devices. WP# control s all bl ock
locking and VPP provides protection against
spurious wri tes. Tabl e 8 defines t he write protecti on
methods.
3.4 VPP Program and Erase
Voltages
Intel’s Smart 3 products provide in-system
programming and erase at 2.7V–3.6V VPP. For
customers requiring fast programming in their
manufacturing environment, Smart 3 Advanced
Boot Block includes an additional low-cost,
backward-compatible 12V programming feature.
The 12V VPP mode enhances programming
performance duri ng the short period of time typi cally
found in manufacturing processes; however, it is
not intended f or extended use. 12V may be applied
to VPP during program and erase operations for a
maximum of 1000 cycles on the main blocks and
2500 cycles on the parameter blocks. VPP may be
connected to 12V for a tot al of 80 hours maximum.
Stressing the device beyond these l i m i t s may caus e
permanent damage.
Table 8. Write Protection Truth Table for
Advanced Boot Block Flash Memory Family
VPP WP# RP# Write Protection
Provided
XXV
IL All Blocks Locked
VIL XV
IH All Blocks Locked
≥ VPPLK VIL VIH Lockable Blocks
Locked
≥ VPPLK VIH VIH All Blocks Unlocked
3.5 Power Consumption
While in operation, the flash device consumes
active power. However, Intel flash devices have a
three-tiered approach to power savings that can
significantly reduce overall system power
consumption. The Automatic Power Savings (APS)
feature reduces power consumption when the
device is idle. If the CE# is deasserted, the flash
enters its standby mode, where current
consumption is even lower. If RP# = VIL the flash
enters a deep power-down mode, where current is
at a minimum. The combination of these features
can minimize overall memory power consumption,
and therefore, overall system power consumption.
3.5.1 ACTIVE POWER
With CE# at a logic-low level and RP# at a logic-
high level, the devi ce i s in t he act iv e mode. Ref er to
the DC Charact eris tic s tables f or ICC c urrent v alues.
Active power is the largest contributor to overall
system power consumption. Minimizing the active
current could have a profound effect on system
power consumption, especially for battery-operated
devices.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
27
PRELIMINARY
3.5.2 AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings provides low-power
operation during active mode. Power Reduction
Control (PRC) circuitry allows the flash to put itself
into a low current state when not being accessed.
After data is read from the memory array, PRC
logic controls the device’s power consumption by
entering the APS mode where typical ICC current is
comparable to ICCS. The flash stays in this static
state with outputs valid until a new location is read.
APS reduces active current to standby current
levels for 2.7V–3.6V CMOS input levels.
3.5.3 STANDBY POWER
With CE# at a logic-high level (VIH) and the CUI in
read mode, the flash memory is in standby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
(DQ0–DQ7) are placed in a high-impedance state
independent of t he status of the OE# signal. If CE#
transitions to a logic-high level during erase or
program operations, the device will continue to
perform the operation and consume corresponding
active power until the operation is completed.
Syst em engi neers s hould analy ze t he break down of
standby time versus active time and quantify the
respective power consumption in each mode for
their specific application. This will provide a more
accurat e measure of applic ation-specif ic power and
energy requirements.
3.5.4 DEEP POWER-DOWN MODE
The deep power-down mode of the Smart 3
Advanced B oot Block products switches t he device
into a low power savings m ode, which i s especiall y
important for battery-based devices. This mode is
activated when RP# = VIL. (GND ± 0.2V).
During read modes, RP# going low de-selects the
memory and places the output drivers in a high
impedance state. Recovery from the deep power-
down state, requires a mini mum t ime equal t o t PHQV
(see AC Characteristics table).
During program or erase modes, RP# transitioning
low will abort the operation, but the memory
contents of the address being programmed or the
block being erased are no longer valid as the data
integrity has been compromised by the abort.
During deep power-down, all internal circuits are
switched to a low power savings mode (RP#
transit i oni ng to VIL or turni ng off power to the device
clears the status register).
3.6 Power-Up/Down Operation
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since the
device is indifferent as to which power supply, VPP
or VCC, powers-up first.
3.6.1 RP# CONNECTED TO SYSTEM
RESET
The use of RP# during system reset is important
with automated program/erase devices since the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization will not occur because the flash
memory may be providing status information
instead of array data. Int el recommends c onnecting
RP# to the system CPU RESET# signal to allow
proper CPU/flash initialization following system
reset.
System designers must guard against spurious
writes when VCC voltages are above VLKO and VPP
is activ e. Since both WE# and CE# mus t be low for
a command write, driving either signal to VIH will
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabled until RP# is brought to
VIH, regardless of the state of its control inputs. By
holding the device in reset (RP# connected to
system PowerGood) during power-up/down, invalid
bus conditions during power-up can be masked,
providing yet another level of memory protection.
3.6.2 VCC, VPP AND RP# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon
power-up, after exit f rom deep power-down mode or
after VCC transitions above VLKO (Lockout voltage),
is read array mode.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
28 PRELIMINARY
After any program or block erase operation is
complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read array mode
via the Read Array command if access to the flash
memory array is desired.
Refer to
AP-617 Additional Flash Data Protection
Using V
PP
, RP#, and WP#
for a circuit-level
description of how to implement the protection
schemes discussed in Section 3.5.
3.7 Power Supply Decoupling
Flash memory’s power switching characteristics
require careful device decoupling. System
designers should consider three supply current
issues:
1. Standby current levels (ICCS)
2. Active current levels (ICCR)
3. Transient peaks produced by falling and rising
edges of CE#.
Transient c urrent magnit udes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 µF ceramic
capacitor connected between each VCC and GND,
and between its VPP and GND. These high-
frequency, inherently low-inductance capacitors
should be placed as close as possible to the
package leads.
3.7.1 VPP TRACE ON PRINTED CIRCUIT
BOARDS
Designing for in-system writes to the flash memory
requires special consideration of the VPP power
supply trace by the printed circuit board designer.
The VPP pin suppl ies t he fl ash mem ory c ells c urrent
for programming and eras ing. VPP trace widt hs and
layout should be similar to that of VCC. Adequate
VPP supply traces, and decoupling capacitors
placed adjacent to the component, will decrease
spikes and overshoots.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
29
PRELIMINARY
4.0 ABSOLUTE MAXIMUM
RATINGS*
Extended Operating Temperature
During Read............................ –40°C to +85°C
During Block Erase
and Program............................ –40°C to +85°C
Temperature Under Bias ......... –40°C to +85°C
Storage Temperature................... –65°C to +125°C
Voltage on Any Pin
(except VCC, VCCQ and VPP)
with Respect to GND...............–0.5V to +5.0V1
VPP Voltage (for Block
Erase and Program)
with Respect to GND.........–0.5V to +13.5V1,2,4
VCC and VCCQ Supply Voltage
with Respect to GND...............–0.2V to +5.0V1
Output Short Circuit Current...................... 100 mA3
NOTICE: This datasheet contains preliminary information on
products in production. The specifications are subject to
change without notice. Verify with your local Intel Sales
office that you have the latest datasheet before finalizing a
design.
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage. These
are stress ratings only. Operation beyond the "Operating
Conditions" is not recommended and extended exposure
beyond the "Operating Conditions" may effect device
reliability.
NOTES:
1. Minimum DC voltage is –0.5V on input/output pins.
During transitions, this level may undershoot to –2.0V
for periods < 20 ns. Maximum DC voltage on
input/output pins is VCC + 0.5V which, during
transitions, may overshoot to VCC + 2.0V for periods <
20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0V
for periods < 20 ns.
3. Output shorted for no more than one second. No more
than one output shorted at a time.
4. VPP Program voltage is normally 2.7V–3.6V.
Connection to supply of 11.4V–12.6V can only be done
for 1000 cycles on the main blocks and 2500 cycles on
the parameter blocks during program/erase. VPP may
be connected to 12V for a total of 80 hours maximum.
See Section 3.4 for details.
5.0 OPERATING CONDITIONS (VCCQ = 2.7V–3.6V)
Table 9. Temperature and Voltage Operating Conditions4
Symbol Parameter Notes Min Max Units
TAOperating Temperature –40 +85 °C
VCC 2.7V–3.6V VCC Supply Voltage 1,4 2.7 3.6 Volts
VCCQ 2.7V–3.6V I/O Supply Voltage 1,2,4 2.7 3.6 Volts
VPP1 Program and Erase Voltage 4 2.7 3.6 Volts
VPP2 3 11.4 12.6 Volts
Cycling Block Erase Cycling 5 10,000 Cycles
NOTES:
1. See DC Characteristics tables for voltage range-specific specifications.
2. The voltage swing on the inputs, VIN is required to match VCCQ.
3. Applying VPP = 11.4V–12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum. See section 3.4
for details.
4. VCC, VCCQ and VPP1 must share the same supply when all three are between 2.7V and 3.6V.
5. For operating temperatures of –25°C– +85°C the device is projected to have a minimum block erase cycling of 10,000 to
30,000 cycles.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
30 PRELIMINARY
5.1 DC Characteristics: VCCQ = 2.7V–3.6V
Table 10. DC Characteristics
Sym Parameter Notes VCC = 2.7V–3.6V Unit Test Conditions
Typ Max
ILI Input Load Current 1 ± 1.0 µA VCC = VCCMax = VCC
Q
Max
VIN = VCCQ or GND
ILO Output Leakage Current 1 ± 10 µA VCC = VCCMax = VCC
Q
Max
VIN = VCCQ or GND
ICCS VCC Standby Current 1,7 20 50 µA CMOS INPUTS
VCC = VCCMax = VCCQMax
CE# = RP# = VCCQ
ICCD VCC Deep Power-Down
Current 1,7 1 10 µA CMOS INPUTS
VCC = VCCMax = VCC
Q
Max
VIN = VCC
Q
or GND
RP# = GND ± 0.2V
ICCR VCC Read Current 1,5,7 10 20 mA CMOS INPUTS
VCC = VCCMax = VCC
Q
Max
OE# = VIH , CE# =VIL
f = 5 MHz,
IOUT = 0 mA
Inputs = VIL or VIH
ICCW VCC Program Current 1,4,7 8 20 mA VPP = VPPH1 (3V)
Program in Progress
820mAV
PP = VPPH2 (12V)
Program in Progress
ICCE VCC Erase Current 1,4,7 8 20 mA VPP = VPPH1 (3V)
Erase in Progress
820mAV
PP = VPPH2 (12V)
Erase in Progress
ICCES VCC Erase Suspend
Current 1,2,4,7 20 50 µA CE# = VIH
Erase Suspend in Progress
ICCWS VCC Program Suspend
Current 1,2,4,7 20 50 µA CE# = VIH
Program Suspend in Progress
IPPD VPP Deep Power-Down
Current 1 0.2 5 µA RP# = GND ± 0.2V
IPPR VPP Read Current 1 2 ±50 µA VPP ≤ VCC
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
31
PRELIMINARY
Table 10. DC Characteristics (Continued)
Sym Parameter Notes VCC = 2.7V–3.6V Unit Test Conditions
Typ Max
IPPW VPP Program Current 1,4 15 40 mA VPP = VPPH1 (3V)
Program in Progress
10 25 mA VPP = VPPH2 (12V)
Program in Progress
IPPE VPP Erase Current 1,4 13 25 mA VPP = VPPH1 (3V)
Erase in Progress
825mAV
PP = VPPH2 (12V)
Erase in Progress
IPPES VPP Erase Suspend
Current 1,4 50 200 µA VPP = VPPH1 or VPPH2
Erase Suspend in Progress
IPPWS VPP Program Suspend
Current 1,4 50 200 µA VPP = VPPH1 or VPPH2
Program Suspend in Progress
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
32 PRELIMINARY
Table 10. DC Characteristics (Continued)
Sym Parameter Notes VCC = 2.7V–3.6V Unit Test Conditions
Min Max
VIL Input Low Voltage –0.4 0.4 V
VIH Input High Voltage VCCQ –
0.4V V
VOL Output Low Voltage 0.10 V VCC = VCCMin= VCCQMin
IOL = 100 µA
VOH Output High Voltage VCCQ –
0.1V VV
CC = VCCMin = VCCQMin
IOH = –100 µA
VPPLK VPP Lock-Out Voltage 3 1.5 V Complete Write Protection
VPPH1 V
PP
during Prog/Erase
Operations 3 2.7 3.6 V
VPPH2 3,6 11.4 12.6 V
VLKO VCC Program/Erase Lock
Voltage 1.5 V
VLKO2 VCCQ Program/Erase
Lock Voltage 1.2 V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25°C.
2. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is I
CCR. If the
device is read while in program suspend, current draw is ICCR.
3. Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPPH1 and VPPH2.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
6. Applying VPP = 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum. See Section 3.4
for details.
7. Includes the sum of VCC and VCCQ current.
Table 11. Capacitance (TA = 25°C, f = 1 MHz)
Sym Parameter Notes Typ Max Units Conditions
CIN Input Capacitance 1 6 8 pF VIN = 0V
COUT Output Capacitance 1 10 12 pF VOUT = 0V
NOTE:
1. Sampled, not 100% tested.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
33
PRELIMINARY
TEST POINTSINPUT OUTPUT
VCCQ
0.0
VCCQ
2VCCQ
2
0605-011
NOTE:
AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at VCCQ/2.
Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are when VCCQ=2.7V.
Figure 10. 2.7V–3.6V Input Range and Measurement Points
CL
Out
V
CCQ
Device
under
Test
R1
R2
0605-012
NOTE:
See table for component values.
Figure 11. Test Configuration
Test Configuration Component Values
for Worst Case Speed Conditions
Test Configuration CL (pF) R1 (Ω)R
2
(Ω)
2.7V Standard Test 50 25K 25K
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
34 PRELIMINARY
6.0 OPERATING CONDITIONS (VCCQ = 1.8V–2.2V)
Table 12. Temperature and VCC Operating Conditions
Symbol Parameter Notes Min Max Units
TAOperating Temperature –40 +85 °C
VCC1 2.7V–2.85V VCC Supply Voltage 1 2.7 2.85 Volts
VCC2 2.7V–3.3V VCC Supply Voltage 1 2.7 3.3 Volts
VCCQ 1.8V–2.2V I/O Supply Voltage 1,4 1.8 2.2 Volts
VPP1 Program and Erase Voltage 1 2.7 2.85 Volts
VPP2 1 2.7 3.3 Volts
VPP3 1,2 11.4 12.6 Volts
Cycling Block Erase Cycling 3 10,000 Cycles
NOTES:
1. See DC Characteristics tables for voltage range-specific specifications.
2. Applying VPP = 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter. VPP may be connected to 12V for a total of 80 hours maximum. See Section 3.4 for
details.
3. For operating temperatures of –25°C– +85°C the device is projected to have a minimum block erase cycling of 10,000 to
30,000 cycles.
4. The voltage swing on the inputs, VIN is required to match VCCQ.
6.1 DC Characteristics: VCCQ = 1.8V–2.2V
These tables are valid for the following power supply combinations only:
1. VCC1 and VCCQ and (VPP1 or VPP3)
2. VCC2 and VCCQ and (VPP2 or VPP3)
Wherever the input voltage VIN is mentioned, it is required that VIN matches the chosen VCCQ.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
35
PRELIMINARY
Table 13. DC Characteristics: VCCQ = 1.8V–2.2V
Sym Parameter Notes VCC1:
2.7V–2.85V
VCC2:
2.7V–3.3V
Unit Test Conditions
Typ Max
ILI Input Load Current 1 ± 1.0 µA VCC = VCCMax
VCCQ = VCC
Q
Max
VIN = VCCQ or GND
ILO Output Leakage Current 1 ± 10 µA VCC = VCC Max
VCCQ = VCC
Q
Max
VIN = VCCQ or GND
ICCS VCC Standby Current 1,7 20 50 µA CMOS INPUTS
VCC = VCC1 Max (2.7V–2.85V)
VCCQ = VCCQMax
CE# = RP# = VCCQ
150 250 µACMOS INPUTS
VCC = VCC2 Max (2.7V–3.3V)
VCCQ = VCCQMax
CE# = RP# = VCCQ
ICCD VCC Deep Power-Down
Current 1,7 1 10 µA CMOS INPUTS
VCC = VCCMax (VCC1 or VCC2)
VCCQ = VCC
Q
Max
VIN = VCC
Q
or GND
RP# = GND ± 0.2V
ICCR VCC Read Current 1,5,7 8 18 mA CMOS INPUTS
VCC = VCC1Max (2.7V–2.85V)
VCCQ = VCCQMax
OE# = VIH , CE# = VIL
f = 5 MHz, IOUT = 0 mA
Inputs = VIL or VIH
12 23 mA CMOS INPUTS
VCC = VCC2Max (2.7V–3.3V)
VCCQ = VCCQMax
OE# = VIH , CE# = VIL
f = 5 MHz, IOUT = 0 mA
Inputs = GND ± 0.2V or VCCQ
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
36 PRELIMINARY
Table 13. DC Characteristics: VCCQ = 1.8V–2.2V (Continued)
Sym Parameter Notes VCC1:
2.7V–2.85V
VCC2:
2.7V–3.3V
Unit Test Conditions
Typ Max
ICCW VCC Program Current 1,4,7 8 20 mA VPP = VPPH1 or VPPH2
Program in Progress
820mAV
PP = VPPH3 (12V)
Program in Progress
ICCE VCC Erase Current 1,4,7 8 20 mA VPP = VPPH1 or VPPH2
Erase in Progress
820mAV
PP = VPPH3 (12V)
Erase in Progress
ICCES VCC Erase Suspend
Current 1,2,4,7 20 50 µA CE# = VIH
Erase Suspend in Progress
ICCWS VCC Program Suspend
Current 1,2,4,7 20 50 µA CE# = VIH
Program Suspend in Progress
IPPD VPP Deep Power-Down
Current 1 0.2 5 µA RP# = GND ± 0.2V
IPPR VPP Read and Standby
Current 1 2 ±50 µA VPP ≤ VCC
IPPW VPP Program Current 1,4 15 40 mA VPP = VPPH1 or VPPH2
Program in Progress
10 25 mA VPP = VPPH3 (12V)
Program in Progress
IPPE VPP Erase Current 1,4 13 25 mA VPP = VPPH1 or VPPH2
Erase in Progress
825mAV
PP = VPPH3 (12V)
Erase in Progress
IPPES VPP Erase Suspend
Current 1 50 200 µA VPP = VPPH1 , VPPH2 , or VPPH3
Erase Suspend in Progress
IPPWS VPP Program Suspend
Current 1 50 200 µA VPP = VPPH1 , VPPH2 , or VPPH3
Program Suspend in Progress
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
37
PRELIMINARY
Table 13. DC Characteristics: VCCQ = 1.8V–2.2V (Continued)
Sym Parameter Notes VCC1:
2.7V–2.85V
VCC2:
2.7V–3.3V
Unit Test Conditions
Typ Max
VIL Input Low Voltage –0.2 0.2 V
VIH Input High Voltage VCCQ –
0.2V V
VOL Output Low Voltage –0.10 0.10 V VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
VOH Output High Voltage VCCQ –
0.1V VVCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
VPPLK VPP Lock-Out Voltage 3 1.5 V Complete Write Protection
VPPH1 VPP during Prog./Erase
Operations 3 2.7 2.85 V
VPPH2 3 2.7 3.3 V
VPPH3 3,6 11.4 12.6 V
VLKO1 VCC Program/Erase Lock
Voltage 1.5 V
VLKO2 VCCQ Program/Erase
Lock Voltage 1.2 V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25°C.
2. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is I
CCR. If the
device is read while in program suspend, current draw is ICCR.
3. Erases and Writes inhibited when VPP < VPPLK, and not guaranteed outside the valid VPP ranges of VPPH1,VPPH2. or VPPH3.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
6. Applying VPP = 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks. VPP may be connected to 12V for a total of 80 hours maximum. See Section 3.4
for details.
7 Includes the sum of VCC and VCCQ current
Table 14. Capacitance (TA = 25°C, f = 1 MHz)
Sym Parameter Notes Typ Max Units Conditions
CIN Input Capacitance 1 6 8 pF VIN = 0V
COUT Output Capacitance 1 10 12 pF VOUT = 0V
NOTE:
1. Sampled, not 100% tested.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
38 PRELIMINARY
TEST POINTSINPUT OUTPUT
VCCQ
0.0
VCCQ
2VCCQ
2
0605-011
NOTE:
AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at VCCQ/2.
Input rise and fall times (10%–90%) <10 ns. For worst case speed conditions VCCQ=1.8V.
Figure 12. 1.8V—2.2V Input Range and Measurement Points
CL
Out
V
CCQ
Device
under
Test
R1
R2
0605-012
NOTE:
See table for component values.
Figure 13. Test Configuration
Test Configuration Component Values
for Worst Case Speed Conditions
Test Configuration CL (pF) R1 (Ω)R
2
(Ω)
1.8V Standard Test 50 16.7K 16.7K
NOTE:
CL includes jig capacitance.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
39
PRELIMINARY
7.0 AC CHARACTERISTICS
AC Characteristics are applicable to both VCCQ ranges.
Table 15. AC Characteristics: Read Operations (Extended Temperature)
Load CL = 50 pF
# Symbol Parameter VCC 2.7V–3.6V4Units
Prod 120 ns 150 ns
Notes Min Max Min Max
R1 tAVAV Read Cycle Time 120 150 ns
R2 tAVQV Address to Output Delay 120 150 ns
R3 tELQV CE# to Output Delay 2 120 150 ns
R4 tGLQV OE# to Output Delay 2 65 65 ns
R5 tPHQV RP# to Output Delay 600 600 ns
R6 tELQX CE# to Output in Low Z 3 0 0 ns
R7 tGLQX OE# to Output in Low Z 3 0 0 ns
R8 tEHQZ CE# to Output in High Z 3 40 40 ns
R9 tGHQZ OE# to Output in High Z 3 40 40 ns
R10 tOH Output Hold from Address, CE#,
or OE# Change, Whichever
Occurs First
30 0 ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
3. Sampled, but not 100% tested.
4. See Test Configuration (Figures 11 and 13), 2.7V–3.6V and 1.8V–2.2V Standard Test component values.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
40 PRELIMINARY
Address Stable
Device and
Address Selection
IH
V
IL
V
ADDRESSES (A)
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
CE# (E)
OE# (G)
WE# (W)
DATA (D/Q)
IH
V
IL
V
RP#(P)
OL
V
OH
VHigh Z Valid Output
Data
Valid Standby
High Z
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
0605-015
Figure 14. AC Waveform: Read Operations
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
41
PRELIMINARY
Table 16. AC Characteristics: Write Operations (Extended Temperature)1
Load 50 pF
# Symbol Parameter VCC 2.7V–3.6V52.7V-3.6V5Units
Prod 120 ns 150 ns
Notes Min Max Min Max
W1 tPHWL
tPHEL
RP# High Recovery to
WE# (CE#) Going Low 600 600 ns
W2 tELWL
tWLEL
CE# (WE#) Setup to
WE# (CE#) Going Low 00ns
W3 tWLWH
tELEH
WE# (CE#) Pulse Width 90 90 ns
W4 tDVWH
tDVEH
Data Setup to WE#
(CE#) Going High 370 70 ns
W5 tAVWH
tAVEH
Address Setup to WE#
(CE#) Going High 290 90 ns
W6 tWHEH
tEHWH
CE# (WE#) Hold Time
from WE# (CE#) High 00ns
W7 tWHDX
tEHDX
Data Hold Time from
WE# (CE#) High 30 0 ns
W8 tWHAX
tEHAX
Address Hold Time from
WE# (CE#) High 20 0 ns
W9 tWHWL
tEHEL
WE# (CE#) Pulse Width
High 30 30 ns
W10 tVPWH
tVPEH
V
PP
Setup to WE# (CE#)
Going High 4 200 200 ns
W11 tQVVL VPP Hold from Valid SRD 4 0 0 ns
tLOCK Block Unlock / Lock
Delay 4, 6 200 200 ns
NOTES:
1. Read timing characteristics during program suspend and erase suspend are the same as during read-only operations.
Refer to AC Characteristics during read mode.
2. Refer to command definition table for valid AIN (Table6).
3. Refer to command definition table for valid DIN (Table 6).
4. Sampled, but not 100% tested.
5. See Test Configuration (Figure 11 and 13), 2.7V–3.6V and 1.8V–2.2V Standard Test component values.
6. Time tLOCK is required for successful locking and unlocking of all lockable blocks.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
42 PRELIMINARY
ADDRESSES [A]
CE#(WE#) [E(W)]
OE# [G]
WE#(CE#) [W(E)]
DATA [D/Q]
RP# [P]
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IL
V
IL
V
IN
D
IN
AIN
A
Valid
SRD
IN
D
IH
V
High Z
IH
V
IL
V
V [V]
PP
PPH
V
PPLK
VPPH
V1
2
WP# IL
V
IH
V
IN
D
AB C D E F
W8
W6
W9
W3
W4
W7
W1
W5
W2
W10 W11
(Note 1)
(Note 1)
0605-016
NOTES:
1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register
Data.
A. VCC Power-Up and Standby.
B. Write Program or Erase Setup Command.
C. Write Valid Address and Data (for Program) or Erase Confirm Command.
D. Automated Program or Erase Delay.
E. Read Status Register Data (SRD): reflects completed program/erase operation.
F. Write Read Array Command.
Figure 15. AC Waveform: Program and Erase Operations
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
43
PRELIMINARY
7.1 Reset Operations
IH
V
IL
V
RP# (P)
PLPH
t
IH
V
IL
V
RP# (P)
PLPH
t
(A) Reset during Read Mode
Abort
Complete PHQV
tPHWL
tPHEL
t
PHQV
tPHWL
tPHEL
t
(B) Reset during Program or Block Erase, <
PLPH
tPLR
H
t
PLRH
t
IH
V
IL
V
RP# (P)
PLPH
t
Abort
Complete PHQV
tPHWL
tPHEL
t
PLRH
t
Deep
Power-
Down
(C) Reset Program or Block Erase, >
PLPH
tPLRH
t0605-17
Figure 16. AC Waveform: Deep Power-Down/Reset Operation
Reset Specifications
VCC = 2.7–3.6V
Symbol Parameter Notes Min Max Unit
tPLPH RP# Low to Reset during Read
(If RP# is tied to VCC, this specification is not
applicable)
1,3 100 ns
tPLRH RP# Low to Reset during Block Erase or Program 2,3 22 µs
NOTES:
1. If tPLPH is < 100 ns the device may still RESET but this is not guaranteed.
2. If RP# is asserted while a block erase or byte program operation is not executing, the reset will complete within 100 ns.
3. Sampled but not 100% tested.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
44 PRELIMINARY
Table 17. Erase and Program Timings
VPP = 2.7V VPP = 12V
Sym Parameter Notes Typ1Max3Typ1Max3Unit
tBWPB Block Program Time
(Parameter) 2 .16 .48 .08 .24 sec
tBWMB Block Program Time (Main) 2 1.23 3.69 .58 1.74 sec
tWHQV1
tEHQV1
Program Time 2 17 165 8 185 µs
tWHQV2
tEHQV2
Block Erase Time (Parameter) 2 1 5.0 0.8 4.8 sec
tWHQV3
tEHQV3
Block Erase Time (Main) 2 1.8 8.0 1.1 7.0 sec
tWHRH1
tEHRH1
Program Suspend Latency 3 5 10 5 10 µs
tWHRH2
tEHRH2
Erase Suspend Latency 3 5 20 6 12 µs
NOTES:
1. Typical values measured at TA = +25°C and nominal voltages.
2. Excludes external system-level overhead.
3. Sampled but not 100% tested.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
45
PRELIMINARY
APPENDIX A
ORDERING INFORMATION
T E 2 8 F 1 6 0 B 3 T 1 2 0
Package
TE = 40-Lead TSOP
GT = 48-Ball µBGA* CSP
Product line designator
for all Intel Flash products
Access Speed (ns)
(120, 150)
Product Family
B3 = Smart 3 Advanced Boot Block
V
CC
= 2.7V - 3.6V
V
PP
= 2.7V - 3.6V or 11.4V - 12.6V
Device Density
016 = x8 (16-Mbit)
008 = x8 (8-Mbit)
T =
Top Blocking
B =
Bottom Blocking
VALID COMBINATIONS 40-Lead TSOP 48-Ball µBGA* CSP
Extended 16M TE28F016B3T120 GT28F016B3T120
TE28F016B3B120 GT28F016B3B120
TE28F016B3T150 GT28F016B3T150
TE28F016B3B150 GT28F016B3B150
Extended 8M TE28F008B3T120 GT28F008B3T120
TE28F008B3B120 GT28F008B3B120
TE28F008B3T150 GT28F008B3T150
TE28F008B3B150 GT28F008B3B150
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
46 PRELIMINARY
APPENDIX B
WRITE STATE MACHINE CURRENT/NEXT STATES
Command Input (and Next State)
Current
State SR.7 Data
When
Read
Read
Array
(FFH)
Program
Setup
(40/10H)
Erase
Setup
(20H)
Erase
Confirm
(D0H)
Program /
Erase
Susp.
(B0H)
Program /
Erase
Resume
(D0)
Read
Status
(70H)
Clear
Status
(50H)
Read ID
(90H)
Read Array “1” Array Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
Program
Setup “1” Status Pgm.1Program (Command input = Data to be programmed)
Program
(Not Comp.) “0” Status Program Pgm Susp.
to Status Program
Program
(Complete) “1” Status Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
Program
Suspend to
Status
“1” Status Prog.
Susp. to
Array
Program Suspend
to Array
Program Program
Susp. to
Array
Program Prog.
Susp. to
Status
Program Suspend to
Array
Program
Suspend to
Array
“1” Array Prog.
Susp. to
Array
Program Suspend
to Array Program Program
Susp. to
Array
Program Prog.
Susp. to
Status
Prog.
Susp. to
Array
Prog.
Susp. to
Array
Erase Setup “1” Status Erase Command Error Erase Erase
Cmd. Err. Erase Erase Command Error
Erase
Cmd. Error “1” Status Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
Erase
(Not Comp) “0” Status Erase Ers. Susp.
to Status Erase
Erase
(Complete) “1” Status Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
Erase
Suspend to
Status
“1” Status Erase
Susp. to
Array
Program
Setup Erase
Susp. to
Array
Erase Erase
Susp. to
Array
Erase Erase
Susp. to
Status
Erase Suspend
to Array
Erase. Susp.
to Array “1” Array Erase
Susp. to
Array
Program
Setup Erase
Susp. to
Array
Erase Erase
Susp. to
Array
Erase Erase
Susp. to
Status
Erase Suspend
to Array
Read Status “1” Status Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
Read
Identifier “1” ID Read
Array Program
Setup Erase
Setup Read Array Read
Status Read
Array Read
Identifier
1. You cannot program “1”s to the flash. Writing FFH following the Program Setup will initiate the internal program algorithm
of the WSM. Although the algorithm will execute, array data is not changed. The WSM returns to read status mode without
reporting any error. Assuming VPP > VPPLK writing a second FFH while in read status mode will return the flash to read
array mode.
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
47
PRELIMINARY
APPENDIX C
ACCESS TIME VS. CAPACITIVE LOAD
(tAVQV vs. CL)
Acce ss Time vs. Loa d Capacita nce
Der at in g C u rve
115
116
117
118
119
120
121
122
123
124
30 50 70 100
Load Capacitance(pF )
Access Time(ns)
Smart 3 Advanced Boot
Block
NOTE:
VCCQ = 2.7V
This chart shows a derating curve for device access time with respect to capacitive load. The value in the
DC characteristics section of the specification corresponds to CL = 50 pF.
NOTE:
1. Sampled, but not 100% tested
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
48 PRELIMINARY
APPENDIX D
ARCHITECTURE BLOCK DIAGRAM
Output
Multiplexer
8-Kbyte
Parameter Block
64-Kbyte
Main Block
64-Kbyte
Main Block
8-Kbyte
Parameter Block
Y-Gating/Sensing Write State
Machine Program/Erase
Voltage Switch
Data
Comparator
Status
Register
Identifier
Register
Data
Register
I/O Logic
Address
Latch
Address
Counter
X-Decoder
Y-Decoder
Power
Reduction
Control
Input Buffer
Output Buffer
GND
V
CC
V
PP
CE#
WE#
OE#
RP#
Command
User
Interface
Input Buffer
A
0
-A
20
DQ
0
-DQ
7
V
CCQ
WP#
ESMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
49
PRELIMINARY
APPENDIX E
ADDITIONAL INFORMATION(1,2)
Order Number Document/Tool
210830
1997 Flash Memory Databook
290580
Smart 3 Advanced Boot Block Word-Wide 4-Mbit (256K x 16), 8-Mbit (512K
x16), 16-Mbit (1024K x16) Flash Memory Family Datasheet
292172
AP-617 Additional Flash Data Protection Using V
PP
, RP# and WP#
NOTE:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.
