1
LTC4301
4301fb
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
Supply Independent Hot
Swappable 2-Wire Bus Buffer
Allows Bus Pull-Up Voltages Above or Below V
CC
Bidirectional Buffer* for SDA and SCL Lines
Increases Fanout
Prevents SDA and SCL Corruption During Live Board
Insertion and Removal from Backplane
Isolates Input SDA and SCL Line from Output
10kV Human Body Model ESD Protection
1V Precharge On All SDA and SCL Lines
Supports Clock Stretching, Arbitration and
Synchronization
High Impedance SDA, SCL Pins for V
CC
= 0V
CS Gates Connection from Input to Output
Compatible with I
2
C
TM
, I
2
C Fast Mode and SMBus
Standards (Up to 400kHz Operation)
Small 8-Pin MSOP and DFN (3mm × 3mm) Packages
Hot Board Insertion
Servers
Capacitance Buffer/Bus Extender
Desktop Computers
CompactPCI
TM
and ATCA Systems
The LTC
®
4301 supply independent, hot swappable, 2-wire
bus buffer allows I/O card insertion into a live backplane
without corruption of the data and clock busses. In addi-
tion, the LTC4301 allows the V
CC
, SDAIN and SCLIN pull-
up voltage and the SDAOUT and SCLOUT pull-up voltage
to be independent from each other. Control circuitry
prevents the backplane from being connected to the card
until a stop bit or a bus idle is present. When the connec-
tion is made, the LTC4301 provides bidirectional buffer-
ing, keeping the backplane and card capacitances isolated.
During insertion, the SDA and SCL lines are precharged to
1V to minimize bus disturbances. When driven low, the CS
input pin allows the part to connect after a stop bit or bus
idle occurs. Driving CS high breaks the connection be-
tween SCLIN and SCLOUT and between SDAIN and
SDAOUT. The READY output pin indicates that the back-
plane and card sides are connected together.
The LTC4301 is offered in 8-pin DFN (3mm × 3mm) and
MSOP packages.
10k10k
5V
BACK_SCL
BACKPLANE
CONNECTOR
CARD
BACK_SDA
3.3V
10k
5V
CS
CARD_SCL
CARD_SDA
SCLOUTSCLIN
SDAOUTSDAIN
GND
V
CC
LTC4301
READY
0.01µF
4301 TA01
10k 10k
STAGGERED CONNECTOR
Input-Output Connection
4301 TA01b
OUTPUT
SIDE
20pF
INPUT
SIDE
55pF
1µs/DIV
1V/DIV
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7032051.
2
LTC4301
4301fb
ORDER PART
NUMBER
V
CC
to GND ................................................. –0.3V to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT, CS ........ –0.3V to 7V
READY ........................................................ –0.3V to 6V
Operating Temperature Range
LTC4301C ............................................... 0°C to 70°C
LTC4301I............................................ 40°C to 85°C
LTC4301CDD
LTC4301IDD
T
JMAX
= 125°C, θ
JA
= 43°C/W
EXPOSED PAD (PIN 9)
PCB CONNECTION OPTIONAL
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
W
UU
DD PART
MARKING*
LBBY
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
Storage Temperature Range
MSOP ............................................... 65°C to 150°C
DFN .................................................. 65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
(Note 1)
ORDER PART
NUMBER
LTC4301CMS8
LTC4301IMS8
MS8 PART
MARKING*
LTBBW
TOP VIEW
9
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
5
6
7
8
4
3
2
1CS
SCLOUT
SCLIN
GND
V
CC
SDAOUT
SDAIN
READY
T
JMAX
= 125°C, θ
JA
= 200°C/W
1
2
3
4
CS
SCLOUT
SCLIN
GND
8
7
6
5
V
CC
SDAOUT
SDAIN
READY
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
The indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
V
CC
Positive Supply Voltage 2.7 5.5 V
I
CC
Supply Current V
CC
= 5.5V, V
SDAIN
= V
SCLIN
= 0V 4.5 6.2 mA
V
CC
= 5.5V, CS = 5.5V 300 µA
Start-Up Circuitry
V
PRE
Precharge Voltage SDA, SCL Floating 0.85 1.05 1.25 V
t
IDLE
Bus Idle Time 60 95 175 µs
RDY
VOL
READY Output Low Voltage I
PULLUP
= 3mA 0.4 V
V
THRCS
Connection Sense Threshold 0.8 1.4 2 V
I
CS
CS Input Current CS from 0V to V
CC
±0.1 ±1µA
V
THR
SDA, SCL Logic Input Threshold Voltage Rising Edge 1.55 1.8 2.0 V
V
HYS
SDA, SCL Logic Input Threshold Voltage (Note 3) 50 mV
Hysteresis
t
PLH
CS Delay On-Off 10 ns
READY Delay Off-On 10 ns
t
PHL
CS Delay Off-On 95 µs
READY Delay On-Off 10 ns
I
OFF
Ready Off Leakage Current ±0.1 µA
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
3
LTC4301
4301fb
The indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input-Output Connection
V
OS
Input-Output Offset Voltage 10k to V
CC
on SDA, SCL, V
CC
= 3.3V, 0 100 175 mV
SDA or SCL = 0.2V (Note 2)
C
IN
Digital Input Capacitance SDAIN, SDAOUT, (Note 3) 10 pF
SCLIN, SCLOUT
I
LEAK
Input Leakage Current SDA, SCL Pins ±5µA
V
OL
Output Low Voltage, Input = 0V SDA, SCL Pins, I
SINK
= 3mA, V
CC
= 2.7V 0 0.4 V
Timing Characteristics
f
I2C,MAX
I
2
C Maximum Operating Frequency (Note 3) 400 600 kHz
t
BUF
Bus Free Time Between Stop and Start (Note 3) 1.3 µs
Condition
t
HD,STA
Hold Time After (Repeated) Start Condition (Note 3) 100 ns
t
SU,STA
Repeated Start Condition Set-Up Time (Note 3) 0 ns
t
SU,STO
Stop Condition Set-Up Time (Note 3) 0 ns
t
HD,DATI
Data Hold Time Input (Note 3) 0 ns
t
SU,DAT
Data Set-Up Time (Note 3) 100 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and V
CC
voltage is shown in the Typical Performance
Characteristics section.
Note 3: Determined by design, not tested in production.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
ICC vs Temperature
Input – Output High to Low
Propagation Delay vs Temperature Connection Circuitry VOUT – VIN
50 25 0 25 50 75 100
TEMPERATURE (°C)
TIME (ns)
4301 G02
100
80
60
40
20
0
VCC = 2.7V
VCC = 3.3V
VCC = 5.5V
CIN = COUT = 100pF
RPULLUPIN = RPULLUPOUT = 10k
R
PULLUP
()
010,000 20,000 30,000 40,000
V
OUT
– V
IN
(mV)
4301 G03
300
250
200
150
100
50
0
V
CC
= 3.3V
V
CC
= 5V
T
A
= 25°C
V
IN
= 0V
TEMPERATURE (°C)
–80
ICC (mA)
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9 –40 020 100
4301 G01
–60 –20 40 60 80
VCC = 5.5V
VCC = 3.3V
VCC = 2.7V
4
LTC4301
4301fb
UU
U
PI FU CTIO S
CS (Pin 1): The connection sense pin is a 1.4V threshold
digital input pin. For normal operation CS is grounded.
Driving CS above the 1.4V threshold isolates SDAIN from
SDAOUT and SCLIN from SCLOUT and asserts READY
low.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL
on the bus backplane.
GND (Pin 4): Ground. Connect this pin to a ground plane
for best results.
READY (Pin 5): The READY pin is an open drain N-channel
MOSFET output which pulls down when CS is high or
when the start-up sequence described in the Operation
section has not been completed. READY goes high when
CS is low and a start-up is complete.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card.
V
CC
(Pin 8): Main Input Supply. Place a bypass capacitor
of at least 0.01µF close to V
CC
for best results.
Exposed Pad (Pin 9): Exposed pad may be left open or
connected to device ground.
BLOCK DIAGRA
W
CONNECT PRECHARGE
CONNECT
PRECHARGE
CONNECT
CONNECT
1
R2
200k
R1
200k
R3
200k
R4
200k
PRECHARGE
LOGIC PRECHARGE
CONNECT
95µs
DELAY
UVLO
1.4V
CS
1.8V
3SCLIN
6SDAIN
1.8V
CONNECT
CONNECT
7
SDAOUT
8
V
CC
2
SCLOUT
READY 5
GND
4301 BD
4
LTC4301 Supply Independent 2-Wire Bus Buffer
5
LTC4301
4301fb
OPERATIO
U
Start-Up
When the LTC4301 first receives power on its V
CC
pin,
either during power-up or live insertion, it starts in an
undervoltage lockout (UVLO) state, ignoring any activity
on the SDA or SCL pins until V
CC
rises above 2.5V (typical).
This is to ensure that the part does not try to function until
it has enough voltage to do so.
During this time, the 1V precharge circuitry is active and
forces 1V through 200k nominal resistors to the SDA and
SCL pins. Because the I/O card is being plugged into a live
backplane, the voltage on the backplane SDA and SCL
busses may be anywhere between 0V and V
CC
. Precharging
the SCL and SDA pins to 1V minimizes the worst-case
voltage differential these pins will see at the moment of
connection, therefore minimizing the amount of distur-
bance caused by the I/O card.
Once the LTC4301 comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the backplane side to indicate
the completion of a data transaction. When either one
occurs, the part also verifies that both the SDAOUT and
SCLOUT voltages are high. When all of these conditions
are met, the input-to-output connection circuitry is acti-
vated, joining the SDA and SCL busses on the I/O card with
those on the backplane.
Connection Circuitry
Once the connection circuitry is activated, the functional-
ity of the SDAIN and SDAOUT pins is identical. A low
forced on either pin at any time results in both pin voltages
being low. For proper operation, logic low input voltages
should be no higher than 0.4V with respect to the ground
pin voltage of the LTC4301. SDAIN and SDAOUT enter a
logic high state only when all devices on both SDAIN and
SDAOUT release high. The same is true for SCLIN and
SCLOUT. This important feature ensures that clock stretch-
ing, clock synchronization, arbitration and the acknowl-
edge protocol always work, regardless of how the devices
in the system are tied to the LTC4301.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms as
described here.
Input-to-Output Offset Voltage
When a logic low voltage, V
LOW1
, is driven on any of the
LTC4301’s data or clock pins, the LTC4301 regulates the
voltage on the other side of the device (call it V
LOW2
) at a
slightly higher voltage, as directed by the following
equation:
V
LOW2
= V
LOW1
+ 75mV + (V
CC
/R) • 70 (typical)
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV where V
CC
= 3.3V and the pull-up resistor R on SDAIN is 10k, then the
voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 =
108mV (typical). See the Typical Performance Character-
istics section for curves showing the offset voltage as a
function of V
CC
and R.
Propagation Delays
During a rising edge, the rise time on each side is deter-
mined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between
the two sides. This effect is displayed in Figure 1 for
V
CC
= 5V and a 10k pull-up resistor on each side (55pF on
one side and 20pF on the other). SDAIN and SCLIN are
pulled-up to 3.3V, and SDAOUT and SCLOUT are pulled-
up to 5V. Since the output side has less capacitance than
the input, it rises faster and the effective low to high
propagation delay is negative.
Figure 1. Input-Output Connection
4301 F01
OUTPUT
SIDE
20pF
INPUT
SIDE
55pF
1µs/DIV
1V/DIV
6
LTC4301
4301fb
OPERATIO
U
There is a finite high to low propagation delay through the
connection circuitry for falling waveforms. Figure 2 shows
the falling edge waveforms for the same pull-up resistors
and equivalent capacitance conditions as used in Figure 1.
An external N-channel MOSFET device pulls down the
voltage on the side with 55pF capacitance; LTC4301 pulls
down the voltage on the opposite side with a delay of 60ns.
This delay is always positive and is a function of supply
voltage, temperature and the pull-up resistors and equiva-
lent bus capacitances on both sides of the bus. The Typical
Performance Characteristics section shows high to low
propagation delay as a function of temperature and volt-
age for 10k pull-up resistors pulled-up to V
CC
and 100pF
equivalent capacitance on both sides of the part. Larger
output capacitances translate to longer delays (up to
150ns). Users must quantify the difference in propagation
times for a rising edge versus a falling edge in their
systems and adjust setup and hold times accordingly.
Figure 2. Input-Output Connection
High to Low Propagation Delay
Ready Digital Output
This pin provides a digital flag which is low when either CS
is high or the start-up sequence described earlier in this
section has not been completed. READY goes high when
CS is low and start-up is complete. The pin is driven by an
open-drain pull-down capable of sinking 3mA while hold-
ing 0.4V on the pin. Connect a resistor of 10k to V
CC
to
provide the pull-up.
Connection Sense
When the CS pin is driven above 1.4V with respect to the
LTC4301’s ground, the backplane side is disconnected
from the card side and the READY pin is internally pulled
low. When the pin voltage is low, the part waits for data
transactions on both the backplane and card sides to be
complete (as described in the Start-Up section) before
reconnecting the two sides. At this time the internal
pulldown on READY releases.
4301 F02
INPUT
SIDE
55pF
OUTPUT
SIDE
20pF
1V/DIV
20ns/DIV
7
LTC4301
4301fb
Live Insertion and Capacitance Buffering Application
Figures 3 illustrates applications of the LTC4301 with
different bus pull-up and V
CC
voltages, demonstrating its
ability to recognize and buffer bus data levels that are
above or below its V
CC
supply. All of these applications
take advantage of the LTC4301’s Hot Swap
TM
controlling,
capacitance buffering and precharge features. If the I/O
cards were plugged directly into the backplane without the
LTC4301 buffer, all of the backplane and card capaci-
tances would add directly together, making rise- and fall-
time requirements difficult to meet. Placing an LTC4301
APPLICATIO S I FOR ATIO
WUUU
on the edge of each card, however, isolates the card
capacitance from the backplane. For a given I/O card, the
LTC4301 drives the capacitance of everything on the card
and the backplane must drive only the capacitance of the
LTC4301, which is less than 10pF.
In most applications the LTC4301 will be used with a
staggered connector where V
CC
and GND will be long pins.
SDA and SCL are medium length pins to ensure that the
V
CC
and GND pins make contact first. This will allow the
precharge circuitry to be activated on SDA and SCL before
STAGGERED CONNECTOR
CS
SDAIN
SCLIN
VCC
GND
SDAOUT
SCLOUT
READY
10k 10k
LTC4301 CARD_SCL
CARD_SDA
0.01µF
10k
10k10k
BACKPLANE
CONNECTOR
5V
3.3V
SDA
SCL
STAGGERED CONNECTOR
CS
SDAIN
SCLIN
VCC
GND
SDAOUT
SCLOUT
READY
10k 10k
LTC4301 CARD_SCL
CARD_SDA
0.01µF
10k
10k10k
BACKPLANE
CONNECTOR
3.3V
5V
SDA
SCL
STAGGERED CONNECTOR
CS
SDAIN
SCLIN
VCC
GND
SDAOUT
SCLOUT
READY
4301 F03
10k
2.5V
10k
LTC4301 CARD_SCL
CARD_SDA
0.01µF
10k
10k10k
BACKPLANE
CONNECTOR
CARD
CARD
CARD
3.3V
5V
SDA
SCL
Figure 3. Typical Supply Independent Applications
Hot Swap is a trademark of Linear Technology Corporation.
8
LTC4301
4301fb
APPLICATIO S I FOR ATIO
WUUU
they make contact. CS is a short pin that is pulled up when
not connected. This is to ensure that the connection
between the backplane and the cards data and clock
busses is not enabled until the transients associated with
live insertion have settled.
Figure 4 shows the LTC4301 in a CompactPCI
TM
configu-
ration. The LTC4301 receives its V
CC
voltage from one of
the long “early power” pins. Because this power is not
switched, add a 5 to 10 resistor between V
CC
of the
LTC4301 and the connector V
CC
pin. Establishing early
power V
CC
ensures that the 1V precharge voltage is
present at SDAIN and SCLIN before they make contact.
The CS pin is driven by the CompactPCI’s BD_SEL# pin
using a short pin. This is to ensure that a connection is not
enabled until the transients associated with live insertion
have settled.
Figure 5 shows the LTC4301 in a PCI application where all
of the pins have the same length. In this case, an RC filter
circuit on the I/O card with a product of 10ms provides a
STAGGERED CONNECTOR
R13
10k
R12
10k
R14
10k
I/O PERIPHERAL CARD N
SDAIN
SCLIN
LTC4301
V
CC
GND
CARDN_SCL
CARDN_SDA
SDAOUT
SCLOUT
READY
SDAIN
SCLIN
V
CC
GND
SDAOUT
SCLOUT
READY
CS
SDAIN
SCLIN
V
CC
GND
SDAOUT
SCLOUT
READY
4301 F03
• • •
R9
10k
R8
10k
R10
10k
I/O PERIPHERAL CARD 2
LTC4301 CARD2_SCL
CARD2_SDA
STAGGERED CONNECTORSTAGGERED CONNECTOR
R5
10k
R4
10k
R6
10k
I/O PERIPHERAL CARD 1
LTC4301 CARD_SCL
CARD_SDA
R1
10k
V
CC
V
CC2
R2
10k
BACKPLANE
BACKPLANE
CONNECTOR
SDA
BD_SEL
SCL
0.01µF
R3
10k
5.1
5.1
5.1
R7
10k
R11
10k
0.01µF
0.01µF
CS
CS
Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4301 in a CompactPCI System
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.
9
LTC4301
4301fb
filter to prevent the LTC4301 from becoming activated
until the transients associated with live insertion have
settled. Connect the capacitor between V
CC
and CS, and
the resistor from CS to GND.
Repeater/Bus Extender Application
Users who wish to connect two 2-wire systems separated
by a distance can do so by connecting two LTC4301s
back-to-back as shown in Figure 6. The I
2
C specification
allows for 400pF maximum bus capacitance, severely
limiting the length of the bus. The SMBus specification
places no restriction on bus capacitance, but the limited
impedances of devices connected to the bus require
systems to remain small if rise- and fall-time specifica-
tions are to be met. Using the LTC4301 allows the capaci-
tance to be isolated into smaller sections, enabling the
APPLICATIO S I FOR ATIO
WUUU
R3
100k
SDAIN
SCLIN
VCC
GND
SDAOUT
SCLOUT
READY
CS
SDAIN
SCLIN
VCC
GND
SDAOUT
SCLOUT
READY
4301 F05
R9
10k
R8
10k
R10
10k
I/O PERIPHERAL CARD 2
LTC4301 CARD2_SCL
CARD2_SDA
R5
10k
R4
10k
I/O PERIPHERAL CARD 1
LTC4301 CARD_SCL
CARD_SDA
R1
10k
VCC
VCC2
R2
10k
BACKPLANE
BACKPLANE
CONNECTOR
SDA
SCL
0.01µF
0.1µF
0.01µF
R6
10k
R7
100k CS
0.1µF
system to meet rise- and fall-time requirements. In this
situation, the differential ground voltage between the two
systems may limit the allowed distance, because valid
logic low voltage with respect to the ground at one end of
the system may violate the allowed V
OL
specification with
respect to the ground at the other end. In addition, the
connection circuitry offset voltages of the back-to-back
LTC4301s add together, directly contributing to the same
problem.
Systems with Supply Voltage Droop
In large 2-wire systems, the V
CC
voltages seen by devices
at various points in the system can differ by a few hundred
millivolts or more. This situation is well modelled by a series
resistor in the V
CC
line as shown in Figure 7. For proper
operation, make sure that the V
CC(LTC4301)
is 2.7V.
Figure 5. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4301 in a PCI System
10
LTC4301
4301fb
APPLICATIO S I FOR ATIO
WUUU
R1
10k
R3
5.1k
R5
10k
R2
5.1k
V
CC2
V
CC1
V
CC4
V
CC3
R4
10k
R7
10k
R8
10k
CS
SDAIN
SCLIN
LTC4301
GND
V
CC
0.01µF
SDAOUT
SCLOUT
READY
SCL1
TO OTHER
SYSTEM 1
DEVICES
SDA1
0.01µF
R6
10k LTC4301
SDAIN
SCLIN
4301 F07
SCLOUT
SDAOUT
READY
LONG
DISTANCE
BUS
V
CC5
SCL2
SDA2
TO OTHER
SYSTEM 2
DEVICES
GND
V
CC
CS
R1
10k
VCC (BUS)
R2
10k
RDROP VCC
SDA
SCL 4301 F06
R4
10k
R5
10k
R3
10k
SDAIN
CS
SCLIN
LTC4301
VCC
GND
SCL2
SDA2
SDAOUT
SCLOUT
READY
0.01µF
Figure 6. Repeater/Bus Extender Application
Figure 7. System with VCC Voltage Droop
11
LTC4301
4301fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 1203
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE 0.25 ± 0.05
0.50 BSC
MSOP (MS8) 0204
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 ± 0.152
(.193 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
12
LTC4301
4301fb
© LINEAR TECHNOLOGY CORPORATION 2004
LT 0806 REV B • PRINTED IN THE USA
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
PART NUMBER DESCRIPTION COMMENTS
LTC1380/LTC1393 Single-Ended 8-Channel/Differential 4-Channel Analog Low R
ON
: 35 Single-Ended/70 Differential,
Mux with SMBus Interface Expandable to 32 Single or 16 Differential Channels
LTC1427-50 Micropower, 10-Bit Current Output DAC Precision 50µA ± 2.5% Tolerance Over Temperature,
with SMBus Interface 4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale
LTC1623 Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16-Channel Capability
LTC1663 SMBus Interface 10-Bit Rail-to-Rail Micropower DAC DNL < 0.75LSB Max, 5-Lead SOT-23 Package
LTC1694/LTC1694-1 SMBus Accelerator Improved SMBus/I
2
C Rise-Time,
Ensures Data Integrity with Multiple SMBus/I
2
C Devices
LT1786F SMBus Controlled CCFL Switching Regulator 1.25A, 200kHz, Floating or Grounded Lamp Configurations
LTC1695 SMBus/I
2
C Fan Speed Controller in ThinSOTTM 0.75 PMOS 180mA Regulator, 6-Bit DAC
LTC1840 Dual I
2
C Fan Speed Controller Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0
LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffer Isolates Backplane and Card Capacitances
LTC4301L Hot Swappable 2-Wire Bus Buffer Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN
with Low Voltage Level Translation
LTC4302-1/LTC4302-2 Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled
ThinSOT is a trademark of Linear Technology Corporation.
U
TYPICAL APPLICATIO
10k10k
5V
BACK_SCL
BACKPLANE
CONNECTOR
CARD
BACK_SDA
3.3V
10k
5V
CS
CARD_SCL
CARD_SDA
SCLOUTSCLIN
SDAOUTSDAIN
GND
V
CC
LTC4301
READY
0.01µF
4301 TA01
10k 10k
STAGGERED CONNECTOR
FROM
MICROPROCESSOR
Figure 8. System with Active Connection Control