0.5 Ω CMOS, Dual
2:1 MUX/SPDT Audio Switch
ADG884
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2008 Analog Devices, Inc. All rights reserved.
FEATURES
1.8 V to 5.5 V operation
Ultralow on resistance
0.28 Ω typical at 5 V supply
0.41 Ω maximum at 5 V supply
Excellent audio performance, ultralow distortion
0.1 Ω typical
0.15 Ω maximum RON flatness
High current carrying capability
400 mA continuous
600 mA peak current at 5 V supply
Rail-to-rail switching operation
Typical power consumption (<0.1 μW)
APPLICATIONS
Cellular phones
PDAs
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communications systems
FUNCTIONAL BLOCK DIAGRAM
05028-001
S
1A
S
1B
S
2A
S
2B
IN2
ADG884
D1
D2
NOTES:
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
IN1
Figure 1.
GENERAL DESCRIPTION
The ADG884 is a low voltage CMOS device containing two
independently selectable single-pole, double-throw (SPDT)
switches. This device offers ultralow on resistance of 0.41 Ω
over the full temperature range, making the part an ideal
solution for applications that require minimal distortion
through the switch. The ADG884 also has the capability of
carrying large amounts of current, typically 600 mA at 5 V
operation.
The ADG884 is available in a 10-ball, 2 mm × 1.5 mm WLCSP
package, a 10-lead LFCSP_WD package, and a 10-lead MSOP
package. These tiny packages make the ADG884 the ideal
solution for space-constrained applications.
When on, each switch conducts equally well in both directions
and has an input signal range that extends to the supplies. The
ADG884 exhibits break-before-make switching action.
PRODUCT HIGHLIGHTS
1. Single 1.8 V to 5.5 V operation.
2. High current handling capability (400 mA continuous
current).
3. 1.8 V logic compatible.
4. Low THD + N (0.01% typical).
5. Tiny 2 mm × 1.5 mm WLCSP, 3 mm × 3 mm 10-lead
LFCSP_WD, and 10-lead MSOP packages.
ADG884
Rev. C | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
ESD Caution...................................................................................6
Pin Configurations and Function Descriptions ............................7
Typical Performance Characteristics ..............................................8
Test Circuits ..................................................................................... 11
Terminology .................................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
6/08—Rev. B to Rev. C
Changes to Temperature Range ........................................ Universal
Changes to Product Highlights ....................................................... 1
Changes to Table 4 ............................................................................ 6
Updated Outline Dimensions ....................................................... 14
Changes to the Ordering Guide .................................................... 15
7/06—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Changes to Table 4 ............................................................................ 6
Changes to the Ordering Guide .................................................... 15
6/05—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
10/04—Revision 0: Initial Version
ADG884
Rev. C | Page 3 of 16
SPECIFICATIONS
VDD = 5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter 25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
On Resistance, RON 0.28 Ω typ VDD = 4.5 V, VS = 0 V to VDD, IS = 100 mA
0.37 0.41 Ω max See Figure 18
On-Resistance Match Between Channels, ∆RON 0.01 Ω typ VDD = 4.5 V, VS = 2 V, IS = 100 mA
0.035 0.05 Ω max
On-Resistance Flatness, RFLAT (On) 0.1 Ω typ VDD = 4.5 V, VS = 0 V to VDD
0.13 0.15 Ω max IS = 100 mA
LEAKAGE CURRENTS VDD = 5.5 V
Source Off Leakage, IS (Off) ±0.2 nA typ VS = 0.6 V/4.5 V, VD = 4.5 V/0.6 V; see Figure 19
Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 0.6 V or 4.5 V; see Figure 20
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH
±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ
DYNAMIC CHARACTERISTICS1
tON 42 ns typ RL = 50 Ω, CL = 35 pF
50 53 ns max VS = 3 V/0 V; see Figure 21
tOFF 15 ns typ RL = 50 Ω, CL = 35 pF
20 21 ns max VS = 3 V; see Figure 21
Break-Before-Make Time Delay, tBBM 16 ns typ RL = 50 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 1.5 V; see Figure 22
Charge Injection 125 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24
Channel-to-Channel Crosstalk −120 dB typ S1A to S2A/S1B to S2B, RL = 50 Ω, CL = 5 pF,
f = 100 kHz; see Figure 27
−60 dB typ
S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF,
f = 100 kHz; see Figure 25
Total Harmonic Distortion, THD + N 0.017 % typ RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p
Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; see Figure 26
−3 dB Bandwidth 18 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26
CS (Off) 103 pF typ
CD, CS (On) 295 pF typ
POWER REQUIREMENTS VDD = 5.5 V
IDD 0.003 μA typ Digital inputs = 0 V or 5.5 V
1 μA max
1 Guaranteed by design, not production tested.
ADG884
Rev. C | Page 4 of 16
VDD = 3.4 V to 4.2 V; GND = 0 V, unless otherwise noted.
Table 2.
Parameter 25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
On Resistance, RON 0.33 Ω typ VDD = 3.4 V, VS = 0 V to VDD, IS = 100 mA
0.4 0.47 Ω max See Figure 18
On-Resistance Match Between Channels, ∆RON 0.013 Ω typ VDD = 3.4 V, VS = 2 V, IS = 100 mA
0.042 0.065 Ω max
On-Resistance Flatness, RFLAT (On) 0.13 Ω typ VDD = 3.4 V, VS = 0 V to VDD
0.155 0.175 Ω max IS = 100 mA
LEAKAGE CURRENTS VDD = 4.2 V
Source Off Leakage, IS (Off) ±0.2 nA typ VS = 0.6 V/3.9 V, VD = 3.9 V/0.6 V; see Figure 19
Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 0.6 V or 3.9 V; see Figure 20
DIGITAL INPUTS
Input High Voltage, VINH 2.0 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH
±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ
DYNAMIC CHARACTERISTICS1
tON 42 ns typ RL = 50 Ω, CL = 35 pF
50 54 ns max VS = 1.5 V/0 V; see Figure 21
tOFF 15 ns typ RL = 50 Ω, CL = 35 pF
21 24 ns max VS = 1.5 V; see Figure 21
Break-Before-Make Time Delay, tBBM 17 ns typ RL = 50 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 1.5 V; see Figure 22
Charge Injection 100 pC typ VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 23
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24
Channel-to-Channel Crosstalk −120 dB typ S1A to S2A/S1B to S2B, RL = 50 Ω, CL = 5 pF,
f = 100 kHz; see Figure 27
−60 dB typ
S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF,
f = 100 kHz; see Figure 25
Total Harmonic Distortion, THD + N 0.01 % typ RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p
Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; see Figure 26
−3 dB Bandwidth 18 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26
CS (Off) 110 pF typ
CD, CS (On) 300 pF typ
POWER REQUIREMENTS VDD = 4.2 V
IDD 0.003 μA typ Digital inputs = 0 V or 4.2 V
1 μA max
1 Guaranteed by design, not production tested.
ADG884
Rev. C | Page 5 of 16
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter 25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 to VDD V
On Resistance, RON 0.4 Ω typ VDD = 2.7 V, VS = 0 V to VDD
0.51 0.61 Ω max IS = 100 mA; see Figure 18
On-Resistance Match Between Channels, ∆RON 0.02 Ω typ VDD = 2.7 V, VS = 0.6 V
0.07 0.1 Ω max IS = 100 mA
On-Resistance Flatness, RFLAT (On) 0.18 Ω typ VDD = 2.7 V, VS = 0 V to VDD
0.25 Ω max IS = 100 mA
LEAKAGE CURRENTS VDD = 3.6 V
Source Off Leakage, IS (Off) ±0.2 nA typ VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 19
Channel On Leakage, ID, IS (On) ±0.2 nA typ VS = VD = 0.6 V or 3.3 V; see Figure 20
DIGITAL INPUTS
Input High Voltage, VINH 1.3 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH
±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ
DYNAMIC CHARACTERISTICS1
tON 42 ns typ RL = 50 Ω, CL = 35 pF
56 62 ns max VS = 1.5 V/0 V; see Figure 21
tOFF 14 ns typ RL = 50 Ω, CL = 35 pF
19 21 ns max VS = 1.5 V; see Figure 21
Break-Before-Make Time Delay, tBBM 24 ns typ RL = 50 Ω, CL = 35 pF
10 ns min VS1 = VS2 = 1.5 V; see Figure 22
Charge Injection 85 pC typ VS = 1.25 V, RS = 0 Ω, CL = 1 nF; see Figure 23
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 24
Channel-to-Channel Crosstalk −120 dB typ S1A to S2A/S1B to S2B, RL = 50 V, CL = 5 pF,
f = 100 kHz; see Figure 27
−60 dB typ
S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF,
f = 100 kHz; see Figure 25
Total Harmonic Distortion, THD + N 0.03 % typ RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p
Insertion Loss −0.03 dB typ RL = 50 Ω, CL = 5 pF; see Figure 26
–3 dB Bandwidth 18 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 26
CS (Off) 110 pF typ
CD, CS (On) 300 pF typ
POWER REQUIREMENTS VDD = 3.6 V
IDD 0.003 μA typ Digital inputs = 0 V or 3.6 V
1 μA max
1 Guaranteed by design, not production tested.
ADG884
Rev. C | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +6 V
Analog Inputs,1 Digital Inputs −0.3 V to VDD + 0.3 V or 30 mA
(whichever occurs first)
Peak Current, S or D 600 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current, S or D 400 mA
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
10-Lead MSOP, Thermal Impedance
θJA 206°C/W
θJC 44°C/W
10-Ball WLCSP (4-Layer Board),
Thermal Impedance
θJA 120°C/W
10-Lead LFCSP_WD (4-Layer Board),
Thermal Impedance
θJA 76°C/W
θJC 13.5°C/W
Reflow Soldering (Pb-Free)
Peak Temperature 260(+ 0 or −5)°C
Time at Peak Temperature 10 sec to 40 sec
1 Overvoltages at IN, S, or D pins are clamped by internal diodes. Current
should be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
ADG884
Rev. C | Page 7 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD 1
S1A
2
D1
3
IN1
4
S1B
5
S2A
10
D2
9
IN2
8
S2B
7
GND
6
ADG884
TOP VIEW
(Not to Scale)
05028-002
Figure 2. LFCSP_WD and MSOP Pin Configuration
(SOLDER BALLS ON OPPOSITE SIDE)
S1B GND
IN1
D1
1
9
2
10
S1A V
DD
87
S2B
IN2
D2
3
4
5
S2A
6
ADG884
TOP VIEW
(Not to Scale)
ABC
1
2
3
4
05028-028
Figure 3. WLCSP Pin Configuration
Table 5. LFCSP_WD and MSOP Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2 S1A Source Terminal. Can be an input or output.
3 D1 Drain Terminal. Can be an input or output.
4 IN1 Logic Control Input.
5 S1B Source Terminal. Can be an input or output.
6 GND Ground (0 V) Reference.
7 S2B Source Terminal. Can be an input or output.
8 IN2 Login Control Input.
9 D2 Drain Terminal. Can be an input or output.
10 S2A Source Terminal. Can be an input or output.
Table 6. WLCSP Package Pin Function Description
WLCSP Package
Mnemonic Description
Ball Number Location
1 A1 S1B Source Terminal. Can be an input or output.
2 B1 GND Ground (0 V) Reference.
3 C1 S2B Source Terminal. Can be an input or output.
4 C2 IN2 Login Control Input.
5 C3 D2 Drain Terminal. Can be an input or output.
6 C4 S2A Source Terminal. Can be an input or output.
7 B4 VDD Most Positive Power Supply Potential.
8 A4 S1A Source Terminal. Can be an input or output.
9 A3 D1 Drain Terminal. Can be an input or output.
10 A2 IN1 Logic Control Input.
Table 7. ADG884 Truth Table
Logic (IN1/IN2) Switch 1A/Switch 2A Switch 1B/Switch 2B
0 Off On
1 On Off
ADG884
Rev. C | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
SIGNAL RANGE (V)
ON RESISTANCE (Ω)
0.30
0.25
0.20
0.15
0.10
0.05
0
012345
05028-004
4.5V
4.2V
5.5V
T
A
= 25°C
I
DS
= 100mA
5V
Figure 4. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V
SIGNAL RANGE (V)
ON RESISTANCE (Ω)
0.45
0.35
0.40
0.30
0.20
0.25
0.15
0.05
0.10
0
0 0.5 1.0 1.5 2.0 3.02.5
05028-005
2.7V
3.3V
T
A
= 25°C
I
DS
= 100mA
3V
Figure 5. On Resistance vs. VD (VS), VDD = 2.7 V to 3.3 V
SIGNAL RANGE (V)
ON RESISTANCE (Ω)
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
01 234
05028-006
5
+85°C
+25°C
–40°C
V
DD
= 5V
I
DS
= 100mA
Figure 6. On Resistance vs. VD (VS) for Different Temperature, VDD = 5 V
SIGNAL RANGE (V)
ON RESISTANCE (Ω)
0.45
0.40
0.35
0.30
0.25
0.20
0.10
0.05
0.15
0
0 0.5 1.0 1.5 2.0 2.5 3.0
05028-007
+85°C
+25°C
–40°C
V
DD
= 3.3V
I
DS
= 100mA
Figure 7. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3.3 V
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
5
4
3
2
0
1
–1
–3
–4
–2
–5
01020304050 8060 70
05028-008
I
D
, I
S
(ON)
I
S
(OFF)
V
DD
= 5V
Figure 8. Leakage Current vs. Temperature, VDD = 5 V
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
5
3
4
2
1
0
–1
010 6050403020 8070
05028-009
I
D
, I
S
(ON)
I
S
(OFF)
V
DD
= 4.2V
Figure 9. Leakage Current vs. Temperature, VDD = 4.2 V
ADG884
Rev. C | Page 9 of 16
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
4.0
2.5
3.0
3.5
1.5
2.0
0
0.5
1.0
–0.5
–1.0
010 6050403020 8070
05028-026
I
D
, I
S
(ON)
I
S
(OFF)
V
DD
= 3.3V
Figure 10. Leakage Current vs. Temperature, VDD = 3.3 V
V
S
(V)
Q
INJ
(pC)
600
400
500
300
200
100
0
0 0.5 1.0 1.5 3.53.02.52.0 4.54.0 5.0
05028-010
V
DD
= 5V
V
DD
= 4.2V
V
DD
= 3V
T
A
= 25°C
Figure 11. Charge Injection vs. Source Voltage
TEMPERATURE (°C)
TIME (ns)
50
40
30
20
10
0
–40 –20 0 4020 60 80
05028-011
t
ON
t
OFF
V
DD
= 5V
V
DD
= 3V
V
DD
= 5V
V
DD
= 3V
T
A
= 25°C
Figure 12. tON/tOFF Times vs. Temperature
FREQUENCY (MHz)
A
TTENU
A
TION (dB)
0
–3
–2
–1
–4
–5
–6
–7
–8
0.03 0.10 10.001.00 100.00
05028-022
T
A
= 25°C
V
DD
= 5V/4.2V/3V
Figure 13. Bandwidth, VDD = 5 V/4.2 V/3 V
FREQUENCY (MHz)
A
TTENU
A
TION (dB)
0
–30
–20
–10
–40
–50
–60
–70
–80
10 100 1M 10M1k 10k 100k 100M
05028-023
T
A
= 25°C
V
DD
= 5V/4.2V/3V
Figure 14. Off Isolation vs. Frequency
FREQUENCY (MHz)
A
TTENU
A
TION (dB)
0
–30
–20
–10
–40
–50
–60
–70
–80
100 1M 10M1k 10k 100k 100M
05028-024
T
A
= 25°C
V
DD
= 5V/3V
Figure 15. Crosstalk vs. Frequency
ADG884
Rev. C | Page 10 of 16
FREQUENCY (MHz)
A
TTENU
A
TION (dB)
0
–60
–40
–20
–80
–100
–120
–140
–160
10 100 1M 10M1k 10k 100k 100M
05028-025
T
A
= 25°C
V
DD
= 5V/4.2V/3V
Figure 16. AC PSRR
FREQUENCY (kHz)
THD + N (%)
0.10
0.04
0.05
0.06
0.07
0.08
0.09
0.03
0.02
0.01
0
0102030 70605040 9080 100
05028-027
V
DD
= 4.2V, 2V p-p
V
DD
= 5V, 3.5V p-p
V
DD
= 3V, 1.5V p-p
Figure 17. THD + N
ADG884
Rev. C | Page 11 of 16
TEST CIRCUITS
SD
V
S
R
ON
= V1/I
DS
I
DS
V1
05028-012
Figure 18. On Resistance
SD
V
S
V
D
I
S
(OFF) I
D
(OFF)
A A
05028-013
Figure 19. Off Leakage
SD
V
D
I
D
(ON)
NC A
05028-014
Figure 20. On Leakage
05028-015
D
IN
GND
RL
50Ω
C
L
35pF
V
DD
V
IN
V
OUT
V
S
V
DD
V
OUT
t
ON
t
OFF
50% 50%
90% 90%
0.1µF
S1B
S1A
Figure 21. Switching Times, tON, tOFF
V
OUT
V
IN
tBBM tBBM
50% 50%
80%
0V
D
IN
GND
RL
50Ω
C
L
35pF
V
DD
V
OUT
V
S
V
DD
0.1µF
S1B
S1A 80%
05028-016
Figure 22. Break-Before-Make Time Delay, tBBM
ADG884
Rev. C | Page 12 of 16
05028-017
IN
GND
V
DD
V
S
VIN
VOUT
1nF
VOUT
NC
SW ON
QINJ = CL × ΔVOUT
SW OFF
ΔVOUT
S1B
S1A
D
Figure 23. Charge Injection
05028-018
V
DD
V
S
V
DD
NC
NETWORK
ANALYZER
S1B S1A
GND
OFF ISOLATION = 20 LOG
D
50Ω50Ω
V
OUT
R
L
50Ω
0.1µF
V
OUT
V
S
Figure 24. Off Isolation
05028-020
V
OUT
V
DD
V
DD
GND
V
S
R
L
50Ω
R
L
50Ω
0.1µF
50Ω
S1A
D
S1B
C
HANNEL-TO-CHANNEL CROSSTALK = 20 LOG V
OUT
V
S
Figure 25. Channel-to-Channel Crosstalk (S1A to S1B)
NETWORK
ANALYZER
R
L
GND
V
DD
V
DD
V
OUT
V
S
S1AS1B
0.1µF
D
50Ω
50Ω
INSERTION LOSS = 20 LOG V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
05028-019
Figure 26. Bandwidth
05028-021
V
OUT
50Ω
50Ω
50Ω
V
S
NETWORK
ANALYZER
S2A
S2B
D1
D2 NC
NC
S1A
S1B
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG V
OUT
V
S
Figure 27. Channel-to-Channel Crosstalk (S1A to S2A)
ADG884
Rev. C | Page 13 of 16
TERMINOLOGY
IDD
Positive supply current.
VD (VS)
Analog voltage on Terminal D and Terminal S.
RON
Ohmic resistance between Terminal D and Terminal S.
RFLAT (On)
The difference between the maximum and minimum values of
on resistance as measured on the switch.
ΔRON
On resistance match between any two channels.
IS (Off)
Source leakage current with the switch off.
ID (Off)
Drain leakage current with the switch off.
ID, IS (On)
Channel leakage current with the switch on.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
CS (Off)
Off switch source capacitance. Measured with reference to
ground.
CD (Off)
Off switch drain capacitance. Measured with reference to
ground.
CD, CS (On)
On switch capacitance. Measured with reference to ground.
CIN
Digital input capacitance.
tON
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tBBM
On or off time measured between the 80% points of both
switches when switching from one to another.
Charge Injection
Measure of the glitch impulse transferred from the digital input
to the analog output during on/off switching.
Off Isolation
Measure of unwanted signal coupling through an off switch.
Crosstalk
Measure of unwanted signal that is coupled from one channel to
another as a result of parasitic capacitance.
−3 dB Bandwidth
Frequency at which the output is attenuated by 3 dB.
On Response
Frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
Ratio of the harmonics amplitude plus noise of a signal to the
fundamental.
ADG884
Rev. C | Page 14 of 16
OUTLINE DIMENSIONS
031208-B
TOP VIEW
10
1
6
5
0.30
0.23
0.18
EXPOSED
PAD
(BOTTOM VIEW)
PIN 1 INDEX
AREA
3.00
BSC SQ
SEATING
PLANE
0.80
0.75
0.70
0.20 REF
0.05 MAX
0.02 NOM
0.80 MAX
0.55 NOM
1.74
1.64
1.49
2.48
2.38
2.23
0.50
0.40
0.30
0.50 BSC
PIN 1
INDICATOR
(R 0.20)
Figure 28. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm x 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-BA
0.23
0.08
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10 6
5
1
0.50 BSC
PIN 1
COPLANARITY
0.10
3.10
3.00
2.90
3.10
3.00
2.90
5.15
4.90
4.65
Figure 29. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ADG884
Rev. C | Page 15 of 16
SEATING
PLANE
0.50 BSC
BALL PITCH
1.56
1.50
1.44
0.26
0.22
0.18
0.11
0.09
0.07
0.36
0.32
0.28
0.63
0.57
0.51
BOTTOM
VIEW
(BALL SIDE UP)
2.06
2.00
1.94
TOP VIEW
(BALL SIDE DOWN)
A
123
B
C
D
BALL 1
IDENTIFIE
R
081607-A
Figure 30. 10-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding1
ADG884BRMZ2
−40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 S9C
ADG884BRMZ-REEL2
−40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 S9C
ADG884BRMZ-REEL72
−40°C to +85°C 10-Lead Mini Small Outline Package [MSOP] RM-10 S9C
ADG884BCPZ-REEL2
−40°C to +85°C 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9 S9C
ADG884BCPZ-REEL72
−40°C to +85°C 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] CP-10-9 S9C
ADG884BCBZ-REEL2
−40°C to +85°C 10-Ball Wafer Level Chip Scale Package [WLCSP] CB-10 S9C
ADG884BCBZ-REEL72
−40°C to +85°C 10-Ball Wafer Level Chip Scale Package [WLCSP] CB-10 S9C
EVAL-ADG884EBZ2
Evaluation Board
1 Branding on this package is limited to three characters due to space constraints.
2 Z = RoHS Compliant Part.
ADG884
Rev. C | Page 16 of 16
NOTES
©2004–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05028-0-6/08(C)
