FQD1N60C - Fairchild - Product.Network

FQD1N60C / FQU1N60C

600V N-Ch annel MOSFET

General Description

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for high efficiency switched mode power supplies,

active power factor correction, electronic lamp ballasts

based on half bridge topology.

Features

• 1A, 600V, RDS(on) = 11.5Ω @VGS = 10 V

• Low gate charge ( typical 4.8nC)

• Low Crss ( typical 3.5 pF)

• Fast switching

• 100% avalanche tested

• Improved dv/dt capability

Absolute Maximum Ratin gs TC = 25°C unless otherwise noted

Thermal Characteri stics

* When mounted on the minimum pad size recommended (PCB Mount)

Symbol Parameter FQD1N60C / FQU1N60C Units

VDSS Drain-Source Voltage 600 V

IDDrain Current - Continuous (TC = 25°C) 1A

- Continuous (TC = 100°C) 0.6 A

IDM Drain Current - Pulsed (Note 1) 4A

VGSS Gate-Source Voltage ± 30 V

EAS Single Pulsed Avalanche Energy (Note 2) 33 mJ

IAR Avalanche Current (Note 1) 1A

EAR Repetitive Avalanche Energy (Note 1) 2.8 mJ

dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns

Power Dissipation (TA = 25°C)* 2.5 W

Power Dissipation (TC = 25°C) 28 W

- Derate above 25°C 0.22 W/°C

TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C

Maximum lead temperature for soldering purposes,

1/8" from case for 5 seconds 300 °C

Symbol Parameter Typ Max Units

RθJC Thermal Resistance, Junction-to-Case -- 4.53 °C/W

RθJA Thermal Resistance, Junction-to-Ambient* -- 50 °C/W

RθJA Thermal Resistance, Junction-to-Ambient -- 110 °C/W

I-PAK

FQU Series

D-PAK

FQD Series GSD

January 2009

QFET

Rev. A1, January 2009

• RoHS Compliant

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FQD1N60C / FQU1N60C

Electrical Characteristics TC = 25°C unless otherwise noted

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 59 mH, IAS = 1.1 A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C

3. ISD ≤ 1.1 A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Symbol Parame ter Test Condit ions Min Typ Max Units

Off Characteristics

BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA600 -- -- V

∆BVDSS

/ ∆TJ

Breakdown Voltage Temperature

Coefficient ID = 250 µA, Referenced to 25°C -- 0.6 -- V/°C

IDSS Zero Gate Voltage Drain Current VDS = 600 V, VGS = 0 V -- -- 1 µA

VDS = 480 V, TC = 125°C -- -- 10 µA

IGSSF Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA

IGSSR Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA

On Characteri st ics

VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA2.0 -- 4.0 V

RDS(on) Static Drain-Source

On-Resistance VGS = 10 V, ID = 0.5 A -- 9.3 11.5 Ω

gFS Forward Transconductance VDS = 40 V, ID = 0.5 A (Note 4) -- 0.75 -- S

Dynamic Characteristics

Ciss Input Capacitance VDS = 25 V, VGS = 0 V,

f = 1.0 MHz

-- 130 170 pF

Coss Output Capacitance -- 19 25 pF

Crss Reverse Transfer Capacitance -- 3.5 4.5 pF

Switching Characteristics

td(on) Turn-On Delay Time VDD = 300 V, ID = 1.1 A,

RG = 25 Ω

(Note 4, 5)

-- 7 24 ns

trTurn-On Rise Time -- 21 52 ns

td(off) Turn-Off Delay Time -- 13 36 ns

tfTurn-Off Fall Time -- 27 64 ns

QgTotal Gate Charge VDS = 480 V, ID = 1.1 A,

VGS = 10 V

(Note 4, 5)

-- 4.8 6.2 nC

Qgs Gate-Source Charge -- 0.7 -- nC

Qgd Gate-Drain Charge -- 2.7 -- nC

Drain-Source Di ode Characteristics and Maximum Ratings

ISMaximum Continuous Drain-Source Diode Forward Current -- -- 1 A

ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 4 A

VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.5 A -- -- 1.4 V

trr Reverse Recovery Time VGS = 0 V, IS = 1.1 A,

dIF / dt = 100 A/µs (Note 4)

-- 190 -- ns

Qrr Reverse Recovery Charge -- 0.53 -- µC

Rev. A1. January 2009

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FQD1N60C / FQU1N60C

Typical Characteristics

Figure 5. Capacitance C haracterist i cs Figure 6. Gate Charge Characteris tics

10-1 100101

10-2

10-1

100

VGS

Top : 15.0 V

10.0 V

8.0 V

7.0 V

6.5 V

6.0 V

5.5 V

5.0 V

Bottom : 4.5 V

$ Notes :

1. 250%s Pulse Test

2. TC

= 25&

ID, Drain Current [A]

VDS, Drain-Source Voltage [V]

246810

10-1

100

150oC

25oC

-55oC

$ Notes :

1. VDS = 40V

2. 250%s Pulse Test

ID, Drain Current [A]

VGS, Gate-Source Voltage [V]

0.0 0.5 1.0 1.5 2.0 2.5

VGS = 20V

VGS = 10V

$ Note : T

J = 25&

RDS(ON) ['],

Drain-Source On-Resistance

ID, Drain Current [A]

0.2 0.4 0.6 0.8 1.0 1.2 1.4

10-1

100

150

℃

※

Notes :

1. VGS = 0V

2. 250

s Pulse Test

℃

IDR, Reve rse Dr ain C urren t [A]

VSD, Source-Drain vo ltage [V]

0123456

VDS = 300V

VDS = 120V

VDS = 480V

$ Note : ID

= 1A

VGS, Gate-Source Voltage [V]

G, Total Gate Charge [nC]

10-1 100101

100

150

200

250 C

iss = Cgs + Cgd (Cds = shorted)

oss = Cds + Cgd

rss = Cgd

Notes ;

1. VGS = 0 V

2. f = 1 MHz

Crss

Coss

Ciss

Capacitance [pF]

VDS, Drain-Source Voltage [V]

Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Character i st ics

Figure 3. On-Resistanc e Variation vs

Drain Current and Gate Voltage Figure 4 . Bod y Diode Fo rwa rd Voltage

Variation with Source Current

and Temperature

Rev. A1, October 2008

Rev. A1, January 2009

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FQD1N60C / FQU1N60C

Typical Characteristics (Continued)

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

vs Case Temperature

-100 -50 0 50 100 150 200

0.8

0.9

1.0

1.1

1.2

Notes :

1. VGS = 0 V

2. ID

= 250 %A

BV DSS , (Normalized)

Drain-Source Breakdown Voltage

, Junction Temperature [o

-100 -50 0 50 100 150 200

0.0

0.5

1.0

1.5

2.0

2.5

3.0

$ Notes :

1. VGS = 10 V

2. ID

= 0.5 A

RDS( ON) , (Normalized)

Drain-Source On-Resistance

TJ, Junction Temperature [oC]

Figure 11. Transien t The rm al Respo nse Curve

10-5 10-4 10-3 10-2 10-1 100101

10-1

100

$ Notes :

1 . Z (JC(t) = 4.53 &/W M ax.

2 . D u ty F actor, D = t1/t2

3 . T JM - TC = PDM * Z(JC(t)

single pulse

D=0.5

0.02

0.2

0.05

0.1

0.01

Z(JC

(t), Thermal Response

t1, S q ua re W ave P uls e D u ratio n [s e c]

PDM

100101102103

10-2

10-1

100

101

10 ms

100 ms

1 ms

100 µs

Operation in This Area

is Limited by R DS( on)

$ Notes :

1. TC

= 25 oC

2. TJ = 150 oC

3. Single Pulse

, Drain Current [A]

VDS, Drain-Source Voltage [V]

25 50 75 100 125 150

0.0

0.2

0.4

0.6

0.8

1.0

1.2

ID, Drain Current [A]

TC, Case Temperature [&

]

Figu re 7. Br ea kdown Voltage Variatio n

vs Temperature Figure 8. On-Resistance Variation

vs Temperature

Rev. A1, October 2008

Rev. A1, January 2009

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FQD1N60C / FQU1N60C

Gate Charge Test Circuit & Waveform

Resistive Switching Test Circuit & Waveforms

Unclamped Inductive Switching Test Circuit & Waveforms

Charge

VGS

10V

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50K)

200nF

12V

Same Type

as DUT

Charge

VGS

10V

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50K)

200nF

12V

Same Type

as DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

10V

VDS

DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

10V

VDS

DUT

VGS

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

EAS =LI

AS2

----

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

Rev. A1, October 2008

Rev. A1, January 2009

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FQD1N60C / FQU1N60C

Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT

VDS

Driver

RGSame Type

as DUT

VGS • dv/dt controlled by RG

•I

SD controlled by pulse period

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pulse Period

--------------------------

DUT

VDS

Driver

RGSame Type

as DUT

VGS • dv/dt controlled by RG

•I

SD controlled by pulse period

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pulse Period

--------------------------

D = Gate Pulse Width

Gate Pulse Period

--------------------------

Rev. A1, October 2008

Rev. A1, January 2009

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FQD1N60C / FQU1N60C

Mechanical Dimensions

Rev. A1, January 2009

TO-252 (DPAK) (FS PKG Code 36)

1:1

Scale 1:1 on letter size paper

Dimensions shown below are in:

millimeters

Part Weight per unit (gram): 0.33

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FQD1N60C / FQU1N60C

Mechanical Dimensions

Dimensions in Millimeters

I - PAK

Rev. A1, January 2009

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Rev. I37

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As used herein:

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intended for surgical implant into the body or (b) support or sustain life,

and (c) whose failure to perform when properly used in accordance with

instructions for use provided in the labeling, can be reasonably

expected to result in a significant injury of the user.

2. A critical component in any component of a life support, device, or

system whose failure to perform can be reasonably expected to cause

the failure of the life support device or system, or to affect its safety or

effectiveness.

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Definition of Terms

Build it Now™

CorePLUS™

CorePOWER™

CROSSVOLT™

CTL™

Current Transfer Logic™

EcoSPARK®

EfficentMax™

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™

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Programmable Active Droop™

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QS™

Quiet Series™

RapidConfigure™

™

Saving our world, 1mW /W /kW at a time™

SmartMax™

SMART START™

SPM®

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may change in any manner without notice.

Preliminary First Production

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make changes at any time without notice to improve the design.

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FQD1N60C / FQU1N60C

Mechanical Dimensions

FQD1N60C / FQU1N60C

Rev. A1. January 2009

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