PCS3P623Z05BG-16-TT - ON Semiconductor L.L.C.

August, 2011 − Rev. P2

1Publication Order Number:

PCS3P623Z05/D

PCS3P623Z05A,

PCS3P623Z05B,

PCS3P623Z09A,

PCS3P623Z09B

Product Preview

TIMINGSAFEt Peak EMI

Reduction IC

Description

PCS3P623Z05/09 is a versatile, 3.3 V Zero−delay buffer designed

to distribute Timing−Safe clocks with Peak EMI reduction.

PCS3P623Z05 is an eight−pin version, accepts one reference input

and drives out five low−skew Timing−Safe clocks. PCS3P623Z09

accepts one reference input and drives out nine low−skew

Timing−Safe clocks.

PCS3P623Z05/09 has a DLY_CTRL for adjusting the Input−Output

clock delay, depending upon the value of capacitor connected at this

pin to GND.

PCS3P623Z05/09 operates from a 3.3 V supply and is available in

two different packages, as shown in the ordering information table,

over commercial and Industrial temperature range.

Application

PCS3P623Z05/09 is targeted for use in Displays and memory

interface systems.

Features

•Clock Distribution with Timing−Safe Peak EMI Reduction

•Input Frequency Range: 20 MHz − 50 MHz

•Multiple Low Skew Timing−Safe Outputs:

PCS3P623Z05: 5 Outputs

PCS3P623Z09: 9 Outputs

•External Input−Output Delay Control Option

•Supply Voltage: 3.3 V ± 0.3 V

•Commercial and Industrial Temperature Range

•Packaging Information:

ASM3P623Z05: 8 pin SOIC, and TSSOP

ASM3P623Z09: 16 pin SOIC, and TSSOP

•True Drop−in Solution for Zero Delay Buffer, ASM5P2305A / 09A

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

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See detailed ordering and shipping information in the package

dimensions section on page 13 of this data sheet.

ORDERING INFORMATION

TSSOP−8

T SUFFIX

CASE 948AL

SOIC−8

S SUFFIX

CASE 751BD

TSSOP−16

T SUFFIX

CASE 948AN

SOIC−16

S SUFFIX

CASE 751BG

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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Figure 1. General Block Diagrams

PLL

CLKIN

DLY_CTRL

CLKOUT1

CLKOUT2

CLKOUT3

CLKOUT4

PCS3P623Z05A/B S2

Select

Input

Decoding

PLL

CLKIN MUX DLY_CTRL

CLKOUTA1

CLKOUTA2

CLKOUTA3

CLKOUTA4

CLKOUTB1

CLKOUTB2

CLKOUTB3

CLKOUTB4

PCS3P623Z09A/B

Spread Spectrum Frequency Generation

The clocks in digital systems are typically square waves

with a 50% duty cycle and as frequencies increase the edge

rates also get faster. Analysis shows that a square wave is

composed of fundamental frequency and harmonics. The

fundamental frequency and harmonics generate the energy

peaks that become the source of EMI. Regulatory agencies

test electronic equipment by measuring the amount of peak

energy radiated from the equipment. In fact, the peak level

allowed decreases as the frequency increases. The standard

methods of reducing EMI are to use shielding, filtering,

multi−layer PCBs, etc. These methods are expensive.

Spread spectrum clocking reduces the peak energy by

reducing the Q factor of the clock. This is done by slowly

modulating the clock frequency. The PCS3P623Z05/09 uses

the center modulation spread spectrum technique in which

the modulated output frequency varies above and below the

reference frequency with a specified modulation rate. With

center modulation, the average frequency is the same as the

unmodulated frequency and there is no performance

degradation.

Zero Delay and Skew Control

All outputs should be uniformly loaded to achieve Zero

Delay between input and output. Since the DLY_CTRL pin

is the internal feedback to the PLL, its relative loading can

adjust the input−output delay.

For applications requiring zero input−output delay, all

outputs, including DLY_CTRL, must be equally loaded.

Even if DLY_CTRL is not used, it must have a capacitive

load equal to that on other outputs, for obtaining zero

input−output delay.

Timing−Safe Technology

Timing−Safe technology is the ability to modulate a clock

source with Spread Spectrum technology and maintain

synchronization with any associated data path.

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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Pin Configuration for PCS3P623Z05A/B

DLY_CTRL

CLKOUT4

VDD

CLKOUT3

CLKIN

CLKOUT1

CLKOUT2

GND

PCS3P623Z05A/B

Table 1. PIN DESCRIPTION FOR PCS3P623Z05A/B

Pin # Pin Name Type Description

1CLKIN (Note 1) I External reference Clock input, 5 V tolerant input

2CLKOUT1 (Note 2) O Buffered clock output (Note 4)

3CLKOUT2 (Note 2) O Buffered clock output (Note 4)

4 GND P Ground

5CLKOUT3 (Note 2) O Buffered clock output (Note 4)

6 VDD P 3.3 V supply

7CLKOUT4 (Note 2) O Buffered clock output (Note 4)

8 DLY_CTRL O External Input−Output Delay control. This pin can be used as clock output (Note 4)

1. Weak pull down

2. Weak pull−down on all outputs

3. Weak pull−up on these Inputs

4. Buffered clock output is Timing−Safe

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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Pin Configuration for PCS3P623Z09A/B

DLY_CTRL

CLKOUTA4

CLKOUTA3

VDD

GND

CLKOUTB4

CLKOUTB3

PCS3P623Z09A/B

CLKIN

CLKOUTA1

CLKOUTA2

VDD

GND

CLKOUTB1

CLKOUTB2

Table 2. PIN DESCRIPTION FOR PCS3P623Z09A/B

Pin # Pin Name Pin Type Description

1CLKIN (Note 5) I External reference Clock input, 5 V tolerant input

2CLKOUTA1 (Note 6) O Buffered clock Bank A output (Note 8)

3CLKOUTA2 (Note 6) O Buffered clock Bank A output (Note 8)

4 VDD P 3.3 V supply

5 GND P Ground

6CLKOUTB1 (Note 6) O Buffered clock Bank B output (Note 8)

7CLKOUTB2 (Note 6) O Buffered clock Bank B output (Note 8)

8S2 (Note 7) I Select input, bit 2. See Select Input Decoding table for PCS3P623Z09 for more details

9S1 (Note 7) I Select input, bit 1. See Select Input Decoding table for PCS3P623Z09 for more details

10 CLKOUTB3 (Note 6) O Buffered clock Bank B output (Note 8)

11 CLKOUTB4 (Note 6) O Buffered clock Bank B output (Note 8)

12 GND P Ground

13 VDD P 3.3 V supply

14 CLKOUTA3 (Note 6) O Buffered clock Bank A output (Note 8)

15 CLKOUTA4 (Note 6) O Buffered clock Bank A output (Note 8)

16 DLY_CTRL (Note 6) O External Input−Output Delay control. This pin can be used as clock output.

5. Weak pull down

6. Weak pull−down on all outputs

7. Weak pull−up on these Inputs

8. Buffered clock output is Timing−Safe

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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Table 3. SELECT INPUT DECODING TABLE FOR PCS3P623Z09

S2 S1 CLKOUT A1 − A4 CLKOUT B1 − B4 DLY_CTRL (Note 9) Output Source PLL Shut−Down

0 0 Three−state Three−state Driven PLL N

0 1 Driven Three−state Driven PLL N

1 0 Driven Driven Driven Reference Y

1 1 Driven Driven Driven PLL N

9. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the

reference and the Output.

Table 4. SPREAD SPECTRUM CONTROL AND INPUT−OUTPUT SKEW TABLE

Frequency (MHz) Device Deviation (+%) Input−Output Skew (+TSKEW) (Note 10)

32 PCS3P623Z05A / 09A 0.125 0.125

PCS3P623Z05B / 09B 0.25 0.25

10.TSKEW is measured in units of the Clock Period.

Table 5. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Rating Unit

VDD Supply Voltage to Ground Potential −0.5 to +4.6 V

VIN DC Input Voltage (CLKIN) −0.5 to +7

TSTG Storage temperature −65 to +125 °C

TsMax. Soldering Temperature (10 sec) 260 °C

TJJunction Temperature 150 °C

TDV Static Discharge Voltage (As per JEDEC STD22− A114−B) 2 KV

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 6. OPERATING CONDITIONS

Parameter Description Min Max Unit

VDD Supply Voltage 3.0 3.6 V

TA Operating Temperature (Ambient Temperature) −40 +85 °C

CL Load Capacitance 30 pF

CIN Input Capacitance 7 pF

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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Table 7. ELECTRICAL CHARACTERISTICS

Parameter Description Test Conditions Min Typ Max Unit

VIL Input LOW Voltage (Note 11) 0.8 V

VIH Input HIGH Voltage (Note 11) 2.0 V

IIL Input LOW Current VIN = 0 V 50 mA

IIH Input HIGH Current VIN = VDD 100 mA

VOL Output LOW Voltage (Note 12) IOL = 8 mA 0.4 V

VOH Output HIGH Voltage (Note 12) IOH = −8 mA 2.4 V

IDD Supply Current Unloaded outputs 27 mA

Zo Output Impedance 23 W

11. CLKIN input has a threshold voltage of VDD/2

12.Parameter is guaranteed by design and characterization. Not 100% tested in production.

Table 8. SWITCHING CHARACTERISTICS

Parameter Test Conditions Min Typ Max Unit

Input Frequency 20 50 MHz

Output Frequency 30 pF load 20 50 MHz

Duty Cycle = (t2 / t1) * 100 (Notes 13, 14) Measured at VDD/2 40 50 60 %

Output Rise Time (Notes 13, 14) Measured between 0.8 V and 2.0 V 2.5 nS

Output Fall Time (Notes 13, 14) Measured between 2.0 V and 0.8 V 2.5 nS

Output−to−output skew (Notes 13, 14) All outputs equally loaded 250 pS

Delay, CLKIN Rising Edge to

CLKOUT Rising Edge (Note 14)

Measured at VDD/2 ±350 pS

Device−to−Device Skew (Note 14) Measured at VDD/2 on the CLKOUT

pins of the device

700 pS

Cycle−to−Cycle Jitter (Notes 13, 14) Loaded outputs ±250 pS

PLL Lock Time (Note 14) Stable power supply, valid clock

presented on CLKIN pin

1.0 mS

13.All parameters specified with 30 pF loaded outputs.

14.Parameter is guaranteed by design and characterization. Not 100% tested in production.

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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Switching Waveforms

Figure 2. Duty Cycle Timing

OUTPUT

VDD/2

VDD/2 VDD/2

Figure 3. All Outputs Rise/Fall Time

0 V

3.3 V

OUTPUT

2 V

0.8 V

t3t4

0.8 V

2 V

Figure 4. Output − Output Skew

OUTPUT

VDD/2

Figure 5. Input − Output Propagation Delay

OUTPUT

INPUT

VDD/2

Figure 6. Device − Device Skew

CLKOUT, Device 1

CLKOUT, Device 2

VDD/2

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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TSKEW represents input−output

skew when spread spectrum is ON

For example, TSKEW = ±0.125 for an Input

clock 12 MHz, translates in to

(1/12 MHz) * 0.125 = 10.41 nS

Figure 7. Input − Output Skew

TSKEW−TSKEW+

Input

Timing−Safe

Output

One clock cycle

N = 1

Figure 8. Test Circuit

GND

LOAD

CLKOUT

OUTPUT

+3.3 V

VDD

0.1 mF

Figure 9. Typical Example of Timing−Safe Waveform

Input

CLKOUT with SSOFF

Input

Timing−Safe CLKOUT

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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PACKAGE DIMENSIONS

TSSOP8, 4.4x3

CASE 948AL−01

ISSUE O

E1 E

TOP VIEW

SIDE VIEW END VIEW

L1 L

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

SYMBOL

MIN NOM MAX

0º 8º

0.05

0.80

0.19

0.09

0.50

2.90

6.30

4.30

0.65 BSC

1.00 REF

1.20

0.15

1.05

0.30

0.20

0.75

3.10

6.50

4.50

0.90

0.60

3.00

6.40

4.40

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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PACKAGE DIMENSIONS

SOIC−16, 150 mils

CASE 751BG−01

ISSUE O

TOP VIEW

PIN#1 IDENTIFICATION

ebA1 L

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

9.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

10.00

6.20

4.00

L0.40 1.27

1.35

9.90

6.00

3.90

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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PACKAGE DIMENSIONS

TSSOP16, 4.4x5

CASE 948AN−01

ISSUE O

PIN#1

IDENTIFICATION

θ1

TOP VIEW

SIDE VIEW END VIEW

SYMBOL

MIN NOM MAX

0º 8º

0.05

0.85

0.19

0.13

0.45

4.90

6.30

4.30

0.65 BSC

1.00 REF

1.10

0.15

0.95

0.30

0.20

0.75

5.10

6.50

4.50

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

PCS3P623Z05A, PCS3P623Z05B, PCS3P623Z09A, PCS3P623Z09B

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Table 9. ORDERING INFORMATION

Part Number (Note 15) Marking (Note 15) Package Type Temperature

PCS3P623Z0xyG−08−ST 3P623Z0xyG 8−pin 150−mil SOIC − TUBE, Green Commercial

PCS3I623Z0xyG−08−ST 3I623Z0xyG 8−pin 150−mil SOIC − TUBE, Green Industrial

PCS3P623Z0xyG−08−SR 3P623Z0xyG 8−pin 150−mil SOIC − TAPE & REEL, Green Commercial

PCS3I623Z0xyG−08−SR 3I623Z0xyG 8−pin 150−mil SOIC − TAPE & REEL, Green Industrial

PCS3P623Z0xyG−08−TT 3P623Z0xyG 8−pin 4.4−mm TSSOP − TUBE, Green Commercial

PCS3I623Z00xyG−08−TT 3I623Z0xyG 8−pin 4.4−mm TSSOP − TUBE, Green Industrial

PCS3P623Z0xyG−08−TR 3P623Z0xyG 8−pin 4.4−mm TSSOP − TAPE & REEL, Green Commercial

PCS3I623Z0xyG−08−TR 3I623Z0xyG 8−pin 4.4−mm TSSOP − TAPE & REEL, Green Industrial

PCS3P623Z0xyG−16−ST 3P623Z0xyG 16−pin 150−mil SOIC − TUBE, Green Commercial

PCS3I623Z0xyG−16−ST 3I623Z0xyG 16−pin 150−mil SOIC − TUBE, Green Industrial

PCS3P623Z0xyG−16−SR 3P623Z0xyG 16−pin 150−mil SOIC − TAPE & REEL, Green Commercial

PCS3I623Z0xyG−16−SR 3I623Z0xyG 16−pin 150−mil SOIC − TAPE & REEL, Green Industrial

PCS3P623Z0xyG−16−TT 3P623Z0xyG 16−pin 4.4−mm TSSOP − TUBE, Green Commercial

PCS3I623Z0xyG−16−TT 3I623Z0xyG 16−pin 4.4−mm TSSOP − TUBE, Green Industrial

PCS3P623Z0xyG−16−TR 3P623Z0xyG 16−pin 4.4−mm TSSOP − TAPE & REEL, Green Commercial

PCS3I623Z0xyG−16−TR 3I623Z0xyG 16−pin 4.4−mm TSSOP − TAPE & REEL, Green Industrial

15.x = 5 / 9; y = A / B

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PCS3P623Z05/D

TIMING SAFE is a trademark of Semiconductor Components Industries, LLC.

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