1
®
July 2004
HIP4083
80V, 300mA Three Phase High Side Driver
The HIP4083 is a three phase high side N-channel MOSFET
driver, specifically targeted for PWM motor control. Two
HIP4083 may be used together for 3 phase full bridge
applications (see application block diagram). Alternatively,
the lower gates may be controlled directly from a buffered
microprocessor output.
Unlike other members of the HIP408x family, the HIP4083
has no built in turn-on delay. Each output (AHO, BHO, and
CHO) will turn-on 65ns after its input is switched low.
Likewise, each output will turn-off 60ns after its input is
switched high. Very short and very long dead times are
possible when two HIP4083 are used to drive a full bridge.
This dead time is controlled by the input signal ti ming.
The HIP4083 does not have a built in charge pump.
Therefore, the bootstrap capacitors must be recharged on a
periodic basis by initiating a short refresh pulse. In most
bridge applications, this will happen automatically every time
the lower FETs turn-on and the upper FETs turn-off.
However, it is still possible to use the HIP4083 in
applications that require the high side FETs to be on for
extended periods of time. This can be easily accomplished
by sending a short refresh pulse to the DIS pin.
The HIP4083 has reduced drive current compa re d to the
HIP4086 making it ideal for low to moderate power
applications. The HIP4083 is optimized for applications
where size an d cost ar e important. For hig h power
applications driving large power FETs, the HIP4086 is
recommended.
Pinout HIP4083
(PDIP, SOI C)
TOP VIEW
Features
• Independently Drives Three High Side N-Chan nel
MOSFETs in Three Phase Bridge Configuration
• Bootstrap Supply Max Voltage to 95VDC
• Bias Supply Operation from 7V to 15V
• Drives 1000pF Load with Typical Rise Times of 35ns and
Fall Times of 30ns
• CMOS/TTL Compatible Inputs
• Programmable Undervoltage Protection
• Pb-free Available
Applications
• Brushless Motors
• High Side Switches
• AC Motor Drives
• Switched Reluctance Motor Drives
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
AHI
BHI
CHI
DIS
AHO
VSS
BHB
CHS
CHO
UVLO
VDD
AHS
AHB
BHO
CHB
BHS
Ordering Information
PART NUMBER TEMP.
RANGE (°C) PACKAGE PKG.
DWG. #
HIP4083AB -40 to 105 16 Ld SOIC M16.15
HIP4083ABZ (Note) -40 to 105 16 Ld SOIC (Pb-free) M16.15
HIP4083AP -40 to 105 16 Ld PDIP E16.3
HIP4083APZ (Note) -40 to 105 16 Ld PDIP (Pb-free) E16.3
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
Data Sheet FN4223.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1995. Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2
Application Block Diagram
Functional Block Diagram
12V 80V
GND
GND
AHI
BHI
CHI
AHO
BHO
CHO
HIP4083
12V
GND
AHI
BHI
CHI
AHO
BHO
CHO
MICRO-
CONTROLLER
(OPTIONAL)
HIP4083
CHI
BHI
VDD
DIS
AHB
AHO
AHS
UV
3
4
AHI 1
2
13
UVLO
12
LEVEL
SHIFTER
DRIVER 6
7
8
AHB
AHO
AHS
UV
DRIVER 6
8
AHB
AHO
AHS
UV
DRIVER 6
7
8
LEVEL
SHIFTER 7
LEVEL
SHIFTER
LOGIC
EN
UNDERVOLTAGE
DETECTOR UV
HIP4083
3
Typical Application: Three Phase Bridge Driver with Programmable Dead Time
TRUTH TABLE
INPUT OUTPUT
AHI, BHI, CHI UV DIS AHO, BHO, CHO
X1X0
XX10
1000
0001
NOTE: X signifies that input can be either a “1” or “0”.
POWER BUS
AHI
BHI
VSS
CHI
DIS
AHB
CHB
CHS
UVLO
CHO
VDD
BHO
BHS
4
3
2
1
6
5
8
7
AHS 9
13
10
11
16
12
15
14
BHB
AHO
CHIP SUPPLY
CBYPASS
CBS
CBS
CBS
OPTIONAL
MICROPROCESSOR
INPUTS
OPTIONAL
MICROPROCESSOR
INPUTS
OC SENSE
3-PHASE
LOAD
AHI
BHI
VSS
CHI
DIS
AHB
CHB
CHS
UVLO
CHO
VDD
BHO
BHS
4
3
2
1
6
5
8
7
AHS 9
13
10
11
16
12
15
14
BHB
AHO
RCURRENT
SENSE
HIP4083HIP4083
4
Typical Application: High Side Switch
80V
HIP4083
12V
GND
AHI
BHI
CHI
AHO
BHO
CHO
DIS
REFRESH
MICRO-
PROCESSOR
BOOT STRAP CAPACITOR
AND DIODE REQUIRED
LIGHT
Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
6
11
16
AHB
BHB
CHB
(xHB)
Gate driver supplies. One external bootstrap diode and one capacitor are required for each. The bootstrap diode
and capacitor may be omitted when the HIP4083 is used to drive the lower gates in three phase full bridge
applications. In this case, tie all three xHB pins to VDD and tie the xHS pins to the sources of the lower FETs. In
full bridge applications, the lower FET s must be turned on fir st at start up to refresh th e bootstrap capacitors. In
high side switch applications, the load will keep xHS low and refresh should happen automatically at start up.
1
2
3
AHI
BHI
CHI
(xHI)
Logic level inputs. Logic at these three pins cont rols the three output drivers, AHO, BHO and C HO. Wh en xHI is
low, xHO is high. When xHI is high, xHO is lo w. DIS (Disable) overrides all input signals. xHI can be driven by
signal levels of 0V to 15V (no greater than VDD).
5V
SS Chip ground.
13 UVLO Undervoltage setting. A resistor can be connected between this pin and VSS to program the under voltage set
point - see Figure 7. With this pin not connected the undervoltage set point is typically 7V. When this pin is tied to
VDD, the undervoltage set point is typically 6.2V.
4 DIS Disable input. Logic level input that when taken high sets all three outputs low. DIS high overrides all other inputs.
When DIS is taken low the outputs are c ontrolled by the ot her inputs. DIS can be driven by signal levels o f 0V to
15V (no greater than VDD).
7
10
15
AHO
BHO
CHO
(xHO)
Gate connections. Connect to the gates of the power MOSFETs in each phase.
8
9
14
AHS
BHS
CHS
(xHS)
MOSFET source connection. Connect the sources of the power MOSFETs and the negative side of the bootstrap
capacitors to these pins. In high side switch applications, 2mA of current will flo w out of these pins into the load
when the upper FETs are off. This current is necessary to guarantee that the upper FETs stay off. This current
tends to pull xHS high. For proper refresh, the load must pull the voltage on xHS down to at least 7V below VDD.
For example, when VDD = 12V, xHS must be pulled down to 5V. Therefore, the minimum load necessary for
proper refresh is given by the following equation: RMIN = 5V/2mA = 2.5kΩ. So in this case, if the load has an
impedance less than 5kΩ, refresh will happen automatically at start up.
12 VDD Positive supply rail. Bypass this pin to VSS with a capacitor >1µF. In applications where the bus voltage and chip
VDD are at the same potential, it is a good idea to run a separate line from the supply to each. This greatly
simplifies the filtering requirements.
HIP4083HIP4083
5
Absolute Maximum Ratings TA= 25°C Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on xHS . . . . . . . . . -6V (Transient) to 85V (-40°C to 150°C)
Voltage on xHB . . . . . . . . . . . . . . . . . . . . VxHS -0.3V to VxHS +VDD
Voltage on xLO . . . . . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V
Voltage on xHO . . . . . . . . . . . . . . . . . . . .VxHS -0.3V to VxHB +0.3V
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V to +15V
Voltage on xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 80V
Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS +VDD
Operating Ambient Temperature Range . . . . . . . . . .-40°C to 125°C
Thermal Resistance (Typical, Note 1) θJA (°C/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specifi ca tion is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. All voltages are relative to VSS unless otherwise specified.
3. x = A, B and C. For example, xHS refers to AHS, BHS and CHS.
Electrical Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, Gate Capacitance (CGATE) = 1000pF, RUV = ∞
PARAMETER TEST CONDITIONS
TJ = 25°C TJ = -40°C TO
150°C
UNITSMIN TYP MAX MIN MAX
SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION
VDD Quiescent Current xHI = 5V 0.5 1.5 2.25 0.25 2.3 mA
VDD Operating Current f = 20kHz, 50% Duty Cycle 1.0 2.0 2.5 0.75 3.0 mA
xHB On Quiescent Current xHI = 0V 65 100 240 45 250 µA
xHB Off Quiescent Current xHI = 5V 0.6 0.85 1.3 0.5 1.4 mA
xHB Operating Current f = 20kHz, 50% Duty Cycle 0.6 0.85 1.2 0.5 1.3 mA
VDD Rising Undervoltage Threshold RUV OPEN 6.2 7.0 8.0 6.1 8.1 V
VDD Falling Undervoltage Threshold RUV OPEN 5.75 6.5 7.5 5.25 7.6 V
Minimum Undervoltage Threshold RUV = VDD 5.0 6.2 6.9 4.5 7.0 V
INPUT PINS: AHI, BHI, CHI AND DIS
Low Level Input Voltage - - 1.0 - 0.8 V
High Level Input Voltage 2.5 - - 2.7 - V
Input Voltage Hysteresis - 35 - - - mV
Low Level Input Current VIN = 0V -145 -100 -60 -150 -50 µA
High Level Input Current VIN = 5V -1 - +1 -10 +10 µA
GATE DRIVER OUTPUT PINS: AHO, BHO, AND CHO
Average Turn-On Current VOUT 0V to 5V 100 240 400 50 500 mA
Average Turn-Off Current VOUT VDD to 4V 150 300 450 100 550 mA
HIP4083HIP4083
6
Switching Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, CGATE = 1000pF
PARAMETER TEST CONDITIONS
TJ = 25°C TJS = -40°C TO
150°C
UNITSMIN TYP MAX MIN MAX
Turn-Off Propagation Delay (xHI - xHO) No Load - 60 80 90 ns
Turn-On Propagation Delay (xHI - xHO) No Load - 65 90 100 ns
Rise Time (10 - 90%) CGATE = 1000pF - 35 60 - 65 ns
Fall Time (90 - 10%) CGATE = 1000pF - 30 50 - 55 ns
Disable Turn-Off Propagation Delay No Load - 65 - - 100 ns
Disable to Output Enable (DIS - xHO) No Load - 70 - - 100 ns
Typical Performance Curves
FIGURE 1. VDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE FIGURE 2. VDD SUPPLY CURRENT vs SWITCHING FREQUENCY
FIGURE 3. FLOATING SUPPLY OFF BIAS CURRENT FIGURE 4. FLOATING SUPPLY ON BIAS CURRENT
-60 -40 -20 020 40 60 80 100 120 140 160
1.0
1.2
1.4
1.6
1.8
2.0
JUNCTION TEMPERATURE (°C)
VDD SUPPLY CURRENT (mA)
VDD = 16V
VDD = 15V
VDD = 12V
VDD = 10V
VDD = 8V
VDD = 7V
-60 -40 -20 020 40 60 80 100 120 140 160
3.0
3.5
4.0
4.5
JUNCTION TEMPERATURE (°C)
VDD SUPPLY CURRENT (mA)
200kHz
100kHz
50kHz
10kHz
20kHz
-60 -40 -20 020 40 60 80 100 120 140 160
650
700
750
800
850
900
950
JUNCTION TEMPERATURE (°C)
xHB SUPPLY OFF CURRENT (µA)
(VXHB - VXHS) = 15V
(VXHB - VXHS) = 14V
(VXHB - VXHS) = 10V
(VXHB - VXHS) = 8V
(VXHB - VXHS) = 7V
(VXHB - VXHS) = 13V
(VXHB - VXHS) = 12V
-60 -40 -20 020 40 60 80 100 120 140 160
60
70
80
90
100
110
120
JUNCTION TEMPERATURE (°C)
xHB ON SUPPLY CURRENT (µA)
(VXHB - VXHS) = 15V
(VXHB - VXHS) = 12V
(VXHB - VXHS) = 10V
(VXHB - VXHS) = 8V
(VXHB - VXHS) = 7V
HIP4083HIP4083
7
FIGURE 5. FLOATING SUPPLY SWITCHING BIAS CURRENT FIGURE 6. FLOATING SUPPLY SWITCHING BIAS CURRENT
FIGURE 7. UNDERVOLTAGE THRESHOLD FIGURE 8. PROPAGATION DELAY
FIGURE 9. RISE AND FALL TIME (10-90%) FIGURE 10. GATE DRIVER AVERAGE TURN-ON CURRENT
Typical Performance Curves (Continued)
-60 -40 -20 020 40 60 80 100 120 140 160
0
1
2
3
4
JUNCTION TEMPERATURE (°C)
xHB SUPPLY CURRENT (mA)
CGATE = 1000pF
200kHz
100kHz
50kHz
20kHz
10kHz
-60 -40 -20 020 40 60 80 100 120 140 160
0
0.5
1.0
1.5
2.0
2.5
JUNCTION TEMPERATURE (°C)
xHB SUPPLY CURRENT (mA)
NO LOAD
200kHz
100kHz
50kHz
20kHz
10kHz
-60 -40 -20 020 40 60 80 100 120 140 160
5
6
7
8
9
10
JUNCTION TEMPERATURE (°C)
UNDERVOLTAGE SHUTDOWN/ENABLE
ENABLE (50K, UVLO TO GND)
TRIP (50K, UVLO TO GND)
ENABLE (UVLO OPEN)
TRIP (UVLO OPE N)
TRIP/ENABLE (OK, UVLO TO VDD)
VOLTAGE (V)
-60 -40 -20 020 40 60 80 100 120 140 160
40
60
80
100
JUNCTION TEMPERATURE (°C)
PROPAGATION DELAY (ns)
TURN-OFF
TURN-ON
ENABLE TURN-ON
DISABLE TURN-OFF
-60 -40 -20 020 40 60 80 100 120 140 160
20
30
40
50
JUNCTION TEMPERATURE (°C)
RISE AND FALL TIME (ns)
TURN-ON
TURN-OFF
CGATE = 1000pF
-60 -40 -20 020 40 60 80 100 120 140 160
0.1
0.15
0.2
0.25
0.3
0.35
JUNCTION TEMPERATURE (°C)
AVERAGE TURN-ON CURRENT (A)
0V TO 5V
15V
12V
10V
8V
7V
HIP4083HIP4083
8
FIGURE 11. GATE DRIVER AVERAGE TURN- OFF CURRENT FIGURE 12. HIGH VOLTAGE LEAKAGE CURRENT
Typical Performance Curves (Continued)
-60 -40 -20 020 40 60 80 100 120 140 160
0
0.1
0.2
0.3
0.4
0.5
JUNCTION TEMPERATURE (°C)
AVERAGE TURN-OFF CURRENT (A)
VDD TO 4V
15V
12V
10V
8V
7V
-60 -40 -20 020 40 60 80 100 120 140 160
0
10
20
30
40
50
JUNCTION TEMPERATURE (°C)
xHS LEAKAGE CURRENT (µA)
HIP4083HIP4083
9
HIP4083
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or
protrusions. Mold flash or protrusions shall not exceed 0.010
inch (0.25mm).
6. E and are measured with the leads constrained to be
perpendicular to datum .
7. eB and eC are measured at the lead tips with the leads
unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C A
MBS
eA-C-
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93
HIP4083
10
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is grant ed by impl icati on or ot herwise under any pate nt or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
HIP4083HIP4083
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) B
MM
α
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A0.053 0.069 1.35 1.75 -
A1 0.004 0.010 0.10 0.25 -
B0.014 0.019 0.35 0.49 9
C0.007 0.010 0.19 0.25 -
D0.386 0.394 9.80 10.00 3
E0.150 0.157 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H0.228 0.244 5.80 6.20 -
h0.010 0.020 0.25 0.50 5
L0.016 0.050 0.40 1.27 6
N16 167
α0o8o0o8o-
Rev. 1 02/02
