1/51March 2010
M29DW323DT
M29DW323DB
32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block)
3V Supply Flash Memory
FEATURES SUMMARY
SUPPLY VOLTAGE
–V
CC = 2.7V to 3.6V for Program, Erase
and Read
–V
PP =12V for Fast Program (optional)
ACCESS TIME: 70ns
PROGRAMMING TIME
– 10µs per Byte/Wor d typical
– Double Word/ Quadruple Byte Program
MEMORY BLOCKS
– Dual Bank Memory Array: 8Mbit+24Mbit
– Parameter Blocks (Top or Bottom
Location)
DUAL OPERATIONS
– Read in one ban k while Program or Erase
in other
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspen d
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
VPP/WP PIN for FAST PROGRAM and
WRITE PROTECT
TEMPORARY BLOCK UNPROTECTION
MODE
COMMON FLASH INTERFACE
– 64 bit Security Code
EXTENDED MEMORY BLOCK
– Extra block used as security block or to
store additional information
LOW POWER CONSUMPTION
– Standby and Automatic Standby
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29DW323DT: 225Eh
– Bottom Device Code M29DW323DB:
225Fh
Automotive Certified Parts Available
Figure 1. APac ka g es
TSOP48 (N)
12 x 20mm
FBGA
TFBGA48 (ZE)
6 x 8mm
M29DW323DT, M29DW323DB
2/51
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset/Block Temporary Unprotect (RP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Bus Operation s, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Bus Operation s, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Auto Select Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/51
M29DW323DT, M29DW323DB
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Fast Program Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Enter Extended Block Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Protect and Chip Unprotect Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Commands, 16-bit mode, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Program, Erase Times and Program, Erase Endu rance Cycles. . . . . . . . . . . . . . . . . . . 19
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Dual Operations Allowed In the Other Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 12.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
M29DW323DT, M29DW323DB
4/51
Figure 13.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14.Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled. . . . . . . . . . . . 29
Figure 15.Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled . . . . . . . . . . 29
Table 18. Toggle and Alternative Toggle Bits AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16.Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline. . 31
Table 20. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . . 31
Figure 19.TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline. . . . . . 32
Table 21. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . . 32
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. Ordering Inf or m at ion Sche m e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
APPENDIX A.BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 23. Top Boot Block Addresses, M29DW323DT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 24. Bottom Boot Block Addresses, M29DW323DB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 25. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 26. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 27. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 28. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 29. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 30. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
APPENDIX C.EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Customer Lockable Extended Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 31. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
APPENDIX D.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 32. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 20.Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 22.In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 23.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
M29DW323DT, M29DW323DB
6/51
SUMMARY DESCRIPTION
The M29DW323D is a 32 Mbit (4Mb x8 or 2Mb
x16) non-volatile memor y that can be read, erased
and reprogra mmed. These operations can be per -
formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode.
The devic e features an asy mmetrical block a rchi-
tecture. The M29DW323D has an array of 8 pa-
rameter and 63 main blocks and is divided into two
Banks, A and B, providing Dual Ba nk operations.
While programming or e rasing in Bank A, read op-
erations are possible in Bank B and vice versa.
Only one bank at a time is allowed to be in pro-
gram or erase mode. The bank architecture is
summarized in Table 2. M29DW323DT locates the
Parameter Blocks at the top of the memory ad-
dress space while the M29DW323DB locates the
Parameter Blocks starting from the bottom.
M29DW323D has an extra 32 KWord (x16 mode)
or 64 KByte (x8 mo de) b l ock, th e Exten ded Block,
that can be accessed using a dedicated com-
mand. The E xtended Block can be protec ted and
so is useful for storing security information. How-
ever the protection is irreversible, once protected
the protection cannot be undone.
Each block can be erased independently so it is
possible to preserve valid data while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase com-
mands are written to the Command Interface of
the memory. An on-ch ip Program/Erase Controller
simplifies the process of programming or erasing
the memory by taking care of all of the special op-
erations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identi-
fied. The command set required to control the
memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP48 (12x20mm), and
TFBGA48 (6x8mm, 0.8mm pitch) packages. The
memory is supplied with all the bits erased (set to
’1’).
Figure 2. Logic Diagram Table 1. Signal Names
AI05523
21
A
0-A20
W
DQ0-DQ1
4
VCC
M29DW323DT
M29DW323DB
E
VSS
15
G
RP
DQ15A–1
BYTE
RB
VPP/WP
A0-A20 Address Inputs
DQ0-DQ7 Data Input s/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
EChip Enable
GOutput Enable
WWrite Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
BYTE Byte/Word Organization Select
VCC Supply Voltage
VPP/WP VPP/Write Protect
VSS Ground
NC Not Connected Internally
7/51
M29DW323DT, M29DW323DB
Figure 3. TSOP Connections
DQ3
DQ9
DQ2
A6 DQ0
W
A3
RB
DQ6
A8
A9 DQ13
A17
A10 DQ14
A2
DQ12
DQ10
DQ15A–1
VCC
DQ4
DQ5
A7
DQ7
VPP/WP
NC
AI05524
M29DW323DT
M29DW323DB
12
1
13
24 25
36
37
48
DQ8
A20
A19
A1
A18
A4
A5
DQ1
DQ11
G
A12
A13
A16
A11
BYTE
A15
A14 VSS
E
A0
RP
VSS
M29DW323DT, M29DW323DB
8/51
Figure 4. TFBGA48 Connections (Top view through package)
Table 2. Bank Architecture
Bank Bank Size Parameter Blocks Main Blocks
No. of Blocks Block Size No. of Blocks Block Size
A 8 Mbit 8 8KByte/ 4 KWord 15 64KByte/ 32 KWord
B 24 Mbit - 48 64KByte/ 32 KWord
654321
VSS
A15
A14
A12
A13
DQ3
DQ11
DQ10
A18
VPP
/
WP
RB
DQ1
DQ9
DQ8
DQ0
A6
A17
A7
G
E
A0
A4
A3
DQ2
DQ6
DQ13
DQ14
A10
A8
A9
DQ4
VCC
DQ12
DQ5
A19
NC
RP
W
A11
DQ7
A1
A2
VSS
A5 A20
A16
BYTE
C
B
A
E
D
F
G
H
DQ15
A–1
AI08084
9/51
M29DW323DT, M29DW323DB
Figure 5. Block Addresses (x8)
Note: Also see APPENDIX A., Table 23. and Tabl e 24. for a full listing of the Block Addresses.
AI05556
64 KByte or
32 KWord
000000h
00FFFFh
64 KByte or
32 KWord
3E0000h
3EFFFFh
Top Boot Block (x8)
Address lines A20-A0, DQ15A-1
64 KByte or
32 KWord
2F0000h
2FFFFFh
Total of 48
Main Blocks
64 KByte or
32 KWord
300000h
30FFFFh
8 KByte or
4 KWord
3FE000h
3FFFFFh
8 KByte or
4 KWord
3F0000h
3F1FFFh
Total of 15
Main Blocks
Total of 8
Parameter
Blocks (1)
Bank B
Bank A
8 KByte or
4 KWord
000000h
001FFFh
64 KByte or
32 KWord
0F0000h
0FFFFFh
Bottom Boot Block (x8)
Address lines A20-A0, DQ15A-1
8 KByte or
4 KWord
00E000h
00FFFFh
Total of 8
Parameter
Blocks (1)
64 KByte or
32 KWord
010000h
01FFFFh
64 KByte or
32 KWord
3F0000h
3FFFFFh
64 KByte or
32 KWord
100000h
10FFFFh
Total of 15
Main Blocks
Total of 48
Main Blocks
Bank B
Bank A
Note 1. Used as Extended Block Addresses in Extended Block mode.
M29DW323DT, M29DW323DB
10/51
Figure 6. Block Addresses (x16)
Note: Also see APPENDIX A., Table 23. and Tabl e 24. for a full listing of the Block Addresses.
AI05555
64 KByte or
32 KWord
000000h
007FFFh
64 KByte or
32 KWord
1F0000h
1F7FFFh
Top Boot Block (x16)
Address lines A20-A0
64 KByte or
32 KWord
178000h
17FFFFh
Total of 48
Main Blocks
64 KByte or
32 KWord
180000h
187FFFh
8 KByte or
4 KWord
1FF000h
1FFFFFh
8 KByte or
4 KWord
1F8000h
1F8FFFh
Total of 15
Main Blocks
Total of 8
Parameter
Blocks (1)
Bank B
Bank A
8 KByte or
4 KWord
000000h
000FFFh
64 KByte or
32 KWord
078000h
07FFFFh
Bottom Boot Block (x16)
Address lines A20-A0
8 KByte or
4 KWord
007000h
007FFFh
Total of 8
Parameter
Blocks (1)
64 KByte or
32 KWord
008000h
00FFFFh
64 KByte or
32 KWord
1F8000h
1FFFFFh
64 KByte or
32 KWord
080000h
087FFFh
Total of 15
Main Blocks
Total of 48
Main Blocks
Bank B
Bank A
Note 1. Used as Extended Block Addresses in Extended Block mode.
11/51
M29DW323DT, M29DW323DB
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera -
tions they control the commands sent to the
Command Interface of the Program/Erase Con-
troller.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE is High,
VIH. When BYTE is Low, VIL, these pins are not
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
BYTE is Low, VIL, this pin behaves as an address
pin; DQ15A–1 Low will select the LSB of the ad-
dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE is
High and references to the Address Inputs to in-
clude this pin when BYTE is Low except when
stated explicitly otherwise.
Chip Enable (E). The Chip Enable, E, activates
the memory, allo wing Bus Read and Bus Write op -
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). Th e Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interf ace.
VPP/Write Protect (VPP/WP). The VPP/Write
Protect pin provides two functions. The VPP func-
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Program operations. This is achieved by by-
passing the unlock cycles and/or using the Dou-
ble Word or Quadruple Byte Program commands.
The Write Protect function provides a hardware
method of protecting the two outermost boot
blocks.
When VPP/Write Protect is Low, VIL, the memory
protects the two outermost boot blocks; Program
and Erase operations in these blocks are ignored
while VPP/Write Protect is Low, even when RP is
at VID.
When VPP/Write Protect is High, VIH, the memory
reverts to the previous protection status of the two
outermost boot blocks. Program and Erase oper-
ations can now modify the data in these blocks un-
less the blocks are protected using Block
Protection.
When VPP/Write Protect is rai sed to VPP the mem-
ory automatically enters the Unlock Bypass mode.
When VPP/Write Protect returns to VIH or VIL nor-
mal operation resumes. During Unlock Bypass
Program operations the memory draws IPP from
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
VIH to VPP and from VPP to VIH must be slower
than tVHVPP, see Figure 17.
Never raise VPP/Write Protect to VPP from any
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The VPP/Write Protect pin must not be left floating
or unconnected or the device may become unreli-
able. A 0.1µF capacitor should b e connected be-
tween the VPP/Write Protect pin and the VSS
Ground pin to decouple the current surges from
the power supply. The PCB tra c k wid ths mu st be
sufficient to carry the currents required during
Unlock Bypass Program, IPP.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memor y or
to temporar ily un prot ect all Blocks that have been
protected.
Note that if VPP/WP is at VIL, then the two outer-
most boot blocks will remain protected even if RP
is at VID.
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, VIL, for at least
tPLPX. After Reset/Block Temporary Unprotect
goes High, VIH, the memory will be ready for Bus
Read and Bus Write operations after tPHEL or
tRHEL, whichever occurs last. See the Read y/Busy
Output section, Table 19. and Figure 16., Reset/
Block Temporary Unprotect AC Waveforms, for
more details.
Holding RP at VID will temporarily unprotect the
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from VIH to VID must be slower than
tPHPHH.
Ready/Busy Output (RB). The Ready/Busy pin
is an open-drain output that can be used to identify
when the device is performing a Progra m or Erase
M29DW323DT, M29DW323DB
12/51
operation. During Program or Erase operations
Ready/Busy is Low, VOL. Ready/Busy is high-im-
pedance during Read mode, Auto Select mode
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy be-
comes high-impe dance. See Table 19. and Figure
16., Reset/Block Temporary Unprotect AC Wave-
forms.
The use of an open-drain output allows the Ready/
Busy pins from several memo ries to be con nected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Wo rd Organization Select (BYTE). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
memory. When Byte/Word Organization Select is
Low, VIL, the memory is in x8 mode, when it is
High, VIH, the memory is in x16 mode.
VCC Supply Voltage (2.7V to 3.6V). VCC pro-
vides the power supply for all operations (Read,
Program and Erase).
The Command Interface is disabled when the VCC
Supply Voltage is less than the Lockout Voltage,
VLKO. This prevents Bus Write operations from ac-
cidentally damaging the data during power up,
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo-
ry contents being altered will be invalid.
A 0.1µF capacitor should be connected between
the VCC Supply Voltage pin and the VSS Ground
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase opera tio ns, ICC3.
VSS Ground. VSS is the reference for all voltage
measurements. The device features two VSS pins
which must be both connected to the system
ground.
13/51
M29DW323DT, M29DW323DB
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby and Automatic Standby.
The Dual Bank ar chitecture of the M29DW3 23 al-
lows read/write operations in Bank A, while read
operations are being executed in Bank B or vice
versa. Write operations are only allowed in one
bank at a time.
See Tables 3 and 4, Bus Operations, for a summa-
ry. Typically glitches of less than 5ns on Chip En-
able or Write Enable are ignored by the memory
and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the d esired addre ss on the Ad dress
Inputs, applying a Low signal, VIL, to C hip Enable
and Output Enable and keeping Write Enable
High, VIH. The Data Inputs/Out puts will output the
value, see Figure 11., Read Mode AC Waveforms,
and Table 15., Read AC Characteristics, for de-
tails of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad-
dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inpu ts/Output s are latched by the Com-
mand Interfa ce on the rising edge of Ch ip Enable
or Write Enable, whichever occurs first. Output En-
able must remain High, VIH, during the whole Bus
Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 16 and 17, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Curre nt, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 14., DC Characteristics.
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, ICC3, for Program or Er ase operations un-
til the operation c omp let es .
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera-
tions are intended for use by programming equip-
ment and are not usually used in applications.
They requir e VID to be applied to some pins.
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3 and 4, Bus Operations.
Block Pro tect and
Chip Unprotect.
Groups of
blocks can be protected against accidental Pro-
gram or Erase. The Protection Groups are shown
in APPENDIX A., Tables 23 and 24, Block Ad-
dresses. The whole chip can be unprotected to al-
low the data inside the blo cks to be changed.
The VPP/Write Protect pin can be use d to protect
the two outermost boot blocks. When VPP/Write
Protect is at VIL the two outermost boot blocks are
protected and remain protected regardless of the
Block Protection Status or the Reset/Block Tem-
porary Unprotect pin s tatu s.
Block Protect and Chip Unprotect operations are
described in APPENDIX D.
M29DW323DT, M29DW323DB
14/51
Table 3. Bus Operations, BYTE = VIL
Note: X = VIL or VIH.
Table 4. Bus Operations, BYTE = VIH
Note: X = VIL or VIH.
Operation E G W Address Inputs
DQ15A–1, A0-A20 Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
Bus Read VIL VIL VIH Cell Address Hi-Z Data Output
Bus Write VIL VIH VIL Command Address Hi-Z Data Input
Output Disable X VIH VIH X Hi-Z Hi-Z
Standby VIH X X X Hi-Z Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH Hi-Z 20h
Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL,
A9 = VID, Others VIL or VIH Hi-Z 5Eh (M29DW323DT)
5Fh (M29DW323DB)
Extended Memory
Block Verify Code VIL VIL VIH A0 = VIH, A1 = VIH, A6 = VIL,
A9 = VID, Others VIL or VIH Hi-Z 81h (factory locked)
01h (not factory locked)
Operation E G W Address Inputs
A0-A20 Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read VIL VIL VIH Cell Address Data Output
Bus Write VIL VIH VIL Command Address Data Input
Output Disable X VIH VIH XHi-Z
Standby VIH XXX Hi-Z
Read Manufacturer
Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH 0020h
Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID,
Others VIL or VIH 225Eh (M29DW323DT)
225Fh (M29DW323DB)
Extended Memory
Block Verify Code VIL VIL VIH A0 = VIH, A1 = VIH, A6 = VIL,
A9 = VID, Others VIL or VIH 81h (factory locked)
01h (not factory locked)
15/51
M29DW323DT, M29DW323DB
COMMAND INTERFACE
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return-
ing to Read mode. T he long co mmand sequen ces
are imposed to maximize data securi ty.
The address used for the com mand s change s de -
pending on whether the memory is in 16-bit or 8-
bit mode. See either Table 5, or 6, depending on
the configuration that is being used, for a summary
of the comma nd s.
Read/Reset Command
The Read/Reset command re tu rn s th e memo ry to
its Read mode. It also resets the errors in the Sta-
tus Register. Either one or three Bus Write opera-
tions can be used to issue the Read/Reset
command.
The Read/Reset command can be issued, be-
tween Bus Write cycles before the start of a pro-
gram or erase operation, to return the device to
read mode. If the Read/Reset command is issued
during the time-out of a Block erase operation then
the memory will take up to 10µs to abort. During
the abort period no va lid data can be read from the
memory. The Read/Reset command will not abort
an Erase operation when issued while in Erase
Suspend.
Auto Select Command
The Auto Select command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Extended Memory Block
Verify Code. It can be addressed to either Bank.
Three consecutive Bus Write operations are re-
quired to issue the Auto Select command. The fi-
nal Write cycle must be addressed to one of the
Banks. Once the Auto Select command is issued
Bus Read operations to the Bank where the com-
mand was issued output the Auto Select data. Bus
Read operations to the other Bank will output the
contents of the memory array. The memory re-
mains in Auto Select mode until a Read/Reset or
CFI Query command is issued.
In Auto Select mode the Manufacturer Code can
be read using a Bus Read operation with A0 = VIL
and A1 = VIL and A19-A20 = Bank Address. The
other address bits may b e se t to eithe r VIL or VIH.
The Device Code can be read using a Bus Read
operation with A0 = VIH and A1 = VIL and A19-A20
= Bank Address. The other address bits may be
set to either VIL or VIH.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = VIL,
A1 = VIH, A19-A20 = Bank Address and A12-A18
specifying the address of the block inside the
Bank. The ot her addr ess bits m ay be se t to either
VIL or VIH. If the addressed block is protected then
01h is output on Data Inputs/Outputs DQ0-DQ7,
otherwise 00h is output.
Read CFI Query Command
The Read CFI Query Command is used to read
data from the Common Flash Interface (CFI)
Memory Area. This command is valid when the de-
vice is in the Read Array mode, or when the device
is in Auto Se lect mode.
One Bus Write cycle is requir ed to issu e the Read
CFI Query Command. Once the command is is-
sued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to re-
turn the device to the previous mode (the Read Ar-
ray mode or Auto Select mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Auto Select
mode.
See APPENDIX B., Tables 25, 26, 27, 28, 29 and
30 for details on the information contained in the
Common Flash Interface (CFI) memory area.
Program Command
The Program comman d can be used to program a
value to one address in the memory array at a
time. The c omm an d re qu ir es f our Bus Write oper-
ations, the final write operation latches the ad-
dress and data, and starts the Program/Erase
Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never re ad and
no error condition is given.
During the program operation the memory will ig-
nore all commands. It is not possible to issue any
command to abort or pause the operation. After
programming has started , Bus Read oper ations in
the Bank being programmed output the Status
Register content, while Bus Read operations to
the other Bank output the contents of the memory
array. See the section on the Status Register for
more details. Typical program times are given in
Table 7.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition a nd return to Read mode.
Note that the Program com mand cannot change a
bit set at ’0’ back to ’1’. One of the Erase Com-
mands must be used to set all th e bits in a block or
in the whole memory from ’0’ to ’1’.
M29DW323DT, M29DW323DB
16/51
Fast Program Commands
There are two Fast Program commands available
to improve the programming throughput, by writing
several adjacent words or bytes in parallel. The
Quadruple Byte Program command is available for
x8 operations, while the Double Word Program
command is available for x16 opera tions.
Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.
Fast Program commands should not be attempted
when VPP/WP is not at VPP. Care must be taken
because applying a 12V VPP voltage to the VPP/
WP pin will temporarily unprotect any protected
block.
After programming has started, Bus Read opera-
tions in the Bank being programmed output the
Status Register content, while Bus Read opera-
tions to the other Bank output the contents of the
memory array.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition and re turn to Read m ode.
Note that the Fast Program commands cannot
change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in Table
7., Program, Erase Times and Program, Erase
Endurance Cycles.
Quadruple Byte Program Command. The Qua-
druple Byte Program command is used to write a
page of four adjacent Bytes in parallel. The four
bytes must differ on ly for addresses A0, DQ15A-1.
Five bus write cycles are necessary to issue the
Quadruple Byte Program command.
The first bus cycle sets up the Quadruple Byte
Program Command.
The second bus cycle latches the Address and
the Data of the first byte to be written.
The third bus cycle latches the Address and
the Data of the second byte to be written.
The fourth bu s cycle la tch es the Address an d
the Data of the third byte to be written.
The fifth bus cycle latches the Address and the
Data of the fourth byte to be written and sta rts
the Program/Erase Controller.
Double Word Program Command. The Double
Word Program command is used to write a page
of two adjacent words in parallel. The two words
must differ only for the address A0.
Three bus write cycles are necessary to issue the
Double Word Program command.
The first bus cycle set s up th e Do ub le Wo rd
Program Command.
The second bus cycle latches the Address and
the Data of the first word to be written.
The third bus cycle latches the Address and
the Data of the second word to be written and
starts the Program/Erase Controller.
Unlock Bypass Command
The Unlock Bypass command is used in conjunc-
tion with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When the cycle time to the
device is long, considerable time saving can be
made by using these commands. Th ree Bus Write
operations are required to issue the Unlock By-
pass command.
Once the Unlock Bypass command has been is-
sued the bank enters Unlo ck Bypass mod e. When
in Unlock Bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands
are valid. The Unlock Bypass Program command
can be issued to program addresses within the
bank, and the Unlock Bypass Reset command to
return the bank to Read mode. In Unlock Bypass
mode the memory can be read as if in Read mode.
When VPP is applied to the VPP/Write Protect pin
the memory automatically enters the Unlock By-
pass mode and the Unlock Bypass Program com-
mand can be issued immediately. Care must be
taken because applying a 12V VPP voltage to the
VPP/WP pin will temporarily unprotect any protect-
ed block.
Unlock Bypass Program Command
The Unlock Bypass Program command can be
used to program o ne address in the memory arr ay
at a time. The command requires two Bus Write
operations, the final write operation latches the ad-
dress and data, and starts the Program/Erase
Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Pr o-
gram operation using the Program comma nd. The
operation cannot be aborted, a Bus Read opera-
tion to the Bank where the command was issued
outputs the Status Register. See the Program
command for details on the behavior.
Unlock Bypass Reset Command
The Unlock Bypass Reset command can be used
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.
17/51
M29DW323DT, M29DW323DB
Chip Erase Command
The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations are re-
quired to issue the Chip Erase Command and start
the Program/Erase Controller.
If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap -
pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ign ored.
During the erase operation the memory will ignore
all commands, including the Erase Suspend com-
mand. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 7. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See th e sec-
tion on the Status Register for more details.
After the C hip Er ase oper atio n ha s com plet ed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis-
ter. A Read/Reset command mu st be issued to re-
set the error condition an d return to Read Mode.
The Chip Erase Command sets all of the bits in un-
protected blocks of the memor y to ’1 ’. All pr evious
data is lost.
Block Erase Command
The Block Erase command can be used to erase
a list of one or more blocks in a Bank. It sets all of
the bits in the unprotected selected blocks to ’1’.
All previous data in the selected blocks is lost.
Six Bus Write operations are required to sele ct the
first block in the list. Each additional block in the
list can be selected by repeating the sixth Bus
Write operation using the address of the additional
block. All blocks must belong to the same Bank; if
a block belonging to the other Bank is given it will
not be erased. The Block Erase operation starts
the Program/Erase Controller after a time-out pe-
riod of 50µs after the last Bus Write operation.
Once the Program/Erase Controller starts it is not
possible to select any more blo cks. Each addition-
al block must th erefor e be se lected wit hin 50 µs of
the last block. The 50µs timer restarts when an ad-
ditional block is selected. After the sixth Bus Write
operation a Bus Read operation within the same
Bank will output the Status Register. See the Sta-
tus Regist er section fo r details on how to identify if
the Program/Erase Controller has started the
Block Erase operation.
If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will
terminate within about 100µs, leaving the data un-
changed. No error co ndition is given when protec t-
ed blocks are ignored.
During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command and the Read /Reset comman d which is
only accepted during the 50µs time-out period.
Typical block erase times are given in Table 7.
After the Erase operatio n has started all Bus Read
operations to the Bank being erased will output the
Status Register on the Data Inputs/Outputs. See
the section on the Status Register for more details.
After the Block Erase operation h as completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg-
ister. A Read/Reset command must be issued to
reset the error condition a nd return to Read mode.
Erase Suspend Command
The Erase Suspend Command may be used to
temporarily suspend a Block Erase operation and
return the memory to Read mode. The command
requires one Bus Write operation.
The Program/Erase Controller will suspend within
the Erase Suspend Latency time of the Erase Sus-
pend Command being issued. Once the Pro gram/
Erase Controller has stopped the memory will be
set to Read mode and the Erase will be suspend-
ed. If the Erase Suspend comm and is issued dur-
ing the period when the memory is waiting for an
additional block (before the Program/Erase Con-
troller starts) then the Erase is suspended immedi-
ately and will start immediately when the Erase
Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase
Resume.
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchang ed. The Status Register
is not read and no error condition is given. Read-
ing from blocks that are being erased will output
the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac-
cepted.
During Erase Suspend a Bus Read operation to
the Extended Block will output the Extended Block
data.
M29DW323DT, M29DW323DB
18/51
Erase Resume Command
The Erase Resume command must be used to re-
start the Program/Erase Controller after an Erase
Suspend. The device must be in Read Array mode
before the Resume command will be accepted. An
erase can be suspended and resumed more than
once.
Enter Extended Block Command
The M29DW323D has an extra 64KByte block
(Extended Block) that can on ly be accessed using
the Enter Extended Block command. Three Bus
write cycles are required to issue the Extended
Block command. Once the co mmand has bee n is-
sued the device enters Extended Block mode
where all Bus Read or Program operations to the
Boot Block addresse s access the Extended Block.
The Extended Block (with the same address as
the boot block) cannot be erased, and can be
treated as one-time programmable (OTP) memo-
ry. In Extended Block mode the Boot Blocks are
not accessible. In Extended Block mode dual op-
erations are possible, with the Extended Block
mapped in Bank A. When in Extended Block
mode, Erase Commands in Bank A are not al-
lowed.
To exit from the Extended Block m ode the Exit Ex-
tended Block command must be issued.
The Extended Block can be protected, however
once protected the protection cannot be undone.
Exit Extended Block Command
The Exit Extended Block command is used to exit
from the Extended Block mode and return the de-
vice to Read mode . Four Bus Write operatio ns are
required to issue the command .
Block Protect and Chip Unp rotect Commands
Groups of blocks can be protected against acci-
dental Program or Erase. The Protection Groups
are shown in APPENDIX A., Tables 23 and 24,
Block Addresses. The whole chip can be unpro-
tected to allow the data inside the blocks to be
changed. Block Protect and Chip Unprotect oper-
ations are described in APPENDIX D.
Table 5. Commands, 16-bit mode, BYTE = VIH
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the table are in
hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ 14 and DQ15 are Don’t
Care. DQ15 A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset 1X F0
3 555 AA 2AA 55 X F0
Auto Select 3 555 AA 2AA 55 (BKA)
555 90
Program 4 555 AA 2AA 55 555 A0 PA PD
Double Word Program 3 555 50 PA0 PD0 PA1 PD1
Unlock Bypass 3 555 AA 2AA 55 555 20
Unlock Bypass
Program 2 X A0 PA PD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30
Erase Suspend 1 BKA B0
Erase Resume 1 BKA 30
Read CFI Query 1 55 98
Enter Extended Block 3 555 AA 2AA 55 555 88
Exit Extended Block 4 555 AA 2AA 55 555 90 X 00
19/51
M29DW323DT, M29DW323DB
Table 6. Commands, 8-bit mode, BYTE = VIL
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block . All values in the table are in hexadecimal .
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ 14 and DQ15 are Don’t
Care. DQ15 A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
Table 7. Program, Erase Times and Program, Erase Endurance Cycle s
Note: 1. Typical values measured at room temper ature and nomin al voltages.
2. Sampled, but not 100% tested.
3. Maximum val ue measured at worst case conditions for both temperat ure and VCC after 100,00 program/erase cycles.
4. Maximum val ue measured at worst case conditions for both temperat ure and VCC.
Command
Length
Bus Write Operations
1st 2nd 3rd 4th 5th 6th
Add Data Add Data Add Data Add Data Add Data Add Data
Read/Reset 1X F0
3 AAA AA 555 55 X F0
Auto Select 3 AAA AA 555 55 (BKA)
AAA 90
Program 4 AAA AA 555 55 AAA A0 PA PD
Quadruple Byte Program 5 AAA 55 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3
Unlock Bypass 3 AAA AA 555 55 AAA 20
Unlock Bypass Program 2 X A0 PA PD
Unlock Bypass Reset 2 X 90 X 00
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30
Erase Suspend 1 BKA B0
Erase Resume 1 BKA 30
Read CFI Query 1 AA 98
Enter Extended Block 3 AAA AA 555 55 AAA 88
Exit Extended Block 4 AAA AA 555 55 AAA 90 X 00
Parameter Min Typ (1, 2) Max(2) Unit
Chip Erase 40 200(3) s
Block Erase (64 KBytes) 0.8 6(3) s
Erase Suspend Latency Time 50(4) µs
Program (Byte or Word) 10 200(4) µs
Double Word Program (Byte or Word) 10 200(3) µs
Chip Program (Byte by Byte) 40 200(3) s
Chip Program (Word by Word) 20 100(3) s
Chip Program (Quadruple Byte or Double Word) 10 100(3) s
Program/Erase Cycles (per Block) 100,000 cycles
Data Retention 20 years
M29DW323DT, M29DW323DB
20/51
STATUS REGISTER
The M29DW323D has a Status Register that pro-
vides information on the current or previous Pro-
gram or Erase operations executed in each bank.
The various bits convey information and errors on
the operation. Bus Read operations from any ad-
dress within the Bank, always read the Status
Register du ring Program and Er ase operations. It
is also read during Erase Suspend when an ad-
dress within a block being erased is accessed.
The bits in t he St atus Regist er are summ ariz ed in
Table 8., Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera-
tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit
outputs the complement of the bit being pro-
grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad-
dress just programmed output DQ7, not its com-
plement.
During Erase operations the Data Polling Bit out-
puts ’0’, the complement of the erased state of
DQ7. After successful comp letion of the Erase op-
eration the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0 ’ to a ’1’ when the Prog ram/Erase
Controller ha s susp en de d the Eras e op er a tion .
Figure 7., Data Polling Flowchart, gives an exam-
ple of how to use the Data Polling Bit. A V alid A d-
dress is the address being programmed or an
address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Contr oller has
successfully completed its operation or if it has re-
sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.
During Prog ram and Er ase opera tions the T oggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-
sive Bus Read operations at any address. After
successful completion of the opera tion the memo -
ry returns to Read mode.
During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
Figure 8., Toggle Flowchart, gives an example of
how to use the Data Toggle Bit. Figures 14 and 15
describe Toggle Bit timing waveform.
Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro-
gram, Block Erase or Chip Erase oper ation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.
Note that the Program com mand cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad-
dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com-
mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase a nd Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the opera tion completes the memory returns
to Read mode.
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block ha s erased cor-
rectly.
Figures 14 and 15 describe Alternative Toggle Bit
timing waveform.
21/51
M29DW323DT, M29DW323DB
Table 8. Status Register Bits
Note: Unspecifie d da ta bits should be ignored.
Figure 7. Data Polling Flowchart Figure 8. Toggle Flowchart
Note: BA = Address of Bank being Programmed or Erased.
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB
Program Bank Address DQ7 Toggle 0 – – 0
Program During Erase
Suspend Bank Address DQ7 Toggle 0 – – 0
Program Error Bank Address DQ7 Toggle 1 – – Hi-Z
Chip Erase Any Address 0 Toggle 0 1 Toggle 0
Block Erase before
timeout Erasing Block 0 Toggle 0 0 Toggle 0
Non-Erasing Block 0 Toggle 0 0 No Toggle 0
Block Erase Erasing Block 0 Toggle 0 1 Toggle 0
Non-Erasing Block 0 Toggle 0 1 No Toggle 0
Erase Suspend Erasing Block 1 No Toggle 0 – Toggle H i-Z
Non-Erasing Block Data read as normal Hi-Z
Erase Error Good Block Address 0 Toggle 1 1 No Toggle Hi-Z
Faulty Block Address 0 Toggle 1 1 Toggle Hi-Z
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
at VALID ADDRESS
FAIL PASS
AI90194
DQ7
=
DATA YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA YES
NO
READ DQ6
ADDRESS = BA
START
READ DQ6
TWICE
ADDRESS = BA
FAIL PASS
AI08929b
DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6
=
TOGGLE
READ
DQ5 & DQ6
ADDRESS = BA
M29DW323DT, M29DW323DB
22/51
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE
The Multiple Bank Architecture of the
M29DW323DT and M29DW323DB gives greater
flexibility for software deve lopers to split the code
and data spaces within the memory array. The
Dual Operations feature simplifies the software
management of the device by allowing code to be
executed from one bank while the other bank is
being programmed or erased.
The Dual Operations feature means that while pro-
gramming or erasing in on e bank, read oper ations
are possible in the other bank with zero latency.
Only one bank at a time is allowed to be in pro-
gram or eras e mode.
If a read operation is required in a bank, which is
programming or er asing, the program or erase op-
eration can be suspended.
Also if the suspended operation was erase then a
program command can be issued to another
block, so the device can have one block in Erase
Suspend mode, one programming and other
banks in read mode.
By using a combination of these fe atures, read op-
erations are possible at any moment.
Table 9. and Table 10. show the dual operations
possible in other banks and in the same bank.
Note that only the commonly used comma nds are
represented in these tables.
Table 9. Dual Operations Allowed In the Other Bank
Note: 1. If one bank is involved in a program or erase operation, then the other bank is available for dual operations.
2. Only after an Erase operation in that bank.
3. Only after an Erase Sus pend command in that bank.
Table 10. Dual Operations Allowed In Same Bank
Note: 1. Not allowed in the Block or Word that is being erased or programmed.
2. Only after an Erase operation in that bank.
3. Only after an Erase Sus pend command in that bank.
4. Read Status Register is not a command. The Status Register can be read during a block program or erase operation.
5. The Status Register ca n be read by addressing the bl ock being erase suspended.
Status of First
Bank(1)
Commands allowed in the Other Bank(1)
Read
Array Read Status
Register(6)
Read
CFI
Query
Auto
Select Program Erase Erase
Suspend Erase
Resume
Idle Yes Yes(2) Yes Yes Yes Yes Yes(2) Yes(3)
Programming Yes No No No – – No No
Erasing Yes No No No – – No No
Erase Suspended Yes Yes Yes Yes Yes No - Yes
Status of bank
Commands allowed in same bank
Read
Array
Read
Status
Register(4)
Read
CFI Query Auto
Select Program Erase Erase
Suspend Erase
Resume
Idle Yes Yes Yes Yes Yes Yes Yes(2) Yes(3)
Programming No Yes No No – – No -
Erasing No Yes No No – No Yes(5) -
Erase Suspended Yes(1) Yes(5) Yes Yes Yes(1) No - Yes(4)
23/51
M29DW323DT, M29DW323DB
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. Exposure to Abso-
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of the device at
these or any other conditio ns above those indica t-
ed in the Operating sections of this specificati on is
not implied. Refer also to the Numonyx SURE Pro-
gram and other relevan t quality documents.
Table 11. Absolute Maximum Ratings
Note: 1. Compliant with the JE DEC Std J- STD-020 B (for sm all body, S n-Pb or Pb assembl y), and th e Europe an directi ve on Res trictions on
Hazardous Substances (RoHS) 2002/95/EU.
2. Minimum vol tage may undershoot to –2V during transition and for less than 20ns during tra nsitions.
3. Maximum vol tage may oversh oot to VCC +2V during transition and for less than 20ns during transitions.
4. VPP must not remain at 12V for more than a total of 80hrs.
Symbol Parameter Min Max Unit
TBIAS Temperature Under Bias –50 125 °C
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering (1) °C
VIO Input or Output Voltage (2,3) –0.6 VCC +0.6 V
VCC Supply Voltage –0.6 4 V
VID Identification Voltage –0.6 13.5 V
VPP(4) Program Voltage –0.6 13.5 V
M29DW323DT, M29DW323DB
24/51
DC AND AC PARAMETERS
This section summarizes the operating measure-
ment conditions, and the DC and AC characteris-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are de rived
from tests performed under the Measurement
Conditions summarized in Table 12., Operating
and AC Measurement Conditions. Designers
should chec k that the operat ing co nd itions in their
circuit match the operating conditions when rely-
ing on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
Figure 9. AC Measurement I/O Waveform Figure 10. AC Measurement Load Circuit
Table 13. Device Capacitance
Note: Sampled only, not 100% t ested.
Parameter
M29DW323D
Unit70ns
Min Max
VCC Supply Voltage 2.7 3.6 V
Ambient Operating Temperature –40 85 °C
Load Capacitance (CL)30 pF
Input Rise and Fall Times 10 ns
Input Pulse Voltages 0 to VCC V
Input and Output Timing Ref. Voltages VCC/2 V
AI05557
VCC
0V
VCC/2
AI05558
CL
CL includes JIG capacitance
DEVICE
UNDER
TEST
25kΩ
VCC
25kΩ
VCC
0.1µF
VPP
0.1µF
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6pF
COUT Output Capacitance VOUT = 0V 12 pF
25/51
M29DW323DT, M29DW323DB
Table 14. DC Characteristics
Note: 1. Sampled only, not 100% tested.
2. In Dual op erations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase).
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA
ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA
ICC1(2) Supply Current (Read) E = VIL, G = VIH,
f = 6MHz 10 mA
ICC2 Supply Current (Standby) E = VCC ±0.2V,
RP = VCC ±0.2V 100 µA
ICC3 (1,2) Supply Current (Program/
Erase) Program/Erase
Controller active
VPP/WP =
VIL or VIH 20 mA
VPP/WP = VPP 20 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7VCC VCC +0.3 V
VPP Voltage for VPP/WP Program
Acceleration VCC = 2.7V ±10% 11.5 12.5 V
IPP Current for VPP/WP Program
Acceleration VCC = 2.7V ±10% 15 mA
VOL Output Low Voltage IOL = 1.8mA 0.45 V
VOH Output High Voltage IOH = –100µAVCC –0.4 V
VID Identification Voltage 11.5 12.5 V
VLKO Program/Erase Lockout Supply
Voltage 1.8 2.3 V
M29DW323DT, M29DW323DB
26/51
Figure 11. Read Mode AC Waveforms
Table 15. Read AC Characteristics
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter Test Condition M29DW323D Unit
tAVAV tRC Address Valid to Next Address Valid E = VIL,
G = VIL Min 70 ns
tAVQV tACC Address Valid to Output Valid E = VIL,
G = VIL Max 70 ns
tELQX (1) tLZ Chip Enable Low to Output T ransition G = VIL Min 0 ns
tELQV tCE Chip Enable Low to Output Valid G = VIL Max 70 ns
tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 ns
tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 ns
tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 25 ns
tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 25 ns
tEHQX
tGHQX
tAXQX tOH Chip Enable, Output Enable or Address
Transition to Output Transition Min 0 ns
tELBL
tELBH tELFL
tELFH Chip Enable to BYTE Low or High Max 5 ns
tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 ns
tBHQV tFHQV BYTE High to Output Valid Max 30 ns
AI05559
tAVAV
tAVQV tAXQX
tELQX tEHQZ
tGLQV
tGLQX tGHQX
VALID
A0-A20/
A–1
G
DQ0-DQ7/
DQ8-DQ15
E
tELQV tEHQX
tGHQZ
VALID
tBHQV
tELBL/tELBH tBLQZ
BYTE
27/51
M29DW323DT, M29DW323DB
Figure 12. Write AC Waveforms, Write Enable Controlled
Table 16. Write AC Characteristics, Write Enable Controlled
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter M29DW323D Unit
tAVAV tWC Address Valid to Next Address Valid Min 70 ns
tELWL tCS Chip Enable Low to Write Enable Low Min 0 ns
tWLWH tWP Write Enable Low to Write Enable High Min 45 ns
tDVWH tDS Input Valid to Write Enable High Min 45 ns
tWHDX tDH Write Enable High to Input Transition Min 0 ns
tWHEH tCH Write Enable High to Chip Enable High Min 0 ns
tWHWL tWPH Write Enable High to Write Enable Low Min 30 ns
tAVWL tAS Address Valid to Write Enable Low Min 0 ns
tWLAX tAH Write Enable Low to Address Transition Min 45 ns
tGHWL Output Enable High to Write Enable Low Min 0 ns
tWHGL tOEH Write Enable High to Output Enable Low Min 0 ns
tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 ns
tVCHEL tVCS VCC High to Chip Enable Low Min 50 µs
AI05560
E
G
W
A0-A20/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWHtGHWL
RB
tWHRL
M29DW323DT, M29DW323DB
28/51
Figure 13. Write AC Waveforms, Chip Enable Controlled
Table 17. Write AC Characteristics, Chip Enable Controlled
Note: 1. Sampled only, not 100% tested.
Symbol Alt Parameter M29DW323D Unit
tAVAV tWC Address Valid to Next Address Valid Min 70 ns
tWLEL tWS Write Enable Low to Chip Enable Low Min 0 ns
tELEH tCP Chip Enable Low to Chip Enable High Min 45 ns
tDVEH tDS Input Valid to Chip Enable High Min 45 ns
tEHDX tDH Chip Enable High to Input Transition Min 0 ns
tEHWH tWH Chip Enable High to Write Enable High Min 0 ns
tEHEL tCPH Chip Enable High to Chip Enable Low Min 30 ns
tAVEL tAS Address Valid to Chip Enable Low Min 0 ns
tELAX tAH Chip Enable Low to Address Tr ansition Min 45 ns
tGHEL Output Enable High Chip Enable Low Min 0 ns
tEHGL tOEH Chip Enable High to Output Enable Low Min 0 ns
tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 ns
tVCHWL tVCS VCC High to Write Enable Low Min 50 µs
AI0556
1
E
G
W
A0-A20/
A–1
DQ0-DQ7/
DQ8-DQ15
VALID
VALID
VCC
tVCHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEHtGHEL
RB
tEHRL
29/51
M29DW323DT, M29DW323DB
Figure 14. Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled
Note: 1. The Togg le bit is output on DQ6.
2. The Alternative Toggle bit is output on DQ2.
Figure 15. Toggle and Alternative Togg le Bits Mechanism, Output Enable Controlled
Note: 1. The Togg le bit is output on DQ6.
2. The Alternative Toggle bit is output on DQ2.
Table 18. Toggle and Alternative Toggle Bits AC Characteristics
Note: tELQV and tGLQV values are presented in Table 15., Read AC Characteristics.
Symbol Alt Parameter M29DW323D Unit
tAXEL Address Transition to Chip Enable Low Min 10 ns
tAXGL Address Transition to Output Enable Low Min 10 ns
AI08914c
G
A0-A20
DQ2
(1)
/DQ6
(2)
E
tAXEL
tELQV
Data Data
Alternative Toggle/
Toggle Bit
tELQV
Address in the Bank
Being Programmed or Erased
Read Operation outside the Bank
Being Programmed or Erased
Address Outside the Bank
Being Programmed or Erased
Address Outside the Bank
Being Programmed or Erased
Alternative Toggle/
Toggle Bit
Read Operation Outside the Ban
k
Being Programmed or Erased
Read Operation in the Bank
Being Programmed or Erased
AI08915c
G
A0-A20
DQ2
(1)
/DQ6
(2)
E
tAXGL
tGLQV
Data Data
Alternative Toggle/
Toggle Bit
tGLQV
Address in the Bank
Being Programmed or Erased
Read Operation outside the Bank
Being Programmed or Erased
Address Outside the Bank
Being Programmed or Erased
Address Outside the Bank
Being Programmed or Erased
Alternative Toggle/
Toggle Bit
Read Operation Outside the Ban
k
Being Programmed or Erased
Read Operation in the Bank
Being Programmed or Erased
M29DW323DT, M29DW323DB
30/51
Figure 16. Reset/Block Temporary Unprotect AC Waveforms
Table 19. Reset/Block Temporary Unprotect AC Characteristics
Note: 1. Sampled only, not 100% tested.
Figure 17. Accelerated Program Timing Waveforms
Symbol Alt Parameter M29DW323D Unit
tPHWL (1)
tPHEL
tPHGL (1) tRH RP High to Write Enable Low, Chip Enable Low,
Output Enable Low Min 50 ns
tRHWL (1)
tRHEL (1)
tRHGL (1) tRB RB High to Write Enable Low, Chip Enable Low,
Output Enable Low Min 0 ns
tPLPX tRP RP Pulse Width Min 500 ns
tPLYH tREADY RP Low to Read Mode Max 50 µs
tPHPHH (1) tVIDR RP Rise Time to VID Min 500 ns
tVHVPP (1) VPP Rise and Fall Time Min 250 ns
AI02931B
RB
W,
RP tPLPX
tPHWL, tPHEL, tPHGL
tPLYH
tPHPHH
E, G
tRHWL, tRHEL, tRHGL
AI05563
VPP/WP
VPP
VIL or VIH tVHVPP tVHVPP
31/51
M29DW323DT, M29DW323DB
PACKAGE MECHANICAL
Figure 18. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline
Note: Drawing not to scale.
Table 20. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.100 0.050 0.150 0.0039 0.0020 0.0059
A2 1.000 0.950 1.050 0.0394 0.0374 0.0413
B 0.220 0.170 0.270 0.0087 0.0067 0.0106
C 0.100 0.210 0.0039 0.0083
CP 0.080 0.0031
D1 12.000 11.900 12.100 0.4724 0.4685 0.4764
E 20.000 19.800 20.200 0.7874 0.7795 0.7953
E1 18.400 18.300 18.500 0.7244 0.7205 0.7283
e 0.500 – – 0.0197 – –
L 0.600 0.500 0.700 0.0236 0.0197 0.0276
L1 0.800 0.0315
α305305
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
M29DW323DT, M29DW323DB
32/51
Figure 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline
Note: Drawing not to scale.
Table 21. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.260 0.0102
A2 0.900 0.0354
b 0.350 0.450 0.0138 0.0177
D 6.000 5.900 6.100 0.2362 0.2323 0.2402
D1 4.000 – – 0.1575 – –
ddd 0.100 0.0039
E 8.000 7.900 8.100 0.3150 0.3110 0.3189
E1 5.600 – – 0.2205 – –
e 0.800 – – 0.0315 – –
FD 1.000 – – 0.0394 – –
FE 1.200 – – 0.0472 – –
SD 0.400 – – 0.0157 – –
SE 0.400 – – 0.0157 – –
E1E
D1
D
eb
A2
A1
A
BGA-Z32
ddd
FD
FE SD
SE
e
BALL "A1"
33/51
M29DW323DT, M29DW323DB
PART NUMBERING
Table 22. Ordering Information Scheme
Note: This product is also available with the Extended Block factory locked. For further details and ordering
informatio n contact your nearest Numonyx sales office.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,
please contact the Numonyx Sales Office nearest to you.
Example: M29DW323DB 70 N 1 T
Device Type
M29
Architecture
D = Dual Operation
Operating Voltage
W = VCC = 2.7 to 3.6V
Device Function
323D = 32 Mbit (x8/x16), Boot Block, 1/4-3/4 partitioning
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70 ns
7A = Automotive -40C to 85C Certified, available only in
conjuction with Temperature Range Option 6
Package
N = TSOP48: 12 x 20 mm
ZE = TFBGA48: 6 x 8mm, 0.8mm pitch
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing
M29DW323DT, M29DW323DB
34/51
APPENDIX A. BLOCK ADDRESSES
Table 23. Top Boot Block Addresse s, M29DW323DT
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
Bank B
0 64/32 Protection Group 000000h–00FFFFh 000000h–07FFFh
1 64/32
Protection Group
010000h–01FFFFh 008000h–0FFFFh
2 64/32 020000h–02FFFFh 010000h–17FFFh
3 64/32 030000h–03FFFFh 018000h–01FFFFh
4 64/32
Protection Group
040000h–04FFFFh 020000h–027FFFh
5 64/32 050000h–05FFFFh 028000h–02FFFFh
6 64/32 060000h–06FFFFh 030000h–037FFFh
7 64/32 070000h–07FFFFh 038000h–03FFFFh
8 64/32
Protection Group
080000h–08FFFFh 040000h–047FFFh
9 64/32 090000h–09FFFFh 048000h–04FFFFh
10 64/32 0A0000h–0AFFFFh 050000h–057FFFh
11 64/32 0B0000h–0BFFFFh 058000h–05FFFFh
12 64/32
Protection Group
0C0000h–0CFFFFh 060000h–067FFFh
13 64/32 0D0000h–0DFFFFh 068000h–06FFFFh
14 64/32 0E0000h–0EFFFFh 070000h–077FFFh
15 64/32 0F0000h–0FFFFFh 078000h–07FFFFh
16 64/32
Protection Group
100000h–10FFFFh 080000h–087FFFh
17 64/32 110000h–11FFFFh 088000h–08FFFFh
18 64/32 120000h–12FFFFh 090000h–097FFFh
19 64/32 130000h–13FFFFh 098000h–09FFFFh
20 64/32
Protection Group
140000h–14FFFFh 0A0000h–0A7FFFh
21 64/32 150000h–15FFFFh 0A8000h–0AFFFFh
22 64/32 160000h–16FFFFh 0B0000h–0B7FFFh
23 64/32 170000h–17FFFFh 0B8000h–0BFFFFh
24 64/32
Protection Group
180000h–18FFFFh 0C0000h–0C7FFFh
25 64/32 190000h–19FFFFh 0C8000h–0CFFFFh
26 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh
27 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh
28 64/32
Protection Group
1C0000h–1CFFFFh 0E0000h–0E7FFFh
29 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh
30 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh
31 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh
35/51
M29DW323DT, M29DW323DB
Bank B
32 64/32
Protection Group
200000h–20FFFFh 100000h–107FFFh
33 64/32 210000h–21FFFFh 108000h–10FFFFh
34 64/32 220000h–22FFFFh 110000h–117FFFh
35 64/32 230000h–23FFFFh 118000h–11FFFFh
36 64/32
Protection Group
240000h–24FFFFh 120000h–127FFFh
37 64/32 250000h–25FFFFh 128000h–12FFFFh
38 64/32 260000h–26FFFFh 130000h–137FFFh
39 64/32 270000h–27FFFFh 138000h–13FFFFh
40 64/32
Protection Group
280000h–28FFFFh 140000h–147FFFh
41 64/32 290000h–29FFFFh 148000h–14FFFFh
42 64/32 2A0000h–2AFFFFh 150000h–157FFFh
43 64/32 2B0000h–2BFFFFh 158000h–15FFFFh
44 64/32
Protection Group
2C0000h–2CFFFFh 160000h–167FFFh
45 64/32 2D0000h–2DFFFFh 168000h–16FFFFh
46 64/32 2E0000h–2EFFFFh 170000h–177FFFh
47 64/32 2F0000h–2FFFFFh 178000h–17FFFFh
Bank A
48 64/32
Protection Group
300000h–30FFFFh 180000h–187FFFh
49 64/32 310000h–31FFFFh 188000h–18FFFFh
50 64/32 320000h–32FFFFh 190000h–197FFFh
51 64/32 330000h–33FFFFh 198000h–19FFFFh
52 64/32
Protection Group
340000h–34FFFFh 1A0000h–1A7FFFh
53 64/32 350000h–35FFFFh 1A8000h–1AFFFFh
54 64/32 360000h–36FFFFh 1B0000h–1B7FFFh
55 64/32 370000h–37FFFFh 1B8000h–1BFFFFh
56 64/32
Protection Group
380000h–38FFFFh 1C0000h–1C7FFFh
57 64/32 390000h–39FFFFh 1C8000h–1CFFFFh
58 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh
59 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh
60 64/32
Protection Group
3C0000h–3CFFFFh 1E0000h–1E7FFFh
61 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh
62 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
M29DW323DT, M29DW323DB
36/51
Note: 1. Used as the Extended Block Addresses in Extended Block mode.
Bank A
63 8/4 Protection Group 3F0000h–3F1FFFh(1) 1F8000h–1F8FFFh(1)
64 8/4 Protection Group 3F2000h–3F3FFFh(1) 1F9000h–1F9FFFh(1)
65 8/4 Protection Group 3F4000h–3F5FFFh(1) 1FA000h–1FAFFFh(1)
66 8/4 Protection Group 3F6000h–3F7FFFh(1) 1FB000h–1FBFFFh(1)
67 8/4 Protection Group 3F8000h–3F9FFFh(1) 1FC000h–1FCFFFh(1)
68 8/4 Protection Group 3FA000h–3FBFFFh(1) 1FD000h–1FDFFFh(1)
69 8/4 Protection Group 3FC000h–3FDFFFh(1) 1FE000h–1FEFFFh(1)
70 8/4 Protection Group 3FE000h–3FFFFFh(1) 1FF000h–1FFFFFh(1)
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
37/51
M29DW323DT, M29DW323DB
Table 24. Bottom Boot Block Addresses, M29DW323DB
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
Bank A
0 8/4 Protection Group 000000h-001FFFh(1) 000000h–000FFFh(1)
1 8/4 Protection Group 002000h-003FFFh(1) 001000h–001FFFh(1)
2 8/4 Protection Group 004000h-005FFFh(1) 002000h–002FFFh(1)
3 8/4 Protection Group 006000h-007FFFh(1) 003000h–003FFFh(1)
4 8/4 Protection Group 008000h-009FFFh(1) 004000h–004FFFh(1)
5 8/4 Protection Group 00A000h-00BFFFh(1) 005000h–005FFFh(1)
6 8/4 Protection Group 00C000h-00DFFFh(1) 006000h–006FFFh(1)
7 8/4 Protection Group 00E000h-00FFFFh(1) 007000h–007FFFh(1)
8 64/32
Protection Group
010000h-01FFFFh 008000h–00FFFFh
9 64/32 020000h-02FFFFh 010000h–017FFFh
10 64/32 030000h-03FFFFh 018000h–01FFFFh
11 64/32
Protection Group
040000h-04FFFFh 020000h–027FFFh
12 64/32 050000h-05FFFFh 028000h–02FFFFh
13 64/32 060000h-06FFFFh 030000h–037FFFh
14 64/32 070000h-07FFFFh 038000h–03FFFFh
15 64/32
Protection Group
080000h-08FFFFh 040000h–047FFFh
16 64/32 090000h-09FFFFh 048000h–04FFFFh
17 64/32 0A0000h-0AFFFFh 050000h–057FFFh
18 64/32 0B0000h-0BFFFFh 058000h–05FFFFh
19 64/32
Protection Group
0C0000h-0CFFFFh 060000h–067FFFh
20 64/32 0D0000h-0DFFFFh 068000h–06FFFFh
21 64/32 0E0000h-0EFFFFh 070000h–077FFFh
22 64/32 0F0000h-0FFFFFh 078000h–07FFFFh
Bank B
23 64/32
Protection Group
100000h-10FFFFh 080000h–087FFFh
24 64/32 110000h-11FFFFh 088000h–08FFFFh
25 64/32 120000h-12FFFFh 090000h–097FFFh
26 64/32 130000h-13FFFFh 098000h–09FFFFh
27 64/32
Protection Group
140000h-14FFFFh 0A0000h–0A7FFFh
28 64/32 150000h-15FFFFh 0A8000h–0AFFFFh
29 64/32 160000h-16FFFFh 0B0000h–0B7FFFh
30 64/32 170000h-17FFFFh 0B8000h–0BFFFFh
M29DW323DT, M29DW323DB
38/51
Bank B
31 64/32
Protection Group
180000h-18FFFFh 0C0000h–0C7FFFh
32 64/32 190000h-19FFFFh 0C8000h–0CFFFFh
33 64/32 1A0000h-1AFFFFh 0D0000h–0D7FFFh
34 64/32 1B0000h-1BFFFFh 0D8000h–0DFFFFh
35 64/32
Protection Group
1C0000h-1CFFFFh 0E0000h–0E7FFFh
36 64/32 1D0000h-1DFFFFh 0E8000h–0EFFFFh
37 64/32 1E0000h-1EFFFFh 0F0000h–0F7FFFh
38 64/32 1F0000h-1FFFFFh 0F8000h–0FFFFFh
39 64/32
Protection Group
200000h-20FFFFh 100000h–107FFFh
40 64/32 210000h-21FFFFh 108000h–10FFFFh
41 64/32 220000h-22FFFFh 110000h–117FFFh
42 64/32 230000h-23FFFFh 118000h–11FFFFh
43 64/32
Protection Group
240000h-24FFFFh 120000h–127FFFh
44 64/32 250000h-25FFFFh 128000h–12FFFFh
45 64/32 260000h-26FFFFh 130000h–137FFFh
46 64/32 270000h-27FFFFh 138000h–13FFFFh
47 64/32
Protection Group
280000h-28FFFFh 140000h–147FFFh
48 64/32 290000h-29FFFFh 148000h–14FFFFh
49 64/32 2A0000h-2AFFFFh 150000h–157FFFh
50 64/32 2B0000h-2BFFFFh 158000h–15FFFFh
51 64/32
Protection Group
2C0000h-2CFFFFh 160000h–167FFFh
52 64/32 2D0000h-2DFFFFh 168000h–16FFFFh
53 64/32 2E0000h-2EFFFFh 170000h–177FFFh
54 64/32 2F0000h-2FFFFFh 178000h–17FFFFh
55 64/32
Protection Group
300000h-30FFFFh 180000h–187FFFh
56 64/32 310000h-31FFFFh 188000h–18FFFFh
57 64/32 320000h-32FFFFh 190000h–197FFFh
58 64/32 330000h-33FFFFh 198000h–19FFFFh
59 64/32
Protection Group
340000h-34FFFFh 1A0000h–1A7FFFh
60 64/32 350000h-35FFFFh 1A8000h–1AFFFFh
61 64/32 360000h-36FFFFh 1B0000h–1B7FFFh
62 64/32 370000h-37FFFFh 1B8000h–1BFFFFh
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
39/51
M29DW323DT, M29DW323DB
Note: 1. Used as the Extended Block Addresses in Extended Block mode.
Bank B
63 64/32
Protection Group
380000h-38FFFFh 1C0000h–1C7FFFh
64 64/32 390000h-39FFFFh 1C8000h–1CFFFFh
65 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh
66 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh
67 64/32
Protection Group
3C0000h-3CFFFFh 1E0000h–1E7FFFh
68 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh
69 64/32 3E0000h-3EFFFFh 1F0000h–1F7FFFh
70 64/32 Protection Group 3F0000h-3FFFFFh 1F8000h–1FFFFFh
Bank
Block (Kbytes/
Kwords) Protection Block
Group (x8) (x16)
M29DW323DT, M29DW323DB
40/51
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC ap-
proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem-
ory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when
necessary.
When the CFI Query Command is issued the de-
vice enters CFI Query mode and the data structure
is read from the memory. Tables 25, 26, 27, 28, 29
and 30 show the addresses used to retrieve the
data.
The CFI data structure also contains a security
area where a 6 4 bit unique security number is wri t-
ten (see Table 30., Security Code Area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the securit y num-
ber after it has been written by Numonyx.
Table 25. Query Structure Overview
Note: Query data are always presented on the lowest order data outputs.
Table 26. CFI Query Identification String
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘ 0’.
Address Sub-section Name Description
x16 x8
10h 20h CFI Query Identification String C ommand set ID and algorithm data offset
1Bh 36h System Interface Information Device timing & voltage information
27h 4Eh Device Geometry Definition Flash device layout
40h 80h Primary Algorithm-specific Extended
Query table Additional information specific to the Primary
Algorithm (optional)
61h C2h Security Code Area 64 bit unique device number
Address Data Description Value
x16 x8
10h 20h 0051h “Q”
11h 22h 0052h Query Unique ASCII String "QRY" "R"
12h 24h 0059h "Y"
13h 26h 0002h Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm AMD
Compatible
14h 28h 0000h
15h 2Ah 0040h Address for Primary Algorithm extended Query table (see Table 29.) P = 40h
16h 2Ch 0000h
17h 2Eh 0000h Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported NA
18h 30h 0000h
19h 32h 0000h Address for Alternate Algorithm extended Query table NA
1Ah 34h 0000h
41/51
M29DW323DT, M29DW323DB
Table 27. CFI Query System Interface Information
Table 28. Device Geometry Definition
Note: For the M29DW323DB, Region 1 corresponds to addresses 000000h to 007FFFh and Region 2 to addresses 008000h to 1FFFFFh.
For the M29DW323DT, Region 1 co rresponds to a ddresses 1F8000h to 1FFFFFh and Region 2 to addresses 000000h to 1F7FFFh.
Address Data Description Value
x16 x8
1Bh 36h 0027h VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV 2.7V
1Ch 38h 0036h VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV 3.6V
1Dh 3Ah 00B5h VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV 11.5V
1Eh 3Ch 00C5h VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV 12.5V
1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs 16µs
20h 40h 0000h Typical timeout for minimum size write buffer program = 2n µs NA
21h 42h 000Ah T ypical timeout per individual block erase = 2n ms 1s
22h 44h 0000h Typical timeout for full Chip Erase = 2n ms NA
23h 46h 0004h Maximum timeout for byte/word program = 2n times typical 256 µs
24h 48h 0000h Maximum timeout for write buffer program = 2n times typical NA
25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical 8s
26h 4Ch 0000h Maximum timeout for Chip Erase = 2n times typical NA
Address Data Description Value
x16 x8
27h 4Eh 0016h Device Size = 2n in number of bytes 4 MByte
28h
29h 50h
52h 0002h
0000h Flash Device Interface Code description x8, x16
Async.
2Ah
2Bh 54h
56h 0000h
0000h Maximum number of bytes in multi-byte program or page = 2n NA
2Ch 58h 0002h Number of Erase Block Regions. It specifie s the number of
regions containing contiguous Erase Blocks of the same size. 2
2Dh
2Eh 5Ah
5Ch 0007h
0000h Region 1 Information
Number of Erase Blocks of identical size = 0007h+1 8
2Fh
30h 5Eh
60h 0020h
0000h Region 1 Information
Block size in Region 1 = 0020h * 256 byte 8Kbyte
31h
32h 62h
64h 003Eh
0000h Region 2 Information
Number of Erase Blocks of identical size = 003Eh+1 63
33h
34h 66h
68h 0000h
0001h Region 2 Information
Block size in Region 2 = 0100h * 256 byte 64Kbyte
M29DW323DT, M29DW323DB
42/51
Table 29. Primary Algorithm-Specific Extended Query Table
Table 30. Security Code Area
Address Data Description Value
x16 x8
40h 80h 0050h
Primary Algorithm extended Query table unique ASCII st ring “PRI”
"P"
41h 82h 0052h "R"
42h 84h 0049h "I"
43h 86h 0031h Major version number, ASCII "1"
44h 88h 0030h Minor version number, ASCII "0"
45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
Yes
46h 8Ch 0002h Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write 2
47h 8Eh 0001h Block Protection
00 = not supported, x = number of blocks in per group 1
48h 90h 0001h Temporary Block Unprotect
00 = not supported, 01 = supported Yes
49h 92h 0004h Block Protect /Unprotect
04 = M29DW323D 04
4Ah 94h 0030h Simultaneous Operations,
x = number of blocks in Bank B 48
4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No
4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No
4Dh 9Ah 00B5h VPP Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
11.5V
4Eh 9Ch 00C5h VPP Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
12.5V
4Fh 9Eh 000xh Top/Bottom Boot Block Flag
02h = Bottom Boot device, 03h = Top Boot device –
Address Data Description
x16 x8
61h C3h, C2h XXXX
64 bit: unique device number
62h C5h, C4h XXXX
63h C7h, C6h XXXX
64h C9h, C8h XXXX
43/51
M29DW323DT, M29DW323DB
APPENDIX C. EXTENDED MEMORY BLOCK
The M29DW323D has an extra block, the Extend-
ed Block, that can be accessed using a dedicated
command.
This Extended Block is 32 KWords in x16 mode
and 64 KBytes in x8 mode. It is used as a security
block (to provide a permanent security identifica-
tion number) or to store additional information.
The Extended Block is either Factory Locked or
Customer Lockable, its status is indicated by bit
DQ7. This bit is permanently set to either ‘1’ or ‘0’
at the factory and cannot be changed. When set to
‘1’, it indicates that the device is factory locked and
the Extended Block is protec ted. When set to ‘0’, it
indicates that the device is customer lockable and
the Extended Block is unprot ected. Bit DQ7 being
permanently locked to either ‘1’ or ‘0’ is another
security feature which ensures that a customer
lockable device cannot b e used instead of a facto-
ry locked one.
Bit DQ7 is the most significant bit in the Extended
Block Verify Code and a specific procedure must
be followed to read it. See “Extended Memory
Block Verify Code” in Tables 3 and 4, Bus Opera-
tions, BYTE = VIL and Bus Operations, BYTE =
VIH, respectively, for details of how to read bit
DQ7.
The Extended Block can only be accessed when
the device is in Extended Block mode. For details
of how the Extended Block mode is entered and
exited, refer to the Enter Extended Block Com-
mand and Exit Extended Block Command para-
graphs, and to Tables 5 and 6, “Commands, 16-bit
mode, BYTE = VIH” and “Commands, 8-bit mode,
BYTE = VIL”, respectively.
Factory Locked Extended Block
In devices where the Extended Block is factory
locked, the Security Identification Number is writ-
ten to the Extended Block address space (see Ta-
ble 31., Extended Block Address and Data) in the
factory. The DQ7 bit is set to ‘1’ and the Extended
Block cannot be unprotected.
Customer Lockable Extended Block
A device where the Extended Block is customer
lockable is delivered with the DQ7 bit set to ‘0’ and
the Extended Block unprotected. It is up to the
customer to program and protect the Extended
Block but care must be taken because the protec-
tion of the Extended Block is not reversible.
There are two ways of protecting the Extended
Block:
Issue the Enter Extended Block command to
place the device in Extended Block mode,
then use the In-System Technique with RP
either at VIH or at VID (refer to APPENDIX D.,
In-System Technique and to the
corresponding flowchar ts, Figures 22 and 23,
for a detailed explanation of the technique).
Issue the Enter Extended Block command to
place the device in Extended Block mode,
then use the Pro grammer Te chnique (r efer to
APPENDIX D., Programmer Technique and to
the corresponding flowcharts, Figu res 20 and
21, for a detailed explanation of the
technique).
Once the Extended Block is programmed and pro-
tected, the Exit Extended Block co mmand must be
issued to exit the Exten ded Block mode and return
the device to Read mode.
Table 31. Extended Block Address and Data
Note: 1. See Tables 23 and 24, Top and Bott om Boot Block Addr esses.
Device Address(1) Data
x8 x16 Factory Locked Customer Lockable
M29DW323DT 3F0000h-3F000Fh 1F8000h-1F8007h Security Identification
Number Determined by
Customer
3F0010h-3FFFFFh 1F8008h-1FFFFFh Unavailable
M29DW323DB 000000h-00000Fh 000000h-000007h Security Identification
Number Determined by
Customer
000010h-00FFFFh 000008h-007FFFh Unavailable
M29DW323DT, M29DW323DB
44/51
APPENDIX D. BLOCK PROTECTION
Block protection can be used to prevent any oper-
ation from modifying the data stored in the memo-
ry. The blocks are protected in groups, refer to
APPENDIX A., Tables 23 and 24 for details of the
Protection Groups. Once prot ected, Program and
Erase operations within the protecte d group fail to
change the data.
There are three techniques that can be used to
control Block Protection, these are the Program-
mer technique, the In-System technique and Tem-
porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro-
tection pin, RP; this is described in the Signal De-
scriptions section.
Programmer Technique
The Programmer technique uses high (VID) volt-
age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.
To protect a g roup of blocks follow th e flowchart in
Figure 20., Programmer Equ ipment Group Protect
Flowchart. To unprote ct the whole chip it is neces-
sary to protect all of the groups first, then all
groups can be unprotected at the same time. To
unprotect the chip follow Figure 21., Programmer
Equipment Chip Unprotect Flowchart. Table
32., Programmer Technique Bus Operations,
BYTE = VIH or VIL, gives a summary of each op-
eration.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.
In-System Technique
The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect
pin, RP(1). This can be achieved without violating
the maximum ratings of the components on the mi-
croprocessor bus, therefore this technique is suit-
able for use after the memory has been fitted to
the system.
To protect a group of bl ocks follow the flowchart in
Figure 22., In-System Equipment Group Protect
Flowchart. To unprotect the whole chip it is neces-
sary to protect all of the groups first, then all the
groups can be unprotected at the same time. To
unprotect the chip follow Figure 23., In-System
Equipment Chip Un pr ot ec t Flo wch a rt.
The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the pro-
cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.
Note: 1. RP can be ei ther at VIH or at VID when using the In-Sys-
tem Technique to protect the Extended Block.
Table 32. Programmer Technique Bu s Operations, BYTE = VIH or VIL
Note: 1. Block Protection Groups are shown in APPENDIX A., Tables 23 and 24.
Operation E G W Address Inputs
A0-A20 Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Block (Group)
Protect(1) VIL VID VIL Pulse A9 = VID, A12-A20 Block Address
Others = X X
Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = V IH, A15 = VIH
Others = X X
Block (Group)
Protection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,
A12-A20 Block Address
Others = X
Pass = XX01h
Retry = XX00h
Block (Group)
Unprotection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,
A12-A20 Block Address
Others = X
Retry = XX01h
Pass = XX00h
45/51
M29DW323DT, M29DW323DB
Figure 20. Programmer Equipment Group Protect Flowchart
Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.
ADDRESS = GROUP ADDRESS
AI05574
G, A9 = VID,
E = VIL
n = 0
Wait 4µs
Wait 100µs
W = VIL
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
A9 = VIH
E, G = VIH
++n
= 25
START
FAIL
PASS
YES
NO
DATA
=
01hYES
NO
W = VIH
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
Verify Protect Set-upEnd
A9 = VIH
E, G = VIH
M29DW323DT, M29DW323DB
46/51
Figure 21. Programmer Equipment Chip Unprotect Flowchart
Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.
PROTECT ALL GROUPS
AI05575
A6, A12, A15 = VIH(1)
E, G, A9 = VID
DATA
W = VIH
E, G = VIH
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1, A6 = VIH
Wait 10ms
=
00h
INCREMENT
CURRENT GROUP
n = 0
CURRENT GROUP = 0
Wait 4µs
W = VIL
++n
= 1000
START
YES
YESNO
NO LAST
GROUP
YES
NO
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
FAIL PASS
Verify Unprotect Set-upEnd
A9 = VIH
E, G = VIH A9 = VIH
E, G = VIH
47/51
M29DW323DT, M29DW323DB
Figure 22. In-System Equipment Group Protect Flowchart
Note: 1. Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.
2. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block.
AI05576
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
n = 0
Wait 100µs
WRITE 40h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
RP = VIH ++n
= 25
START
FAIL
PASS
YES
NO
DATA
=
01hYES
NO
RP = VIH
Wait 4µs
Verify Protect Set-upEnd
READ DATA
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
M29DW323DT, M29DW323DB
48/51
Figure 23. In-System Equipment Chip Unprotect Flowchart
Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.
AI05577
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
n = 0
CURRENT GROUP = 0
Wait 10ms
WRITE 40h
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
RP = VIH
++n
= 1000
START
FAIL PASS
YES
NO
DATA
=
00h
YESNO
RP = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
RP = VID
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
PROTECT ALL GROUPS
INCREMENT
CURRENT GROUP
LAST
GROUP
YES
NO
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Verify Unprotect Set-upEnd
49/51
M29DW323DT, M29DW323DB
REVISION HISTORY
Table 33. Document Revision History
Date Version Revision Details
20-Sep-2001 -01 First Issue (Target Specification)
26-Oct-2001 -02 Document expanded to full Product Preview
16-Jan-2002 -03 Corrections made in “Primary Algorithm-Specific Extended Query” Table in Appendix-B
19-Apr-2002 -04
Description of Ready/Busy signal clarified (and Figure 16. modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section
tPLYH (time to reset device) re-specified.
24-Apr-2002 -05 Values for addresses 23h and 25h corrected in CFI Query System Interface Information
table in Appendix B
19-Jul-2002 -06 When in Extended Block mode, the block at the boot block address can be used as
OTP. Data Toggle Flow chart corrected. Document promoted from “Product Preview” to
“Preliminary Data”.
08-Apr-2003 6.1
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot
(revision version 06 equals 6.0).
Revision History moved to end of document.
TFBGA48, 6 x 8mm, 0.80mm pitch package added. Identification Current IID removed
from Table 14., DC Characteristics. Erase Suspend Latency time and Data Retention
parameters and notes added to Table 7., Program, Erase Times and Program, Erase
Endurance Cycles.
APPENDIX C., EXTENDED MEMORY BLOCK, added. Auto Select Command sued to
read the Extended Memory Block. Extended Memory Block Verify Code row added to
Tables 3 and 4, Bus Operations, BYTE = VIL and Bus Operations, BYTE = VIH. Bank
Address modified in Auto Select Command. Chip Erase Address modified in Table 8.,
Status Register Bits. VSS pin connection to ground clarified. Note added to Table
22., Ordering Information Scheme.
07-May-2003 6.2 Table 20., TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical
Data, and Figure 18., TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom
View Package Outline, corrected.
25-Jun-2003 7.0 Document promoted from Preliminary Data to full Datasheet status. Packing option
added to Table 22., Ordering Information Scheme.
18-Sep-2003 7.1
Status of Ready/Busy signal for Erase Suspend Operation modified in Table 8., Status
Register Bits.
Figures 14 and 15, Toggle and Alternative Toggle Bits Mechanisms added.
Table 18., Toggle and Alternative Toggle Bits AC Characteristics, added.
Note 1 of Table 28., Device Geometry Definition, modified
07-Oct-2003 7.2
Figures 14 and 15, Toggle and Alternative Toggle Bits Mechanisms modified and Notes
1 and 2 added.
Table 18., Toggle and Alternative Toggle Bits AC Characteristics modified.
Figure 8. renamed and flowchart modified; Note added.
07-Nov-2003 7.3 St atus of Ready/Busy signal for Program Error , Chip Erase and Block Erase modified in
Table 8., Status Register Bits.
M29DW323DT, M29DW323DB
50/51
19-Dec-2003 7.4
VCC minimum value updated in Table 12. , Operating and AC Measurement Conditions.
VPP and IPP test conditions updated in Table 14., DC Characteristics.
Architecture option updated in Table 22. Ordering Information Scheme.
Block Protect/Unprotect code updated in APPENDIX B., Table 29.
Customer Lockable Extended Block mechanism modified in APPENDIX C., Extended
Memory Block.
APPENDIX D., Block Protection updated: Note 1 added in the In-System Technique
section and Note 2 added below Figure 22., In-System Equipment Group Protect
Flowchart.
23-Mar-2004 8.0 Introduction of the STATUS REGISTER chapter clarified.
12-July-2004 9.0 90ns speed class removed from datasheet.
12-Aug-2004 10.0 Section , DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE added.
27-Sep-2004 11.0 TFBGA63 package removed.
10-Dec-2004 12.0 St atus of Ready/Busy signal for Program Error , Chip Erase and Block Erase modified in
Table 8., Status Register Bits.
14-Mar-2005 13.0 RB updated in Table 8., Status Register Bits.
Fast Program Commands restructured and updated.
Unlock Bypass Command updated.
27-Mar-2008 14.0 Applied Numonyx branding.
1-March-2010 15.0
Added the following:
– to cover page: “Automotive Certified Parts Available”
– to Ordering Information Scheme Table: “7A = Autom otive -40C to 85C Certified,
available only in conjuction with Temperature Range Option 6”
Date Version Revision Details
51/51
M29DW323DT, M29DW323DB
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