Vishay Siliconix
DG406, DG407
Document Number: 70061
S11-0179-Rev. J, 07-Feb-11
www.vishay.com
1
16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers
FEATURES
• Low on-resistance - RDS(on): 50
• Low charge injection - Q: 15 pC
• Fast transition time - tTRANS: 200 ns
• Low power: 0.2 mW
• Single supply capability
• 44 V supply max. rating
BENEFITS
• Higher accuracy
• Reduced glitching
• Improved data throughput
• Reduced power consumption
• Increased ruggedness
• Wide supply ranges: ± 5 V to ± 20 V
APPLICATIONS
• Data acquisition systems
• Audio signal routing
• Medical instrumentation
• ATE systems
• Battery powered systems
• High-rel systems
• Single supply systems
DESCRIPTION
The DG406 is a 16 channel single-ended analog multiplexer
designed to connect one of sixteen inputs to a common
output as determined by a 4-bit binary address. The DG407
selects one of eight differential inputs to a common
differential output. Break-before-make switching action
protects against momentary shorting of inputs.
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up
to the power supply rails. An enable (EN) function allows the
user to reset the multiplexer/demultiplexer to all switches off
for stacking several devices. All control inputs, address (Ax)
and enable (EN) are TTL compatible over the full specified
operating temperature range.
Applications for the DG406, DG407 include high speed data
acquisition, audio signal switching and routing, ATE
systems, and avionics. High performance and low power
dissipation make them ideal for battery operated and remote
instrumentation applications.
Designed in the 44 V silicon-gate CMOS process, the
absolute maximum voltage rating is extended to 44 V,
allowing operation with ± 20 V supplies. Additionally single
(12 V) supply operation is allowed. An epitaxial layer
prevents latchup.
For applications information please request documents
70601 and 70604.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
* Pb containing terminations are not RoHS compliant, exemptions may apply
V+
S11
S10
S9
NC
A3
D
S2
S1
GND
A1
A2
NC
Dual-In-Line and SOIC Wide-Body
A0
EN
V-
NC S8
S16 S7
S15 S6
S14 S5
S13 S4
S12 S3
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
Top View
920
10 19
11
12
18
17
13 16
14 15
DG406
Decoders/Drivers
DG407
V+
S3b
S2b
S1b
NC
NC
Da
S2a
S1a
GND
A1
A2
Db
Dual-In-Line and SOIC Wide-Body
A0
EN
V-
NC S8a
S8b S7a
S7b S6a
S6b S5a
S5b S4a
S4b S3a
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
Top View
9220
10 19
11
12
18
17
13 16
14 15
Decoders/Drivers
Available
Pb-free
RoHS*
COMPLIANT
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Document Number: 70061
S11-0179-Rev. J, 07-Feb-11
Vishay Siliconix
DG406, DG407
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Logic “0” = VAL 0.8 V
Logic “1” = VAH 2.4 V
X = Do not Care
Decoders/Drivers
7
8
9
5
20
19
21
22
23
24
25
1234
10
11
12 13 14 15 16 17 18
262728
Top View
6
PLCC and LCC
S13
S15
S5
S12 S4
S7
S11
S14 S6
S3
S10 S2
S9S1
SGND
NCNC
NC
3
V+
2
D
1
V-
0
SEN
DG406
A
A
A
A
16
8
S7b
S5a
S4b S4a
S7a
S3b
S6b S6a
S3a
S5b
S2b S2a
S1b S1a
PLCC and LCC
Top View
GND
NCNC
DNC
V+
D
V-
EN
S
2
1
0
S
A
A
A
8b
8a
b
a
DG407
Decoders/Drivers
7
8
9
5
20
19
21
22
23
24
25
1234
10
11
12 13 14 15 16 17 18
262728
6
TRUTH TABLE (DG406)
A3 A
2 A
1 A
0 EN On Switch
X X X X 0 None
0 0 0 0 1 1
0 0 0 1 1 2
0 0 1 0 1 3
0 0 1 1 1 4
0 1 0 0 1 5
0 1 0 1 1 6
0 1 1 0 1 7
0 1 1 1 1 8
1 0 0 0 1 9
1 0 0 1 1 10
1 0 1 0 1 11
1 0 1 1 1 12
1 1 0 0 1 13
1 1 0 1 1 14
1 1 1 0 1 15
1 1 1 1 1 16
TRUTH TABLE (DG407)
A2 A
1 A
0 EN On Switch Pair
X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8
ORDERING INFORMATION (DG406)
Temp. Range Package Part Number
- 40 °C to 85 °C
28-Pin Plastic DIP DG406DJ
DG406DJ-E3
28-Pin PLCC DG406DN
DG406DN-T1-E3
28-Pin Widebody SOIC DG406DW
DG406DW-E3
ORDERING INFORMATION (DG407)
Temp. Range Package Part Number
- 40 °C to 85 °C
28-Pin Plastic DIP DG407DJ
DG407DJ-E3
28-Pin PLCC DG407DN
DG407DN-T1-E3
28-Pin Widebody SOIC DG407DW
DG407DW-E3
Document Number: 70061
S11-0179-Rev. J, 07-Feb-11
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Vishay Siliconix
DG406, DG407
Notes:
a. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6 mW/°C above 75°C.
d. Derate 12 mW/°C above 75°C.
e. Derate 13.5 mW/°C above 75°C .
ABSOLUTE MAXIMUM RATINGS
Parameter Limit Unit
Voltages Referenced to V- V+ 44
V
GND 25
Digital Inputsa, VS, VD
(V-) - 2 to (V+) + 2 V
or 20 mA, whichever occurs first
Current (Any terminal) 30 mA
Peak Current, S or D (Pulsed at 1 ms, 10 % duty cycle max.) 100
Storage Temperature (AK, AZ Suffix) - 65 to 150 °C
(DJ, DN Suffix) - 65 to 125
Power Dissipation (Package)b
28-Pin Plastic DIPb625 mW
28-Pin CerDIPd1.2 W
28-Pin Plastic PLCCc450 mW
LCC-28e1.35 W
28-Pin Widebody SOIC 450 mW
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Document Number: 70061
S11-0179-Rev. J, 07-Feb-11
Vishay Siliconix
DG406, DG407
SPECIFICATIONSa
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V
VAL = 0.8 V, VAH = 2.4 VfTemp.b Typ.c
A Suffix
- 55 °C to 125 °C
D Suffix
- 40 °C to 85 °C
Unit Min.d Max.dMin.d Max.d
Analog Switch
Analog Signal RangeeVANALOG Full - 15 15 - 15 15 V
Drain-Source
On-Resistance RDS(on)
VD = ± 10 V, IS = - 10 mA
sequence each switch on
Room
Full 50 100
125
100
125
RDS(on) Matching Between
ChannelsgRDS(on) VD = ± 10 V Room 5 %
Source Off Leakage Current IS(off)
VEN = 0 V
VD = ± 10 V
VS = ± 10 V
Room
Full 0.01 - 0.5
- 50
0.5
50
- 0.5
- 5
0.5
5
nA
Drain Off Leakage Current ID(off)
DG406 Room
Full 0.04 - 1
- 200
1
200
- 1
- 40
1
40
DG407 Room
Full 0.04 - 1
- 100
1
100
- 1
- 20
1
20
Drain On Leakage Current ID(on)
VS = VD = ± 10
sequence each
switch on
DG406 Room
Full 0.04 - 1
- 200
1
200
- 1
- 40
1
40
DG407 Room
Full 0.04 - 1
- 100
1
100
- 1
- 20
1
20
Digital Control
Logic High Input Voltage VINH Full 2.4 2.4 V
Logic Low Input Voltage VINL Full 0.8 0.8
Logic High Input Current IAH VA = 2.4 V, 15 V Full - 1 1 - 1 1 µA
Logic Low Input Current IAL VEN = 0 V, 2.4 V, VA = 0 V Full - 1 1 - 1 1
Logic Input Capacitance Cin f = 1 MHz Room 7 pF
Dynamic Characteristics
Transition Time tTRANS see figure 2 Room
Full
200 350
450
350
450
ns
Break-Before-Make Interval tOPEN see figure 4 Room
Full
50 25
10
25
10
Enable Turn-On Time tON(EN)
see figure 3
Room
Full
150 200
400
200
400
Enable Turn-Off Time tOFF(EN)
Room
Full
70 150
300
150
300
Charge Injection Q VS = 0 V, CL = 1 nF, RS = 0 Room 15 pC
Off IsolationhOIRR VEN = 0 V, RL = 1 k
f = 100 kHz Room - 69 dB
Source Off Capacitance CS(off) VEN = 0 V, VS = 0 V, f = 1 MHz Room 8
pF
Drain Off Capacitance CD(off) VEN = 0 V
VD = 0 V
f = 1 MHz
Room 130
DG407 Room 65
Drain On Capacitance CD(on)
DG406 Room 140
DG407 Room 70
Power Supplies
Positive Supply Current I+
VEN = VA = 0 or 5 V
Room
Full
13 30
75
30
75
µA
Negative Supply Current I- Room
Full
- 0.01 - 1
- 10
- 1
- 10
Positive Supply Current I+
VEN = 2.4 V, VA = 0 V
Room
Full
50 500
900
500
700
Negative Supply Current I- Room
Full - 0.01 - 20
- 20
- 20
- 20
Document Number: 70061
S11-0179-Rev. J, 07-Feb-11
www.vishay.com
5
Vishay Siliconix
DG406, DG407
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. RDS(on) = RDS(on) max. - RDS(on) min.
h. Worst case isolation occurs on Channel 4 due to proximity to the drain pin.
Stresses beyond those listed under “A bsolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, an d functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONSa (for Single Supply)
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 12 V, V- = 0 V
VAL = 0.8 V, VAH = 2.4 VfTemp.b Typ.c
A Suffix
- 55 °C to 125 °C
D Suffix
- 40 °C to 85 °C
Unit Min.d Max.dMin.d Max.d
Analog Switch
Analog Signal RangeeVANALOG Full 0 12 0 12 V
Drain-Source
On-Resistance RDS(on) VD = 3 V, 10 V, IS = - 1 mA
sequence each switch on
Room 90 120 120
RDS(on) Matching Between
ChannelsgRDS(on) Room 5 %
Source Off Leakage Current IS(off) VEN = 0 V
VD = 10 V or 0.5 V
VS = 0.5 V or 10 V
Room 0.01
nA
Drain Off Leakage Current ID(off)
DG406 Room 0.04
DG407 Room 0.04
Drain On Leakage Current ID(on)
VS = VD = ± 10
sequence each
switch on
DG406 Room 0.04
DG407 Room 0.04
Dynamic Characteristics
Switching Time of Multiplexer tOPEN VS1 = 8 V, VS8 = 0 V, VIN = 2.4 V Room 300 450 450
nsEnable Turn-On Time tON(EN) VINH = 2.4 V, VINL = 0 V
VS1 = 5 V
Room 250 600 600
Enable Turn-Off Time tOFF(EN) Room 150 300 300
Charge Injection Q CL = 1 nF, VS = 6 V, RS = 0 Room 20 pC
Power Supplies
Positive Supply Current I+
VEN = 0 V or 5 V, VA = 0 V or 5 V
Room
Full
13 30
75
30
75 µA
Negative Supply Current I- Room
Full - 0.01 - 20
- 20
- 20
- 20
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Document Number: 70061
S11-0179-Rev. J, 07-Feb-11
Vishay Siliconix
DG406, DG407
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
RDS(on) vs. VD and Supply
RDS(on) vs. VD and Supply
ID , IS Leakages vs. Temperature
V
D
- Drain Voltage (V)
160
120
80
40
0
- 20 20 - 4- 12 4 12
±5 V
± 10 V
± 12 V
± 15 V
± 20 V
± 8 V
- On-Resistance (Ω)
RDS(on)
V
D
- Drain Voltage (V)
160
120
80
40
0
0204 8 12 16
V+ = 7.5 V
200
240 V- = 0 V
10 V
12 V
15 V
20 V 22 V
- On-Resistance (Ω)R
DS(on)
Temperature (°C)
- Current , I S
ID
V+ = 15 V
V- = - 15 V
V
D
= "14 V
I
D(on)
, I
D(of f)
I
S( of f)
100 nA
10 nA
1 nA
100 pA
10 pA
1 pA
0.1 pA
- 55 - 35 - 15 5 2 5 4 5 6 5 8 5 105 125
RDS(on) vs. VD and Temperature
ID , IS Leakage Currents vs. Analog Voltage
Switching Times vs. Bipolar Supplies
V
D
- Drain Voltage (V)
0
40
30
20
10
80
70
60
50
15105- 15 - 10 - 5 0
- 55 °C
- 40 °C
0 °C
25 °C
85 °C
125 °C
V+ = 15 V
V- = - 15 V
- On-Resistance (Ω)
RDS(on)
V
S
, V
D
- Source Drain Voltage (V)
- Current (pA), I S
ID
120
- 120
- 15 - 10 - 5 0 5 10 15
- 80
- 40
0
40
80
V+ = 15 V
V- = - 15 V
V
S
= - V
D
for I
D(of f)
V
D
= V
S(open)
for I
D(on)
DG406 I
D(on)
, I
D(of f)
I
S( of f)
DG407 I
D(on)
, I
D(of f)
V
SUPPL Y
- Supply Voltage (V)
Time (ns)
350
300
150
100
50
0
± 5 ± 10 ± 15 ± 20
200
250 t
TRA N S
t
ON(E N)
t
OFF(E N )
Document Number: 70061
S11-0179-Rev. J, 07-Feb-11
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Vishay Siliconix
DG406, DG407
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
Switching Times vs. Single Supply
Off-Isolation vs. Frequency
tON/tOFF vs. Temperature
V+ - Supply Voltage (V)
T ime (ns)
700
600
300
200
100
0
51 0 1 5 20
400
500
t
TRA N S
t
ON(E N)
t
OFF(E N )
V- = 0 V
f - Frequency (Hz)
ISOL (dB)
- 80
- 60
- 40
- 20
0
10K 100K 1M 10M
- 100
- 120
1K100
- 140
Temperature (°C)
Time (ns)
180
140
100
60
220
t
ON(E N)
t
OFF(E N )
t
TRA N S
260
300
V+ = 15 V
V- = - 15 V
- 55 - 35 125- 15 5 25 45 65 85 105
Charge Injection vs. Analog Voltage
Supply Currents vs. Switching Frequency
Switching Threshold vs. Supply Voltage
V
S
- Source Voltage (V)
Q (pC)
0
40
30
20
10
70
60
50
15 10 5 - 15 - 10 - 5 0
V+ = 15 V ,
V- = - 15 V
V+ = 12 V ,
V- = 0 V
f - Frequency (Hz)
I - Current (mA)
10
- 10
10 100 1K 10K 100K 1M 10M
0
4
6
IGND
2
8
I-
I+
E
N
= 5 V
A
X
= 0 or 5 V
- 8
- 6
- 4
- 2
VSUPPLY - Supply Voltage (V)
(V)V TH
3
1
0
510 1520
2
0
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Document Number: 70061
S11-0179-Rev. J, 07-Feb-11
Vishay Siliconix
DG406, DG407
SCHEMATIC DIAGRAM (Typical Channel)
TEST CIRCUITS
Figure 1.
EN
A0
GND
S1
V+
D
V+
Sn
V-
Decode/
Drive
Level
Shift
V-
V+
VREF
AX
Figure 2. Transition Time
Logic
Input
Switch
Output
V
S8
V
O
t
TRA N S
t
r
< 20 ns
t
f
< 20 ns
S
8
ON S
1
ON
t
TRA N S
0 V
V
S1
50 %
90 %
90 %
3 V
0 V
DG406
S
1b
S
8b
A
2
D
b
A
1
*
A
0
* = S1a - S8a, S2b S ± 7b
, D
a
50 Ω 300 Ω
V
O
± 10 V
± 10 V
+ 2.4 V
+ 15 V
- 15 V
EN V+
V- GND
35 pF
S
1
S
2
- S 15
S
16
A
2
A
1
A
0
50 Ω 300 Ω
V
O
A
3
± 10 V
± 10 V
+ 2.4 V
+ 15 V
- 15 V
EN V+
V- GND
D
35 pF
DG407
Document Number: 70061
S11-0179-Rev. J, 07-Feb-11
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Vishay Siliconix
DG406, DG407
TEST CIRCUITS
Figure 3. Enable Switching Time
VO
tr < 20 ns
tf < 20 ns
VO
Logic
Input
tON(EN)
90 %
Switch
Output
50 %
tOFF(EN)
3 V
0 V
0 V
A1
50 Ω
A0
S1
VO
A2
- 5 V
+ 15 V
- 15 V
300 Ω
EN
S2 - S 16
V+
V-GND
D
35 pF
A3
VO
S1b
A2
S1a - S8a
S2b - S8b
A1
Da and Db
A0
50 Ω 300 Ω
+ 15 V
- 15 V
EN
V+
V-GND 35 pF
DG406
DG407
- 5 V
90 %
Figure 4. Break-Before-Make Interval
50 %
80 %
Logic
Input
Switch
Output
VO
VS
tOPEN
tr < 20 ns
tf < 20 ns
0 V
3 V
0 V
50 Ω
A0
All S and Da
300 Ω
A3
D,D b
A1
A2
+ 2.4 V
+ 15 V
- 15 V
EN
V+
V-
VO
GND
+ 5 V
35 pF
DG406
DG407
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Document Number: 70061
S11-0179-Rev. J, 07-Feb-11
Vishay Siliconix
DG406, DG407
APPLICATIONS HINTS
Sampling speed is limited by two consecutive events: the
transition time of the multiplexer, and the settling time of the
sampled signal at the output.
tTRANS is given on the data sheet. Settling time at the load
depends on several parameters: RDS(on) of the multiplexer,
source impedance, multiplexer and load capacitances,
charge injection of the multiplexer and accuracy desired.
The settling time for the multiplexer alone can be derived
from the model shown in figure 5. Assuming a low
impedance signal source like that presented by an op amp or
a buffer amplifier, the settling time of the RC network for a
given accuracy is equal to n:
The maximum sampling frequency of the multiplexer is:
(1)
where N = number of channels to scan
tSETTLING = n = n x RDS(on) x CD(on)
For the DG406 then, at room temp and for 12-bit accuracy,
using the maximum limits:
(2)
or
fs = 694 kHz (3)
From the sampling theorem, to properly recover the original
signal, the sampling frequency should be more than twice
the maximum component frequency of the original signal.
This assumes perfect bandlimiting. In a real application
sampling at three to four times the filter cutoff frequency is a
good practice.
Therefore from equation 2 above:
(4)
From this we can see that the DG406 can be used to sample
16 different signals whose maximum component frequency
can be as high as 173 kHz. If for example, two channels are
used to double sample the same incoming signal then its
cutoff frequency can be doubled.
The block diagram shown in Figure 6 illustrates a typical data
acquisition front end suitable for low-level analog signals.
Differential multiplexing of small signals is preferred since
this method helps to reject any common mode noise. This is
especially important when the sensors are located at a
distance and it may eliminate the need for individual
amplifiers. A low RDS(on), low leakage multiplexer like the
DG407 helps to reduce measurement errors. The low power
dissipation of the DG407 minimizes on-chip thermal
gradients which can cause errors due to temperature
mismatch along the parasitic thermocouple paths. Please
refer to Application Note AN203 for additional information.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70061.
% ACCURACY # BITS N
0.25 8 6
0.012 12 9
0.0017 15 11
Figure 5. Simplified Model of One Multiplexer Channel
RS = 0
RDS(on)
VOUT
CD(on)
fs = 1
N(tSETTLING + tTRANS)
fs
= 1
16 (9 x 100 Ω x 10
-12
F) + 300 x 10
-12
s
f
c = 1
4x fs = 173 kHz
Figure 6. Measuring low-level analog signals is more accurate when using a differential multiplexing technique
12-Bit
A/D
Converter
Analog
Multiplexer
DG407
Controller
To
Sensor 1
To
Sensor 8
Inst
Amp S/H
E1E
Q1
A
L
A(1)
e1BB1
S
CeA
L
A1
D
15°
MAX.
1234567891011121314
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Package Information
Vishay Siliconix
Document Number: 71243
06-Jul-01 www.vishay.com
1
PDIP: 28ĆLEAD
MILLIMETERS INCHES
Dim Min Max Min Max
A2.29 5.08 0.090 0.200
A10.39 1.77 0.015 0.070
B0.38 0.56 0.015 0.022
B10.89 1.65 0.035 0.065
C0.204 0.30 0.008 0.012
D35.10 39.70 1.380 1.565
E15.24 15.88 0.600 0.625
E113.21 14.73 0.520 0.580
e12.29 2.79 0.090 0.110
eA14.99 15.49 0.590 0.610
L2.60 5.08 0.100 0.200
Q10.95 2.345 0.0375 0.0925
S0.995 2.665 0.0375 0.105
ECN: S-03946—Rev. F, 09-Jul-01
DWG: 5488
Document Number: 71264 www.vishay.com
28-Sep-09 1
Package Information
Vishay Siliconix
PLCC: 28-LEAD
D
0.101 mm
0.004"
D-SQUARE
D1-SQUARE
B
B1
e1
A1
A
A2
D2
DIM. MILLIMETERS INCHES
MIN. MAX. MIN. MAX.
A 4.20 4.57 0.165 0.180
A12.29 3.04 0.090 0.120
A20.51 - 0.020 -
B 0.331 0.553 0.013 0.021
B10.661 0.812 0.026 0.032
D 12.32 12.57 0.485 0.495
D111.430 11.582 0.450 0.456
D29.91 10.92 0.390 0.430
e11.27 BSC 0.050 BSC
ECN: T09-0766-Rev. D, 28-Sep-09
DWG: 5491
Package Information
www.vishay.com Vishay Siliconix
Revision: 01-Aug-11 1Document Number: 71268
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SOIC (WIDE-BODY): 28-LEADS
ECN: E11-2209-Rev. D, 01-Aug-11
DWG: 5850
0.3525 0.001 0.06 0.002D
CAVITY NO.
0.295 0.001
0.070 0.005
0.1475 0.001
0.055 0.005
PIN 1 INDICATOR
0.047 0.007 0.001 dp
SURFACE POLISHED
0.010
0.334 0.005
R0.004
R0.008
R0.009
R0.004
0.032 0.005
4°2°
0.041 0.001
0.705 0.001
0.091 0.001
0.017 0.00030.050 TYP. 0.00825 ± 0.00325
0.098 0.002
0.334 0.005
0.291 0.001
0.295 0.001
0.406 0.004
R0.004
7°(4 )
0.020 45°
DETAIL A
DETAIL A
1 2345678
28 27 26 25 24 23 22 21
910
20 19
11
18
12
17
13
16
14
15
All Dimensions In Inches
D
L1
E
BL
e
A1
A
28
1
2
Package Information
Vishay Siliconix
Document Number: 71278
02-Jul-01 www.vishay.com
1
28ĆLEAD LCC
MILLIMETERS INCHES
Dim Min Max Min Max
A1.37 2.24 0.054 0.088
A11.63 2.54 0.064 0.100
B0.56 0.71 0.022 0.028
D11.23 11.63 0.442 0.458
E11.23 11.63 0.442 0.458
e1.27 BS C 0.050 BSC
L1.14 1.40 0.045 0.055
L11.96 2.36 0.077 0.093
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5319
E1E
Q1
A
L
A1
e1B
B1
L1
S
C
eA∝
D
12 3
28
Package Information
Vishay Siliconix
Document Number: 71283
03-Jul-01 www.vishay.com
1
CERDIP: 28ĆLEAD
MILLIMETERS INCHES
Dim Min Max Min Max
A4.06 5.92 0.160 0.232
A10.38 1.52 0.015 0.060
B0.38 0.51 0.015 0.020
B11.14 1.65 0.045 0.065
C0.20 0.30 0.008 0.012
D36.58 37.08 1.440 1.460
E15.24 15.88 0.600 0.625
E112.95 13.46 0.510 0.530
e12.54 BS C 0.100 BSC
eA15.24 BSC 0.600 BSC
L3.18 3.81 0.125 0.150
L13.81 5.08 0.150 0.200
Q11.27 2.16 0.050 0.085
S1.52 2.29 0.060 0.090
∝0°15°0°15°
ECN: S-03946—Rev. E, 09-Jul-01
DWG: 5434
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Revision: 02-Oct-12 1Document Number: 91000
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