INTEGRATED CIRCUITS DIVISION
DS-IX2127-R04 www.ixysic.com 1
Driver Characteristics
Features
•Floating Channel Designed f or Bootst rap Operation
up to 600V
•Tolerant to Negativ e Tr ansient Voltages; dV/dt
Immune
•Undervo lt age Lock out
•3.3V, 5V, and 12V Input Logic Compatible
•Open-Drain FA ULT Ind icator Pin Shows
Ov er-Current Shu tdo wn
•Output in Phase with the Input
Applications
•High-Speed Gate Driver
•Motor Drive Inverter
Description
The IX2127 is a high-voltage , high- speed po w er
MOSFET and IGBT driver. High-voltage level-shift
circuitry enables this device to oper ate up t o 600V.
IXYS Integr ated Circuits Division’s proprietary
common-mode design techniques pro vide stable
operation in high dV/dt noise en vironments.
An on-board comparator can be used t o det ect an
over-current condition in the driven MOSFET or IGBT
de vice, and then shut do wn drive to that device. An
open-drain output, FA ULT, indicates that an
over-current shutdown has occurred.
The gate driver output typically can source 250mA
and sink 500mA, which is suitable f or fluorescent lamp
ballast, motor control, SMPS, and other converter
drive topologies.
The IX2127 is provided in 8-pin DIP and 8-pin SOIC
packages, and is av ailable in Tape & Reel version s.
See ordering information below.
Ordering Information
IX2127 Block Diagram
Parameter Rating Units
VOFFSET 600 V
IO +/- (Source/Sink) 250/500 mA
VCSth 250 mV
tON / tOFF (Typical) 100 ns
Part Description
IX2127G 8-Pin DIP (50/Tube)
IX2127N 8-Pin SOIC (100/Tube)
IX2127NTR 8-Pin SOIC (2000/Reel)
VCC
IN
FAULT
COM
VB
HO
VS
CS
Buffer
Comparator
Delay
Undervoltage Lockout
Data LatchTransmitter
High-Low
Level Shift
Low-High
Level Shift ReceiverTransmitterData Latch
Receiver
Low Side High Side
QR
S
Enable
Enable
Blanking
Signal
+
_
VCC
IX2127
High-Voltage
Power MOSFET & IGBT Driver
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IX2127
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1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.7 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Soldering Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
INTEGRATED CIRCUITS DIVISION
IX2127
R04 www.ixysic.com 3
1 Specifications
1.1 Package Pinout
1.2 Pin Description
1.3 Absolut e Max imum Rating s
Unless otherwise specified, rat ings are provided at TA=25°C and all bias levels are with r espect t o COM.
Absolute maximum electrical ratings are at 25°C
Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device . Functional operation of the de vice at conditions
beyond those indicated in the operational sections of th is
data sheet is not implied.
1
2
3
45
6
7
8
VCC
IN
COM
FAULT
VB
HO
VS
CS
Pin# Name Description
1VCC Logic Supply Voltage
2IN
Logic Input
3FAULT
Faul t Indicator Output
4COM
Logic Ground
5VSHigh Side Return
6CS
Comparator Input,
Over-Current Detect
7HO
High Side Gate Drive Output
8VBHigh Side Supply Voltage
Parameter Symbol Minimum Maximum Units
Logic Supply Voltage VCC -0.3 15
V
High Side Floating Supply Voltage VB-0.3 625
High Side Floating Offset Voltage VSVB-12 VB+0.3
Logic Input Voltage VIN -0.3 VCC+0.3
High Side Floating Output Voltage VHO VS-0.3 VB+0.3
Current Sense Voltage VCS VS-0.3 VB+0.3
FAULT Output Voltage VFLT -0.3 VCC+0.3
Allowable Offset Supply Voltage Transient dVS/dt -50V/ns
Package Power Dissipation
8-Lead DIP PD-1
W
8-Lead SOIC - 0.625
Junction Temperature TJ-150
°C
Storage Temperature TS-55 150
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1.4 Recommended Operating Conditions
1.5 General Conditions
Typical values are char acteristic of the de vice at 25°C
and are the result of engineering evaluations . They are
provided for information purposes only and are not
part of the manufacturing testing requirements .
Unless otherwise noted, all electrical specifications
are listed for TA=25°C .
Parameter Symbol Minimum Maximum Units
Logic Supply VCC 912
V
High Side Floating Supply VBVS+9 VS+12
High Side Offset Voltage VS-5 600
Logic Input Voltage VIN 0VCC
High Side Floating OutputVHO VSVB
Current Sense Signal Voltage VCS VSVS+5
FAULT Output Voltage VFLT 0VCC
Ambient Temperature T
A-40 +125 °C
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IX2127
R04 www.ixysic.com 5
1.6 Electrical Ch ara ct e ri st ic s
Unless otherwise specified, the test conditions are: VCC=VBS=12V; VCC, IN, FAULT, and Leakage voltages and
currents are referenced to COM; VB, HO , and CS voltages and currents are referenced to VS .
1.6.1 Power Supply Specifications
1.6.2 Gate Drive and Shutdown Specifications
* RGATE value m ust be 2 0 or greater.
1.6.3 Logic I/O Specifications
1.6.4 Thermal Specifications
Parameter Conditions Symbol Minimum Typical Maximum Units
Quiescent VCC Supply Current VIN=0V IQCC -280400
A
Quiescent VBS Supply Current VIN=0V IQBS - 500 1000
VBS UVLO Positive-Going Threshold -VBS_UV+ 6.8 7.7 8.6 V
VBS UVLO Negative-Going Threshold -VBS_UV- 6.3 7.2 8.1
Offset Supply Leakage Current VB=VS=600V ILKG --2
A
Parameter Conditions Symbol Minimum Typical Maximum Units
High Level Output Voltage, VB-VHO IHO=0A VOH --100
mV
Low Level Output Voltage, VHO IHO=0A VOL --100
Output Short Circuit Pulsed Current
VHO=0V, VIN=5V, PW<10s,
RGATE=20* (see Figure 1) IHO+ -200 -250 -
mA
VHO=12V, VIN=0V, PW<10s,
RGATE=20* (see Figure 1) IHO- 420 500 -
CS Input, Positive-Going Threshold VCC=9V to 12V VCS_TH+ 180 260 320 mV
“High” CS Bias Current VCS=3V ICS+ --1
A
VCS=0V ICS- ---1
Parameter Conditions Symbol Minimum Typical Maximum Units
Logic “1” Input Voltage VCC=9V to 12V VIH 3.0 - - V
Logic “0” Input Voltage VCC=9V to 12V VIL --0.8
Logic “1” Input Bias Current VIN=5V IIN+ -2.615
A
Logic “0” Input Bias Current VIN=0V IIN- ---1
FAULT On-Resistance - FLT, RON -72-
Parameter Conditions Symbol Minimum Typical Maximum Units
Thermal Resistance, Junction to Ambient:
8-Lead DIP -RJA --125
°C/W
8-Lead SOIC --200
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IX2127
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1.7 Timing Characteristics
Figure 1. Typical Connection Diagram
Parameter Conditions Symbol Minimum Typical Maximum Units
Turn-On Propagation Delay
VCC=VBS=12V,
CL=1nF,
T
A=25°C
ton -100200
ns
Turn-Off Propagation Delay toff -73200
Turn-On Rise Time tr-23130
Turn-Off Fall Time tf-2065
Start-Up Blanking Delay tblk 550 766 950
CS Shutdown Propagation Delay tCS -220360
CS to FLT Propagation Delay tFLT -236510
1
2
3
45
6
7
8
FAULT FAULT
VCC VCC
IN IN
COM
VB
HO
CS
VS
RGATE
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IX2127
R04 www.ixysic.com 7
1.7.1 I/O Timing Diagram
1.7.2 Switching Time Waveforms
1.7.3 Startup Blanking Time Waveforms
1.7.4 CS Shutdown Waveforms
1.7.5 CS to FLT Waveforms
IN
CS
FAULT
HO
50%
90%
10%
ton trtoff tf
IN
HO
50%
90%
IN
CS
t
blk
HO
FAULT
90%
CS
HO
VCS_TH+
tcs
90%
CS
FAULT
VCS_TH+
tflt
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2 Performance Data
VCC Supply Voltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
IQCC (μA)
0
50
100
150
200
250
Quiescent VCC Supply Current IQCC
vs. V oltage
V
BS
Supply Voltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
I
QBS
(μA)
0
100
200
300
400
500
Quiescent V
BS
Supply Current I
QBS
vs. V oltage
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Threshold UVLO+ (V)
0
2
4
6
8
10
VBS Undervoltage Lockout
Positive-Going Threshold UVLO+
vs. Temperature
Temperature (ºC)
-50 -25 0 25 50 75 100 125
IQBS (μA)
0
100
200
300
400
500
Quiescent VBS Supply Current IQBS
vs. Temperature
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Threshold UVLO- (V)
VBS Undervoltage Lockout
Negative-Going Threshold UVLO-
vs. Temperature
0
2
4
6
8
10
VCC Supply (V)
Input V oltage (V)
Logic "1" Input Threshold Voltage
vs. VCC
9.0 9.5 10.0 10.5 11.0 11.5 12.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VCC Supply Voltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Input V oltage (V)
Logic "0" Input Threshold Voltage
vs. VCC
0.0
0.5
1.5
2.5
3.0
2.0
1.0
V
CC
Supply Voltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Threshold (mV)
CS Input Positive Going Threshold
vs. VCC
0
50
100
150
200
250
300
350
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Input V oltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Logic "1" Input Threshold Voltage
vs. Temperature
(VCC=12V)
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Input V oltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Logic "0" Input Threshold Voltage
vs. Temperature
(VCC=12V)
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Threshold (mV)
0
50
100
150
200
250
300
350
CS Input Positive Going Threshold
vs. Temperature
(VCC=12V)
INTEGRATED CIRCUITS DIVISION
IX2127
R04 www.ixysic.com 9
Voltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Input Current (μA)
0
1
2
3
4
5
Logic "1" Input Current IIN+
vs. V oltage
V
BIAS
Supply Voltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Turn-On Delay Time (ns)
Turn-On Time vs. Supply Voltage
0
25
50
75
100
125
150
175
200
Supply V oltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Rise Time (ns)
0
25
50
75
100
125
150
175
200
Turn-On Rise Time
vs. Supply Voltage
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Input Current (μA)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Logic "1" Input Current IIN+
vs. Temperature
Temperature (ºC)
-50 -25 0 25 50 75 100 125
T urn-On Time (ns)
0
25
50
75
100
125
150
175
200
T urn-On Time vs. T emperature
(VCC=VBS=12V)
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Rise Time (ns)
0
50
100
150
200
Turn-On Rise Time vs. Temperature
(VCC=VBS=12V)
Voltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Input Current (μA)
-1.0
-0.5
0.0
0.5
1.0
Logic "0" Input Current IIN-
vs. V oltage
V
BIAS
Supply Voltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Turn-Off Delay Time (ns)
T urn-Off Time vs. Supply V oltage
0
25
50
75
100
125
150
175
200
Supply V oltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Turn-Off Fall Time (ns)
0
5
10
15
20
25
Turn-Off Fall Time
vs. Supply Voltage
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Input Current (μA)
-1.0
-0.5
0.0
0.5
1.0
Logic "0" Input Current IIN-
vs. Temperature
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Turn-Off Delay Time (ns)
0
25
50
75
100
125
150
175
200
T urn-Off Time vs. T emperature
(VCC=VBS=12V)
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Turn-Off Fall Time (ns)
0
10
20
30
40
50
T urn-Off Fall Time vs. T emperature
(VCC=VBS=12V)
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Temperature (ºC)
-50 -25 0 25 50 75 100 125
Output V oltage (mV)
-10
0
10
20
30
40
50
60
70
80
90
100
High-Level Output Voltage VOH (VB-VHO)
vs. Temperature
VBIAS V oltage (V)
10.0 10.5 11.0 11.5 12.0
Output Source Current (mA)
Output Source Current vs. Voltage
(VCC=VBS=VBIAS, VIN=5V, PW≤10μs)
0
50
100
150
200
250
300
Ref. Fig. 1: RGATE=20Ω
V
BIAS
V oltage (V)
10.0 10.5 11.0 11.5 12.0
Output Sink Current (mA)
Output Sink Current
vs. V Bias V oltage
(VCC=VBS=VBIAS, VIN=0V, PW≤10μs)
0
100
200
300
400
500
600
Ref. Fig. 1: R
GATE
=20Ω
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Output V oltage (mV)
-10
0
10
20
30
40
50
60
70
80
90
100
Low-Level Output Voltage VOL
vs. Temperature
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Output Source Current (mA)
0
50
100
150
200
250
300
350
Output Source Current
vs. Temperature
(VCC=VBS=12V, VIN=5V, PW≤10μs)
Ref. Fig. 1: R
GATE
=20Ω
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Output Sink Current (mA)
Output Sink Current
vs. Temperature
(VCC=VBS=12V, VIN=0V, PW≤10μs)
Ref. Fig. 1: R
GATE
=20Ω
0
100
200
300
400
500
600
Input V oltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Delay (ns)
Start-Up Blanking Delay
vs. Input Voltage
0
100
200
300
400
500
600
700
Input V oltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Delay (nS)
CS Shutdown Propagation Delay
vs. Input Voltage
0
50
100
150
200
250
V
CC
Supply Voltage (V)
9.0 9.5 10.0 10.5 11.0 11.5 12.0
Delay (ns)
CS to FLT Propagation Delay
vs. VCC Supply Voltage
0
50
100
150
200
250
300
350
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Delay (ns)
0
100
200
300
400
500
600
700
800
Start-Up Blanking Delay
vs. Temperature
(VCC=VBS=12V)
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Delay (ns)
0
50
100
150
200
250
300
CS Shutdown Propogation Delay
vs. Temperature
Temperature (ºC)
-50 -25 0 25 50 75 100 125
Delay (ns)
0
50
100
150
200
250
300
350
CS to FLT Propagation Delay
vs. Temperature
(VCC=VBS=12V)
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IX2127
R04 www.ixysic.com 11
3 Manufacturing Information
3.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptib le to moisture ing r ession. IXYS Integ rated
Circuits Division classifies its plastic encapsulated devices f or moisture se nsitivity according to the lat est
v ersion o f the joint indust ry standard, IPC/JEDEC J-STD-020, in force at the time of product evaluation.
We test all of our products to t he maximum conditions set forth in the standard, and guarantee proper
operation of our devices when handled according to the limit ations and information in that st andard as well as to any
limitations set forth in the inf ormation or standards referenced below.
Failure to adhere to the wa rnings or limitations as estab l ished by the listed specifications could result in reduced
product performance, reduction of operable lif e, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) classification as sho wn below, and should be handled
according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
3.2 ESD Sensitivi ty
This product is ESD Sensitive, and should be handled according to the industry standard JESD-625.
3.3 Soldering Profile
Provided in the table below is the Classification Temperature (TC) of this product and the maximum dwell time the
body temperature of this device may be (TC - 5)ºC or greater. The classification temperature sets the Maximum Bo dy
Temperature allowed for this device during lead-free ref low processes . For through-hole devices, and any other
processes, the guidelines of J-STD-020 must be observ ed.
3.4 Board Was h
IXYS Integr ated Circu it s Division recommends t he use of no-clean f lux formulations. Boar d washing to reduce or
remove flux residue f ollowing the solder reflow process is accep table provided proper precautions ar e taken to
pre vent damage to the device. These precautions include but are not limited to: using a low pressure wash and
providing a follow up bake cycle sufficient to remove any moistur e trapped within the device due to the washing
process. Due to the v ariability of the wash par ameters used to clean the board, determination of the bake temper ature
and duration necessary to remove the moisture trapped within the package is the responsibility of t he user
(assembler) . Cleaning or drying methods that employ ultrasonic energy ma y damage the device and should not be
used. Additionally, the device must n ot be exposed to flux or solv ents tha t are Chlorine- or Fluorine-based.
Device Moisture Sensitivity Level (MSL) Classification
IX2127G / IX2127N MSL 1
Device Classification Temperature (TC)Dwell Time (tp)Max Reflow Cycles
IX2127G 250°C 30 seconds 3
IX2127N 260°C 30 seconds 3
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3.5 Mechanical D ime ns io n s
3.5.1 8-Pin DIP Through-Hole Package
3.5.2 8-Pin SOIC Package
Dimensions
mm
(inches)
PCB Hole Pattern
2.540 ± 0.127
(0.100 ± 0.005)
6.350 ± 0.127
(0.250 ± 0.005) 9.144 ± 0.508
(0.360 ± 0.020)
0.457 ± 0.076
(0.018 ± 0.003)
9.652 ± 0.381
(0.380 ± 0.015)
7.239 TYP.
(0.285)
7.620 ± 0.254
(0.300 ± 0.010)
4.064 TYP
(0.160)
0.813 ± 0.102
(0.032 ± 0.004)
8-0.800 DIA.
(8-0.031 DIA.) 2.540 ± 0.127
(0.100 ± 0.005)
7.620 ± 0.127
(0.300 ± 0.005)
7.620 ± 0.127
(0.300 ± 0.005)
3.302 ± 0.051
(0.130 ± 0.002)
Pin 1
0.254 ± 0.0127
(0.010 ± 0.0005)
Dimensions
MIN / MAX
1.75 MAX
(0.069 MAX)
1.25 MIN
(0.049 MIN)
0.10 / 0.25
(0.004 / 0.010)
0.10
(0.004)
4
4.80 / 5.00
(0.189 / 0.197)
TOP VIEW
PIN #1
5.80 / 6.20
(0.228 / 0.244)
5
3.80 / 4.00
(0.150 / 0.157)
0.31 / 0.51
(0.012 / 0.020)
8x
SEATING PLANE
GAUGE PLANE
8°- 0°
0.10 / 0.25
(0.004 / 0.010)
0.40 / 1.27
(0.016 / 0.050)
A
0.25
(0.010)
PCB Land Pattern
1.55
(0.061)
0.60
(0.024)
3.75
(0.148)
A
Notes:
1. Controlling dimension: millimeters.
2. All dimensions are in mm (inches).
3. This package conforms to JEDEC Standard MS-012, variation AA, Rev. F.
4. Dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15mm per end.
5. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side.
6. Lead thickness includes plating.
6x
1.27
0.05
INTEGRATED CIRCUITS DIVISION
IX2127
R04 www.ixysic.com 13
3.5.3 Tape & Reel Packaging for 8-Pin SOIC Package
Dimensions
mm
(inches)
NOTE: Tape dimensions not shown comply with JEDEC Standard EIA-481-2
Embossment
Embossed Carrier
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
330.2 DIA.
(13.00 DIA.)
K0= 2.10
(0.083)
W=12.00
(0.472)
B0=5.30
(0.209)
User Direction of Feed
A0=6.50
(0.256) P1=8.00
(0.315)
For additional information please visit our website at: www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or complet eness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are ex pressed
or implied. Except as set forth in IXYS Integrated Circuits Division ’s Standard Terms and Conditions of Sale, IXYS Integra ted Circuits Division assumes no liability
whatsoe ver, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical
harm, injury, or death to a person or severe property or environment al dama ge . I XYS Inte g r a ted Circu its Divi sion res erves th e right to discont inue or make changes
to its products at any ti me without notice.
Specification: DS-IX2127-R04
©Cop yright 2017, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
10/25/2017