STw5098T - STMicroelectronics

34.807IRELESS

IMPORTANT NOTICE

Dear customer,

As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a

new company, ST-NXP Wireless.

As a result, the following changes are applicable to the attached document.

●Company name - STMicroelectronics NV is replaced with ST-NXP Wireless.

●Copyright - the copyright notice at the bottom of the last page “© STMicroelectronics

reserved”.

●Web site - http://www.st.com is replaced with http://www.stnwireless.com

●Contact information - the list of sales offices is found at http://www.stnwireless.com

under Contacts.

If you have any questions related to the document, please contact our nearest sales office.

Thank you for your cooperation and understanding.

ST-NXP Wireless

34.807IRELESS

www.stnwireless.com

April 2007 Rev 1 1/85

STw5098

Dual low power asynchronous stereo audio Codec

with integrated power amplifiers

Features

■Dual 20 bit audio resolution, 8kHz to 96kHz

independent rate ADC and DAC

■Dual I2S or PCM digital interfaces for dual

master

■Sustain complex voice and audio flow with or

without mixing

■I2C/SPI compatible control I/F

■Asynchronous sampling ADC and DAC: they

do not require oversampled clock and

information on the audio data sampling

frequency (fs). Jitter tolerant fs

■Wide master clock range: from 4MHz to 32MHz

■Stereo headphones drivers, handsfree

loudspeaker driver, line out drivers

■Mixable analog line inputs

■Voice filters: 8/16kHz with voice channel filters

■Automatic gain control for microphone and line-

in inputs

■Freque ncy pr ogr am mab le cl ock outputs

■Multibit Σ∆ modulators with data weighted

averaging ADC and DAC

■DSP functions for bass-treble-volume control,

mute, mono/stereo selection, voice channel

filters, de-emphasis filter and dynamic

compression

■93 dB dynamic range ADC, 0.001% THD with

full scale output @ 2.7V

■95 dB dynamic range DAC, 0.02% THD

performance @ 2.7V over 16Ω load

Applications

■Digital cellular telephones with application

processor such as mp3 or gaming and

Bluetooth concurrent application

Description

STw5098 is a dual low power asynchronous

stereo audio CODEC device with headphones

amplifiers for high quality audio listening and

recording.

Two I2S/PCM digital interfaces are available, one

per master for e xample Bluetooth and Application

Processor, enabling concurrent audio and voice

flow between Network and user.

The STw5098 control registers are accessible

through a selectable I2C-bus compatible or SPI

compatible interface.

STw5098

VFBGA 5x5x1 (112 pins)

LFBGA 6x6x1.4 (112 pins)

www.st.com

Contents STw5098

2/85

Contents

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 Device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.4 Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.5 Master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.6 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.7 Clock generators and master mode function . . . . . . . . . . . . . . . . . . . . . . 20

4.8 A udio digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.9 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.10 Analog output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.11 Analog mix ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.12 AD paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.13 DA paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.14 Analog-onl y operati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.15 Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.16 Interrupt request: IRQ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.17 Headset plug-in and push-button detection . . . . . . . . . . . . . . . . . . . . . . . 26

4.18 Micr ophone biasin g circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.2 Supply and power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3 Gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.4 DSP control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.5 Analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

STw5098 Contents

3/85

5.6 Digital audio interfaces master mode and clock generators . . . . . . . . . . . 41

5.7 Digi tal audio int e rfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.8 Digital filters, software reset and master clock control . . . . . . . . . . . . . . . 45

5.9 Interrupt control and control interface SPI out mode . . . . . . . . . . . . . . . . 46

5.10 AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6 Control interface and master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.1 Contr ol interface I2C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.2 Contr ol interface SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.3 Master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

7 Audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

8 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

9 Operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.2 Oper ative supply v o ltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

9.3 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

9.4 Typical power dissipation by entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10.1 Digital interf aces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10.2 AMCK with sinusoid input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10.3 Analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

10.4 Headset plug-in and push-button detector . . . . . . . . . . . . . . . . . . . . . . . . 64

10.5 Microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.6 Pow er supply rejection ra tio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

10.7 LS and EAR gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11 Analog input/output operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.1 Analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.2 Microphone inpu t lev els . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

11.3 Line output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

11.4 Power output levels HP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Contents STw5098

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11.5 Pow er output levels LS and EAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

12 Stereo audio ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

13 Stereo audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

14 AD to DA mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . 71

15 Stereo analog-only path specifications . . . . . . . . . . . . . . . . . . . . . . . . 72

16 ADC (TX) & DAC (RX) specifications with voice filters selected . . . . . 73

17 Typical performance plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

18 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

18.1 LFBGA 6x6x1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

18.2 VFBGA 5x5x1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

19 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

20 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

STw5098 List of tables

5/85

List of tables

Table 1. STw5098 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 2. Control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 3. CR0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 4. CR1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 5. CR2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 6. CR3 and CR4 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 7. CR5 and CR6 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 8. CR7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 9. CR8 and CR9 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. CR10 and CR11 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. CR12 and CR13 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 12. CR14 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 13. CR15 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 14. CR16 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 15. CR17 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 16. CR18 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 17. CR19 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 18. CR21-20 and CR24-23 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 19. CR22 and CR25 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 20. CR26 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 21. CR27 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 22. CR28 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 23. CR29 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 24. CR30 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25. CR31 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26. CR32 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 27. CR33 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 28. CR 34 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 29. CR 35 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 30. Control interface timing with I²C format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 31. Control interface signal timing with SPI format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 32. AMCK timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 33. Audio interface signal timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 34. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 35. Operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 36. Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 37. Typical power dissipation, no master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 38. Typical power dissipation with master clock AMCK = 13 MHz . . . . . . . . . . . . . . . . . . . . . . 61

Table 39. Digital interfaces specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 40. AMCK with sinusoid input specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 41. Analog interface specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 42. Headset plug-in and push-button detector specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 43. Microphone bias specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 44. Power supply rejection ratio specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 45. LS and EAR gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 46. Reference full scale analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 47. Microphone input levels, absolute levels at pins connected to preamplifiers . . . . . . . . . . . 66

Table 48. Microphone input levels, absolute levels at pins connected to the line-in amplifiers . . . . . 66

List of tables STw5098

6/85

Table 49. Absolute levels at OLP/OLN, ORP/ORN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 50. Absolute levels at HPL - HPR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 51. Absolute levels at 1EARP-1EARN and 2LSP - 2LSN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 52. Stereo audio ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 53. Stereo audio DAC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 54. AD to DA mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 55. Stereo analog-only path specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 56. ADC (TX) & DAC (RX) specifications with voice filters selected. . . . . . . . . . . . . . . . . . . . . 73

Table 57. Dimensions of LFBGA 6x6x1.4 112 4R11x11. 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 58. Dimensions of VFBGA 5x5x1.0 112 balls 0.4 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 59. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 60. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

STw5098 List of figures

7/85

List of figures

Figure 1. Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. STw5098 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 3. Power up block diagram: example shown for one entity . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 4. Plug-in and push-button detection application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 5. Control interface I2C format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 6. Control interface: I2C format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 7. Control interface SPI format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 8. Control interface: SPI format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 9. Audio interfaces formats: delayed, left and right justified . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 10. Audio interfaces formats: DSP, SPI and PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 11. Audio interface timings: master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 12. Audio interface timing: slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 13. A.C. testing input-output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 14. Bass treble control, de-emphasis filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 15. Dynamic compressor transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 16. ADC audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 17. ADC in band audio path measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 18. DAC digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 19. DAC in band digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Figure 20. ADC 96 kHz audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 21. ADC 96 kHz audio in-band measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 22. ADC voice TX path measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 23. ADC voice TX path measured in-band filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 24. DAC voice (RX) digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 25. DAC voice (RX) in-band digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 26. ADC path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 27. ADC S/N versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 28. DAC path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 29. DAC S/N versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 30. Analog path FFT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 31. Analog path S/N versus input-level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 32. LFBGA 6x6x1.4 112 4R11x11 0.5 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 33. VFBGA 5x5x1.0 112 0.4 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 34. STw5098 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Overview STw5098

8/85

1 Overview

●Dual 20 bit audio resolution, 8kHz to 96kHz independent rate ADC and DAC

●Dual I2S/PCM digital interfaces for dual master

●Sustain complex voice and audio flow with or without mixing

●Two I2C/SPI compatible independent control interfaces

●Asynchronous sampling ADC and DAC that do not require oversampled clock and

information on the audio data sampling frequency (fs). Jitter tolerant fs

●Wide master clock range from 4MHz to 32MHz

●Two stereo headphones drivers, hand free loudspeaker driver, line out drivers

●Mixable analog line inputs

●Voice filters: 8/16kHz with voice channel filters

●Automatic gain control for microphone and line-in inputs

●Four programmable master/slave serial audio data interfaces: I2S, SPI, PCM

compatible and other formats

●Frequency programmable clock outputs

●Multibit Σ∆ modulators with data weighted averaging ADC and DAC

●Four DSP functions for bass-treble-v olume control, mute, mono/stereo selection, voice

channel filters, de-emphasis filter and dynamic compression

●93 dB dynamic range ADC, 0.001% THD with full scale with full scale output @ 2.7V

●95 dB dynamic range DAC, 0.02% THD performance @ 2.7V over 16Ω load

Analog inputs

●Selectable stereo differential or single-ended microphone amplifier inputs with 51dB

range programmable gain

●2 microphone biasing output

●Microphone plug-in and push-button detection input

●Selectable stereo differential or single-ended line inputs with 38dB range

programm able gain

Analog output drivers

●2 Stereo headphones outputs. driving capability: 40mW (0.1% THD) over 16Ω with

40dB range programmable gain

●Common mode voltage headphones driver (phantom ground)

●1 Balanced loudspeaker output with driving capability up to 500mW (VCCLS>3.5V; 1%

THD) over 8Ω with 30dB range programmable gain

●1 Balanced earphone output with driving capability up to 125mW

●Transient suppression filter during power up and power down

●Balanced/unbalanced stereo line outputs with 1 kΩ driving capability

STw5098 Pinout

9/85

2 Pinout

Figure 1. Pin assignment

GND

2SCLK

1HDET

1MICLN1AUX1L2AUX1L

1MICLP

2CAPMIC

1LINEINL

1AUX2LP 2AUX2LP

1OLP

GNDCM

VCCP

1HPL

2HPL

1EARPS

2VCMHP

1VCMHP

GNDP

1CAPEAR

2CAPLS

GNDP

1EARP

1EARNS

2LSNS

1HPR

2ORP

1DA_DATA

1IRQ

2MBIAS

VCCA 2AUX1R

1MICRN 2MICRN

1CAPLINEIN 2MICRP

2AUX2RN1AUX2RN

2AUX2RP

1LINEINR

2ORN

GNDP

VCCA

2AD_OCK

1AD_OCK

1CMOD

VCCIO

2DA_OCK

1DA_OCK

1DA_CK

2DA_CK

1AD_DATA

AMCK

1AS/CSB

2AD_SYNC

1AD_SYNC

2DA_DATA2HDET

2MICLN1AUX3L2AUX3L

1CAPMIC GNDA

1AUX2LN 2LINEINL2AUX2LN

2OLN

1OLN

GNDCM VCCP

2OLP

VCC

1SCLK

2CMOD

2SDA/SDIN

1SDA/SDIN 2AD_CK

1AD_CK 2AS/CSB 2AD_DATA

VCC 2DA_SYNC

2IRQ

GND

1DA_SYNC

1MBIAS

1AUX1R

2CAPLINEIN 2AUX3R

1MICRP 1AUX3R

1AUX2RPGNDA

2LINEINR

1ORN

1ORP

GNDP 1VCMHPS

2VCMHPS VCCLS

2LSPS 2LSP

VCCP

1EARN

2LSN

VCCLS

VCCP 2HPR

2MICLP

VCCA

1234567891011

Pinout STw5098

10/85

Table 1. STw5098 pin description

Position Type Pin name Description

A1 P GND Ground pin for the digital section

A2 DI 1SCLK Control interface serial clock input

A3 DO 1AD_OCK Oversampled clock out from AD clock generator

A4 DIOD 2SDA/SDIN Control interface serial data input-output in I2C mode (SDA), control

interface serial data input in SPI mode (SDIN).

A5 DO 1DA_OCK Oversampled clock out from DA clock generator

A6 DIO 1AD_CK Serial data clock for stereo A/D converter

A7 DI 2AS/CSB Control interface address select in I2C mode (AS).

Interface enable signal in SPI mo de (CSB).

A8 DO 2AD_DATA Serial data out for stereo A/ D converter

A9 DIO 2AD_SYNC Frame sync for stereo A/D converter

A10 DIO 1DA_SYNC Frame sync for stereo D/A converter

A11 DI 1DA_DATA Serial data In for stereo D/A converter

B1 AI 2HDET Headset detection input

(microphone plug-in and push-button detection)

B2 DI 2SCLK Control interface serial clock input

B3 DO 2AD_OCK Oversampled clock out from AD clock generator

B4 DI 1CMOD Control interface type selector I2C-bus mode or SPI mode

B5 DO 2DA_OCK Oversampled clock out from DA clock generator

B6 DIO 2DA_CK Serial data clock for stereo D/A converter

B7 DI

AI AMCK Master clock input. Accepted range 4 MHz to 32 MHz.

AMCK is a digital square wave

AMCK is an analog sinewave (

Section 10.2 on page 62

)

B8 P VCC Power supply pin for the digital section.

Operating range: from 1.71 V to 2.7 V

B9 DIO 2DA_SYNC Frame sync for stereo D/A converter

B10 DI 2DA_DATA Serial data in for stereo D/A converter

B11 P GND Ground pin for the digital section

C1 P VCCA Power supply pin for the analog section.

Standard operating range: from 2.7V to 3.3V

Low voltage (LV) range: from 2.4V to 2.7V

C2 AI 1HDET Headset detection input

(microphone plug-in and push-button detection)

C3 P VCCA Power supply pin for the analog section.

Standard operating range: from 2.7V to 3.3V

Low voltage (LV) range: from 2.4V to 2.7V

C4 DI 2CMOD Control interface ty pe sele ctor I2C-bus mode or SPI mode.

STw5098 Pinout

11/85

C5 DIOD 1SDA/SDIN Control i nte rface s erial da ta i npu t-output in I 2C m od e (SDA). Control

interface serial data input in SPI mode (SDIN).

C6 DIO 2AD_CK Serial data clock for stereo A/D converter

C7 DO 1AD_DATA Serial data out for stereo A/D converter

C8 DIO 1AD_SYNC Frame sync for stereo A/D converter

C9 DO 2IRQ Programmable interrupt output. Active low signal.

C10 AO 2MBIAS Microphone biasing pin. Fixed vo ltage reference

C11 AO 1MBIAS Microphone biasing pin. Fixed vo ltage reference

D1 AI 2AUX1L Left and right channel single ended pins for microphone or line input

D2 AI 1AUX1L Left and right channel single ended pins for microphone or line input

D3 AI 1MICLN Left and right channel differential pins for microphone input

D4 P VCC Power supply pin for the digital section.

Operating range: from 1.71V to 2.7V

D5 P VCCIO Power supply pin for the digital I ⁄O buffers.

Operating ranges: from 1.2V to 1.8V and from 1.71V to VCC

D6 DIO 1DA_CK Serial data clock for stereo D/A conver ter

D7 DI 1AS/CSB Control interface address select in I2C mode (AS)

Interface enable signal in SPI mo de (CSB)

D8 DO 1IRQ Programmable interrupt output. Active low signal.

D9 P VCCA Power supply pin for the analog section.

Standard operating range: from 2.7V to 3.3V

Low voltage (LV) range: from 2.4V to 2.7V

D10 AI 1AUX1R Left and right channel single ended pins for microphone or line input

D11 AI 2AUX1R Left and right channel single ended pins for microphone or line input

E1 AI 2AUX3L Left and right channel single ended pins for microphone or line input

E2 AI 1AUX3L Left and right channel single ended pins for microphone or line input

E3 AI 1MICLP Left and right channel differential pins for microphone input

E4 AI 2MICLN Left and right channel differential pins for microphone input

E8 AI 2CAPLINEIN A capacitor must be connected between CAPLINEIN and ground

E9 AI 1MICRN Left and right channel differential pins for microphone input

E10 AI 2AUX3R Left and right channel single ended pins for microphone or line input

E11 AI 2MICRN Left and right channel differential pins for microphone input

F1 AI 2CAPMIC A capacitor must be connected between CAPMIC and ground.

F2 AI 1CAPMIC A capacitor must be connected between CAPMIC and ground

F3 P GNDA Ground pin for the analog section

F4 AI 2MICLP Left and right channel differential pins for microphone input

Table 1. STw5098 pin description

Position Type Pin name Description

Pinout STw5098

12/85

F8 AI 1CAPLINEIN A capacitor must be connected between CAPLINEIN and ground

F9 AI 1MICRP Left and right channel differential pins for microphone input

F10 AI 1AUX3R Left and right channel single ended pins for microphone or line input

F11 AI 2MICRP Left and right channel differential pins for microphone input

G1 AI 1AUX2LN Left and right channel differential pins for microphone or line input

G2 AI 2AUX2LN Left and right channel differential pins for microphone or line input

G3 AI 1LINEINL Left and right channel single ended pins for line input

G4 AI 2LINEINL Left and right channel single ended pins for line input

G8 P GNDA Ground pin for the analog section

G9 AI 1AUX2RP Left and right channel differential pins for microphone or line input.

G10 AI 1AUX2RN Left and right channel differential pins for microphone or line input

G11 AI 2AUX2RN Left and right channel differential pins for microphone or line input

H1 AI 1AUX2LP Left and right channel differential pins for microphone or line input

H2 AI 2AUX2LP Left and right channel differential pins for microphone or line input

H3 AO 2OLN Audio differential line out amplifier for left and right channels. This

outputs can drive up to 1kΩ resistive load. Can be used as single

ended out put.

H4 P GNDCM Ground pin fo r analog reference.

GNDCM can be conne cted to GNDA

H5 AO 1EARPS EARPS, EARNS (sense) pins must be connected on the application

board to EARP, EARN pins respectively. The connection must be as

close as possible to the pins.

H6 AO 1EARP

Analog differential loudspea ker amplif ier outp ut for left chann el or

right channel or the sum of both. This output can drive 50nF (with

serie s resistor) or directly an earpiece transductor fr om 8Ω. to 32Ω.

Can deliver from 500mW to 125mW.

H7 P VCCP Power supply pin for the left and right output drivers (headphones

and line-out). Operating range: from VCCA to 3.3V

H8 AO 1HPR Audio single ended headphones amplifier outputs for left and right

channels. The outputs can drive 50nF (with series resistor) or

directly an earpiece transductor of 16Ω.

H9 AO 2ORN Audio differential line out amplifier for left and right channels. This

outputs can drive up to 1kΩ resistive load. Can be used as single

ended out put.

H10 AI 2LINEINR Left and right channel single ended pins for line input

H11 AI 2AUX2RP Left and right channel differential pins for microphone or line input

J1 AO 1OLN Audio differential line out amplifier for left and right channels. This

outputs can drive up to 1kΩ resistive load. Can be used as single

ended out put.

Table 1. STw5098 pin description

Position Type Pin name Description

STw5098 Pinout

13/85

J2 AO 1OLP Audio differential line out amplifier for left and right channels. This

outputs can drive up to 1kΩ resistive load. Can be used as single

ended out put.

J3 AO 2OLP Audio differential line out amplifier for left and right channels. This

outputs can drive up to 1kΩ resistive load. Can be used as single

ended out put.

J4 AO 2HPL Audio single ended headphones amplifier outputs for left and right

channels. The outputs can drive 50nF (with series resistor) or

directly an earpiece transductor of 16Ω.

J5 AO 1VCMHP Common mode voltage headphones output. The negative pins of

headphones left and right speakers can be connected to this pin to

avoid decoupling capacitors.

J6 AI 1CAPEAR A capacitor can be connected between this node and ground

J7 AO 1EARN

Analog differential loudspea ker amplif ier outp ut for Left chann el or

Right channel or the sum of both. This output can drive 50nF (with

serie s resistor) or directly an earpiece transductor fr om 8Ω to 32Ω.;

It can deliver from 500mW to 125mW.

J8 P VCCLS Power supply pin for the mono differential output driver. Operating

range: from VCCA to 5.5V

J9 AO 2ORP Audio differential line out amplifier for left and right channels. This

outputs can drive up to 1kΩ resistive load. Can be used as single

ended out put.

J10 AO 1ORN Audio differential line out amplifier for left and right channels. This

outputs can drive up to 1kΩ resistive load. Can be used as single

ended out put.

J11 AI 1LINEINR Left and right channel single ended pins for line input

K1 P GNDCM Ground pin for analog reference.

GNDCM can be conne cted to GNDA

K2 P VCCP Power supply pins for the left and right output drivers (headphones

and line-out).

Operating range: from VCCA to 3.3V

K3 AO 1HPL Audio single ended headphones amplifier outputs for left and right

channels. The outputs can drive 50nF (with series resistor) or

directly an earpiece transductor of 16Ω.

K4 AO 2VCMHPS VCMHPS (sense) p in m ust b e con necte d on t he app licat ion bo ard to

VCMHP pin. The connection must be as close as possible to the

pins.

K5 P VCCLS Power supply pin for the mono differential output driver. Operating

range: from VCCA to 5.5V

K6 P GNDP Ground pin for the left, right and mono-differential output drivers.

GNDP and GNDA must be connected together.

K7 P GNDP Ground pin for the left, right and mono-differential output drivers.

GNDP and GNDA must be connected together.

Table 1. STw5098 pin description

Position Type Pin name Description

Pinout STw5098

14/85

K8 AO 1EARNS EARPS, EARNS (sense) pins must be connected on the application

board to EARP, EARN pins respectively. The connection must be as

close as possible to the pins.

K9 P VCCLS Power supply pins for the mono differential output driver. Operating

range: from VCCA to 5.5V

K10 AO 1ORP Audio differential line out amplifier fo r left and right channels. This

outputs can drive up to 1kΩ resistive load. Can be used as single

ended out put.

K11 P GNDP Ground pin for the left, right and mono-differential output drivers.

GNDP and GNDA must be connected together.

L1 P VCCP Power supply pin for the left and right output drivers (headphones

and line-out).

Operating range: from VCCA to 3.3V

L2 P GNDP Ground pin for the left, right and mono-differe ntial output drivers.

GNDP and GNDA must be connected together.

L3 AO 1VCMHPS VCMHPS (se nse) p in m ust b e con nected o n t he app licat ion bo ard to

VCMHP pin. The connection must be as close as possible to the

pins.

L4 AO 2VCMHP Common mode voltage headphones output. The negative pins of

headphones left and right speakers can be connected to this pin to

avoid decoupling capacitors.

L5 AO 2LSPS LSPS, LSNS (sense) pins must be connected on the application

board to LSP, LSN pins respectively. The connection must be as

close as possible to the pins.

L6 AO 2LSP

Analog differential loudspea ker amplif ier outp ut for Left chann el or

Right channel or the sum of both. This output can drive 50nF (with

serie s resistor) or directly an earpiec e transductor of 8Ω.; It can

deliver up to 500mW.

L7 AI 2CAPLS A capacitor can be connected between this node and ground

L8 AO 2LSN

Analog differential loudspea ker amplif ier outp ut for Left chann el or

Right channel or the sum of both. This output can drive 50nF (with

series resis tor) o r di rectly an e arpiece transdu ct or of 8Ω. C an d eli ver

up to 500mW.

L9 AO 2LSNS LSPS, LSNS (sense) pins must be connected on the application

board to LSP, LSN pins respectively. The connection must be as

close as possible to the pins.

L10 P VCCP Power supply pin for the left and right output drivers (headphones

and line-out). Operating range: from VCCA to 3.3V

L11 AO 2HPR Audio single ended headphones amplifier outputs for left and right

channels. The outputs can drive 50nF (with series resistor) or

directly an earpiece transductor of 16Ω.

Table 1. STw5098 pin description

Position Type Pin name Description

STw5098 Pinout

15/85

Type definitions

AI - Analog input

A O - Analog output

AIO - Analog input output

DI - Digital input

DO - Digital output

DIO - Digital input output

DIOD - Digital input output open drain

P - Power supply or ground

Block diagram STw5098

16/85

3 Block diagram

Figure 2. STw5098 block diagram

Transient

Suppr.

Filter

Transient

Suppr.

Filter

Transient

Suppr.

Filter

Left

LineOut

-40:0 dB Step 2

Right

Driver

LOG: -18:0 dB Step 3

Right

LineOut

(L+R)/2

Stereo

Diff.

Stereo

Sing.E.

Stereo

Sing.E.

Stereo

Diff.

Stereo

Sing.E.

Comm.

Mode

Left

Driver

Voltage

Reference

-20

+18 dB Step 2

-24

6 dB Step 2

Mono

Driver

MICLO1

LSSEL1

MIXLIN1

MIXMIC1

ADMIC1

ADLIN1

1CAPLINEIN

1CAPMIC

1LINEINL

1LINEINR

1AUX3R

1AUX3L

AUX2NR

1AUX2PR

1AUX2NL

1AUX2PL

1AUX1R

1AUX1L

1MICRN

1MICRP

1MICLN

1MICLP

1MBIAS

1VCMHP

1VCMHPS

1OLP

1OLN

1HPL

1EARPS

1EARP

1CAPEAR

1EARN

1EARNS

1HPR

1ORP

1ORN

Mic.

Bias

LINEIN

AUX1

AUX2

AUX3

MUTE

LIN L-R

Amps

LINSEL1 LINLG1

LINRG1

Stereo Path

2.1V

Reference

AGC

(fro m DSP)

AGC

(fro m DSP)

LSG1

HPLG1

HPRG1

39 dB

Step 1.5

MIC

AUX1

AUX2

AUX3

MUTE

MIC L-R

PreAmps

MICSEL1 MICLG1

MICRG1

-12

0 dB

Step 1.5

MICLA1

MICRA1

Transient

Suppr.

Filter

Transient

Suppr.

Filter

Transient

Suppr.

Filter

Left

LineOut

-40:0 dB Step 2

Right

Driver

LOG: -18:0 dB S tep 3

Right

LineOut

(L+R)/2

Stereo

Diff.

Stereo

Sing.E.

Stereo

Sing.E.

Stereo

Diff.

Stereo

Sing.E.

Comm.

Mode

Left

Driver

Voltage

Reference

-20

+18 dB Step 2

-24

6 dB Step 2

Mono

Driver

MICLO2

LSSEL2

MIXLIN2

MIXMIC2

ADMIC2ADLIN2

2CAPLINEIN

2CAPMIC

2LINEINL

2LINEINR

2AUX3R

2AUX3L

2AUX2NR

2AUX2PR

2AUX2NL

2AUX2PL

2AUX1R

2AUX1L

2MICRN

2MICRP

2MICLN

2MICLP

2MBIAS

2VCMHP

2VCMHPS

2OLP

2OLN

2HPL

2LSPS

2LSP

2CAPLS

2LSN

2LSNS

2HPR

2ORP

2ORN

Mic.

Bias

LINEIN

AUX1

AUX2

AUX3

MUTE

LIN L-R

Amps

LINSEL2

LINLG2

LINRG2

Stereo Path

2.1V

Reference

AGC

(from DSP)

AGC

(from DSP)

LSG2

HPLG2

HPRG2

39 dB

Step 1.5 MIC

AUX1

AUX2

AUX3

MUTE

MIC L-R

PreAmps

MICSEL2MICLG2

MICRG2

-12

0 dB

Step 1.5

MICLA2

MICRA2

MCK1

DA Sample

Rate

Converter

CK Gen/

Master

Mode

Digital

DA-PLL

PLL

Audio

AD-I/F

Stereo DAC

1AD_SYNC

1AD_CK

1AD_DATA

1AD_OCK

AMCK

1DA_OCK

1DA_SYNC

1DA_CK

1DA_DATA

DSP1

AD to DA

Mixing

Gain

AGC

(Mic&Lin)

DACHSW

ADMONO

DAMONO

(sidetone)

DAC

Digital

Gain

ADC

Digital

Gain

Dyn.Comp.

Bass

Treble

(Audio only)

DA to AD

Mixing

Gain

(Audio Only)

ADCHSW

Filter

Audio/Voice

Filter

Audio/Voice

Σ∆

Modulator

Σ∆

ADC

Audio

DA-I/F

DA_SYNC1

CK Gen/

Master

Mode

MCK2

CK Gen/

Master

Mode

PLL

Audio

AD-I/F

2AD_SYNC

2AD_CK

2AD_DATA

2AD_OCK

AMCK

2DA_OCK

2DA_SYNC

2DA_CK

2DA_DATA

DSP2

AD to DA

Mixing

Gain

AGC

(Mic&Lin)

DACHSW

ADMONO

DAMONO

(sidetone)

DAC

Digital

Gain

ADC

Digital

Gain

Dyn.Comp.

Bass

Treble

(Audio only)

DA to AD

Mixing

Gain

(Audio Only)

ADCHSW

Filter

Audio/Voice

Filter

Audio/Voice

Audio

DA-I/F

CK Gen/

Master

Mode

Bandgap

Control

Logic

Power-On

Reset Registers

Control I/F

Headset

Detection

VCCIO GNDVCC

GNDCMGNDPVCCLSVCCP GNDA

CurrentBias

STw5098

IRQ

Gen

2CMOD2AS/CSB1SCLK 2SDA/SDIN1HDET

Oscillator

Stereo ADC

DAC

MIXDAC1

Analog

Filter

AD Sample

Rate

Converter Digital

AD-PLL

AD_SYNC1

Stereo DAC

Σ∆

ADC

Stereo ADC

AD Sample

Rate

Converter

Digital

AD-PLL

AD_SYNC2

DA Sample

Rate

Converter

Digital

DA-PLL

Σ∆

Modulator

DA_SYNC2

DAC

MIXDAC2

Analog

Filter

1IRQ 2HDET

AMCK

VCCA 1SDA/SDIN 2SCLK

1CMOD 1AS/CSB

2IRQ

STw5098 Functional description

17/85

4 Functional description

4.1 Naming convention

The STw5098 is composed of two identical entities, with their respective set of control

registers.

Regarding the pin labelling, a pin name preceded by 1 refers to entity 1 and a pin name

preceded by 2 refers to entity 2 (ie.g. 1SCLK, 2SCLK). In the following sections, no

distinction is made between the two entities when it is not relev ant. Consequently, the 1 and

2 prefix es for entities 1 and 2 respectively are omitted. The same naming convention applies

to the control registers (CRxxx).

4.2 Power supply

STw5098 can have different supply voltages for different blocks, to optimize performance,

power consumption and connectivity. See

Section 9.2 on page 59

for voltage definition.

The correct sequence to apply supply voltage is to set first (and unset last) the digital I/O

suppl y (V CCIO). The other supply voltages can be set in any order and can be disconnected

individually, if needed. Disconnection does not cause any harm to the device and no extra

current is pulled from any supply during this operation. Moreover if a voltage conflict is

detected, like VCCA < VCC (not allow ed), simply all blocks connected to VCCA are set to

power down and no extra current is pulled from supply.

When VCCIO is set and VCC (digital supply) is not set, all the d igital output pins are in h igh

impedance state, while the digital inputs are disconnected to avoid power consumption for

any input voltage value between GND and VCCIO. Before VCC is disconnected the device

has to be reset (SWRES bit in CR30).

When the analog supply (VCCA) is set and VCC is not set, all the analog inputs are in high

impedance state.

The two sets of control registers are powered by VCC pins (digital supply) so if these pins

are disconnected all the information stored in control registers is lost. When the digital

supply voltage is set, a power-on-reset (POR) circuit sets all the registers content to the

default value and then generates IRQ signals writing 1 in bits PORMSK end POREV in

CR31 and CR32 respectively for both entities.

All supplies must be on during operation.

Functional description STw5098

18/85

4.3 Device programming

STw5098 can be programmed by writing Control Registers with SPI or I2C compatible

control interface (both slave). The interface is always active, there is no need to have the

master clock running to program the device registers. The control interfaces of each entity

can be operated independently either in SPI or I2C modes.

The choice between the two interfaces for each entity is done via their input pins 1CMOD

and 2CMOD (CMOD):

1. CMOD connected to GND: I2C compatible mode selected

The device address is selected with AS pin:

When this mode is selected control registers are accessed through pins:

SCLK (clock)

SDA (serial data out/in, open drain)

2. CMOD connected to VCCIO: SPI compatible mode selected

When this mode is selected control registers are accessed through:

AS/CSB (chip select, active low)

SCLK (clock)

SDIN (serial data in)

AD_OCK or DA_OCK or IRQ (serial data out, if selected)

Device Programming: I2C. The I2C Control Interface timing is shown in

Section 6.1 on

page 50

. The interface has an internal counter that keeps the current address of the control

loaded with the data of the

field. The value in the address counter is

increased after each data byte read or write. It is possible to access the interface in 2

modes: single-byte mode in which the address and data of a single register are specified,

and multi-byte mode in which the address of the first register to be written or read is

specified and all the following bytes e xchanged are the data of successive registers starting

from the one specified (in multi-byte mode the internal address counter restart from register

0 after the last register 36). Using the multi-byte mode it is possible to write or read all the

registers with a single access to the device on the I2C bus. This applies to both entities of

the device.

Device Programming: SPI. The SPI Control Interface timing is shown in section

Section 6.2 on page 51

. Bits SPIOSEL (SPI Output Select) in CR33 control the out pin

selection fo r serial data out (none, AD_OCK, DA_OCK or IRQ), while bit SPIOHIZ=1 in

CR33 selects the high impedance state of serial data out pin when idle. The first bit sent on

SDIN, after AS/CSB falling edge, sets the interface for writing (SDIN=1) or reading

(SDIN=0), then a 7-bit Control Register address follows.

If the interface is set f or writing then the last 8 bits on SDIN are written in the control register.

If the interface is set for reading then after the 7 bit address STw5098 sends out 8 bits data

on the pin selected with bits SPIOSEL in CR33, while bits present at SDIN pin are ignored.

If SPIOSEL=00 (no out pin selected) the reading access on SPI interface can still be useful

to clear the IRQ event bits in CR32.

AS/CSB connected to GND: chip address 00110101(35hex) for reading, 00110100 (34hex) for writing

AS/CSB connected to VCCIO: chip address 00110111(37hex) for reading, 00110110 (36hex) for writing

STw5098 Functional description

19/85

4.4 Power up

STw5098 internal blocks can individually be switched on and off according to the user

needs. A general power-up bit is present at bit 7 of CR0. The output drivers should always

be powered up after the general power up. See the following drawing to select the needed

block for the desired function. A fast-settling function is activated to quickly charge external

capacitors when the device is switched on (CAPLS, CAPLINEIN and CAPMIC).

Figure 3. Power up block diagram: example shown for one entity

4.5 Master clock

Master clock is applied to both entities. The master clock pin (AMCK) accepts any frequency

from 4 MHz to 32 MHz. The 4-32 MHz range is divided in sub-ranges that have to be

programmed in bits CKRANGE in CR30. The jitter and spectral properties of this clock have

a direct impact on the DA C and ADC performance because it is used to directly or by integer

division drive the continuous-time to sampled-time interfaces.

POWERUP

ENANA

STw5098

ENMIXL

ENHPVCM

ENHPL

ENLS

ENHPR

ENMICR

ENMICL

ENLINR

ENLINL

ENOSC

ENADCR

ENADCL

ENDACR

ENDACL

AUDIO I/F

ENLOL

ENLOR

ENHSD

ENPLL

DAMAST ENDAOCK

ADMAST ENADOCK

MBIAS

ENAMCK

ENDACKGEN

ENADCKGEN

ENOSC=1

ENOSC=0

Functional description STw5098

20/85

Note that AMCK clock does not need to have an y relation to any other digital or analog input

or outpu t.

AMCK can be either a square wav e or a sinewa ve , bit AMCKSIN in CR30 selects the proper

input mode. When a sinewave is used as input, AMCK pin must be decoupled with a

capacitor. Specification for sinusoid input can be found in

Section 10.2 on page 62

The AMCK clock is not needed when only analog functions are used. For this purpose an

internal oscillator with no external components can be used to operate the device (see

Section 4.14 on page 25

4.6 Data rates

STw5098 supports any data rate in 2 ranges: 8 kHz to 48 kHz and 88 kHz to 96 kHz. The

range is selected with bits DA96K and AD96K in CR29 for AD and DA paths respectively.

Note: When AD96K=1 it is required to have DA96K=1.

The rates are fully independent in A/D and D/A paths. Moreover the rates do not have to be

specified to the device and they can change on the fly, within one range, while data is

flowing.

The 2 audio data interfaces (for A/D and D/A) can independently operate in master or slave

modes.

4.7 Clock generators and master mode function

STw5098 provides 4 internal clock generators that can drive, if needed, the audio interfaces

(master mode), and/or two independent master clocks.

The AMCK clock input frequency is internally raised via a PLL on each entity to obtain a

clock (MCK) in the range 32 MHz to 48 MHz. The ratio MCK/AMCK is defined in CR30 (see

MCKCOEFF in

Section 4.7 on page 20

MCK is used to obtain, by fractional division, the oversampled clock (OCK), word clock

(SYNC) and bit clock (CK), that will therefore hav e edges aligned with MCK (the OCK period

can have jitter of 1 MCK period).

The frequency of OCK, SYNC and CK is set with D A OCKF in CR21/20 for D A interface , and

ADOCKF in CR24/23 for AD interface.

The ratio between OCK and SYNC clocks is selected with bit DAOCK512 in CR22 for DA

interface and bit ADOCK512 in CR25 for AD interface. The ratio between CK and SYNC

clocks depends on the selected interface format (see

Audio digital interfaces

paragraph

below). Note that SPI format can only be slave.

The ADOCK and DAOCK output clocks are activated by bits ENADOCK and ENDAOCK

respectively, while master mode generation is activated with two bits: first ADMAST

(DAMAST) sets ADSYNC and ADCK (DASYNC and DACK) pins as outputs, then

ADMASTGEN (DAMASTGEN) generates the SYNC and CK clocks. The logical value at

SYNC and CK pins before data generation depends on the interface selected format.

See description of CR20 to CR25 for further details.

STw5098 Functional description

21/85

4.8 Audio digital interfaces

Four separate audio data interfaces are provided for AD and DA paths to have maximum

flexibility in communicating with other devices. The 4 interfaces can have diff erent rates and

can work in diff erent formats and modes (i.e an AD interf ace can be 8 kHz PCM slave while

a DA is 44.1 kHz I2S master).

The pins used by the interfaces are:

AD_SYNC, AD_CK and AD_DATA for AD paths word clock, bit clock and data, respectively,

and

DA_SYNC, DA_CK and DA_DATA for DA paths word clock, bit clock and data, respectively.

Data is exchanged with MSB first and left channel data first in all formats. Data word-length

is selected with bits DAWL in CR26 and ADWL in CR27. AD_D ATA pin, outside the selected

time slot, is in the impedance condition selected by bit ADHIZ in CR28 in all data formats

except right aligned format.

In the following paragraphs SYNC, CK and DATA will be used when the distinction between

AD and DA is not relevant. When Master Mode is selected (bits DAMAST and ADMAST in

CR22 and CR25 respectiv ely) the SYNC and CK clocks are generated internally. In addition,

an oversampled clock can be generated for each interface (AD_OCK and DA_OCK). The

clock is available in Slave Mode also, if needed.

The AD and DA interf aces can also be used as a single bidirectional interface when they are

configured with the same format (Delay ed, DSP, etc.) and AD_SYNC is connected to

DA_SYNC and DA_CK to AD_CK. Master Mode is still available selecting ADMAST or

DAMAST (not both).

The interfaces features are controlled with control registers CR26, CR27 and CR28.

Supported operating formats:

●Delayed format (I2S compatible) (DAFORM or AD FORM =0 00): the A u dio I nterface is

I2S compatible (

Figure 9 on page 54

). The number of CK periods within one SYNC

period is not relevant, as long as enough CK periods are used to transfer the data and

the maximum frequency limit specified for bit clock is not e xceeded. CK can be either a

continuous clock or a sequence of bursts. In master mode there are 32 CK periods per

SYNC period (that means 16 CK periods per channel) when the word length is 16 bit,

while there are 64 CK periods per SYNC period (or 32 CK periods per channel) when

word length is 18bit or higher. Bits ADSYNCP, DASYNCP and ADCKP, DACKP affect

the interface format inverting the polarity of SYNC and CK pins respectively.

●Left aligned format (D AFORM or ADFORM =001): this f ormat is equivalent to delayed

format without the 1 bit clock delay at the beginning of each frame (

Figure 9 on

page 54

●Right aligned format (DAFORM or ADFORM =010): this format is equivalent to

delayed format, except that the audio data is right aligned and that the number of CK

periods i s fixed to 64 for each SYNC period (

Figure 9 on page 54

●DSP format (DAFORM or ADFORM =011) in this format the audio interface starting

from a frame sync pulse on SYNC receives (DA) or sends (AD) the left and right data

one after the other (

Figure 10 on page 55

). The number of CK periods within one

SYNC period is not relevant, as long as enough CK periods are used to transfer the

data and the maximum frequency limit specified for bit clock is not exceeded. CK can

be either a continuous clock or a sequence of bursts. In Master Mode there are 32 CK

periods per SYNC period when the word length is 16 bit, while there are 64 CK periods

per SYNC period when word length is 18bit or higher. Bit CKP (ADCKP and DACKP)

Functional description STw5098

22/85

affects the interf ace format inv erting the polarity of CK pin. Bit SYNCP (ADSYNCP and

DASYNCP) switches between delayed (SYNCP=0) and non delayed (SYNCP=1)

formats.

DSP format is suited to interface with a multi-channel serial port.

●SPI format (DAFORM or ADFORM =100) in this format left and right data is received

with separate data burst. Every burst is identified with a low level on SYNC signal

(

Figure 10 on page 55

). There is no timing difference between the left and right data

burst: the two channels are identified by the startup order: the first burst after AD path

or DA path power-up identifies the left channel data, the second one is the Right

channel data, then left and right data repeat one after the other. CK must have 16

periods per channel in case of 16 bit data word and 32 periods per channel in case of

18 bit to 32 bit data word.

The SPI interface can be configured as a single-channel (mono) interface with bit SPIM

(ADSPIM and DASPIM). The mono interf ace always exchanges the left channel

sample.

SPI-format can only be slav e: if Master Mode is selected the CK and SYNC pins are set

to 0. Bi t C KP ( A DCK P and DAC K P) af fects th e in t e rface format inve rting th e po l arit y of

CK pin.

●PCM format (DAFORM or ADFORM =111): this format is monophonic, as it can only

receive (D A) and transmit (AD) single channel data (

Figure 10 on page 55

). It is mainly

used when voice filters are selected. If audio filters are used then the same sample is

sent from DA-PCM interface to both channel of DA path, and the left channel sample

from AD path is sent to AD-PCM interface. If in the AD path the right channel has to be

sent to the PCM interface then the following must be set: ADRTOL=1 (CR27) and

ENADCR=0 (CR1). In Master Mode the number of CK periods per SYNC period is

between 16 and 512 (see DAPCMF in CR22 and ADPCMF in CR25

Section 4.7 on

page 20

for details). Bit CKP (ADCKP and DACKP) affects the interface format

inverting the polarity of CK pin. Bit SYNCP (ADSYNCP and DASYNCP) switches

between delayed (SYNCP=0) and non delayed (SYNCP=1) formats.

4.9 Analog inputs

Each entity of the STw5098 has a stereo Microphone preamplifier and a stereo Line In

amplifier, with inputs selectable among 5: MIC (for Microphone preamplifiers only), LINEIN

(for Line In amplifiers only) and 3 different AUX inputs (for Microphone and Line In

amplifiers). The AUX inputs can be used simultaneously for Line In amplifiers and

Micropho ne pr eam pli fi ers.

The following description is for one entity, it is similar for the other entity.

●Microphone preamplifier: it has a very low noise input, specifically designed for low

amplitude signals. For this reason the preamplifier has a high input gain (up to 39 dB)

keeping a constant 50 kΩ input impedance for the whole gain range. Howe ver it can

also be used as line in preamplifier because it can accept a high dynamic input signal

(up to 4 Vpp). There are two separate gain and attenuation stages in order to improve

the S/N ratio when the preamplifier output range is below full scale (volume

control).The gain and attenuation controls are separate for left and right channel (CR3

and CR4 respectively). The Preamplifier input is selected with bits MICSEL in CR18,

and it is disconnected when MICMUTE=1. If a single ended input is selected then the

preamplifier uses the selected pin as the positive input and connects the negative input

(for both left and right channels) to CAPMIC pin, which has to be connected through a

capacitor to a low noise ground (typically the same reference ground of the input).

STw5098 Functional description

23/85

Each stereo Microphone preamplifier is powered up with bits ENMICL and ENMICR in

CR1.

●Line In amplifier: each line in amplifier is designed for high lev el input signal. The input

gain is in the range -20 dB up to 18 dB. The Line In amplifier input is selected with bits

LINSEL in CR18, and it is disconnected when LINMUTE=1. If a single ended input is

selected then the amplifier uses the selected pin as the positive input and connects the

negative input (for both left and right channels) to CAPLINEIN pin, which has to be

connected through a capacitor to a low noise ground (typically the same reference

ground of the input).

The stereo Line In amplifier is powered up with bits ENLINL and ENLINR in CR1.

4.10 Analog output drivers

Each entity of the STw5098 provides 3 different analog signal outputs and 1 common mode

reference output. The description here below is for one entity. VCCP and VCCL are common

for both entities.

●Line out drivers: it is a stereo differential output, it can be used as single-ended output

just by using the positive or negative pin. It can drive 1 kΩ resistive load. The load can

be connected between the positive and negative pins or between one pin and ground

through a decoupling capacitor. The output gain is regulated with LOG bits in CR7, in

the range 0 to -18 dB, simultaneously for left and right channels. When used as a single

ended output the eff ective gain is 6 dB lower . It is muted with bit MUTELO in CR19. The

input signal of this stereo output can come from the analog mixer or directly from MIC

preamplifiers. The output Common Mode Voltage level is controlled with bits VCML in

CR19. T he su pply voltage of line ou t dr ivers is VCCP.

The line out drivers are powered up with bits ENLOL and ENLOR in CR1. The output

pins are in high impedance state with a 180kΩ pull-down resistor when the line out

dr ivers are powered down.

●Headphones drivers: it is a stereo single ended output. It can drive 16 ohm resistive

load and deliver up to 40 mW. The output gain is regulated with HPLG and HPRG bits

in CR8 and CR9 respectively, with a range of -40 to 6 dB. It is muted with bit MUTEHP

in CR19. The input signal of this stereo output comes from the analog mixer.The output

common mode voltage is controlled with bits VCML in CR19. The supply voltage of

headpho nes drivers is VCCP.

The headphones drivers are powered up with bits ENHPL and ENHPR in CR2.The

output pins are in high impedance state when the headphones driv ers are powered

down.

●Common mode voltage driver: it is a single ended output with output voltage value

selectable with bits VCML in CR19, from 1.2 V to 1.65 V in steps of 150 mV. The output

voltage should be set to the value closest to VCCP/2 to optimize output drivers

performance. The common mode voltage driver is designed to be connected to the

common pin of stereo headphones, so that decoupling capacitors are not needed at

HPL and HPR outputs. The supply voltage of the common mode voltage driver is

VCCP.

The common mode voltage driver is powered up with bit ENHPVCM in CR2.The output

pin is in high impedance state when the common mode v oltage driver is powered down.

Functional description STw5098

24/85

●Loudspeaker driver (one entity only): it is a monophonic differential output. It can

drive 8 Ω resistive load and deliver up to 500 mW to the load. The output gain is

regulated with LSG bits in CR7, in the range -24 to +6 dB. The input signal of the

loudspeaker driver comes from the analog mixers: bits LSSEL in CR29 select left

channel, right channel, (L+R)/2 (mono) or mute. The output common mode voltage is

obtained with an internal v oltage divider from VCCLS and it is connected to CAPLS pin.

The supply voltage of the loudspeaker driver is VCCLS.

The loudspeaker driver is powered up with bit ENLS in CR2.The output pin is in high

impedance state when the loudspeaker driver is powered down.

Note: 1 Together with the LS driver, only a second power output is allowed among:

Ear (1EARP - 1EARN)

Headphones 1 (1HPL and 1HPR)

Headphones 2 (2HPL and 2HPR)

●Earphone driver (one entity only): it is a monophonic diff erential output. It can drive

32 Ω resistive load and deliver up to 125 mW to the load. The output gain is regulated

with EARG bits in CR7, in the range -24 to +6 dB. The input signal of the loudspeaker

driver comes from the analog mixers: bits EARSEL in CR29 select left channel, right

channel, (L+R)/2 (mono) or mute. The output Common Mode Voltage is obtained with

an internal voltage divider from VCCLS and it is connected to CAPEAR pin. The supply

voltage of the loudspeaker driver is VCCLS.

The loudspeaker driver is powered up with bit ENEAR in CR2.The output pin is in high

impedance state when the loudspeaker driver is powered down.

Note: Note on direct connection of VCCLS to the battery:

The voltage of batteries of handheld devices during charging is usually below 5.5 V, making

VCCLS supply pin suitable for a direct connection to the battery. In this case if STw5098 is

delivering the maximum power to the load and the ambient temperature is abov e 70 °C then

the simultaneous charging of the battery can ov erheat the device. A basic protection

scheme is implemented in STw5098 (activated with bit LSLIM in CR19): it limits the

maximum gain of the loudspeaker to -6 dB when VCCLS is above 4.2 V, and it removes the

limi t for VCCLS below 4.0 V. The loudspeaker gain is left unchanged if it is set below -6 dB

with bits LSG. This event (VCCLS > 4.2 V) can generate, if enabled (bit VLSMSK in CR31),

an IRQ signal.

4.11 Analog mixers

STw5098 can send to the output drivers the sum of stereo audio signals from 3 different

sources of each entity: DA path (bit MIXDAC in CR17), Microphone Preamplifiers (bit

MIXMIC in CR17) and Line In Amplifiers (bit MIXLIN in CR17). The analog mixers do not

have a gain control on the inputs, therefore the user should reduce the levels of the input

signals within the analog signal range.

The stereo analog mixers are powered up with bits ENMIXL and ENMIXR in CR2.

4.12 AD paths

In each entity the AD path converts audio signals from Microphone Preamplifiers (selected

with bit ADMIC in CR17) and Line In Amplifiers (bit ADLIN in CR17) inputs to digital domain.

If both inputs are selected then the sum of the two is converted. After AD conversion the

audio data is resampled with a sample rate converter and then processed with the internal

DSP. Two different filters are selectable in the DSP (bit ADVOICE in CR29): stereo Audio

STw5098 Functional description

25/85

Filter, with DC offset removal and FIR image filtering; and a standard mono voice-channel

filter (uses left channel input and feeds both channel output). The AD path includes a digital

gain control (ADCLG, ADCRG in CR12 and CR13 respectively) in the range -57 to +8 dB.

The maximum gain from Mic Preamplifier to AD interface is then 47 dB. When A udio filter is

selected in both AD and D A paths then D A audio data can be summed to AD data and sent

to the AD Audio Interface (see DA2ADG in CR15). Left and right channels can be

independently switched on and off to save power, if needed (bits ENADCL and ENADCR in

CR1)

4.13 DA paths

In each entity the DA path converts digital data from the digital audio interface to analog

domain and feeds it to the analog mixer. Incoming audio data is processed with a DSP

where different filters are selectable (bit DAVOICE in CR29): Audio filter, stereo, with FIR

image filtering, bass and treble controls (bits BASS and TREBLE in CR14), de-emphasis

filter; and a standard voice channel filter, mono (uses left channel input and feeds both

channel output). A dynamic compression function is available f or both audio and voice filters

(bit DYNC in CR14). The DA path includes a digital gain control (DACLG, DACRG in CR10

and CR11 respectively) in the range -65 to 0 dB. AD to DA mixing (sidetone) can be

enabled: see CR16 f or details. Left and right channel can be independently switched on and

off to save power, if needed (bits END ACL and ENDACR in CR1).

4.14 Analog-only operations

Each entity from the STw5098 can operate without AMCK master clock if analog-only

functions are used. It is possible to mix Microphone and Line In preamplifiers signals and

listen through headphones, loudspeaker or send them to line-out. The analog-only operation

is enabled with bit ENOSC in CR0. When ENOSC=1 the AD and DA paths cannot be used.

In Analog Mode, each of the two entities can handle two different stereo audio signals, so it

can be used as a front end for an external voice codec that does not include microphone

preamplifiers and power drivers: mic signal is sent through Microphone preamplifiers directly

to line out drivers (Transmit path), while Receive signal is sent through Line In amplifiers to

the selected power drivers.

4.15 Automatic Gain Control (AGC)

STw5098 provides a digital Automatic Gain Control in AD path for each entity. The circuit

can control the input gain at MIC preamplifier , Line In amplifier or both (bits ENAGCMIC and

ENAGCLIN in CR35). When one input is selected, the center gain value used for the input is

fixed with bits MICLG, MICRG, LINLG and LINRG in CR3 to CR6 (like in normal operation),

then the AGC circuit adds to all the gains a value in the range -10.5 dB to +10.5 dB (or,

extended with bit A GCRANGE in CR35, -21 dB to 21 dB), in order to obtain an average lev el

at the digital interface output in the range -6 dB to -30 dB (selected with bits AGCLEV in

CR35). The AGC added gain acts directly in the input gain, to avoid input saturation and

improve S/N ratio, so it cannot exceed the input gain range. When MIC and Line-In inputs

are selected simultaneously the control is performed on the sum of the two, preserving the

balance fixed with input gains. Different values for Attack and Decay constants can be

selected, depending on the kind of signal the AGC has to control (i.e. voice, music). The

Functional description STw5098

26/85

Attack and Decay time constants are related to the AD data rate (see bits A GCATT and

AGCDEL in CR34).

4.16 Interrupt request: IRQ pins

On each entity of the STw5098, the interrupt request feature can signal to a control device

the occurrence of particular e vents on each entity. Two control registers are used to choose

the behavior of IRQ pin: the first is a Status/Event Register (CR32), where bits can

represent the status of an internal function (i.e. a voltage is above or below a threshold) or

an event (i.e. a voltage changed crossing a threshold); the second is a Mask Register

(CR31) where if a bit in the mask is set to 1 then the corresponding bit in the Status/Event

On each entity, the IRQ pin is always active low. At VCC power up an interrupt request is

generated b y the Power-On-Reset circuit that sets to 1 bits PORMSK in CR31 and POREV

in CR32. After this event the PORMSK bit should be cleared by the user and bit IRQCMOS

in CR33 should be set according to the application (open drain or CMOS).

When an IRQ e v ent occurs a nd SPI co ntrol interface is selecte d with no serial ou tput pin it i s

still possible to identify the event (and relative status) that generated the interrupt request.

This can be done by setting the IRQ mask/enable bits (in CR31) one at the time (with

successive writings) and reading the IRQ pin status. A simple example of this is the headset

plug-in detection: at first we set bit HSDETMSK=1 in CR31 (with all the other bits set to 0). If

there is an interrupt request then we set HSDETMSK=0 and HSDETEN=1, so we can read

the HSDET status at IRQ pin. Then we read CR32 to clear its content (even if no data is

sent out).

4.17 Headset plug-in and push-button detection

Each entity of the STw5098 can detect the plug-in of a microphone connector and the

press/release event of a call/answer push-button. An application example can be found

below, while specifications can be found in

Section 10.4 on page 64

Figure 4. Plug-in and push-button detection application note

Call/Answer Button 10µF

1.5kΩ

VCCA

3kΩ

200nF AUX1L

AUX1R

CAPMIC

HDET

200nF STw5095

Generic Connector

From driver

STw5098 Functional description

27/85

4.18 Microphone biasing circuits

The Microphone Biasing Circuits can drive mono or stereo microphones and can switch

them off when not needed in order to save the current used by the microphone biasing

network on each entity. Two bits control the behavior of the microphone bias circuit: MBIAS

in CR17 enab les the circuit (fixed v oltage at MBIAS pin), while bit MBIASPD in CR17 affects

the behavior of MBIAS pin when the function is not enabled. In particular when MBIASPD=1

the MBIAS pin is pulled down, otherwise it is left in tristate mode. The specification for the

microphone biasing circuits can be found in

Section 10.6 on page 64

Control registers STw5098

28/85

5 Control registers

5.1 Summary

Table 2. Control register summary

CR#

(hex) DescriptionD7D6D5 D4 D3D2D1D0Def.

CR0

(00h) Supply & power

control #1 POWER

UP ENANA ENAMCK ENOSC ENPLL ENHSD A24V D12V 0000

0000

CR1

(01h) Power control #2 ENADCL ENADCR ENDACL ENDACR ENMICL ENMICR ENLINL ENLINR 0000

0000

CR2

(02h) Power control #3 ENLOL ENLOR ENHPL ENHPR ENHPVC

M1ENEAR

2ENLS ENMIXL ENMIXR 0000

0000

CR3

(03h) Mic gain left MICLA(2:0) MICLG(4:0) 0000

0000

CR4

(04h) Mic gain right MICRA(2:0) MICRG(4:0) 0000

0000

CR5

(05h) Line in gain left X X X LINLG(4:0) 0000

1001

CR6

(06h) Line in gain right X X X LINRG(4:0) 0000

1001

CR7

(07h) LO gain & LS

gain XLOG(2:0) 1EARG(3:0)

2LSG(3:0) 0000

0011

CR8

(08h) HPL gai n XXX HPLG(4:0) 0000

0011

CR9

(09h) HPR gain XX X HPRG(4:0) 0000

0011

CR10

(0Ah) DAC digital gain

left X X DACLG(5:0) 0000

0000

CR11

(0Bh) DAC digital gain

right X X DACRG(5:0) 0000

0000

CR12

(0Ch) ADC digital gain

left X X ADCLG(5:0) 0000

1000

CR13

(0Dh) ADC digital gain

right X X ADCRG(5:0) 0000

1000

CR14

(0Eh) Bass/treble/de-

emphasis DYNC TREBLE(2:0) BASS(3:0) 0000

0000

CR15

(0Fh) DA to AD mixing

gain X X X DA2ADG(4:0) 0000

0000

CR16

(10h)

AD to DA

mix/sidetone

gain XX AD2DAG(5:0) 0000

0000

CR17

(11h) Mixer switches &

mic bias MBIAS M

BIASPD ADMIC ADLIN MIXMIC MIXLIN MIXDAC MICLO 0000

0000

STw5098 Control registers

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CR18

(12h) Input switches X IN2VCM LINMUTE LINSEL(1:0) MICMUTE MICSEL(1:0) 0010

0100

CR19

(13h) Drivers control VCML(1:0) X MUTELO MUTEHP 1EARLIM

2LSLIM 1EARSEL(1:0)

2LSSEL(1:0) 0101

1000

CR20

(14h) DAOCK

frequency LSB DAOCKF(7:0) 0000

0000

CR21

(15h) DAOCK

frequency MSB DAOCKF(15:8) 0000

0000

CR22

(16h) DA clock

genera tor contro l XXDAMAST

MASTGEN END

AOCK DAO

CK512 DAPCMF(1:0) 0000

0000

CR23

(17h) ADOCK

frequency LSB ADOCKF(7:0) 0000

0000

CR24

(18h) ADOCK

frequency MSB ADOCKF(15:8) 0000

0000

CR25

(19h) AD Clock

genera tor contro l XXADMAST

MASTGEN ENA

DOCK ADO

CK512 ADPCMF(1:0) 0000

0000

CR26

(1Ah) DAC data IF

control X DAFORM(2:0) DASPIM DAWL(2:0) 0000

0000

CR27

(1Bh) ADC data IF

control ADRTOL ADFORM2:0) ADSPIM ADWL(2:0) 0000

0000

CR28

(1Ch) DAC&ADC data

IF control AMC

KINV DACKP DASYNCP DAMONO ADCKP AD

SYNCP ADMONO ADHIZ 0000

0000

CR29

(1Dh) Digital filters

control X DAVOICE DA96K RXNH ADVOICE AD96K ADNH TXNH 0000

0000

CR30

(1Eh) Soft reset &

AMCK range SWRES X X X AMCKSIN CKRANGE(2:0) 0000

0000

CR31

(1Fh) Interrupt mask VLSHEN PUSH

BEN HSDETEN VLSHMSK PUSH

BMSK HSDET

MSK OVFMSK PORMSK 0000

0000

CR32

(20h) Interrupt status VLSH PUSHB HSDET VLSHEV PUSHBEV HSDETEV OVFEV POREV 0000

0000

CR33

(21h) Misc. control X X SPIOHIZ SPIOSEL(1:0) IRQCMOS OVFDA OVFAD 0000

0000

CR34

(22h)

AGC

attack/decay

coeff. AGCATT(3:0) AGCDEC(3:0) 0000

0000

CR35

(23h) AGC control XENA

GCLIN ENAG

CMIC AGC

RANGE AGCLEV(3:0) 0000

0000

CR36

(24h) RESERVED XXX XXXXX

0000

Note: X reserved, write zero

Table 2. Control register summary

CR#

(hex) DescriptionD7D6D5 D4 D3D2D1D0Def.

Control registers STw5098

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Caution: In the following

Section 5: Control registers

, reference to each entity is omitted. Each entity

of the STw5098 has the same register set.

5.2 Supply and power control

CR#

(hex) DescriptionD7D6D5D4D3D2D1D0Def.

CR0

(00h) Supply & power

control #1 POWER

UP ENANA ENAMCK ENOSC ENPLL ENHSD A24V D12V 0000

0000

CR1

(01h) Power control #2 ENADCL ENADCR ENDACL ENDACR ENMICL ENMICR ENLINL ENLINR 0000

0000

CR2

(02h) Power control #3 ENLOL ENLOR ENHPL ENHPR ENH

PVCM ENLS ENMIXL ENMIXR 0000

0000

Table 3. CR0 description

Bits Name Val. CR0 description Def.

7POWERUP 1

0All the enabled analog and digital blocks are in power up

All the device is in power down 0

6 ENANA 1

0The analog blocks can be enabled

All the analog blocks are in power down 0

5ENAMCK 1

0AMCK clock input pin is enabled

AMCK clock input pin is disabled 0

4ENOSC 1

The Internal oscillator is enabled.

The analog blocks use oscillator clock

The internal oscillator is in power down 0

3ENPLL 1

0The PLL is enabled

The PLL is in power down 0

2 ENHSD 1

0The headset plug-in detector is enabled

The headset plug-in detector is disabled 0

1A24V 1

0Analog supply pins voltage range is 2.4V<VCCA<2.7V

Analog supply pins voltage range is 2.7V<VCCA<3.3V 0

0D12V 1

0Digital I/O pin voltage rang e is 1.2V<VCCIO<1.8V

Digital I/O pin voltage rang e is 1.71V<VCCIO<VCC 0

STw5098 Control registers

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Table 4. CR1 description

Bits Name Value CR1 description Def.

7 ENADCL 1

0The left channel A/D converter is enabled

The left channel A/D converter is in power down 0

6 ENADCR 1

0The right ch annel A/D converter is enabled

The right ch annel A/D converter is in power dow n 0

5ENDACL 1

0The left channel D/A converter is enabled

The left channel D/A converter is in power down 0

4ENDACR 1

0The right ch annel D/A converter is enabled

The right ch annel D/A converter is in power dow n 0

3ENMICL 1

0The left channel microphone preamplifier is enabled

The left channel microphone preamplifier is in power down 0

2ENMICR 1

0The right channel microphone preamplifier is enabled

The right channel microphone preamplifier is in power down 0

1ENLINL 1

0The left channel line-in preamplifier is enabled

The left channel line-in preamplifier is in power down 0

0ENLINR 1

0The right channel line-in preamplifier is ena bled

The right channel line-in preamplifier is in p ower down 0

Table 5. CR2 description

Bit # Name Value CR2 Description Def.

7ENLOL 1

0The left channel line out driver is enabled

The left channel line out driver is in power down (default) 0

6ENLOR 1

0The right channel line out driver is enabled

The right channel line out driver is in power down (default) 0

5 ENHPL 1

0The left channel headphones driver is enabled

The left channel headphones driver is in power down (default) 0

4 ENHPR 1

0The right ch annel headphones driver is enabled

The right channel headphones driver is in power down (default) 0

3 ENHPVCM 1

0The headphones reference voltage generator is enabled

The headphones reference voltage generator is in power down (def) 0

21ENEAR 1

0The 32Ω earphone amplifier is enabled

The 32Ω earphone amplifier is in power down (default) 0

2ENLS 1

0The 8Ω loudspeaker amplifier is enabled

The 8Ω loudspeaker amplifier is in power down (default) 0

1ENMIXL 1

0The left channel analog output mixer is enabled

The left channel analog output mixer is in power down (default) 0

0ENMIXR 1

0The right channel analog output mixer is enabled

The right channel analog output mixer is in power down (default) 0

Control registers STw5098

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5.3 Gains

CR#

(hex) DescriptionD7D6D5D4D3D2D1D0Def.

CR3

(03h) Mic gain left MICLA(2:0) MICLG(4:0) 0000

0000

CR4

(04h) Mic gain right MICRA(2:0) MICRG(4:0) 0000

0000

CR5

(05h) Line in gain left XXX LINLG(4:0) 0000

1001

CR6

(06h) Line in gain right X X X LINRG(4:0) 0000

1001

CR7

(07h) LO gain & LS

gain X LOG(2:0) LSG(3:0) 0000

0011

CR8

(08h) HPL gai n XXX HPLG(4:0) 0000

0011

CR9

(09h) HPR gain XXX HPRG(4:0) 0000

0011

CR10

(0Ah) DAC digital gain

left X X DACLG(5:0) 0000

0000

CR11

(0Bh) DAC digital gain

right X X DACRG(5:0) 0000

0000

CR12

(0Ch) ADC digital gain

left X X ADCLG(5:0) 0000

1000

CR13

(0Dh) ADC digital gain

right X X ADCRG(5:0) 0000

1000

Table 6. CR3 and CR4 description

Bits Name CR3

Name CR4 Value CR3 and CR4 description Def.

7-5 MICLA(2:0)

MICRA(2:0)

000

001

010

...

110

111

Left (CR3) and right (CR4) channels microphone attenuation

0.0 dB gain (default)

-1.5 dB gain

-3.0 dB gain

...step 1.5 dB

-9.0 dB gain

-12.0 dB gain

000

4-0 MICLG(4:0)

MICRG(4:0)

00000

00001

00010

...

11010

Left (CR3) and right (CR4) channels microphone gain

0.0 dB gain (default)

1.5 dB gain

3.0 dB gain

...step 1.5 dB

39.0 dB gain

00000

STw5098 Control registers

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Table 7. CR5 and CR6 description

Bits Name CR5

Name CR6 Value CR5 and CR6 description Def.

4-0 LINLG(4:0)

LINRG(4:0)

00000

00001

00010

...

01001

...

10011

Left (CR5) and right (CR6) channels line in gain

18.0 dB gain

16.0 dB gain

14.0 dB gain

...step 2.0 dB

0.0 dB gain (default)

...step 2.0 dB

-20.0 dB gain

01001

Table 8. CR7 description

Bits Name Value CR7 description Def.

6-4 LOG(2:0) 000

001

010

...

110

Left and right channel line out drivers gain

Gain to differential output Equivalent single-ended gain

18.0 dB gain (default) -24.0 dB gain (default)

-15.0 dB gain -21.0 dB gain

-12.0 dB gain -18.0 dB gain

...step 3 dB ...step 3 dB

00 dB gain -6.0 dB gain

000

3-0

1EARG(3:0) 0000

0001

0010

0011

...

1111

32Ω earphone gain/ 8Ω loudspeaker gain

6.0 dB gain

4.0 dB gain

2.0 dB gain

0.0 dB gain (default)

...step 2.0 dB

-24.0 dB gain

0011

2LSG(3:0)

Table 9. CR8 and CR9 description

Bits Name CR8

Name CR9 Value CR8 and CR9 description Def.

4-0 HPLG(4:0)

HPRG(4:0)

00000

00001

00010

00011

...

10100

Left (CR8) and right (CR9) channels headphones driver gain

0.0 dB gain

-2.0 dB gain

-4.0 dB gain

-6.0 dB gain (default)

...step 2.0 dB

-40.0 dB gain

00011

Control registers STw5098

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Table 10. CR10 and CR11 description

Bits Name CR10

Name CR11 Value CR10 and CR11 description Def.

5-0 DACLG(5:0)

DACRG(5:0)

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

Left (CR10) and right (CR11) channels DAC digital gain

0.0 dB gain (default)

-1.0 dB gain

-2.0 dB gain

-3.0 dB gain

-4.0 dB gain

-5.0 dB gain

-6.0 dB gain

-7.0 dB gain

-8.0 dB gain

-9.0 dB gain

-10.0 dB gain

-11.0 dB gain

-12.0 dB gain

-13.0 dB gain

-14.0 dB gain

-15.0 dB gain

-16.0 dB gain

-17.0 dB gain

-18.0 dB gain

-20.0 dB gain

-22.0 dB gain

-24.0 dB gain

-26.0 dB gain

-28.0 dB gain

-30.0 dB gain

-32.0 dB gain

-34.0 dB gain

-36.0 dB gain

-38.0 dB gain

-41.0 dB gain

-44.0 dB gain

-47.0 dB gain

-50.0 dB gain

-53.0 dB gain

-56.0 dB gain

-59.0 dB gain

-65.0 dB gain

-∞ dB gain

000000

STw5098 Control registers

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Table 11. CR12 and CR13 description

Bits Name CR12

Name CR13 Value CR12 and CR13 description Def.

5-0 ADCLG(5:0)

ACDRG(5:0)

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

Left (CR12) and right (CR13) channels ADC digital gain

8.0 dB gain

7.0 dB gain

6.0 dB gain

5.0 dB gain

4.0 dB gain

3.0 dB gain

2.0 dB gain

1.0 dB gain

0.0 dB gain (default)

-1.0 dB gain

-2.0 dB gain

-3.0 dB gain

-4.0 dB gain

-5.0 dB gain

-6.0 dB gain

-7.0 dB gain

-8.0 dB gain

-9.0 dB gain

-10.0 dB gain

-11.0 dB gain

-12.0 dB gain

-14.0 dB gain

-16.0 dB gain

-18.0 dB gain

-20.0 dB gain

-22.0 dB gain

-24.0 dB gain

-26.0 dB gain

-28.0 dB gain

-30.0 dB gain

-33.0 dB gain

-36.0 dB gain

-39.0 dB gain

-42.0 dB gain

-45.0 dB gain

-48.0 dB gain

-51.0 dB gain

-57.0 dB gain

-∞ dB gain

001000

Control registers STw5098

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5.4 DSP control

CR#

(hex) DescriptionD7D6D5D4D3D2D1D0Def.

CR14

(0Eh) Bass/treble/de-

emphasis DYNC TREBLE(2:0) BASS(3:0) 0000

0000

CR15

(0Fh) DA to AD mixing

gain XXX DA2ADG(4:0) 0000

0000

CR16

(10h)

AD to DA

mix/sidetone

gain XX AD2DAG(5:0) 0000

0000

Table 12. CR14 description

Bits Name Value CR14 description Def.

7DYNC 1

0Audio dynamic compression in D/A path is enabled

Audio dynamic compression in D/A path is disabled 0

6-4 TREBLE(2:0)

011

010

001

000

111

110

101

100

Treble control in D /A path

+6.0 dB tr eble gain

+4.0 dB tr eble gain

+2.0 dB tr eble gain

0.0 dB treble gain

-2.0 dB treble gai n

-4.0 dB treble gai n

-6.0 dB treble gai n

De-emphasis filter enabled

000

3-0 BASS(3:0)

0101

0100

0011

0010

0001

0000

1111

1110

1101

1100

1011

Bass control in D/A path

+12.5 dB bass gain

+10.0 dB bass gain

+7.5 dB bass gain

+5.0 dB bass gain

+2.5 dB bass gain

0.0 dB bass gain

-2.5 dB bass gain

-5.0 dB bass gain

-7.5 dB bass gain

-10.0 dB bass gain

-12.5 dB bass gain

0000

STw5098 Control registers

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Table 13. CR15 description

Bits Name Value CR15 description Def.

4-0 DA2ADG(4:0)*

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

DA to AD mixing (Audio filter in D/A and A/D path selected)

DA to AD mixing disabled (default)

+2.0 dB gain

0.0 dB gain

-2.0 dB gain

-4.0 dB gain

-6.0 dB gain

-8.0 dB gain

-10.0 dB gain

-12.0 dB gain

-14.0 dB gain

-16.0 dB gain

-18.0 dB gain

-20.0 dB gain

-22.0 dB gain

-24.0 dB gain

-26.0 dB gain

-28.0 dB gain

-30.0 dB gain

-32.0 dB gain

-34.0 dB gain

-36.0 dB gain

-38.0 dB gain

-40.0 dB gain

00000

* When Voice filter in D/A or A/D path is selected this function is disabled

Note:

D/A to A/D mixing is performed at AD data rate, so if A/D and D/A rates are different then asynchronous sampling artifacts

may occur.

Control registers STw5098

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Table 14. CR16 description

Bits Name Value CR16 description Def.

5-0 AD2DAG(5:0)

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

AD to DA mixing (sidetone)

AD to DA mixing disabled (default)

-1.0 dB gain

-2.0 dB gain

-3.0 dB gain

-4.0 dB gain

-5.0 dB gain

-6.0 dB gain

-7.0 dB gain

-8.0 dB gain

-9.0 dB gain

-10.0 dB gain

-11.0 dB gain

-12.0 dB gain

-13.0 dB gain

-14.0 dB gain

-15.0 dB gain

-16.0 dB gain

-17.0 dB gain

-18.0 dB gain

-19.0 dB gain

-20.0 dB gain

-21.0 dB gain

-22.0 dB gain

-23.0 dB gain

-24.0 dB gain

-25.0 dB gain

-26.0 dB gain

-27.0 dB gain

-28.0 dB gain

-29.0 dB gain

-30.0 dB gain

-31.0 dB gain

-32.0 dB gain

-33.0 dB gain

-34.0 dB gain

-35.0 dB gain

-36.0 dB gain

-37.0 dB gain

-38.0 dB gain

-39.0 dB gain

-40.0 dB gain

-41.0 dB gain

-42.0 dB gain

000000

STw5098 Control registers

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5.5 Analog functions

CR#

(hex) DescriptionD7D6D5D4D3D2D1D0Def.

CR17

(11h) Mixer switches &

Mic Bias MBIAS MBIASPD ADMIC ADLIN MIXMIC MIXLIN MIXDAC MICLO 0000

0000

CR18

(12h) Input switches X IN2VCM LINMUTE LINSEL(1:0) MICMUTE MICSEL(1:0) 0010

0100

CR19

(13h) Drivers control VCML(1:0) X MUTELO MUTEHP LSLIM LSSEL(1:0) 0101

1000

Table 15. CR17 description

Bits Name Value CR17 description Def.

7 MBIAS 1

0Microphone Bias enabled (2.1V typ at MBIAS pin)

Microphone Bias disabled 0

6 MBIASPD 1

0MBIAS pin is pulled down when microphone bias is disabled

MBIAS pin is in high impedance state when microphone Bias is

disabled 0

5ADMIC 1

0Microphone preamplifiers are connected to AD path

Microphone preamplifiers are not connected to AD path 0

4ADLIN 1

0Line in preamp lifiers are conn ec ted to AD path

Line in preamplifiers are not connected to AD path 0

3MIXMIC 1

0Microphone preamplifiers are connected to mixers

Microphone preamplifiers are not connected to mixers 0

2MIXLIN 1

0Line in preamp lifiers are conn ec ted to mixers

Line in preamplifiers are not connected to mixers 0

1MIXDAC 1

0Stereo DAC path is connected to mixers

Stereo DAC path is not connected to mixers 0

0MICLO 1

0Microphone preamplifiers are connected to line out drivers

Mixers are connected to line out drivers 0

Table 16. CR18 description

Bits Name Value CR18 description Def.

6IN2VCM 1

0Unused analog input pins are biased to common mode voltage

Unused analog input pins are in high impedance state 0

5LINMUTE 1

0Line in preamp lifiers are mu ted

Line in preamplifiers are not muted 1

4-3 LINSEL(1:0) 00

Input pins connected to line in preamplifiers (if LINMUTE=0)

LINEIN (LINEINL, LINEINR)

AUX1 (AUX1L, AUX1R)

AUX2 (AUX2LP-AUX2LN, A UX2 RP-AUX2RN)

AUX3 (AUX3L, AUX3R)

Control registers STw5098

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2MICMUTE 1

0Microphone preamplifiers are muted

Microphone preamplifiers are not muted 1

1-0 MICSEL(1:0) 00

Input pins connected to microphone preamplifiers (if MICMUTE=0)

MIC (MICLP-MICLN, MICRP-MICRN)

AUX1 (AUX1L, AUX1R)

AUX2 (AUX2LP-AUX2LN, A UX2 RP-AUX2RN)

AUX3 (AUX3L, AUX3R)

Table 17. CR19 description

Bits Name Value CR19 Description Def.

7-6 VCML(1:0) 00

Common mode voltage level for line out and headphones drivers

1.20 V

1.35 V (default)

1.50 V

1.65 V

4MUTELO 1

0Line out drivers are muted

Line out drivers are not muted 1

3MUTEHP 1

0Headphones drivers (HP) are muted

Headphones drivers (HP) are not muted 1

21EARLIM 1

0EAR/LS driver gain is limited when VCCLS is above 4.2V typ

EAR/LS driver (LS) gain is not limited 0

2LSLIM

1-0

1EARSEL(1:0) 00

Mute Loudspeaker driver (LS) is muted

Right Right channel mixer only co nnected to loudspeaker driver

Left Left channel mixer only connected to loudspeaker driver

Mono (Left + Right)/2 channel mixers connected to loudspeaker

driver

2LSSEL(1:0)

Table 16. CR18 description

Bits Name Value CR18 description Def.

STw5098 Control registers

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5.6 Digital audio interfaces master mode and clock generators

CR#

(hex) DescriptionD7D6D5 D4 D3D2D1D0Def.

CR20

(14h) DAOCK

frequency LSB DAOCKF(7:0) 0000

0000

CR21

(15h) DAOCK

frequency MSB DAOCKF(15:8) 0000

0000

CR22

(16h) DA c lock

genera tor contro l X X DAMAST DA

MASTGEN END

OCK DAO

CK512 DAPCMF(1:0) 0000

0000

CR23

(17h) ADOCK

frequency LSB ADOCKF(7:0) 0000

0000

CR24

(18h) ADOCK

frequency MSB ADOCKF(15:8) 0000

0000

CR25

(19h)

AD clock

generator

control X X ADMAST AD

MASTGEN ENA

DOCK ADO

CK512 ADPCMF(1:0) 0000

0000

Table 18. CR21-20 and CR24-23 description

Bits Name CR21-20

Name CR24-23 Value CR21-20 and CR24-23 Description Def.

15-0 DAOCKF(15:0)

ADOCKF(15:0) K

The follo w in g formulas can be used to obta in the value of K for the

desired FS or OCK respectively in the clock generator

FS: Data rate (DA_SYNC or AD_SYNC frequency in master mode)

OCK: Oversampled clock frequency (DA_OCK or AD_OCK)

AMCK: Input master clock frequency

MCKCOEFF: See CR30 for definition

OSR: See bit 2 in CR22 and CR25

0000h

Note: CR21-20 and CR24-23 are meaningful in master mode only.

KFS()round 225 FS

AMCK MCKCOEFF⋅

--------------------------------------------------------------

⎝⎠

⎛⎞

KOCK()round 225 OCK

AMCK MCKCOEFF OSR⋅⋅

------------------------------------------------------------------------------------

⎝⎠

⎛⎞

Table 19. CR22 and CR25 description

Bits Name CR22

(Name CR25) Value CR22 and CR25 description Def.

5DAMAST

(ADMAST) 1

0DA (AD) Audio interface is in master mode (low impedance output)

DA (AD) Audio interface is in slave mode (high impedance input) 0

4DAMASTGEN

(ADMASTGEN) 1

0DA (AD) Master generator is enabled

DA (AD) Master generator is disabled 0

3ENDAOCK

(ENADOCK) 1

0DA_O CK (AD_ OCK) output clock is enabled

DA_O CK (AD_ OCK) output clock is disabl ed 0

Control registers STw5098

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2DAOCK512

(ADOCK512) 1

Definition of DA_OSR (AD_OSR)

DA_OCK/DA_SYNC (AD_OCK/AD_SYNC) ratio in maste r mode is

512

da_ock/da_sync (ad_ock/ad_sync) ratio in master mode is 256

1-0 DAPCMF(1:0)

(ADPCMF(1:0))

DA_CK/DA_SYNC (AD_CK/AD_SYNC) Ratio in PCM master mode

- 16 when CR26 DAWL=000 (CR27 ADWL=000)

- 32 when CR26 DAWL≠000 (CR27 ADWL≠000)

- 64

- 128

- 256 when CR22 DAOCK512=0 (CR25 ADOCK512=0)

- 512 when CR22 DAOCK512=1 (CR25 ADOCK512=1)

Table 19. CR22 and CR25 description

Bits Name CR22

(Name CR25) Value CR22 and CR25 description Def.

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5.7 Digital audio interfaces

CR#

(hex) DescriptionD7D6D5D4D3D2D1D0Def.

CR26

(1Ah) DAC data IF

control X DAFORM(2:0) DASPIM DAWL(2:0) 0000

0000

CR27

(1Bh) ADC data IF

control ADRTOL ADFORM2:0) ADSPIM ADWL(2:0) 0000

0000

CR28

(1Ch) DAC&ADC data

IF control AMCKINV DACKP DASYNCP DAMONO ADCKP AD

SYNCP ADMONO ADHIZ 0000

0000

Table 20. CR26 description

Bits Name Value CR26 Description Def.

6-4 DAFORM(2:0)

000

001

010

011

100

111

DA audio interface format selection

Delayed format (I2S compatible )

Left aligned format

Right aligned format

DSP format

SPI format

PCM format (uses left channel)

000

3 DASPIM 1

0DA interface in SPI mode receives one word for both channels

DA interface in SPI mode receives two words

(alternated, left chann el firs t) 0

2-0 DAWL(2:0)

000

001

010

011

100

DA interface word length

16 bit

18 bit

20 bit

24 bit

32 bit

000

Table 21. CR27 description

Bits Name Value CR27 description Def.

7ADRTOL 1

0AD right channel sent to PCM I/F (must set ENADCR=0 in CR1)

Normal operation 0

6-4 ADFORM(2:0)

000

001

010

011

100

111

AD audio interface format selection

Delayed format (I2S compatible )

Left aligned format

Right aligned format

DSP format

SPI format

PCM format (sends out left channel)

000

Control registers STw5098

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3 ADSPIM 1

0AD interface in SPI mode sends one channel (left)

AD interface in SPI mode sends two channels (alternated, left first) 0

2-0 ADWL(2:0)

000

001

010

011

100

AD interface word length

16 bit

18 bit

20 bit

24 bit

32 bit

000

Table 22. CR28 description

Bits Name Value CR28 description Def.

7AMCKINV 1

0AMCK is inverted

AMCK is not inverted 0

6DACKP 1

0DA Bit clock pin (DA_CK) polarity is inverted

DA Bit clock pin (DA_CK) polarity is not inverted 0

5 DASYNCP

DSP and PCM formats in DA interface

Non delayed format

Delayed format 0

Delayed, left-aligned, right-aligned and SPI formats in DA interface

DA sync pin (DA_SYNC) polarity is inverted

DA sync pin (DA_SYNC) polarity is not inverted

4DAMONO 1

Mono mode: (L+R)/2 from Audio Interface is used on both DAC

channels

Stereo mo de 0

3 ADCKP 1

0AD Bit clock pin (AD_CK) polarity is inverted

AD Bit clock pin (AD_CK) polarity is not inverted 0

2 ADSYNCP

DSP and PCM formats in AD interface

Non delayed format

Delayed format 0

Delayed, left-aligned, right-aligned and SPI formats in AD interface

DA sync pin (DA_SYNC) polarity is inverted

DA sync pin (DA_SYNC) polarity is not inverted

1ADMONO 1

Mono m ode : (L +R )/2 fro m ADC is s en t to both ch ann els i n the A udio

interface

Stereo mo de 0

0 ADHIZ 1

AD data pin (AD_DATA) is in high impedance state when no data is

available

AD data pin (AD_DATA) is forced to 0 when no data is available 0

Table 21. CR27 description (continued)

Bits Name Value CR27 description Def.

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5.8 Digital filters, software reset and master clock control

CR#

(hex) DescriptionD7D6D5D4D3D2D1D0Def.

CR29

(1Dh) Digital filters

control X DAVOICE DA96K RXNH ADVOICE AD96K ADNH TXNH 0000

0000

CR30

(1Eh) Soft reset &

AMCK range SWRES X X X AMCKSIN CKRANGE(2:0) 0000

0000

Table 23. CR29 description

Bits Name Value CR29 description Def.

6DAVOICE 1

0DA path voice RX filter is enabled (single channel, left used)

DA path voice filters are enabled 0

5DA96K 1

0DA path data rate is in the range 88 kHz to 96 kHz

DA path data rate is in the range 8 kHz to 48 kHz 0

4RXNH 1

0DA path high pass voice RX filter is disabled

DA path high pass voice RX filter is enabled (300Hz @ 8kHz rate) 0

3ADVOICE 1

0AD path voice TX filter is enabled (single channel, left used)

AD path audio filters are enabled 0

2AD96K 1

0AD path data rate is in the range 88 kHz to 96 kHz

AD path data rate is in the range 8 kHz to 48 kHz 0

1 ADNH 1

0AD path audio DC filter is disab led

AD path audio DC filter is enabled 0

0TXNH 1

0AD path high pass voice TX filter is disabled

AD path high pass voice TX filter is enabled (300Hz @ 8kHz rate) 0

Table 24. CR30 description

Bits Name Value CR30 description Def.

7SWRES 1

0Software reset: All registers content is reset to the default value

Control Register content is left unchanged 0

3 AMCKSIN 1

0Signal at AMCK pin is a sinusoid

Signal at AMCK pin is a square wave 0

2-0 CKRANGE(2:0)

000

001

010

011

100

101

AMCK range MCKCOEFF

4.0 MHz to 6.0 MHz 8.0

6.0 MHz to 8.0 MHz 6.0

8.0 MHz to 12.0 MHz 4.0

12.0 MHz to 16.0 MHz 3.0

16.0 MHz to 24.0 MHz 2.0

24.0 MHz to 32.0 MHz 1.5

000

Control registers STw5098

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5.9 Interrupt control and control interface SPI out mode

Note: Value at IRQ pin is:

CR#

(hex) DescriptionD7D6D5D4D3D2D1D0Def.

CR31

(1Fh) Interrupt mask VLSHEN PUSH

BEN HSDETEN VLSHMSK PUSH

BMSK HSDET

MSK OVFMSK PORMSK 0000

0000

CR32

(20h) Interrupt status VLSH PUSHB HSDET VLSHEV PUSHBEV HSDETEV OVFEV POREV 0000

0000

CR33

(21h) Misc. control x X SPIOHIZ SPIOSEL(1:0) IRQCMOS OVFDA OVFAD 0000

0000

Table 25. CR31 description

Bits Name Value CR31description Def.

7VLSHEN 1

0VLSH status can be seen at IRQ output

VLSH status is masked 0

6 PUSHBEN 1

0PUSHB status can be seen at IRQ output

PUSHB status is masked 0

5 HSDETEN 1

0HSDET status can be seen at IRQ output

HSDET status is masked 0

4VLSHMSK 1

0VLSH event can be seen at IRQ output

VLSH event is masked 0

3 PUSHBMSK 1

0PUSH B event can be seen at IRQ output

PUSHB event is masked 0

2 HSDETMSK 1

0HSDET event can be seen at IRQ output

HSDET event is masked 0

1OVFMSK 1

0OVF event can be seen at IRQ output

OVF event is masked 0

0PORMSK 1

0POR event can be seen at IRQ output

POR event is masked 0

Table 26. CR32 description

Bits Name Read

only CR32 description Def.

7VLSH* 1

0VCCLS is above 4.2 V

VCCLS is below 4.0 V 0

6 PUSHB* 1

0Headset Button is pressed

Headset Button is released 0

5 HSDET* 1

0Headset Connector is inserted

Headset Connector is not inserted 0

IRQ (1 or Z) when (CR31 & CR32) = 00 hex

0 when (CR31 & CR32) 00 hex≠

⎩

⎨

⎧

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4VLSHEV 1

0VLSH bit has changed

VLSH bit has not changed 0

3 PUSHBEV 1

0Headset Button S tatus has changed

Headset Button S tatus has no t changed 0

2 HSDETEV 1

0Headset Connector Status has changed

Headset Connector Status has not changed 0

1 OVFEV 1

0An Audio Data overflow has occurred in DSP

No Audio Data overflow has occurred in DSP 0

0POREV 1

0Device was reset by power-on-reset

Device was not reset by power-on-reset 0

Note: content of bits 4 to 0 in CR32 is cleared after reading, while it is left unchanged if accessed for writing.

*Bits 7 to 5 represent the status when the Control register is read, not when the event occurred.

Table 26. CR32 description (continued)

Bits Name Read

only CR32 description Def.

Table 27. CR33 description

Bits Name Val. CR33 description Def.

5 SPIOHIZ 1

SPI control interface out pin is set to high impedance state when

inactive

SPI control interface out pin is set to zero when inactive 0

4-3 SPIOSEL(1:0) 00

Out pin selection for SPI control interface

No output. Control registers cannot be read in SPI mode

SPI output sent to IRQ pin

SPI output sent to DA_OCK pin

SPI output sent to AD_OCK pin

2 IRQCMOS 1

0IRQ interrupt request pin is set to CMOS (active low)

IRQ interrupt request pin is set to pull down 0

1OVFDA 1

0An overflow (saturation) occurred in DA path

No overflow occurred in DA channel 0

0 OVFAD 1

0An overflow (saturation) occurred in AD path

No overflow occurred in AD channel 0

Note: content of bits 1 to 0 in CR33 is cleared after reading, while it is left unchanged if accessed for writing.

Control registers STw5098

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5.10 AGC

CR#

(hex) DescriptionD7D6D5D4D3D2D1D0Def.

CR34

(22h)

AGC

attack/decay

coeff. AGCATT(3:0) AGCDEC(3:0) 0000

0000

CR35

(23h) AGC control XENAG

CLIN ENAG

CMIC AGC

RANGE AGCLEV(3:0) 0000

0000

Table 28. CR 34 description

Bits Name Value CR 34 description Def.

7-4 AGCATT(3:0)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

AGC attack time constant; FS=AD data rate

0000

A u dio filter in AD path

4096 / FS

2048 / FS

1365 / FS

1024 / FS

683 / FS

512 / FS

341 / FS

256 / FS

171 / FS

128 / FS

85 / FS

64 / FS

43 / FS

32 / FS

Voice filter in AD path

8192 / FS

4096 / FS

2731 / FS

2048 / FS

1365 / FS

1024 / FS

683 / FS

512 / FS

341 / FS

256 / FS

171 / FS

128 / FS

85 / FS

64 / FS

3-0 AGCDEC(3:0)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

AGC decay time constant; FS=AD data rate

0000

A u dio filter in AD path

65536 / FS

32768 / FS

21845 / FS

16384 / FS

10923 / FS

8192 / FS

5461 / FS

4096 / FS

2731 / FS

2048 / FS

1365 / FS

1024 / FS

683 / FS

512 / FS

341 / FS

256 / FS

Voice filter in AD path

131072 / FS

65536 / FS

43691 / FS

32768 / FS

21845 / FS

16384 / FS

10923 / FS

8192 / FS

5461 / FS

4096 / FS

2731 / FS

2048 / FS

1365 / FS

1024 / FS

683 / FS

512 / FS

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Table 29. CR 35 description

Bits Name Value CR35 description Def.

6ENAGCLIN 1

0AGC control on AD path acts on Line In Gain

AGC control on AD path does not act on Line In Gain 0

5ENAGCMIC 1

0AGC control on AD path acts on Mic Gain

AGC control on AD path does not act on Mic Gain 0

4 AGCRANGE 1

0AGC action range is -21.0 dB to +21.0 dB

AGC action range is -10.5 dB to +10.5 dB 0

3-0 AGCLEV(3:0)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

AGC requested output level

-30.0 dB gain

-27.0 dB gain

-24.0 dB gain

-21.0 dB gain

-18.0 dB gain

-15.0 dB gain

-12.0 dB gain

-9.0 dB gain

-6.0 dB gain

0000

Control interface and master clock STw5098

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6 Control interface and master clock

Unless specified, the following description applies to both entities.

6.1 Control interface I2C mode

Figure 5. Control interface I2C format

Note: CMOD pin tied to GND

Figure 6. Control interface: I2C format timing

WRITE

SINGLE BYTE START

DEVICE ADDRESSREG n ADDRESS REG n DATA IN

ACK ACK ACK

STOP

WRITE

MULTI BYTE START

DEVICE ADDRESSREG n ADDRESS REG n DATA IN

ACK ACK ACK

STOP

REG n+m DATA IN

ACK

m+1 data bytes

CURRENT ADDR

START

DEVICE ADDRESS

Current REG DATA OUT

ACK NO ACK

STOP

READ

SINGLE BYTE

CURRENT ADDR

START

DEVICE ADDRESS

Current REG DATA OUT

ACK NO ACK

STOP

READ

MULTI BYTE Curr REG+m DATA OUT

ACK

m+1 data bytes

START

DEVICE ADDRESSREG n ADDRESS

ACK ACK

START

DEVICE ADDRESS REG n DATA OUT

ACK NO ACK

STOP

RANDOM ADDR

READ

SINGLE BYTE

RANDOM ADDR

READ

MULTI BYTE START

DEVICE ADDRESSREG n ADDRESS

ACK ACK

START

DEVICE ADDRESS NO ACK

STOP

REG n+m DATA OUT

ACK ACK

m+1 data bytes

REG n DATA OUT

ACK

001101AS

001101AS0

001101AS

001101AS0

001101AS

(STO)

(STA)

SU (STA)

(DAT)

HIGH

BUF (DAT)

LOW

(STA)

P S P

P=STOP

S = START

Sr = START repeated

SDA

SCLK

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6.2 Control interface SPI mode

Figure 7. Control interface SPI format(a)

Table 30. Control interface timing with I²C format

Symbol Parameter Test conditions Min. Typ. Max. Unit

fSCL Clock frequency 400 kHz

tHIGH Clock pulse width high 600 ns

tLOW Clock pulse width low 1300 ns

tRSDA and SCLK rise time 1000 ns

tFSDA and SCLK fall time 300 ns

tHD:STA Start condition hold time 600 ns

tSU:STA Start condition setup time 600 ns

tHD:DAT Data input hold time 0 ns

tSU:DAT Data input setup time 250 ns

tSU:STO Stop condition setup tim e 6 00 ns

tBUF Bus free time 1300 ns

a. CMOD pin tied to VCCIO; SDO pin position selected with bits SPIOSEL in CR33.

A6 A5

8 bit Addres s

A4 A3 A2 A1 A0

W/R D7 D6 D5 D4 D3 D2 D1 D0

8 bit Data

SDIN

D7 D6 D5 D4 D3 D2 D1 D0

8 bit Data

SDO

SCLK

CSB

SPIOHIZ=1

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Figure 8. Control interface: SPI format timing

tDDO tDDOLtDDOF

SPIOHIZ=0

SPIOHIZ=1

tSCSF tHSCKtLSCK

tSDI tHDI

tSCSR

tHICS

SDIN

SDO

SCLK

CSB

1580

W/R D7

D7 D0

tPSCK tHCS

Table 31. Control interface signal timing with SPI format

Symbol Parameter Test conditions Min. Typ. Max. Unit

tHICS CSB pulse width high 80 ns

tSCSR Setup time CSB rising

edge to SCLK rising edge 20 ns

tSCSF Setup time CSB fa lling

edge to SCLK rising edge 20 ns

tHCS Hold time CSB rising edge

from SCLK rising edge 20 ns

tSDI Setup time SDIN to SCLK

rising edge 20 ns

tHDI Hold time SDIN from SCLK

rising edge 20 ns

tDDOF SDO first Delay time from

SCLK f al lin g edge 30 ns

tDDO SDO Delay time from

SCLK f al lin g edge 20 ns

tDDOL SDO Dela y time fro m CSB

rising edge 30 ns

tPSCK Period of SCK 100 ns

tHSCK SCK pulse width high Measured from VIH to VIH 40 ns

tLSCK SCK pulse width low Measured from VIL to VIL 40 ns

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6.3 Master clock timing

Table 32. AMCK timing

Symbol Parameter AMCK range Min. Typ. Max. Unit

tCKDC AMCK d

uty cyc le

MHz

-8

MHz

-32 M

40 55

60 %

Audio interfaces STw5098

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7 Audio interfaces

Information included in the following section is valid f or both entities.

Figure 9. Audio interfaces formats: delayed, left and right justified

1 2 n-1 n

MSB LSB 1 2 n-1 n

MSB LSB

1 2 n-1 n

MSB LSB 1 2 n-1 n

MSB LSB

1 AD_CK/DA_CK 1 AD_CK/DA_CK

n-bit word Left data

I2S format (delayed) with default polarity settings, ADHIZ=0

Left justified format with default polarity settings, ADHIZ=0

n-bit word Left data

n-bit word Right data

1 2 n-1 n

MSB LSB 1 2 n-1 n

MSB LSB

1 2 n-1 n

MSB LSB 1 2 n-1 n

MSB LSB

n-bit word Left data

n-bit word Right data

1 2 n-1 n

MSB LSB 1 2 n-1 n

MSB LSB

12n-1 n

MSB LSB 1 2 n-1 n

MSB LSB

n-bit word Left data

Right justified format with default polarity settings

n-bit word Left data

n-bit word Right data

32 AD_CK/DA_CK 32 AD_CK/DA_CK

DA_SYNC/

AD_SYNC

DA_DATA

AD_DATA

DA_CK/

AD_CK

DA_SYNC/

AD_SYNC

DA_DATA

AD_DATA

DA_CK/

AD_CK

DA_SYNC/

AD_SYNC

DA_DATA

AD_DATA

DA_CK/

AD_CK

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Figure 10. Audio interfaces formats: DSP, SPI and PCM

DA_SYNC/

1 2 n-1 n

MSB LSB

AD_SYNC

1 2 n-1 n

MSB LSB

1 2 n-1 n

MSB LSB 1 2 n-1 n

MSB LSB

n-bit word Left data

DSP form at delayed and non-delayed (default AD_CK/DA_CK polarity, ADHIZ=0)

SPI format (slave only) (default AD_CK/DA_CK polarity, ADHIZ=1 - Stereo or Mono)

n-bit word Left data

n-bit word Right data

1 2 n-1 n

MSB LSB 1 2

MSB

n-bit word Left/Mo no dat a n-bit word Right/Mo no data

PCM format (default AD_CK/DA_CK polarity, ADHIZ=1)

3 3

1 2 n-1 n

MSB LSB 1 2

MSB

n-bit word Left/Mono data n-bit word Right/Mono data

3 3

1 2 n-1 n

MSB LSB

n-bit word Mono data

1 2 n-1

MSB LSB

n-bit word Mono data

3High impeda nce

MSB

xHigh impedance x

SYNCP=0

SYNCP=1

{

DA_DATA

AD_DATA

DA_CK/

AD_CK

DA_SYNC/

AD_SYNC

DA_DATA

AD_DATA

DA_CK/

AD_CK

DA_SYNC/

AD_SYNC

SYNCP=0

SYNCP=1

{

DA_DATA

AD_DATA

DA_CK/

AD_CK

Audio interfaces STw5098

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Figure 11. Audio interface timings: master mode

Figure 12. Audio interface timing: slave mode

ADHIZ=0

ADHIZ=1

ADHIZ=0

ADHIZ=1

ADHIZ=0

ADHIZ=1

tDSY

tSDDA tHDDA

tDAD

CKP=0

CKP=1

tDAD tDADZ

DA_SYNC/

AD_SYNC

DA_CK/

AD_CK

DA_DATA

{

tDAD

PCM format only

AD_DATA

All other formats

ADHIZ=0

ADHIZ=1

ADHIZ=0

ADHIZ=1

ADHIZ=0

tDADST

tHCK tLCK

tPCK

tSSY

DA_SYNC/

tSDDA tHDDA

tHSY

AD_SYNC

tDAD

CKP=0

CKP=1

tDADZ

DA_CK/

AD_CK

DA_DATA

{

tDAD

PCM format

AD_DATA

All other formats

ADHIZ=1

STw5098 Audio interfaces

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Table 33. Audio interface signal timings

Symbol Parameter Test conditions Min. Typ. Max. Unit

tDSY

Delay of

AD_SYNC/DA_SYNC

edge from AD_CK/DA_CK

active edge

Master Mode 10 ns

tSDDA Setup time DA_DATA to

DA_CK active edge 10 ns

tHDDA Hold time DA_DATA from

DA_CK active edge 10 ns

tDAD Delay of AD_DATA edge

from AD_CK active edge 30 ns

tDADST

Dela y of the first AD_ DATA

edge from AD_SYNC

active edge

AD_SYNC ac tive edge comes

after AD_CK active edge 30 ns

tDADZ

Delay of AD_DATA high

impedance from

AD_SYNC inactive edge PCM format 10 50 ns

tSSY

Setup time

AD_SYNC/DA_SYNC to

AD_CK/DA_CK active

edge

Slave Mode 20 ns

tHSY

Hold time

AD_SYNC/DA_SYNC from

AD_CK/DA_CK active

edge

Slave Mode 20 ns

tPCK Period of AD_CK/DA_CK Slave Mode 100 ns

tHCK AD_CK/DA_CK pulse

width high Measured from VIH to VIH 40 ns

tLCK AD_CK/DA_CK pulse

width low Measured from VIL to VIL 40 ns

Timing specifications STw5098

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8 Timing specifications

Information included in this section is valid for both entities.

Unless otherwise specified, VCCIO = 1.71V to 2.7V, Tamb = -30°C to 85°C, max capacitive

load 20 pF; typical characteristics are specified at VCCIO = 2.4 V, Tamb = 25 °C; all signals

are referenced to GND, see Note below figure for timing definitions.

Figure 13. A.C. testing input-output waveform

Note: A signal is valid if it is above VIH or below VIL and inv alid if it is between VIL and VIH. For the

purpose of this specification the following conditions apply (see Figure 13 above):

a) All input signal are defined as: VIL =0.2

•

VCCIO, VIH =0.8

•

VCCIO, tR < 10ns, tF < 10ns.

b) Delay times are measured from the inputs signal valid to the output signal valid.

c) Setup times are measured from the data input valid to the clock input invalid.

d) Hold times are measured from the clock signal valid to the data input invalid.

Note: All timing specifications subject to change.

AC Testing: inputs are driven at 0.8

•

VCCIO for a logic ‘1’ and 0.2

•

VCCIO for a logic ‘0’.

Timing measurements are made at 0.7

•

VCCIO for a logic ‘1’ and 0.3

•

VCCIO for a logic ‘ 0’.

TEST POINTS 0.7²VCCIO

0.3²VCCIO

0.7²VCCIO

0.3²VCCIO

0.8²VCCIO

0.2²VCCIO

Input/output

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9 Operative ranges

9.1 Absolute maximum ratings

9.2 Operative supply voltage

Table 34. Absolute maximum ratings

Parameter Value Unit

VCC or VCCIO to GND -0.5 to 3.6 V

VCCA or VCCP to GND -0.5 to 5 V

VCCLS to GND -0.5 to 7 V

Voltage at analog inputs (VCCA ≤ 3.3V) GND-0.5 to VCCA+0.5 V

Maxim u m po w er delivered to the load from LSP/N 500 mW

Peak current at HPR,HPL 100 mA

Current at VCCP, VCCLS, GNDP 350 mA

Current at any digital output 50 mA

Voltage at any digital input (VCCIO ≤ 2.7V); limited at ± 50mA GND-0.5 to VCCIO+0.5 V

Storage temperature range -65 to 150 °C

Operating temperature range(1) -30 to 85 °C

Electrostatic discharge voltage (Vesd) Human body model(2)

Charge device model(3) -2 to +2

-500 to +500 kV

1. in some operating conditions the temperature can be limited to 70 °C. See loudspeaker driver description from

Section 4.10

for details.

2. HBM tests have been perform ed in complian ce with JESD22-A114-B and ESD STM 5.1-2001.HBM

3. CDM tests have been performed in compliance with CDM ANSI-ESDSTM5.3.1-1999

Table 35. Operative supply voltage

Symbol Parameter Condition Min. Max. Unit

VCC Digital supply 1.71 2.7 V

VCCA Analog supply

Note: VCCA ≥ VCC

A24V=0 (bit 1 in CR0)

A24V=1 (bit 1 in CR0) 2.7

2.4 3.3

2.7 V

VCCIO Digital I/O supply D12V=0 (bit 0 in CR0)

D12V=1 (bit 0 in CR0) 1.71

1.2 VCC

1.8 V

VCCP Stereo po w er drivers suppl y VCCA 3.3 V

VCCLS Mono power driver supply VCCA 5.5 V

VGSingle supply voltage range VCC

VCCA

VCCIO

VCCP

VCCLS

A24V=1 (bit 1 in CR0) 2.4 2.7 V

Operative ranges STw5098

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9.3 Power dissipation

Unless otherwise specified, VCCP =V

CCLS =V

CCA = 2.7V to 3.3V, VCCIO =V

CC = 1.71V to

2.7V, Tamb = -30°C to 85°C, all analog outputs not loaded; typical characteristics are

specified at VCCIO =V

CC = 1.8V, VCCP =V

CCLS =V

CCA =2.7V, T

amb =25°C.

9.4 Typical power dissipation by entity

Tamb = 25°C; Analog Supply: VCCP =V

CCLS =V

CCA =2.7V;

digital supply: VCCIO =V

CC =1.8V.

Full scale signal in every path, 20kΩ load at analog outputs.

No master clock

Table 36. Power dissipation

Symbol Parameter Test conditions Min. Typ. Max. Unit

POFF Power Down Dissipation No Master Clock

AMCK=13MHz 0.8

5.8 µW

µW

PAD Stereo ADC power 52.6 mW

PDA Stereo DAC power 46.6 mW

PDAAD Stereo ADC+DAC power 93.8 mW

PAA Stereo Analog Path power 27.6 mW

Table 37. Typical power dissipation, no master clock

N. Function CR0-CR2

setting Other settings Supply Current Power

1 Power Down CR0=0x00

CR1=0x00

CR2=0x00

Analog:

Digital:

Total:

0.02 µA

0.20 µA0.05 µW

0.36 µW

0.41 µW

2Stereo analog path

(Mic-LO)

CR0=0xD0

CR1=0x0C

CR2=0xC0

MICLO=1

MICSEL=2

Analog:

Digital:

Total:

4.3 mA

2.0 µA11.6 mW

0.0 mW

11.6 mW

3Stereo analog path

(Mic-Mixer-LO)

CR0=0xD0;

CR1=0x0C;

CR2=0xC3

MIXMIC=1

MICSEL=2

Analog:

Digital:

Total:

5.4 mA

2.0 µA14.6 mW

0.0 mW

14.6 mW

STw5098 Operative ranges

61/85

Master clock AMCK = 13 MHz

Table 38. Typical power dissipation with master clock AMCK = 13 MHz

N. Function CR0-CR2

setting Other settings Supply Current Power

4 Power Down CR0=0x00

CR1=0x00

CR2=0x00

Analog:

Digital:

Total:

0.02 µA

2.20 µA0.05 µW

3.96 µW

4.01 µW

5Stereo ADC CR0=0xE8

CR1=0xCC

CR2=0x00

MICSEL=1

ADMIC=1

Analog:

Digital:

Total:

7.9 mA

2.8 mA 21.3 mW

5.0 mW

26.3 mW

6Stereo DAC CR0=0xE8

CR1=0x30

CR2=0x33 MIXDAC=1 Analog:

Digital:

Total:

6.1 mA

3.8 mA 16.5 mW

6.8 mW

23.3 mW

7Stereo analog path

(Mic-LO)

CR0=0xE8

CR1=0x0C

CR2=0xC0

MICLO=1

MICSEL=2

Analog:

Digital:

Total:

4.8 mA

0.8 mA 13.0 mW

1.4 mW

13.8 mW

8Stereo ADC

Stereo DAC

CR0=0xE8

CR1=0xFC

CR2=0x33

MICSEL=2

ADMIC=1

MIXDAC=1

Analog:

Digital:

Total:

13.5 mA

5.8 mA 36.5 mW

10.4 mW

46.9 mW

9Stereo ADC

Stereo DAC

Stereo analog path

CR0=0xE8

CR1=0xFF

CR2=0xF3

LINSEL=2; MICSEL=2

ADLIN=1;MIXDAC=1

MICLO=1

Analog:

Digital:

Total:

15.2 mA

5.8 mA 41.0 mW

10.4 mW

51.4 mW

10 Voice TX+RX CR0=0xE8

CR1=0xA8

CR2=0x06

MICSEL=2;

LSMODE=2

ADMIC=1 MIXDAC=1

ADVOICE=1

DAVOICE=1

VCCA,VCCP:

VCCLS:

Digital

Total:

6.8 mA

1.3 mA

2.5 mA

18.4 mW

5.5 mW

4.5 mW

28.4 mW

Electrical characteristics STw5098

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10 Electrical characteristics

Unless otherwise specified, VCCIO = 1.71V to 2.7V, Tamb = -30°C to 85°C; typical

characteristic are specified at VCCIO = 2.0V, Tamb = 25°C; all signals are referenced to GND.

10.1 Digital interfaces

Note: See Figure 13: A.C. testing input-output waveform on page 58.

10.2 AMCK with sinusoid input

Table 39. Digital interfaces specifications

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low voltag e All digital inputs DC

AC 0.3•VCCIO

0.2•VCCIO

VIH Input high volt age All digital inputs, DC

AC 0.7•VCCIO

0.8•VCCIO

VOL Output low voltage All digital outputs IL= 10µA

IL=2µA0.1

0.4 V

VOH Output high voltage All digital outputs IL= 10µA

IL=2µAVCCIO-0.1

VCCIO-0.4 V

IIL Input low cur r ent Any digital input,

GND < VIN < VIL -1 1 µA

IIH Input high curre nt Any digital input,

VIH < VIN < VCCIO -1 1 µA

IOZ

Output current in

high imped anc e

(Tristate) Tristate outputs -1 1 µA

Table 40. AMCK with sinusoid input specifications

Symbol Parameter Test conditions Min. Typ. Max. Unit

CAMCK Minimum External

Capacitance AMCKSIN=1, see CR30 100 pF

VAMCK AMCK sinusoidal voltage

swing AMCKSIN=1, see CR30 0.5 VCCIO VPP

STw5098 Electrical characteristics

63/85

10.3 Analog interfaces

Information below is for each entity.

Table 41. Analog interface specifications

Symbol Parameter Test conditions Min. Typ. Max. Unit

IMIC MIC input leakage GND< VMIC< VCCA -100 +100 µA

RMIC MIC input resistance 30 50 kΩ

RLIN Line in input resi sta nc e 30 kΩ

RLHP Headphones (HP) drivers

load resistance HPL, HPR to GNDP or

VCMHP 14.4 16/32 Ω

RLEAR Earphone (EAR) drivers

load resistance 1 EARP to 1EARN 30 32 Ω

RLLS Loudspe aker (LS) driv e rs

load resistance 2LSP to 2LSN 6.4 8 Ω

CLHP Headphones (HP) drivers

load capac itance HPL, HPR to GNDP or

VCMHP 50

50* pF

CLEAR Earphone (EAR) drivers

load capac itance 1 EARP to 1EARN 50

50* pF

CLLS Loudspe aker (LS) driv e rs

load capac itance 2LSP to 2LSN 50

50* pF

VOFFLS Differential offset voltage

at 2LSP, 2LSN RL=50Ω-50 +50 mV

VOFFEAR Differential offset voltage

at 1EARP, 1EARN RL=50Ω-50 +50 mV

RLOL

Line out (OL) diff./single-

ended driver load

resistance

OLP/ORP to OLN/ORN or

OLP/ORP to GND

(decoupled) 1kΩ

* with series resistor

Electrical characteristics STw5098

64/85

10.4 Headset plug-in and push-button detector

Information below is for each entity.

10.5 Microphone bias

Information below is for each entity.

10.6 Power supply rejection ratio

Table 42. Headset plug-in and push-button detector specifications

Symbol Parameter Test conditions Min. Typ. Max. Unit

HDVL Plug-in detected Voltage at HDET VCCA-1 V

HDVH Plug-in undetected Voltage at HDET VCCA-0.5 V

HDHPlug-in detector hysteresis 100 mV

PBVL Push-button pressed Voltage at HDET 0.5 V

PBVH Push-button released Voltage at HDET 1 V

PBDPush-button de-bounce

time 15 50 ms

Table 43. Microphone bias specifications

Symbol Parameter Test conditions Min. Typ. Max. Unit

VMBIAS MBIAS output

voltage 1.95 2.1 2.25 V

IMBIAS MBIAS output

current From MBIAS to ground 1.1 mA

RMBIAS MBIAS output load 3.5 kΩ

CMBIAS MBIAS output

capacitance 150 pF

PSRMB4

PSRMB20

MBIAS power

supply rejection f<4kHz

f<20kHz 60

50 dB

Table 44. Power supply rejection ratio specifications

Symbol Parameter Test conditions Min. Typ. Max. Unit

PSRL20

PSRL200 PSRR VCCLS

Each output (LSP, LSN)

f<20kHz

f<200kHz 65

47 dB

PSRPH

PSRPOS

PSRPOD

PSRR VCCP

Headphones f<20kHz

Line out single ended f<20kHz

Line out differential f<20kHz

PSRAM

PSRAL PSRR VCCA Mic input f<20kHz

Line In f<20kH z 50

50 dB

STw5098 Electrical characteristics

65/85

10.7 LS and EAR gain limiter

Information below is for each entity.

Table 45. LS and EAR gain limiter

Symbol Parameter Test conditions Min. Typ. Max. Unit

VLSLIMH High voltage at VCCLS

(VLSH=1) VCCLS rais ing 4.2 V

VLSLIML Low voltage at VCCLS

(VLSH=0) VCCLS fallin g 4.0 V

VLSLIMD VCCLS Hysteresis 200 mV

Note: See CR32 for VLSH definition. See Loudspeaker driver description in

Section 4.10

for details.

Analog input/output operative ranges STw5098

66/85

11 Analog input/output operative ranges

Information included in this section applies to both entities.

11.1 Analog levels

11.2 Microphone input levels

Analog supply range: 2.7 V < VCCA <3.3V

Table 46. Reference full scale analog levels

Symbol Parameter Test conditions Min. Typ. Max. Unit

0dBFS level 2.7V < VCCA < 3.3V 12

4dBVpp

Vpp

0dBFS level low voltage

mode 2.4V < VCCA < 2.7V 10

3.18 dBVpp

Vpp

Table 47. Microphone input levels, absolute levels at pins connected to preamplifiers

Symbol Parameter Test conditions Min. Typ. Max. Unit

Overload level, single

ended MIC gain = 0 to 6dB 707

-6

mVRMS

Vpp

dBFS

Overload level, single

ended, versus MIC gain MIC gain > 6dB − (MIC_Gain) dBFS

Overload level, differential MIC gain = 0dB 1.41

mVRMS

Vpp

dBFS

Overload level, differential,

versus MIC gain MIC gain > 0dB − (MIC_Gain) dBFS

Note: When 2.4 V < VCCA < 2.7 V, voltage values are reduced by 2dB.

Table 48. Microphone input levels, absolute levels at pins connected to the line-in amplifiers

Symbol Parameter Test conditions Min. Typ. Max. Unit

Overload level, single

ended

Line in

gain from −20dB to 6dB 707

-6

mVRMS

Vpp

dBFS

Overload level (single

ended) versus line in gain

Line in

gain > 6dB − (Line_In_Gain) dBFS

Overload level (differential)

Line in

gain from −20dB to 0dB 1.41

mVRMS

Vpp

dBFS

STw5098 Analog input/output operative ranges

67/85

11.3 Line output levels

Analog supply range: 2.7 V < VCCA <3.3V

11.4 Power output levels HP

Analog supply range: 2.7 V < VCCA <3.3V

11.5 Power output levels LS and EAR

Analog supply range: 2.7 V < VCCA <3.3V

Overload level (differential)

versus line in gain

Line in

gain > 0dB − (Line_In_Gain) dBFS

Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB

Table 48. Microphone input levels, absolute levels at pins connected to the line-in amplifiers

Symbol Parameter Test conditions Min. Typ. Max. Unit

Table 49. Absolute levels at OLP/OLN, ORP/ORN

Symbol Parameter Test conditions Min. Typ. Max. Unit

Output level, single ended 0 dB gain

Full scale digital input

707

-6

mVRMS

Vpp

dBFS

Output level, differential 0 dB gain

Full scale digital input

1.41

mVRMS

Vpp

dBFS

Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB

Table 50. Absolute levels at HPL - HPR

Symbol Parameter Test conditions Min. Typ. Max. Unit

Output level -6dB gain

Full scale digital input

707

-6

mVRMS

Vpp

dBFS

Max output power(1) 16 Ω load

VCCP > 3.2 V 40 mW

1. In some operating conditions the maximum output power can be limited. See “

Section 9.1: Absolute maximum ratings

” and

“loudspeaker driver” description from

Section 4.10: Analog output drivers

for details.

Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB

Analog input/output operative ranges STw5098

68/85

Table 51. Absolute levels at 1EARP-1EARN and 2LSP - 2LSN

Symbol Parameter Test conditions Min. Typ. Max. Unit

Output level 0dB gain

Full scale digital input

1.41

VRMS

Vpp

dBFS

Max EAR output power 32 Ω load

VCCLS > 4V 125 mW

Max LS output power(1) 8Ω load

VCCLS > 4V 500 mW

1. In some operating conditions the maximum output power can be limited. See “

Section 9.1: Absolute maximum ratings

” and

“loudspeaker driver” description from

Section 4.10: Analog output drivers

for details.

Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB

STw5098 Stereo audio ADC specifications

69/85

12 Stereo audio ADC specifications

Information included in this section applies to both entities. Typical measures at

VCCA=VCCP=VCCLS=2.7V; VCCIO=VCC=1.8 V; Tamb=25°C;13 MHz AMCK

Table 52. Stereo audio ADC specifications

Symbol Parameter Test conditions Min. Typ. Max. Unit

ADN Resolution 20 Bits

ADDRM

ADDRLI Dynamic range

20Hz to 20 kHz , A-weig hte d

Meas ured at -60dBFS

MIC input, 21dB gain

Line-In, 0dB gai n 87

89 91

93 dB

ADSNA

ADSN Signal to noise ratio Max level at MIC input, 21dB gain

A-weighted

Unweighted (20 Hz to 20 kHz) 90

86 dB

Input ref e rred ADC

noise

A-weighted Mic input 0dB gai n

Mic input 21dB gain

Mic input 39dB gain

Line in input 0dB gain

Line in input 18dB gai n

3.3

1.9

7.5

µV

ADTHD Total harmonic

distortion Max level at MIC input, 21dB gain 0.001 0.003 %

Deviation from

linear phase

Measurement bandwidth 20Hz to

20kHz, Fs= 48kHz. Combined digital

and analog filter characteristic s 1Deg

ADfPB Passband Combined digital and analog filter

characteristics AD96K=0 00.45FskHz

Passband ripple Combined digital and analog filter

characteristics AD96K=0 0.2 dB

ADfSB Stopband Combined digital and analog filter

characteristics AD96K=0 0.55Fs kHz

Stopband

Attenuation

Measurement bandwidth up to

3.45Fs. Combined digital and analog

filter characteristics, AD96K=0 60 dB

ADtgd Group delay Audio filters, 96kHz FS

Audio filters, 48kHz FS

Audio filters, 8kHz FS

0.11

0.4

2.6

Interchannel

isolation 90 dB

Interchannel gain

mismatch 0.2 dB

Gain error 0.5 dB

Note: When 2.4 V < VCCA < 2.7 V, the values are reduced by 2dB

Stereo audio DAC specifications STw5098

70/85

13 Stereo audio DAC specifications

Information included in this section applies to both entities.

Typical measures at VCCA=VCCP=VCCLS=2 .7V; VCCIO=VCC=1.8V; Tamb=25°C;13MHz

AMCK

Table 53. Stereo audio DAC specifications

Symbol Parameter Test conditions Min. Typ. Max. Unit

DAN Resolution 20 Bits

DADR Dynamic range

20Hz to 20 kHz , A-weig hte d.

Meas ured at -60dBFS

Differenti al line out

Single- end ed lin e out

HPL/HPR to GND or VCMHP

LSP-LSN

90 95

DASNA

DASN Signal to noise ratio

2Vpp outp ut

HPL, HPR gain set to -6dB, 16Ω load

A-weighted

Unweighted (20 Hz to 20 kHz) 94

90 dB

DATHDL Total harmonic

distortion

Worst case load

2Vpp output

HPL, HPR gain set to -6dB, 16Ω load 0.02 0.04 %

DATHD Total harmonic

distortion 2Vpp output,

HPL, HPR gain set to -6dB, 1kΩ lo ad 0.004 %

Deviation from

linear phase

Measurement bandwidth 20Hz to

20kH z, Fs= 48kHz.

Combined digital and analog filter

characteristics

1Deg

DAfPB Passband Combined digital and analog filter

character istics, DA96K= 0 00.45FskHz

Passband ripple Combined digital and analog filter

character istics, DA96K= 0 0.2 dB

DAfSB Stopband Combined digital and analog filter

character istics, DA96K= 0 0.55Fs kHz

Stopband

attenuation

Measurement bandwidth up to

3.45Fs.

Combined digital and analog filter

character istics, DA96K= 0

50 dB

TSF Transient

suppression filter

cut-off frequency 15 23 Hz

Out of band noise Measur ement bandwid th 20 kHz to

100 kHz. Zero input signal -85 dBr

STw5098 AD to DA mixing (sidetone) specifications

71/85

14 AD to DA mixing (sidetone) specifications

Information included in this section applies to both entities.

Typical measures at VCCA=VCCP=VCCLS=2 .7V; VCCIO=VCC=1.8V; Tamb=25°C;13MHz

AMCK.

DAtgd Group delay Audio filters, 96kHz FS

Audio filters, 48kHz FS

Audio filters, 8kHz FS

0.09

0.4

2.6

Interchannel

isolation 2Vpp output HPR, HPL unloaded

HPR, HPL with 16Ω to VCMHP 100

60 dB

Interchannel gain

mismatch 0.2 dB

Gain error 0.5 dB

SUT Startup time from

power up FS=48 kHz Line out

HPL/R out 1

10 ms

Note: When 2.4 V < VCCA < 2.7 V, values are reduced by 2 dB

Table 53. Stereo audio DAC specifications (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Table 54. AD to DA mixing (sidetone) specifications

Symbol Parameter Test conditions Min. Typ. Max. Unit

STDEL AD to DA mixing

(sidetone) delay Valid for audio and voice filters 5 10 µs

Stereo analog-only path specifications STw5098

72/85

15 Stereo analog-only path specifications

Information included in this section applies to both entities.

Measured at differential line-out, ENOSC=1, No master clock.

Typical measures at VCCA=VCCP=VCCLS=2 .7V; VCCIO=VCC=1.8V; Tamb=25°C

Table 55. Stereo analog-only path specifications

Symbol Parameter Test conditions Min. Typ. Max. Unit

AADRM

AADRLI Dynamic range

20Hz to 20 kHz , A-weig hte d.

Meas ured at -60dBFS

MIC input, 21dB gain

Line-In, 0dB gai n 90

90 95

97 dB

AASNA

AASN Signal to noise ratio Max level at line-in input, 0dB gain,

A-weighted

Unweighted (20 Hz to 20 kHz) 97

94 dB

AATHD Total harmonic

distortion

1kHz @ 0dBFS MIC input, 21dB gain

Line-in input, 0dB gai n 0.003

0.004 0.01

0.02 %

Note: When 2.4V<VCCA<2.7V, the values are reduced by 2dB.

STw5098 ADC (TX) & DAC (RX) specifications with voice filters selected

73/85

16 ADC (TX) & DAC (RX) specifications with voice filters

selected

Information included in this section applies to both entities.

Typical measures at VCCA=VCCP=VCCLS=2 .7V; VCCIO=VCC=1.8V; Tamb=25°C;13MHz

AMCK

Table 56. ADC (TX) & DAC (RX) specifications with voice filters selected

Symbol Parameter Test conditions Min. Typ. Max. Unit

TXDR

RXDR Dynamic range 300Hz to 3.4kHz; 1kHz @ -60dBFS

TX Path, MIC input, 21dB gain

RX Path, LS Output, 0dB gain 86

83 89

86 dB

TXSN

RXSN Signal to noise ratio 300Hz to 3.4kHz; 1kHz @ 0dBFS

TX Path, MIC input, 21dB gain

RX Path, LS and EAR outputs, 0dB gain 88

86 dB

THD THD 1kHz @ 0dBFS

TX Path, MIC input, 21dB gain

RX Path, LS and EAR outputs, 0dB gain <0.001

0.005 %

TXG TX gain mask

f=60Hz

f=100Hz

f=200Hz

f=300Hz

f=400Hz-3000Hz

f=3400Hz

f=4000H

f=4600Hzz

f=8000Hz

-1.5

-0.5

-1.5

-30

-24

-6

0.5

0.0

-14

-35

-47

RXG RX gain mask

f=60Hz

f=100Hz

f=200Hz

f=300Hz

f=400Hz-3000Hz

f=3400Hz

f=4000Hz

f=5000Hz

-1.5

-0.5

-1.5

-20

-12

-2

0.5

0.0

-14

-50

RX out of band

noise Measurement bandwidth 4kHz to

100kHz. Zero input signal -85 dBr

Group delay TX path

RX path 0.32

0.28 ms

Note: When 2.4V<VCCA<2.7V, the values are reduced by 2dB

Typical performance plots STw5098

74/85

17 Typical performance plots

Figure 14. Bass treble control, de-emphasis

filter

Figure 15. Dynamic compressor transfer

function

Figure 16. ADC audio path measured filter

response

Figure 17. ADC in band audio path measured

filter response

Figure 18. DAC digital audio filter

characteristics

Figure 19. DAC in band digital audio filter

characteristics

Bass and treble gains are independently selectable in any combination.

The de-emphasis filter (thick line, alternative to treble control)

compensates for pre-emphasis used on some audio CDs.

Gain error < 0.1dB. Filter characteristics at Fs=44.1kHz are plotted

-15

-10

-5

100 1k 10k

Gain @ Fs=44.1 kHz [dB]

Frequency [Hz]

Audio signal transfer function when the Dynamic Compressor is active.

-1

-0.75

-0.5

-0.25

0.25

0.5

0.75

-1 -0.75-0.5-0.25 0 0.25 0.5 0.75 1

Output Amplit u de [FS]

Input Amplitude [FS]

48 kHz sample rate.

Full ADC path Frequency response up to 100 kHz.

-80

-70

-60

-50

-40

-30

-20

-10

100 1k 10k 100k

Gain [dB]

Frequency [Hz]

48 kHz Sample Rate.

In band Frequency response

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0 5k 10k 15k 20k

Gain [dB]

Frequency [Hz]

DA96K=0; 48 kHz Sample Rate

Frequency response up to 166kHz (3.45 Fs @ 48kHz sampling rate)

-80

-60

-40

-20

100 1k 10k 100k

Gain [dB]

Frequency [Hz]

48 kHz Sample Rate

In band Frequency response

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0 5k 10k 15k 20k

Gain [dB]

Fr equency [Hz]

STw5098 Typical performance plots

75/85

Figure 20. ADC 96 kHz audio path measured

filter response

Figure 21. ADC 96 kHz audio in-band

measured filter response

Figure 22. ADC voice TX path measured filter

response

Figure 23. ADC voice TX path measured in-

band filter response

Figure 24. DAC voice (RX) digital filter

characteristics

Figure 25. DAC voice (RX) in-band digital filter

characteristics

The plot is extended down to 5 Hz to show the high pass filter

implemented in the ADC 96 kHz sample rate,

96 kHz audio filter selected signal from Mic input

-80

-70

-60

-50

-40

-30

-20

-10

10 100 1k 10k 100k

Gain [dB]

Frequency [Hz]

96 kHz sample rate,

96 kHz audio filter selected signal from Mic input.

-5

-4

-3

-2

-1

0 5k 10k 15k 20k 25k 30k 35k 40k 45k

Gain [dB]

Frequency [Hz]

8 kHz Sample rate, tx voice filter selected.

Signal from Mic input

-70

-60

-50

-40

-30

-20

-10

100 1k 10k

Gain [dB]

Frequency [Hz]

8 kHz sample rate, tx voice filter selected signal from Mic input.

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

500 1k 1500 2k 2500 3k 3500 4k

Gain [dB]

Frequency [Hz]

8 kHz sample rate, rx voice filter

-70

-60

-50

-40

-30

-20

-10

100 1k 10k

Gain [dB]

Frequency [Hz]

8 kHz sample rate, rx voice filter

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

500 1k 1500 2k 2500 3k 3500 4k

Gain [dB]

Fr equency [Hz]

Typical performance plots STw5098

76/85

Figure 26. ADC path FFT Figure 27. ADC S/N versus input-level

Figure 28. DAC path FFT Figure 29. DAC S/N versus input-level

Figure 30. Analog path FFT Figure 31. Analog path S/N versus input-level

-120

-100

-80

-60

-40

-20

0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k

Amplitu de [dBF S ]

Fr equency [Hz]

12 MHz master clock.

Differential input at Mic preamplifier, 21 dB gain.

48 kHz sampling rate.

Both channels active

100

-60 -50 -40 -30 -20 -10 0

S/N [dB]

Input Level [dBFS]

12 MHz master clock

Differential input at Line-In Amplifier, 0 dB gain.

48 kHz Sampling Rate

A-Weighted, Both channels active

12 MHz master clock.

48 kHz sampling rate

Differential output at line-out, 1kΩ load.

Both channels active

-120

-100

-80

-60

-40

-20

0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k

Amplitude [dBFS]

Frequency [Hz] 20

100

-60 -50 -40 -30 -20 -10 0

S/N [dB]

Input Level [dBFS]

12 MHz master clock.

48 kHz Sampling Rate

Differential output at Line-Out, 1kΩ load.

A-Weighted, Both channels active

-120

-100

-80

-60

-40

-20

0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k

Amplitude [dBFS]

Frequency [Hz]

Differential input at Mic Preamplifier, 2 1 dB gain.

Direct Mic to Line-Out connection (MICLO=1)

Differential output at Line-Out, 20kΩ load. Both channels active

100

-60 -50 -40 -30 -20 -10 0

S/N [dB]

Input Level [dBFS]

Differential input at Line-In Amplifier, 0 dB gain.

Line-In to DA-Mixer to Line-Out connection.

Differential output at Line-Out, 20kΩ load. A-weighted, both channels

active

STw5098 Package mechanical data

77/85

18 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST tradem ark.

ECOPACK specifications are available at: www.st.com.

Package mechanical data STw5098

78/85

18.1 LFBGA 6x6x1.4

Note: 1 LFBGA stands for Low Profile Fine Pitch Ball Grid Array.

- Low profile: the total profile height (DIm A) is measured from the seating plane to the top of

the component. The maximum total package height is calculated as follows:

. Fine pitch: e<1.0 mm pitch

2 The typical ball diameter before mounting is 0.30 mm

3 The tolerance of position that controls the location of the pattern of balls with respect to

datum A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to

datum C and located on true position with respect to datum A and B as defined by e. The

axis perpendicular to datum C of each ball must lie within this tolerance zone.

4 The tolerance of position that controls the location of the balls within the matrix with respect

to each other. F or each ball there is a cylindrical tolerance zone fff perpendicular to datum C

and located on true position as defined by e. The axis perpendicular to datum C of each ball

must lie within this tolerance zone. Each tolerance zone in the array is contained entirely

in the respective zone eee above.

The axis of each ball must lie simultaneously in both tolerance zones.

5 The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink

or metallized markings, or other feature of package body or integral heatslug. A

distinguishing feature is allowable on the bottom surface of the package to identify the

terminal A1 corner. Exact shape of each corner is optional.

Table 57. Dimensions of LFBGA 6x6x1.4 112 4R11x11. 0.5

Reference

Databook (mm) Drawing (mm)

Notes

Min. Typ. Max. Min. Typ. Max.

A 1.40 1.26

Note 1

A1 0.15 0.16 0.21 0.26

A2 0.985 0.93 0.985 1.04

A3 0.20 0.16 0.20 0.24

A4 0.80 0.77 0.785 0.80

b 0.25 0.30 0.35 0.25 0.30 0.35

Note 2

D 5.85 6.00 6.15 5.90 6.00 6.10

D1 5.00 5.00

E 5.85 6.00 6.15 5.90 6.00 6.10

E1 5.00 5.00

e0.50 0.50

F0.50 0.50

ddd 0.08 0.08

eee 0.15 0.15

Note 4

fff 0.05 0.05

Note 5

A2Typ A1Typ A(12A32A42

+ + tolerancevalues)++

STw5098 Package mechanical data

79/85

Figure 32. LFBGA 6x6x1.4 112 4R11x11 0.5 drawing

12345678

A1 C ORNER INDEX AREA

(SEE NOTE 3) Øb (112 BALLS) BOTTOM VIE W

91011

PLANE

SEATING

ddd C

Package mechanical data STw5098

80/85

18.2 VFBGA 5x5x1.0

Note: 1 VFBGA stands for Very thin Profile Fine Pitch Ball Grid Array.

The maximum total package height is calculated by the following methodology:

Very thin profile: Max/Fine pitch: e<1.0 mm

2 The typical ball diameter before mounting is 0.25 mm

3 VFBGA with 0.40mm ball pitch is not yet registered into JEDEC publications.

4 The tolerance of position that controls the location of the pattern of balls with respect to

datum A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to

datum C and located on true position with respect to datum A and B as defined by e. The

axis perpendicular to datum C of each ball must lie within this tolerance zone.

5 The tolerance of position that controls the location of the balls within the matrix with respect

to each other. F or each ball there is a cylindrical tolerance zone fff perpendicular to datum C

and located on true position as defined by e. The axis perpendicular to datum C of each ball

must lie within this tolerance zone. Each tolerance zone in the array is contained entirely

in the respective zone eee above.

The axis of each ball must lie simultaneously in both tolerance zones.

6 The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink

or metallized markings, or other feature of package body or integral heatslug. A

distinguishing feature is allowable on the bottom surface of the package to identify the

terminal A1 corner. Exact shape of each corner is optional.

Table 58. Dimensions of VFBGA 5x5x1.0 112 balls 0.4 mm pitch

Reference

Databook (mm) Drawing (mm)

Notes

Min. Typ. Max. Min. Typ. Max.

A 1.00 0.99

Note 1

A1 0.125 0.125 0.165 0.205

A2 0.765 0.71 0.765 0.82

A3 0.18 0.14 0.18 0.22

A4 0.60 0.57 0.585 0.60

b 0.22 0.26 0.30 0.22 0.26 0.30

Note 2

D 4.95 5.00 5.05 4.95 5.00 5.05

D1 4.00 4.00

E 4.95 5.00 5.05 4.95 5.00 5.05

E1 4.00 4.00

e0.40 0.40

Note 3

F0.50 0.50

ddd 0.08 0.08

eee 0.13 0.13

Note 4

fff 0.04 0.04

Note 5

A2Typ A1Typ A(12A32A42

+ + tolerancevalues)++ 0.80mm A 1.00mm≤<

STw5098 Package mechanical data

81/85

Figure 33. VFBGA 5x5x1.0 112 0.4 drawing

Application schematics STw5098

82/85

19 Application schematics

See

Figure 34: STw5098 application schematics

STw5098 Application schematics

83/85

Figure 34. STw5098 application schematics

1 uF / 0402

Microphone

Jack audio

LOUDSPEAKER 1

LOUDSPEAKER 2

Mono speaker

220 nF / 0406

1 uF / 0402

220 nF / 0406

2.2uF/0603

220 nF / 0406

22uF / 0805

1 uF / 0402

220ohm

R815

C801

1nF

C811 680nF

AUDIO_2V8

2.7kohm

R808

R812

22kohm

1uF

C839

100nF

100nF C804

C803

100nF C805

C806100nF

100nF

C826

VBAT

680nF

C820

R816

220ohm

AUDIO_1V8

1nF

C840

22kohm

R809

C842

22pF

C846

1nF

HP802

J800

JACK_CUI

ST000000144

C821 680nF

1.2kohm

R807

C813

2.2nF

100nF C831

C830100nF

10uF

C833

10kohm

R800

100nF

C832

100nF

C808

HP801

AUDIO_2V8

TP806

C827

33uF

100nF C829

680nF

C809

AUDIO_2V8

22pF

C845

C814100nF

C844

22pF

100nF

C835

C837

1uF

C818

100nF

100nF C802

C834100nF

100nF C810

VBAT

R814

22kohm

100nF C836C812100nF

100nF C824

C823100nF

AUDIO_1V8

C828100nF

22pF

C841

22pF

C843

100nF C822

100nF

C825

HP800

C139

100nF

AUDIO_1V8

TP809

33uF

C807

R810

1.2kohm

R811

2.7kohm

470nF

C815

VCC1

VCC2

VOUT1M

VOUT1P B4

VOUT2M

VOUT2P D4

C816

100nF

MN801

TS4984

ST000000133

BYPASS1

C1 BYPASS2 C5

GND1

D2 E1

GND2

IN1M

IN1P

IN2M

E5 IN2P

STDBY

22kohm

R813

AUDIO_1V8

C800100nF

10kohm

R802

GNDP4

VCC1

D4 VCC2

VCCA1

C1 VCCA2

D9 VCCA3

VCCIO

VCCLS1 I8

VCCLS2

VCCLS3

VCCP1

VCCP2 J2

VCCP3

VCCP4 K10

I9 2ORP

B2 2SCLK

A4 2SDA_SDIN

2VCMHP

J4 2VCMHPS

B7 AMCK

GND1 B11

GND2

GNDA1 F3

GNDA2

GNDCM1

J1 GNDCM2

J6 GNDP1

GNDP2

GNDP3

J11

2HPL

2HPR

K11

2IRQ

2LINEINL

2LINEINR H10

2LSN

K9 2LSNS

K6 2LSP

K5 2LSPS

C10

2MBIAS

2MICLN

2MICLP

E11

2MICRN

F11

2MICRP

2OLN

H3 2OLP

2ORN

2AUX1R

2AUX2LN

2AUX2LP

G11

2AUX2RN

H11

2AUX2RP

2AUX3L E10

2AUX3R

2CAPLINEIN

K7 2CAPLS

2CAPMIC

C4 2CMOD

2DA_CK B10

2DA_DATA

2DA_OCK B9

2DA_SYNC

2HDET

1MICRN

F9 1MICRP

1OLN I1

1OLP

1ORN I10

J10

1ORP

A2 1SCLK

C5 1SDA_SDIN

1VCMHP I5

1VCMHPS

C6 2AD_CK

A8 2AD_DATA

2AD_OCK

A9 2AD_SYNC

A7 2AS_CSB

2AUX1L D11

1DA_DATA

1DA_OCK A10

1DA_SYNC

1HDET

1HPL J3

1HPR

1IRQ

1LINEINL

I11 1LINEINR

1LSN I7

1LSNS J8

1LSP H5

1LSPS

C11 1MBIAS

D3 1MICLN

E3 1MICLP

1AD_OCK

C8 1AD_SYNC

D7 1AS_CSB

D2 1AUX1L

D10 1AUX1R

1AUX2LN

G1 1AUX2LP

1AUX2RN

G10

G9 1AUX2RP

E2 1AUX3L

1AUX3R

F10

1CAPLINEIN

1CAPLS

F2 1CAPMIC

B4 1CMOD

1DA_CK A11

ST000000131

STW5098

MN800

A6 1AD_CK

C7 1AD_DATA

100nF

C838

100nF C817

C819100nF

M800

D801

TRANSIL

ST000000145

GND1 GND2

I_O1

I_O2

I_O3

I_O5 6

AUDIO_EARKIT_RIGHT_SPEAKER

AUDIO_EARKIT_LEFT_SPEAKER

AUDIO_JACK_DETECT

AUDIO_HANDSET_MIC_N

AUDIO_HANDSET_MIC_P

AUDIO_PWR_AMPLIFIER_STANDBY

AUDIO_TO_TVOUT_R

AUDIO_TO_TVOUT_L

AUDIO_FM_ANTENNA

AUDIO_FROM_MODEM_N

AUDIO_FROM_MODEM_P AUDIO_FM_RIGHT

AUDIO_FM_LEFT

AUDIO_TO_MODEM_N

AUDIO_TO_MODEM_P

AUDIO_IRQ

AUDIO_APP_I2S_DA_DATA

AUDIO_FROM_BT_PCM_DATA

AUDIO_PWR_AMPLIFIER_STANDBY

AUDIO_TO_BT_PCM_DATA

AUDIO_FM_LEFT

AUDIO_FM_RIGHT

AUDIO_TO_MODEM_P

AUDIO_TO_MODEM_N

AUDIO_EARKIT_COMMON_VOLTAGE_SPEAKER

AUDIO_APP_I2S_AD_DATA

AUDIO_APP_I2S_AD_DA_SYNC

AUDIO_APP_I2S_AD_DA_CLK

AUDIO_FM_ANTENNA

AUDIO_BT_PCM_FS

AUDIO_IRQ

AUDIO_PCM_CLK

AUDIO_TO_TVOUT_L

AUDIO_TO_BT_PCM_DATA

AUDIO_PCM_CLK

AUDIO_1V8

AUDIO_APP_I2S_AD_DA_SYNC

AUDIO_APP_I2S_AD_DA_CLK

AUDIO_I2C_SCLK

AUDIO_I2C_SDA

AUDIO_CLK

AUDIO_FROM_MODEM_P

AUDIO_FROM_MODEM_N

VBAT

AUDIO_FROM_BT_PCM_DATA

AUDIO_BT_PCM_FS

AUDIO_APP_I2S_AD_DATA AUDIO_APP_I2S_DA_DATA

AUDIO_TO_TVOUT_R

AUDIO_I2C_SCLK

AUDIO_I2C_SDA

AUDIO_CLK

AUDIO_2V8

Ordering information STw5098

84/85

20 Ordering information

21 Revision history

Table 59. Order codes

Part Number Package Packing

STw5098 LFBGA 6x6x1.4, 0.5 mm pitch, 112 pins Tray

STw5098T LFBGA 6x6x1.4, 0.5 mm pitch, 112 pins Tape and reel

STw5098BBLR/LF VFBGA 5x5x1.0, 0.4 mm pitch, 112 pins Tray

STw5098BBLT/LF VFBGA 5x5x1.0, 0.4 mm pitch, 112 pins Tape and reel

Table 60. Document revision history

Date Revision Changes

24-Apr-2007 1Initial release.

STw5098

85/85

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