SRDA05-4 and SRDA12-4
Final Datasheet Rev 7.1
11/20/2018
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Semtech
Proprietary & Condential
SRDA05-4 and SRDA12-4
PROTECTION PRODUCTS
Features
• Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 20-25A (8/20μs)
• Array of surge rated diodes with internal TVS diode
• Protects four I/O lines
• Low capacitance (<15pF)
• Low operating voltage: 5V or 12V
• Low clamping voltage
• Solid-state technology
Mechanical Characteristics
• JEDEC SOIC-8 Package
• Pb-Free, Halogen Free, RoHS/WEEE Compliant
• Lead Finish: Matte Sn
• Marking : Marking Code
• Packaging : Tape and Reel
Applications
• T1/E1 secondary IC Side Protection
• T3/E3 secondary IC Side Protection
• Analog Video Protection
• Microcontroller Input Protection
• Base stations
• I2C Bus Protection
Circuit Diagram Schematic and Pin Conguration
RailClamp®
Low Capacitance TVS Array
SO-8 (Top View)
Description
RailClamp® TVS arrays are low capacitance ESD
protection devices designed to protect sensitive
components from overvoltage caused by electrostatic
discharge (ESD), electrical fast transients (EFT), and
lightning surge. It oers desirable characteristics for
board level protection including fast response time,
low operating and clamping voltage, and no device
degradation.
The unique design incorporates surge rated, low
capacitance steering diodes and a TVS diode in a single
package. During transient conditions, the steering
diodes direct the transient current to ground via the
internal low voltage TVS. The TVS clamps the transient
voltage to a safe level. The low capacitance array
conguration allows the user to protect up to four
data lines. The SRDA05-4 may be used to protect lines
operating up to 5 volts while the SRDA12-4 may be used
on lines operating up to 12 volts.
These devices are in an 8-pin SOIC package. It measures
3.9 x 4.9mm. The high surge capability means it can be
used in high threat environments in applications such as
CO/CPE equipment, telecommunication lines, and video
lines.
I/O 1
5, 8
2, 3
I/O 2 I/O 3 I/O 4
1
2
3
4
8
7
6
5
I/O 1
I/O 2
I/O 3
I/O 4
NC
NC
GND
GND
SRDA05-4 and SRDA12-4
Final Datasheet Rev 7.1
11/20/2018
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Proprietary & Condential
Absolute Maximum Ratings
Electrical Characteristics (T=25OC unless otherwise specied)
Rating Symbol Value Units
Peak Pulse Power (tp = 8/20µs) PPK 500 W
Peak Forward Voltage (IF = 1A, tp = 8/20µs) VPP 1.5 V
Lead Soldering Temperature TL260 (10 sec.) OC
Operating Temperature TOP -40 to +85 OC
Storage Temperature TSTG -55 to +150 OC
SRDA05-4
Parameter Symbol Conditions Min. Typ. Max. Units
Reverse Stand-O Voltage VRWM 5 V
Reverse Breakdown Voltage VBR It = 1 mA 6 V
Reverse Leakage Current IRVRWM = 5V 10 µA
Clamping Voltage VCtp = 8/20µs
IPP = 1A 9.8
VIPP = 10A 12
IPP = 25A 20
Peak Pulse Current IPP tp = 8/20µs 25 A
Junction Capacitance CJVR = 0V, f = 1MHz
I/O to GND 8 15
pF
I/O to I/O 4
SRDA12-4
Parameter Symbol Conditions Min. Typ. Max. Units
Reverse Stand-O Voltage VRWM 12 V
Reverse Breakdown Voltage VBR It = 1 mA 13.3 V
Reverse Leakage Current IRVRWM = 12V 1 µA
Clamping Voltage VCtp = 8/20µs
IPP = 1A 17
VIPP = 10A 20
IPP = 20A 25
Peak Pulse Current IPP tp = 8/20µs 20 A
Junction Capacitance CJVR = 0V, f = 1MHz
I/O to GND 8 15
pF
I/O to I/O 4
SRDA05-4 and SRDA12-4
Final Datasheet Rev 7.1
11/20/2018
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Proprietary & Condential
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve
Pulse Waveform
Variation of Capacitance vs. Reverse Voltage
0
10
20
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30
Percent of IPP
Time (µs)
e-t
td = IPP/2
Waveform
Parameters:
tr = 8µs
td = 20µs
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0246810 12 14
C
J
(V
R
) / C
J
(V
R
= 0)
Reversed Voltage -VR(V)
f = 1 MHz
SRDA05-4 SRDA12-4
0
5
10
15
20
25
0 5 10 15 20 25 30
Clamping Voltage - V
C
(V)
Peak Pulse Current - IPP (A)
TA= 25OC
Waveform: tp= 8x20µs
SRDA05-4
SRDA12-4
0
0.5
1
1.5
2
2.5
3
3.5
4
0 5 10 15 20 25 30
Forward Voltage - V
C
(V)
Peak Pulse Current - IPP (A)
TA= 25OC
Waveform: tp= 8x20µs
SRDA12-4 or SRDA05-4
0.01
0.1
1
10
0.1 1 10 100 1000
Peak Pulse Power - P
PP
(kW)
Pulse Duration - tp (µs)
TA = 25OC
0
20
40
60
80
100
120
0 25 50 75 100 125 150
% of Rated Power or I
PP
Ambient Temperature - TA (
O
C)
DR040514-25-125-150
Clamping Voltage vs. Peak Pulse Current
Forward Voltage vs. Forward Current
SRDA05-4 and SRDA12-4
Final Datasheet Rev 7.1
11/20/2018
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Proprietary & Condential
Application Information
Device Connection Options for Protection of Four
High-Speed Lines
The SRDA TVS is designed to protect four data lines
from transient over voltages by clamping them to a
xed reference. When the voltage on the protected
line exceeds the reference voltage (plus VF) the steering
diodes are forward biased, conducting the transient
current away from the sensitive circuitry. Data lines are
connected at Pins 1, 4, 6 and 7. The negative reference
is connected at Pins 5 and 8. These pins should be
connected directly to a ground plane on the board for
best results. The path length is kept as short as possible
to minimize parasitic inductance.
The positive reference is connected at pins 2 and 3. The
options for connecting the positive reference are as
follows:
1. To protect data lines and the power line, connect pins
2 & 3 directly to the positive supply rail (VCC). In
this conguration the data lines are referenced to
the supply voltage. The internal TVS prevents over-
voltage on the supply rail.
2. The SRDA can be isolated from the power supply by
adding a series resistor between Pins 2 and 3 and VCC.
A value of 10kΩ is recommended. The internal TVS
and steering diodes remain biased, providing the
advantage of lower capacitance.
3. In applications where no positive supply reference
is available, or complete supply isolation is desired,
the internal TVS may be used as the reference. In this
case, pins 2 and 3 are not connected. The steering
diodes will begin to conduct when the voltage on the
protected line exceeds the working voltage of the TVS
(plus one VF drop).
ESD Protection With RailClamps
RailClamps are optimized for ESD protection using the
rail-to-rail topology. Along with good board layout,
these devices virtually eliminate the disadvantages of
using discrete components to implement this topology.
Consider the situation shown in Figure 1 where discrete
diodes or diode arrays are congured for rail-to rail
protection on a high speed line. During positive duration
ESD events, the top diode will be forward biased when
the voltage on the protected line exceeds the reference
voltage plus the VF drop of the diode. For negative events,
the bottom diode will be biased.
Data Line and Power Supply Protection Using VCC
as Reference
1
2
3
4
8
7
6
5
I/O 1
VCC
I/O 2
I/O 3
I/O 4
Data Line Protection with Bias and Power Supply Isolation
Resistor
1
2
3
4
8
7
6
5
I/O 1
VCC
I/O 2
I/O 3
I/O 4
10K
Data Line Protection Using Internal TVS as Reference
1
2
3
4
8
7
6
5
I/O 1
NC
NC
I/O 2
I/O 3
I/O 4
SRDA05-4 and SRDA12-4
Final Datasheet Rev 7.1
11/20/2018
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Semtech
Proprietary & Condential
When the voltage exceeds the VF, at rst approximation,
the clamping voltage due to the characteristics of the
protection diodes is given by:
VC = VCC + VF (for positive duration pulses)
VC = -VF (for negative duration pulses)
However, for fast rise time transient events, the eects of
parasitic inductance must also be considered as shown in
Figure 2. Therefore, the actual clamping voltage seen by
the protected circuit will be:
VC = VCC + VF+ LPdiESD/dt (for positive duration pulses)
VC = -VF - LGdiESD/dt (for negative duration pulses)
ESD current reaches a peak amplitude of 30A in 1ns
for a level 4 ESD contact discharge per IEC 61000-4-2.
Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = LPdiESD/dt = 1X10-9 (30 / 1X10-9) = 30V
Example:
Consider a VCC = 5V, a typical VF of 30V (at 30A) for the
steering diode and a series trace inductance of 10nH. The
clamping voltage seen by the protected IC for a positive
8kV (30A) ESD pulse will be:
VC = 5V + 30V + (10nH X 30V/nH) = 335V
This does not take into account that the ESD current is
directed into the supply rail, potentially damaging any
components that are attached to that rail. Also note the
high VF of the discrete diode. It is not uncommon for the
VF of discrete diodes to exceed the damage threshold
of the protected IC. This is due to the relatively small
junction area of typical discrete components. It is also
possible that the power dissipation capability of the
discrete diode will be exceeded, thus destroying the
device. The RailClamp is designed to overcome the
inherent disadvantages of using discrete signal diodes for
ESD suppression. The RailClamp’s integrated TVS helps to
mitigate the eects of parasitic inductance in the power
supply connection. During an ESD event, the current will
be directed through the integrated TVS to ground.
Figure 1 - Rail-To-Rail Protection Topology
(First Approximation)
VCC
i1
i2
VF + VCC
-VF
Figure 2 - The Eects of Parasitic Inductance When
Using Discrete Components to Implement Rail-To-Rail
Protection
VCC = REF1
Pr ot ected
IC
IESD
I/O
LP
GN D = REF2
+
VTV S
-
Figure 3 - Rail-To-Rail Protection Using
RailClamp TVS Arrays
VCC = REF1
Pr ot ected
IC
IESD
I/O
LP
GN D = REF2
+
VTV S
-
Application Information
SRDA05-4 and SRDA12-4
Final Datasheet Rev 7.1
11/20/2018
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Semtech
Proprietary & Condential
Application Information
The total clamping voltage seen by the protected IC due
to this path will be:
VC = VF(RailClamp) + VTVS
This is given in the datasheet as the rated clamping
voltage of the device. For an SRDA05-4 the typical
clamping voltage is <16V at IPP=30A. The diodes internal
to the RailClamp are low capacitance, fast switching
devices that are rated to handle high transient currents
and maintain excellent forward voltage characteristics.
Using the RailClamp does not negate the need for
good board layout. All other inductive paths must be
considered. The connection between the positive supply
and the SRDA and from the ground plane to the SRDA
must be kept as short as possible. The path between the
SRDA and the protected line must also be minimized. The
protected lines should be routed directly to the SRDA.
Placement of the SRDA on the PC board is also critical for
eective ESD protection. The device should be placed as
close as possible to the input connector. The reason for
this is twofold. First, inductance resists change in current
ow. If a signicant inductance exists between the
connector and the TVS, the ESD current will be directed
elsewhere (lower resistance path) in the system. Second,
the eects of radiated emissions and transient coupling
can cause upset to other areas of the board even if there
is no direct path to the connector. By placing the TVS
close to the connector, it will divert the ESD current
immediately and absorb the ESD energy before it can be
coupled into nearby traces.
SRDA05-4 and SRDA12-4
Final Datasheet Rev 7.1
11/20/2018
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Proprietary & Condential
Typical Application
RTI P
RRING
TTIP
TRING
T1/E1
Transceiver
R1
R3
R2
T1
T2
LC01-6
LC01-6
SRDA05-4
14
5
8
PTC
PTC
PTC
PTC
R4
R5
T1/E1 Interface Protection (GR-1089 Long Haul)
USB
Controller
RT
RT
RT
RT
VBUS
SRDA05-4
CTCT
CTCT
VBUS
D+
D-
GND
VBUS
D+
D-
GND
VBUS
D+
D-
GND V BUS
VBUS
SR05
UP ST REAM
USB PORT
DOW NSTREAM
USB PORT
DOW NSTREAM
USB PORT
Univeral Serial Bus ESD Protection
SRDA05-4 and SRDA12-4
Final Datasheet Rev 7.1
11/20/2018
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Semtech
Proprietary & Condential
Outline Drawing - SO-8
Land Pattern - SO-8
8
0.25
1.27 BSC
6.00
3.90
4.90
-
3.80
4.80
0.39
4.00
5.00
0.47
0°
0.20
0.10
-8°
0.50
0.20
1.30
0.10
-
(1.05)
-
-
0.80
0.24
1.40
-
-1.75
1.50
0.225
0.25 0.50
-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
DATUMS AND TO BE DETERMINED AT DATUM PLANE .
NOTES:
1.
2.
L1
N
01
bbb
aaa
ccc
A
b
A2
A1
D
E
E1
L
h
e
c
DIM MIN
MILLIMETERS
DIMENSIONS
MAXNOM
-B--A- -H-
REFERENCE JEDEC STD MS-012, VARIATION AA.
4.
DETAIL A
bxN
2X N/2 TIP S
SEATING
aaa C
E/2
2X
1 2
N
A
D
A1
E1
bbb C A-B D
ccc C
e/2
A2
c
L
(L1) 01
0.25
H
GAGE
PLANE
h
A
B
C
D
e
PLANE
SEE DETAIL A
SID E VIEW
E5.80 6.20
(5.20)
Z
G
Y
P
(C) 3.00
1.27
0.60
2.20
7.40
X
DIMENSIONS
Z
P
Y
X
DIM
C
G
MILLIMETERS
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
NOTES:
1.
REFERENCE IPC-SM-782A, RLP NO. 300A.2.
SRDA05-4 and SRDA12-4
Final Datasheet Rev 7.1
11/20/2018
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Proprietary & Condential
Marking Code
Tape and Reel Specication
Ordering Information
Part Number Qty per Reel Reel Size
SRDA05-4.TLT 3000 13 Inch
SRDA12-4.TLT 3000 13 Inch
SC YYWW
SRDA05-4
XXXXX
SC YYWW
SRDA12-4
XXXXX
Notes:
YYWW = Date Code
XXXXX = Country of Assembly
Pin 1 Location
User Direction of Feed
SRDA05-4 and SRDA12-4
Final Datasheet Rev 7.1
11/20/2018
10
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Contact Information
Semtech Corporation
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com
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© Semtech 2017
Proprietary & Condential
