L5-00221-00 - LSI CORPORATION

Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com 4163.12E-0716-ss-W3H128M72E-XSBX / XNBX

1GB – 128M x 72 DDR2 SDRAM

208 PBGA Multi-Chip Package

W3H128M72E-XSBX / W3H128M72E-XNBX

FEATURES

 Data rate = 667, 533, 400

 Package:

• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm

• 1.0mm pitch

 Core Supply Voltage = 1.8V

 I/O Supply Voltage = 1.8V - (SSTL_18 compatible)

 Differential data strobe (DQS, DQS#) per byte

 Internal, pipelined, double data rate architecture

 4-bit prefetch architecture

 DLL for alignment of DQ and DQS transitions with clock

signal

 Eight internal banks for concurrent operation

(Per DDR2 SDRAM Die)

 Programmable Burst lengths: 4 or 8

 Auto Refresh and Self Refresh Modes

 On Die Termination (ODT)

 Adjustable data – output drive strength

 Programmable CAS latency (CL)

 Posted CAS additive latency (AL)

 CK/CK# Termination options available

• 0 ohm, 20 ohm

 Write latency = Read latency - 1* tCK

 Commercial, Industrial and Military Temperature Rang es

 Organized as 128M x 72

 Weight: W3H128M72E-XSBX - 4 grams max

 Weight: W3H128M72E-XNBX - TBD

BENEFITS

 56% space savings vs. FBGA

 Re duced part count

 50% I/O reduction vs FBGA

 Re duced trace lengths for low er par a sit ic ca pac i tance

 Suit able for hi-re li abil i ty ap pli ca tions

* This product is subject to change without notice.

FIGURE 1 – DENSITY COMPARISONS

CSP Approach (mm) W3H128M72E-XXXX S

Area 5 x 161mm2 = 805mm2352mm256%

I/O Count 5 x 84 balls = 420 balls 208 Balls 50%

FBGA

11.5

14.0 84

FBGA

11.5

FBGA

11.5

FBGA

11.5

FBGA

11.5

W3H128M72E-XXXX

DDR2 / DDR3

W3H128M72E-XSBX / -XNBX

RAM

SSD (SLC)

MSM032 / MSM064 (SATA BGA)

W7N16GVHxxBI (PATA BGA)

MSD1TB / 512 / 256 / 128 (SATA, 2.5in)

Host

FPGA/

Processor

)

TYPICAL APPLICATION

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DQ16

DQ31

DQ0

DQ15

WE# CS# RAS# CAS# CKE

DQ32

DQ47

DQ0

DQ15

WE# CS# RAS# CAS# CKE

DQ48

DQ63

DQ0

DQ15

CKE

DQ64 DQ0

CKE

A0-13

BA0-2

RAS#

WE#

CAS#

CKE

CS#

A0-13

BA0-2

ODT

A0-13

BA0-2

ODT

A0-13

BA0-2

ODT

A0-13

BA0-2

ODT

A0-13

BA0-2

CK4#

CK#

LDM4

LDM

VCC

UDM

LDQS4

LDQS#

UDQS4

LDQS4#

UDQS4#

UDQS#

LDQS

UDQS

ODT

CK4

ODT

CK3#

CK#

LDM3

LDM

UDM3

UDM

LDQS3

LDQS#

UDQS3

LDQS3#

UDQS3#

UDQS#

LDQS

UDQS

CK3

CK2#

CK#

LDM2

LDM

UDM2

UDM

LDQS2

LDQS#

UDQS2

LDQS2#

UDQS2#

UDQS#

LDQS

UDQS

CK2

CK1#

CK#

LDM1

LDM

UDM1

UDM

LDQS1

LDQS#

UDQS1

LDQS1#

UDQS1#

UDQS#

LDQS

UDQS

CK1

CK0#

CK#

LDM0

LDM

UDM0

UDM

LDQS0

LDQS#

UDQS0

LDQS0#

UDQS0#

UDQS#

LDQS

UDQS

CK0

DQ0

DQ15

DQ0

DQ15

WE# CS# RAS# CAS# CKE

WE# CS# RAS# CAS#

DQ71

DQ7

WE# CS# RAS# CAS#

FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM

NOTE: Connect UDQS4 to ground via a resistor and UDQS4#

to VCC via a resistor. UDM4 is internally tied to VCC.

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1 2 3 4 5 6 7 8 9 10 11

VCC

VSS

DQ35

DQ52

LDM3

DQ38

UDM3

VCC

VSS

VCC

UDQS1#

DQ13

LDQS1#

DQ0

CK0

VSS

VCC

VSS

VCC

VSS

DQ51

DQ36

LDM2

DQ54

DQ44

UDQS1

DQ29

LDQS0#

DQ16

CK0#

CK1#

VSS

VCC

VSS

DQ33

DQ49

DQ60

DQ41

A10

A11

UDQS0

DQ8

DQ10

LDQS1

DQ5

CK1

CK4#

VSS

VCC

DQ43

DQ57

DQ46

VCC

DQ15

DQ24

DQ26

LDQS0

DQ21

DQ2

CK4

VCC

BA2

DQ59

UDM2

DQ62

VCC

VSS

VCC

UDQS0#

DQ31

DQ23

DQ7

DQ18

RAS#

CS#

VCC

DQ50

DQ39

DQ55

DQ63

UDQS2#

VCC

VSS

VCC

DQ30

UDM0

DQ27

UDQS4

DQ71

DQ64

DQ69

Vcc

VCC

VSS

CK3#

CK2#

DQ48

LDQS2#

DQ61

UDQS3

A13

BA1

DQ12

DQ22

LDM0

DQ4

DQ19

DQ68

VSS

VCC

DQ34

DQ53

LDQS2

DQ58

DQ56

DQ47

VCC

BA0

DQ14

DQ25

DQ11

UDQS4#

CKE

DQ70

LDM4

VCC

VSS

CK3

DQ37

LDQS3

DQ42

DQ40

UDQS2

A12

DQ9

DQ28

DQ17

DQ1

WE#

DQ65

DQ67

VSS

DNU

VSS

VCC

VSS

VREF

VSS

VCC

VSS

ODT

LDQS4#

LDQS4

CAS#

DQ66

VSS

VCC

VSS

CK2

DQ32

LDQS3#

DQ45

UDQS3#

VCC

VSS

VCC

UDM1

DQ6

LDM1

DQ20

DQ3

VSS

VCC

VSS

TOP VIEW

FIGURE 3 – PIN CONFIGURATION

NOTE: Connect UDQS4 to ground via a resistor and UDQS4# to VCC via a resistor.

UDM4 is internally tied to VCC

Balls F6 and E6 are reserved for A14 and A15 on future densities.

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TABLE 1 – BALL DESCRIPTIONS

Symbol Type Description

ODT Input

On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only

applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be ignored if

disabled via the LOAD MODE command.

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge

of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.

CKE Input

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The

speciﬁ c circuitry that is enabled/disabled is dependent on the DDR2 SDRAM conﬁ guration and operating mode. CKE LOW provides

PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row active in any bank). CKE

is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh

exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during

self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once VCC is applied during ﬁ rst power-up. After VREF has

become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For

proper SELF-REFRESH operation, VREF must be maintained.

CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when

CS# is registered HIGH.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, WE# (along with CS#) deﬁ ne the command being entered.

LDM, UDM Input

Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a

WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of

DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of U0-U4

BA0–BA2 Input Bank address inputs: BA0–BA2 deﬁ ne to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–

BA2 deﬁ ne which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.

A0-A13 Input

Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/

WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10

HIGH) The address inputs also provide the op-code during a LOAD MODE command.

DQ0-71 I/O Data input/output: Bidirectional data bus

UDQS, UDQS# I/O

Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read

data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

LDQS, LDQS# I/O

Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read

data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE

command.

VCC Supply Power Supply: I/O + core, VCCQ is common to VCC

VREF Supply SSTL_18 reference voltage.

VSS Supply Ground

NC - No connect: These balls should be left unconnected.

DNU - Future use; address bits A14 and A15 are reserved for future densities.

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DESCRIPTION

The 8Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-

access memory containing ﬁ ve 2Gb 2,147,483,648 bits chips. Each

of the ﬁ ve chips in the MCP are internally conﬁ gured as 8-bank

DRAM. The block diagram of the device is shown in Figure 2. Ball

assignments are shown in Figure 3.

The 8Gb DDR2 SDRAM uses a double-data-rate architecture to

achieve high-speed operation. The double data rate architecture is

essentially a 4n-prefetch architecture, with an interface designed

to transfer two data words per clock cycle at the I/O balls. A single

read or write access for the 8Gb DDR2 SDRAM effectively consists

of a single 4n-bit-wide, one-clock-cycle data transfer at the internal

DRAM core and four corresponding n-bit-wide, one-half-clock-cycle

data transfers at the I/O balls.

A bidirectional data strobe (DQS, DQS#) is transmitted externally,

along with data, for use in data capture at the receiver. DQS is a

strobe transmitted by the DDR2 SDRAM during READs and by the

memory controller during WRITEs. DQS is edge-aligned with data

for READs and center-aligned with data for WRITEs. Two strobes

per chip, one for the lower byte (LDQS, LDQS#) and one for the

upper byte (UDQS, UDQS#).

The 8Gb DDR2 SDRAM operates from a differential clock (CK and

CK#); the crossing of CK going HIGH and CK# going LOW will

be referred to as the positive edge of CK. Commands (address

and control signals) are registered at every positive edge of CK.

Input data is registered on both edges of DQS, and output data is

referenced to both edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR2 SDRAM are burst oriented;

accesses start at a selected location and continue for a programmed

number of locations in a programmed sequence. Accesses begin

with the registration of an ACTIVE command, which is then followed

by a READ or WRITE command. The address bits registered

coincident with the ACTIVE command are used to select the bank

and row to be accessed. The address bits registered coincident

with the READ or WRITE command are used to select the bank

and the starting column location for the burst access.

The DDR2 SDRAM provides for programmable read or write

burst lengths of four or eight locations. DDR2 SDRAM supports

interrupting a burst read of eight with another read, or a burst

write of eight with another write. An auto precharge function may

be enabled to provide a self-timed row precharge that is initiated

at the end of the burst access.

As with standard DDR SDRAMs, the pipelined, multibank

architecture of DDR2 SDRAMs allows for concurrent operation,

thereby providing high, effective bandwidth by hiding row precharge

and activation time.

A self refresh mode is provided, along with a power-saving power-

down mode.

All inputs are compatible with the JEDEC standard for SSTL_18.

All full drive-strength outputs are SSTL_18-compatible.

GENERAL NOTES

The functionality and the timing speciﬁ cations discussed in this

data sheet are for the DLL-enabled mode of operation.

Throughout the data sheet, the various ﬁ gures and text refer to

DQs as “DQ.” The DQ term is to be interpreted as any and all

DQ collectively, unless speciﬁ cally stated otherwise. Additionally,

each chip is divided into 2 bytes, the lower byte and upper byte.

For the lower byte (DQ0–DQ7), DM refers to LDM and DQS

refers to LDQS. For the upper byte (DQ8–DQ15), DM refers to

UDM and DQS refers to UDQS. Note that the there is no upper

byte for U4 and therefore no UDM4.

Complete functionality is described throughout the document

and any page or diagram may have been simpliﬁ ed to convey a

topic and may not be inclusive of all requirements.

Any speciﬁ c requirement takes precedence over a general

statement.

INITIALIZATION

DDR2 SDRAMs must be powered up and initialized in a

predeﬁ ned manner. Operational procedures other than those

speciﬁ ed may result in undeﬁ ned operation. The following

sequence is required for power up and initialization and is

shown in Figure 4 on page 6.

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CKE

Power-up:

and stable

clock (CK, CK#)

T = 200μs (MIN)

High-Z

DQS

High-Z

ddress

CK#

Command

NOP

PRE

T0 Ta0

VCC

VCCL

VCCQ tVTD1

tCK

tCL tCL

VTT1

VREF

ODT

High-Z

Tb0

200 cycles of CK are required before a READ command can be issued

MR with

DLL RESET

See note 10

PRE

REF

Tg0 Th0 Ti0 Tj0

MR without

DLL RESET

EMR with

OCD default

Tk0 Tl0 Tm0

Te0 Tf0

EMR(2) EMR(3)

tMRD tMRD tMRD tMRD tMRD tMRD tMRD

A10 = 1

tRPA tRPA tRFC tRFC

Tc0 Td0

SSTL_18

low level2

Valid

EMR with

OCD exit

Normal

operation

Code Code

A10 = 1

Code Code

Code Code Code

EMR

T = 400ns (MIN)

LVCMOS

low level2

Don’t care

Indicates a Break in

Time Scale

REF

FIGURE 4 – POWER-UP AND INITIALIZATION

NOTES:

1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled. To guarantee

RTT (ODT resistance) is off, VREF must be valid and a low level must be applied to the ODT ball

(all other inputs may be undeﬁ ned, I/Os and outputs must be less than VCCQ during voltage ramp

time to avoid DDR2 SDRAM device latch-up). At least one of the following two sets of conditions

(A or B) must be met to obtain a stable supply state (stable supply deﬁ ned as VCC, VCCQ,VREF,

and VTT are between their minimum and maximum values as stated in DC Operating Conditions

table):

A. (single power source) The VCC voltage ramp from 300mV to VCC (MIN) must take no longer

than 200ms; during the VCC voltage ramp, |VCC - VCCQ|  0.3V. Once supply voltage ramping

is complete (when VCCQ crosses VCC (MIN), DC Operating Conditions table speciﬁ cations

apply.

• VCC, VCCQ are driven from a single power converter output

• VTT is limited to 0.95V MAX

• VREF tracks VCCQ/2; VREF must be within ±0.3V with respect to VCCQ/2 during supply ramp

time.

• VCCQ  VREF at all times

B. (multiple power sources) VCC  VCCQ must be maintained during supply voltage ramping,

for both AC and DC levels, until supply voltage ramping completes (VCCQ crosses

VCC [MIN]). Once supply voltage ramping is complete, DC Operating Conditions table

speciﬁ cations apply.

• Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must be  200ms

from when VCC ramps from 300mV to VCC (MIN)

• Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time from when

VCC (MIN) is achieved to when VCCQ (MIN) is achieved must be  500ms; while VCC is

ramping, current can be supplied from VCC through the device to VCCQ

• VREF must track VCCQ/2, VREF must be within ±0.3V with respect to VCCQ/2 during supply

ramp time; VCCQ  VREF must be met at all times

• Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to when VTT (MIN)

is achieved must be no greater than 500ms

2. CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-

up prior to VREF. being stable. After state T0, CKE is required to have SSTL_18 input levels.

Once CKE transitions to a high level, it must stay HIGH for the duration on the initialization

sequence.

3. For a minimum of 200s after stable power and clock (CK, CK#), apply NOP or DESELECT

commands, then take CKE HIGH.

4. Wait a minimum of 400ns then issue a PRECHARGE ALL command.

5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide LOW

to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropriate self refresh

rate; remaining EMR(2) bits must be “0” (see Extended Mode Register 2 (EMR2) for all EMR(2)

requirements).

6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide HIGH

to BA0 and BA1; remaining EMR(3) bits must be “0.” Extended Mode Register 3 (EMR3) for all

EMR(3) requirements.

7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command,

provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set to “0” or

“1;” It is recommended setting them to “0;” remaining EMR bits must be “0.” Extended Mode

8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is required

to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and BA0;

CKE must be HIGH the entire time the DLL is resetting; remaining MR bits must be “0.” Mode

9. Issue PRECHARGE ALL command.

10. Issue two or more REFRESH commands.

11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation (that

is, to program operating parameters without resetting the DLL). To access the MR, set BA0 and

BA1 LOW; remaining MR bits must be set to desired settings. Mode Register (MR) for all MR

requirements.

12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and

E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0 HIGH and

BA1 LOW (see Extended Mode Register (EMR) for all EMR requirements.

13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to

“0,” and then setting all other desired parameters. To access the extended mode registers, EMR,

set BA0 HIGH and BA1 LOW for all EMR requirements.

14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the

DLL RESET at Tf0.

15. DM represents UDM and LDM; DQS represents UDQS, UDQS#, LDQS and LDQS#. DQ

represents DQ[71:0].

16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are

required to be decoded).

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MODE REGISTER (MR)

The mode register is used to deﬁ ne the speciﬁ c mode of operation

of the DDR2 SDRAM. This deﬁ nition includes the selection of a

burst length, burst type, CAS latency, operating mode, DLL RESET,

write recovery, and power-down mode, as shown in Figure 5.

Contents of the mode register can be altered by re-executing the

LOAD MODE (LM) command. If the user chooses to modify only

a subset of the MR variables, all variables must be programmed

when the command is issued.

The mode register is programmed via the LM command will

retain the stored information until it is programmed again or the

device loses power (except for bit M8, which is self-clearing).

Reprogramming the mode register will not alter the contents of

the memory array, provided it is performed correctly.

The LM command can only be issued (or reissued) when all

banks are in the precharged state (idle state) and no bursts are in

progress. The controller must wait the speciﬁ ed time tMRD before

initiating any subsequent operations such as an ACTIVE command.

Violating either of these requirements will result in unspeciﬁ ed

operation.

BURST LENGTH

Burst length is deﬁ ned by bits M0–M2, as shown in Figure 5. Read

and write accesses to the DDR2 SDRAM are burst-oriented, with

the burst length being programmable to either four or eight. The

burst length determines the maximum number of column locations

that can be accessed for a given READ or WRITE command.

When a READ or WRITE command is issued, a block of columns

equal to the burst length is effectively selected. All accesses for

that burst take place within this block, meaning that the burst

will wrap within the block if a boundary is reached. The block is

uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL =

8 (where Ai is the most signiﬁ cant column address bit for a given

conﬁ guration). The remaining (least signiﬁ cant) address bit(s)

is (are) used to select the starting location within the block. The

programmed burst length applies to both READ and WRITE bursts.

BURST TYPE

Accesses within a given burst may be programmed to be either

sequential or interleaved. The burst type is selected via bit M3,

as shown in Figure 5. The ordering of accesses within a burst is

determined by the burst length, the burst type, and the starting

column address, as shown in Table 2. DDR2 SDRAM supports

4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode,

full interleaved address ordering is supported; however, sequential

address ordering is nibble-based.

Burst LengthCAS# Latency BT

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

A10A12 A11BA1BA2

10111213

Burst Length

Reserved

Burst Type

Sequential

Interleaved

CAS Latency (CL)

Reserved

Mode

Normal

Test

1516

DLL TM

DLL Reset

Yes

WRITE RECOVERY

Reserved

M10

M11

A13BA0

Mode Register Definition

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

M15

PD mode

Fast Exit

(Normal)

Slow Exit

(Low Power)

M12

M14

FIGURE 5 – MODE REGISTER (MR) DEFINITION

NOTE: Not all listed CL options are supported in any individual speed grades.

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TABLE 2 – BURST DEFINITION

Burst

Length Starting Column

Address Order of Accesses With in a Burst

Type = Sequential Type = In ter leaved

A1 A0

00 0-1-2-3 0-1-2-3

01 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

11 3-0-1-2 3-2-1-0

A2 A1 A0

0000-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0011-2-3-0-5-6-7-4 1-0-3-2-5-4-7-6

0102-3-0-1-6-7-4-5 2-3-0-1-6-7-4-5

0113-0-1-2-7-4-5-6 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-4-1-2-3-0 5-4-7-6-1-0-3-2

1 1 0 6-7-4-5-2-3-0-1 6-7-4-5-2-3-0-1

1 1 1 7-4-5-6-3-0-1-2 7-6-5-4-3-2-1-0

NOTES:

1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column

within the block.

2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column

within the block.

3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting

column within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

OPERATING MODE

The normal operating mode is selected by issuing a command

with bit M7 set to “0,” and all other bits set to the desired values,

as shown in Figure 5. When bit M7 is “1,” no other bits of the

mode register are programmed. Programming bit M7 to “1” places

the DDR2 SDRAM into a test mode that is only used by the

manufacturer and should not be used. No operation or functionality

is guaranteed if M7 bit is ‘1.’

DLL RESET

DLL RESET is defined by bit M8, as shown in Figure 5.

Programming bit M8 to “1” will activate the DLL RESET function.

Bit M8 is self-clearing, meaning it returns back to a value of “0”

after the DLL RESET function has been issued.

Anytime the DLL RESET function is used, 200 clock cycles must

occur before a READ command can be issued to allow time for the

internal clock to be synchronized with the external clock. Failing

to wait for synchronization to occur may result in a violation of the

tAC or tDQSCK parameters.

WRITE RECOVERY

Write recovery (WR) time is deﬁ ned by bits M9–M11, as shown in

Figure 5. The WR register is used by the DDR2 SDRAM during

WRITE with auto precharge operation. During WRITE with auto

precharge operation, the DDR2 SDRAM delays the internal auto

precharge operation by WR clocks (programmed in bits M9–M11)

from the last data burst.

WR values of 2, 3, 4, 5, 6, 7 or 8 clocks may be used for

programming bits M9–M11. The user is required to program the

value of WR, which is calculated by dividing tWR (in ns) by tCK (in

ns) and rounding up a non integer value to the next integer; WR

[cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used

as unknown operation or incompatibility with future versions may

result.

POWER-DOWN MODE

Active power-down (PD) mode is deﬁ ned by bit M12, as shown

in Figure 5. PD mode allows the user to determine the active

power-down mode, which determines performance versus power

savings. PD mode bit M12 does not apply to precharge PD mode.

When bit M12 = 0, standard active PD mode or “fast-exit” active PD

mode is enabled. The tXARD parameter is used for fast-exit active

PD exit timing. The DLL is expected to be enabled and running

during this mode.

When bit M12 = 1, a lower-power active PD mode or “slow-exit”

active PD mode is enabled. The tXARDS parameter is used for slow-

exit active PD exit timing. The DLL can be enabled, but “frozen”

during active PD mode because the exit-to-READ command timing

is relaxed. The power difference expected between PD normal and

PD low-power mode is deﬁ ned in the ICC table.

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CAS LATENCY (CL)

The CAS latency (CL) is deﬁ ned by bits M4–M6, as shown in Figure

5. CL is the delay, in clock cycles, between the registration of a

READ command and the availability of the ﬁ rst bit of output data.

The CL can be set to 4, 5, 6 or 7 clocks, depending on the speed

grade option being used.

DDR2 SDRAM does not support any half-clock latencies. Reserved

states should not be used as unknown operation or incompatibility

with future versions may result.

DDR2 SDRAM also supports a feature called posted CAS additive

latency (AL). This feature allows the READ command to be issued

prior to tRCD (MIN) by delaying the internal command to the DDR2

SDRAM by AL clocks.

An example of CL = 4 is shown in Figure 6; assume AL = 0. If a

READ command is registered at clock edge n, and the CL is m

clocks, the data will be available nominally coincident with clock

edge n+m (this assumes AL = 0).

OUT

n + 3

OUT

n + 2

OUT

n + 1

CL = 4 (AL = 0)

READ

T0 T1 T2

NOP NOP NOP

OUT

T3 T4 T5

NOP NOP

NOP

DQS, DQS#

Burst length = 4

Posted CAS# additive latency (AL) = 0

Shown with nominal tAC, tDQSCK and tDQSQ

CK#

COMMAND

DON’T CARETRANSITIONING DATA

FIGURE 6 – CAS LATENCY (CL)

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EXTENDED MODE REGISTER (EMR)

The extended mode register controls functions beyond those

controlled by the mode register; these additional functions are DLL

enable/disable, output drive strength, on die termination (ODT),

posted AL, off-chip driver impedance calibration (OCD), DQS#

enable/disable, RDQS/RDQS# enable/disable, and output disable/

enable. These functions are controlled via the bits shown in Figure

7. The EMR is programmed via the LOAD MODE (LM) command

and will retain the stored information until it is programmed again

or the device loses power. Reprogramming the EMR will not alter

the contents of the memory array, provided it is performed correctly.

The EMR must be loaded when all banks are idle and no bursts

are in progress, and the controller must wait the speciﬁ ed time

tMRD before initiating any subsequent operation. Violating either

of these requirements could result in an unspeciﬁ ed operation.

FIGURE 7 – EXTENDED MODE REGISTER DEFINITION

DLLPosted CAS#out

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

A10A12 A11BA1BA2

10111213

Posted CAS# Additive Latency (AL)

Reserved

DLL Enable

Enable (Normal)

Disable (Test/Debug)

RDQS Enable

Yes

E11

OCD Program

A13BA0

ODS

RTT

DQS#

Enable

Disable

E10

RDQS

RTT (nominal)

RTT disabled

75Ω

150Ω

50Ω

Outputs

Enabled

Disabled

E12

Mode Register Set

Mode register set (MRS)

Extended mode register (EMR)

Extended mode register (EMRS2)

Extended mode register (EMRS3)

E15

E14

MRS

OCD Operation1

OCD exit

Reserved

Enable OCD defaults

Output Drive StrengthE1

Full strength (18Ω target)

Reduced strength (40Ω target)

RTT

DQS# Enable

NOTES:

1. During initialization, all three bits must be set to "1" for OCD default state, then must be set to "0" before

initialization is ﬁ nished.

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DLL ENABLE/DISABLE

The DLL may be enabled or disabled by programming bit E0

during the LM command, as shown in Figure 7. The DLL must

be enabled for normal operation. DLL enable is required during

power-up initialization and upon returning to normal operation after

having disabled the DLL for the purpose of debugging or evaluation.

Enabling the DLL should always be followed by resetting the DLL

using an LM command.

The DLL is automatically disabled when entering SELF REFRESH

operation and is automatically re-enabled and reset upon exit of

SELF REFRESH operation.

Any time the DLL is enabled (and subsequently reset), 200 clock

cycles must occur before a READ command can be issued, to

allow time for the internal clock to synchronize with the external

clock. Failing to wait for synchronization to occur may result in a

violation of the tAC or tDQSCK parameters.

OUTPUT DRIVE STRENGTH

The output drive strength is deﬁ ned by bit E1, as shown in Figure

7. The normal drive strength for all outputs is speciﬁ ed to be

SSTL_18. Programming bit E1 = 0 selects normal (full strength)

drive strength for all outputs. Selecting a reduced drive strength

option (E1 = 1) will reduce all outputs to approximately 45 to 60

percent of the SSTL_18 drive strength. This option is intended

for the support of lighter load and/or point-to-point environments.

DQS# ENABLE/DISABLE

The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the

complement of the differential data strobe pair DQS/DQS#. When

disabled (E10 = 1), DQS is used in a single ended mode and the

DQS# ball is disabled. When disabled, DQS# should be left ﬂ oating;

however, it may be tied to ground via a resistor. This function is

also used to enable/disable RDQS#. If RDQS is enabled (E11 =

1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS#

will be enabled. RDQS is not available on this device.

OUTPUT ENABLE/DISABLE

The OUTPUT ENABLE function is deﬁ ned by bit E12, as shown in

Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#)

function normally. When disabled (E12 = 1), all DDR2 SDRAM

outputs (DQs, DQS, DQS#) are disabled, thus removing output

buffer current. The output disable feature is intended to be used

during ICC characterization of read current.

ON-DIE TERMINATION (ODT)

ODT effective resistance, RTT (EFF), is deﬁ ned by bits E2 and E6

of the EMR, as shown in Figure 7. The ODT feature is designed

to improve signal integrity of the memory channel by allowing the

DDR2 SDRAM controller to independently turn on/off ODT for any

or all devices. RTT effective resistance values of 50Ω ,75Ω, and

150Ω are selectable and apply to each DQ, UDQS/UDQS#, LDQS/

LDQS#, and UDM/LDM signals. Bits (E6, E2) determine what ODT

resistance is enabled by turning on/off “sw1,” “sw2,” or “sw3.” The

ODT effective resistance value is selected by enabling switch

“sw1,” which enables all R1 values that are 150Ω each, enabling

an effective resistance of 75Ω (RTT2(EFF) = R2/2). Similarly, if “sw2”

is enabled, all R2 values that are 300Ω each, enable an effective

ODT resistance of 150Ω (RTT2(EFF) = R2/2). Switch “sw3” enables

R1 values of 100Ω enabling effective resistance of 50Ω.

The ODT control ball is used to determine when RTT(EFF) is turned

on and off, assuming ODT has been enabled via bits E2 and E6 of

the EMR. The ODT feature and ODT input ball are only used during

active, active power-down (both fast-exit and slow-exit modes),

and precharge power-down modes of operation. ODT must be

turned off prior to entering self refresh mode. During power-up and

initialization of the DDR2 SDRAM, ODT should be disabled until

issuing the EMR command to enable the ODT feature, at which

point the ODT ball will determine the RTT(EFF) value. Anytime the

EMR enables the ODT function, ODT may not be driven HIGH until

eight clocks after the EMR has been enabled. See “ODT Timing”

section for ODT timing diagrams.

OFF-CHIP DRIVER (OCD) IMPEDANCE

CALIBRATION

The OFF-CHIP DRIVER function is an optional DDR2 JEDEC

feature not supported and thereby must be set to the default state.

Enabling OCD beyond the default settings will alter the I/O drive

characteristics and the timing and output I/O speciﬁ cations will no

longer be valid.

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POSTED CAS ADDITIVE LATENCY (AL)

Posted CAS additive latency (AL) is supported to make the

command and data bus efﬁ cient for sustainable bandwidths in

DDR2 SDRAM. Bits E3–E5 deﬁ ne the value of AL, as shown in

Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM

with an AL of 0, 1, 2, 3, 4, 5 or 6 clocks. Reserved states should

not be used as unknown operation or incompatibility with future

versions may result.

In this operation, the DDR2 SDRAM allows a READ or WRITE

command to be issued prior to tRCD (MIN) with the requirement

that AL ≤ tRCD (MIN). A typical application using this feature would

set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command is

held for the time of the AL before it is issued internally to the

DDR2 SDRAM device. RL is controlled by the sum of AL and CL;

RL = AL+CL. Write latency (WL) is equal to RL minus one clock;

WL = AL + CL - 1 x tCK.

A9 A7 A6 A5 A4 A3 0A1A2A8A

Extended mode

Address bus

976543 0128

A10A12 A11BA0BA1

10111213

1415

A13

E14

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

E15

MRS 0 0 0 00SRT0 000 0 0 0

BA2

SRT Enable

1X refresh rate (+85°C max junction temp.)

2X refresh rate (+85°C to +95°C junction temp.)

FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION

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EXTENDED MODE REGISTER 2

The extended mode register 2 (EMR2) controls functions beyond

those controlled by the mode register. Currently all bits in EMR2

are reserved except for E7, as shown in Figure 8. The EMR2

is programmed via the LM command and will retain the stored

information until it is programmed again or the device loses power.

Reprogramming the EMR will not alter the contents of the memory

array, provided it is performed correctly.

Bit E7 (A7) must be programmed as"1" to provide a faster refresh

rate on devices if the junction temperature (TJ) exceeds 85°C but

doesn't exceed 95°C. Refer to operating junction temperature

limits in "DC operating conditions" table. Self refresh function is

not available for military grade devices.

EMR2 must be loaded when all banks are idle and no bursts are

in progress, and the controller must wait the speciﬁ ed time tMRD

before initiating any subsequent operation. Violating either of these

requirements could result in unspeciﬁ ed operation.

EXTENDED MODE REGISTER 3

The extended mode register 3 (EMR3) controls functions beyond

those controlled by the mode register. Currently, all bits in EMR3

are reserved, as shown in Figure 9. The EMR3 is programmed

via the LM command and will retain the stored information until it

is programmed again or the device loses power. Reprogramming

the EMR will not alter the contents of the memory array, provided

it is performed correctly.

EMR3 must be loaded when all banks are idle and no bursts are

in progress, and the controller must wait the speciﬁ ed time tMRD

before initiating any subsequent operation. Violating either of these

requirements could result in unspeciﬁ ed operation.

COMMAND TRUTH TABLE

The following table provides a quick reference of DDR2 SDRAM

available commands, including CKE power-down modes, and

bank-to-bank commands.

FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION

E14

Mode Register Set

Mode register (MR)

Extended mode register (EMR)

Extended mode register (EMR2)

Extended mode register (EMR3)

E15

A9 A7 A6 A5 A4 A3 0A1A2A8A

Extended mode

Address bus

976543 0128

A10A12 A11

BA0BA1

10111213

1415

A13

MRS 0 0 0 00 00 00000 0

BA2

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TABLE 3 – TRUTH TABLE - DDR2 COMMANDS

Notes 1, 5, and 6 apply to all

Function CKE CS# RAS# CAS# WE# BA2

BA1

BA0

A13

A12

A11 A10 A9-A0 Notes

Cycle Current

Cycle

LOAD MODE H H LLLLBA OP Code 2

REFRESH H H LLLHXXXX

SELF-REFRESH Entry H L LLLHXXXX

SELF-REFRESH Exit LH

HXXXXXXX7

LHHH

Single bank precharge HHLLHLBAXLX2

All banks PRECHARGE HHLLHLXXHX

Bank activate H H L L H H BA Row Address

WRITE HHLHLLBA

Column

Address LColumn

Address 2, 3

WRITE with auto precharge HHLHLLBA

Column

Address HColumn

Address 2, 3

READ H H LHLHBA

Column

Address LColumn

Address 2, 3

READ with auto precharge H H LHLHBA

Column

Address HColumn

Address 2, 3

NO OPERATION H X LHHHXXXX

Device DESELECT H X HXXXXXXX

POWER-DOWN entry HL

HXXXXXXX4

LHHH

POWER-DOWN exit LH

HXXXXXXX4

LHHH

NOTES:

1. All DDR2 SDRAM commands are deﬁ ned by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.

2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.

3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.

4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC parametric section.

5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.

6. “X” means “H or L” (but a deﬁ ned logic level).

7. Self refresh exit is asynchronous.

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DESELECT

The DESELECT function (CS# HIGH) prevents new commands

from being executed by the DDR2 SDRAM. The DDR2 SDRAM

is effectively deselected. Operations already in progress are not

affected. DESELECT is also referred to as COMMAND INHIBIT.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to instruct the

selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#,

CAS#, and WE are HIGH). This prevents unwanted commands

from being registered during idle or wait states. Operations already

in progress are not affected.

LOAD MODE (LM)

The mode registers are loaded via inputs BA2–BA0, and A13–A0.

BA2–BA0 determine which mode register will be programmed.

See “Mode Register (MR)”. The LM command can only be issued

when all banks are idle, and a subsequent execute able command

cannot be issued until tMRD is met.

ACTIVATE COMMAND

The ACTIVATE command is used to open (or activate) a row

in a particular bank for a subsequent access. The value on the

BA2–BA0 inputs selects the bank, and the address inputs select

the row. This row remains active (or open) for accesses until a

PRECHARGE command is issued to that bank. A PRECHARGE

command must be issued before opening a different row in the

same bank.

ACTIVE OPERATION

Before any READ or WRITE commands can be issued to a

bank within the DDR2 SDRAM, a row in that bank must be

opened (activated), even when additive latency is used. This is

accomplished via the ACTIVATE command, which selects both

the bank and the row to be activated.

After a row is opened with an ACTIVATE command, a READ or

WRITE command may be issued to that row, subject to the tRCD

speciﬁ cation. tRCD (MIN) should be divided by the clock period and

rounded up to the next whole number to determine the earliest

clock edge after the ACTIVATE command on which a READ or

WRITE command can be entered. The same procedure is used

to convert other speciﬁ cation limits from time units to clock cycles.

For example, a tRCD (MIN) speciﬁ cation of 20ns with a 266 MHz clock

(tCK = 3.75ns) results in 5.3 clocks, rounded up to 6.

FIGURE 10 – ACTIVE COMMAND

Row

Bank

DON’T CARE

CK#

CS#

RAS#

CAS#

WE#

CKE

ADDRESS

BANK ADDRESS

A subsequent ACTIVATE command to a different row in the

same bank can only be issued after the previous active row has

been closed (precharged). The minimum time interval between

successive ACTIVATE commands to the same bank is deﬁ ned

by tRC.

A subsequent ACTIVATE command to another bank can be issued

while the ﬁ rst bank is being accessed, which results in a reduction

of total row-access overhead. The minimum time interval between

successive ACTIVATE commands to different banks is deﬁ ned by

tRRD. This device has an additional requirement: tFAW. This requires

no more than four ACTIVATE commands may be issued in any

given tFAW (MIN) period.

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READ COMMAND

The READ command is used to initiate a burst read access to an

active row. The value on the BA2–BA0 inputs selects the bank,

and the address provided on inputs A0–i (where i = A9) selects

the starting column location. The value on input A10 determines

whether or not auto precharge is used. If auto precharge is

selected, the row being accessed will be precharged at the end

of the READ burst; if auto precharge is not selected, the row will

remain open for subsequent accesses.

DDR2 SDRAM also supports the AL feature, which allows a READ

or WRITE command to be issued prior to tRCD (MIN) by delaying the

actual registration of the READ/WRITE command to the internal

device by AL clock cycles.

READ OPERATION

READ bursts are initiated with a READ command. The starting

column and bank addresses are provided with the READ

command, and auto precharge is either enabled or disabled for

that burst access. If auto precharge is enabled, the row being

accessed is automatically precharged at the completion of the

burst. If auto precharge is disabled, the row will be left open after

the completion of the burst.

During READ bursts, the valid data-out element from the starting

column address will be available READ latency (RL) clocks later.

RL is deﬁ ned as the sum of AL and CL; RL = AL + CL. The value

for AL and CL are programmable via the MR and EMR commands,

respectively. Each subsequent data-out element will be valid

nominally at the next positive or negative clock edge (at the next

crossing of CK and CK#).

DQS/DQS# is driven by the DDR2 SDRAM along with output data.

The initial LOW state on DQS and HIGH state on DQS# is known

as the read preamble (tRPRE). The LOW state on DQS and HIGH

state on DQS# coincident with the last data-out element is known

as the read postamble (tRPST).

Upon completion of a burst, assuming no other commands have

been initiated, the DQ will go High-Z.

Data from any READ burst may be concatenated with data from

a subsequent READ command to provide a continuous ﬂ ow of

data. The ﬁ rst data element from the new burst follows the last

element of a completed burst. The new READ command should

be issued x cycles after the ﬁ rst READ command, where x equals

BL / 2 cycles.

DDR2 SDRAM does not allow interrupting or truncating of any

READ burst using BL = 4 operations. Once the BL = 4 READ

command is registered, it must be allowed to complete the entire

READ burst. However, a READ (with auto precharge disabled)

using BL = 8 operation may be interrupted and truncated only by

another READ burst as long as the interruption occurs on a 4-bit

boundary due to the 4n prefetch architecture of DDR2 SDRAM.

Data from any READ burst must be completed before a subsequent

WRITE burst is allowed.

FIGURE 11 – READ COMMAND

Col

Bank

ENABLE

DISABLE

A10

DON’T CARE

CK#

CS#

RAS#

CAS#

WE#

CKE

ADDRESS

BANK ADDRESS

UTO PRECHARGE

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WRITE COMMAND

The WRITE command is used to initiate a burst write access to an

active row. The value on the BA2–BA0 inputs selects the bank,

and the address provided on inputs A0–9 selects the starting

column location. The value on input A10 determines whether or

not auto precharge is used. If auto precharge is selected, the

row being accessed will be precharged at the end of the WRITE

burst; if auto precharge is not selected, the row will remain open

for subsequent accesses.

DDR2 SDRAM also supports the AL feature, which allows a READ

or WRITE command to be issued prior to tRCD (MIN) by delaying the

actual registration of the READ/WRITE command to the internal

device by AL clock cycles.

Input data appearing on the DQ is written to the memory array

subject to the DM input logic level appearing coincident with the

data. If a given DM signal is registered LOW, the corresponding

data will be written to memory; if the DM signal is registered HIGH,

the corresponding data inputs will be ignored, and a WRITE will

not be executed to that byte/column location.

WRITE operation

WRITE bursts are initiated with a WRITE command, as shown in

Figure 12. DDR2 SDRAM uses WL equal to RL minus one clock

cycle [WL = RL - 1CK]. The starting column and bank addresses

are provided with the WRITE command, and auto precharge is

either enabled or disabled for that access. If auto precharge is

enabled, the row being accessed is precharged at the completion

of the burst.

During WRITE bursts, the first valid data-in element will be

registered on the ﬁ rst rising edge of DQS following the WRITE

command, and subsequent data elements will be registered on

successive edges of DQS. The LOW state on DQS between the

WRITE command and the ﬁ rst rising edge is known as the write

preamble; the LOW state on DQS following the last data-in element

is known as the write postamble.

The time between the WRITE command and the ﬁ rst rising DQS

edge is WL ± tDQSS. Subsequent DQS positive rising edges are

timed, relative to the associated clock edge, as ± tDQSS. tDQSS is

speciﬁ ed with a relatively wide range (25 percent of one clock

cycle). All of the WRITE diagrams show the nominal case, and

where the two extreme cases (tDQSS [MIN] and tDQSS [MAX]) might

not be intuitive, they have also been included. Upon completion of

a burst, assuming no other commands have been initiated, the DQ

will remain High-Z and any additional input data will be ignored.

Data for any WRITE burst may be concatenated with a subsequent

WRITE command to provide continuous ﬂ ow of input data. The ﬁ rst

data element from the new burst is applied after the last element

of a completed burst. The new WRITE command should be issued

x cycles after the ﬁ rst WRITE command, where x equals BL/2.

DDR2 SDRAM supports concurrent auto precharge options, as

shown in Table 4.

DDR2 SDRAM does not allow interrupting or truncating any WRITE

burst using BL = 4 operation. Once the BL = 4 WRITE command is

registered, it must be allowed to complete the entire WRITE burst

cycle. However, a WRITE (with auto precharge disabled) using BL

= 8 operation might be interrupted and truncated ONLY by another

WRITE burst as long as the interruption occurs on a 4-bit boundary,

due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst

BL = 8 operations may not to be interrupted or truncated with any

command except another WRITE command.

Data for any WRITE burst may be followed by a subsequent READ

command. The number of clock cycles required to meet tWTR is

either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst

may be followed by a subsequent PRECHARGE command. tWR

must be met. tWR starts at the end of the data burst, regardless of

the data mask condition.

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FIGURE 12 – WRITE COMMAND

HIGH

EN AP

DIS AP

A10

DON’T CARE

CK#

CS#

RAS#

CAS#

WE#

CKE

ADDRESS

BANK ADDRESS

NOTE: CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge.

TABLE 4 – WRITE USING CONCURRENT AUTO PRECHARGE

From Command (Bank n) To Command (Bank m)Minimum Delay

(With Concurrent Auto

Precharge) Units

WRITE with Auto Precharge

READ OR READ w/AP (CL-1) + (BL/2) + tWTR tCK

WRITE or WRITE w/AP (BL/2) tCK

PRECHARGE or ACTIVATE 1t

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PRECHARGE COMMAND

The PRECHARGE command, illustrated in Figure 13, is used

to deactivate the open row in a particular bank or the open row

in all banks. The bank(s) will be available for a subsequent row

activation a speciﬁ ed time (tRP

) after the PRECHARGE command

is issued, except in the case of concurrent auto precharge, where

a READ or WRITE command to a different bank is allowed as long

as it does not interrupt the data transfer in the current bank and

does not violate any other timing parameters. Once a bank has

been precharged, it is in the idle state and must be activated prior

to any READ or WRITE commands being issued to that bank. A

PRECHARGE command is allowed if there is no open row in that

bank (idle state) or if the previously open row is already in the

process of precharging. However, the precharge period will be

determined by the last PRECHARGE command issued to the bank.

PRECHARGE OPERATION

Input A10 determines whether one or all banks are to be precharged,

and in the case where only one bank is to be precharged, inputs BA2–

BA0 select the bank. Otherwise BA2–BA0 are treated as “Don’t Care.”

When all banks are to be precharged, inputs BA2–BA0 are treated

as “Don’t Care.” Once a bank has been precharged, it is in the

idle state and must be activated prior to any READ or WRITE

commands being issued to that bank. tRPA timing applies when the

PRECHARGE (ALL) command is issued, regardless of the number

of banks already open or closed. If a single-bank PRECHARGE

command is issued, tRP timing applies. tRPA (MIN) applies to all

8-bank DDR2 devices.

SELF REFRESH COMMAND*

The SELF REFRESH command can be used to retain data in the

DDR2 SDRAM, even if the rest of the system is powered down.

When in the self refresh mode, the DDR2 SDRAM retains data

without external clocking. All power supply inputs (including VREF)

must be maintained at valid levels upon entry/exit and during SELF

REFRESH operation.

The SELF REFRESH command is initiated like a REFRESH

command except CKE is LOW. The DLL is automatically disabled

upon entering self refresh and is automatically enabled upon exiting

self refresh (200 clock cycles must then occur before a READ

command can be issued). The differential clock should remain

stable and meet tCKE speciﬁ cations at least 1 x tCK after entering

self refresh mode. All command and address input signals except

CKE are “Don’t Care” during self refresh.

The procedure for exiting self refresh requires a sequence of

commands. First, the differential clock must be stable and meet

tCK speciﬁ cations at least 1 x tCK prior to CKE going back HIGH.

Once CKE is HIGH (tCLE(MIN) has been satisﬁ ed with four clock

registrations), the DDR2 SDRAM must have NOP or DESELECT

commands issued for tXSNR because time is required for the

completion of any internal refresh in progress. A simple algorithm

for meeting both refresh and DLL requirements is to apply NOP

or DESELECT commands for 200 clock cycles before applying

any other command.

*NOTE: Self refresh not available at military temperature above 95°C.

BA0 - BA2

HIGH

ALL BANKS

ONE BANK

DON’T CARE

CS#

WE#

CAS#

RAS#

CKE

A10

DDRESS

CK#

FIGURE 13 – PRECHARGE COMMAND

NOTE: BA = bank address (if A10 is LOW; otherwise "Don't Care").

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ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min Max Unit Notes

VCC Voltage on VCC pin relative to VSS -1.0 2.3 V 1

VCCQ Voltage on VCCQ pin relative to VSS -0.5 2.3 V 1, 2

VIN, VOUT Voltage on any pin relative to VSS -0.5 2.3 V 3

TSTG Storage temperature -55 125 °C

ILInput leakage current; Any input 0V<VIN<VCC; ; Other pins not under test = 0V -25 25 A

IOZ Output leakage current; 0V<VOUT<VCCQ; DQs and ODT are disabled -5 5 A

IVREF VREF leakage current; VREF = Valid VREF level -10 10 A

NOTES:

1. VCC and VCCQ must be within 300mV of each other at all times; this is not required when power

is ramping down.

2. VREF  0.6 x VCCQ; however, VREF may be  VCCQ provided that VREF  300mV.

3. Voltage on any I/O may not exceed voltage on VCCQ.

Stresses greater than those listed may cause permanent damage to the device. This is a stress

rating only, and functional operation of the device at these or any other conditions outside those

indicated in the operational sections of this speciﬁ cation is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

DC OPERATING CONDITIONS

All voltages referenced to VSS

Parameter Symbol Min Typical Max Unit Notes

Supply voltage VCC 1 .7 1 .8 1 .9 V 1, 5

I/O Supply voltage VCCQ 1 .7 1 .8 1 .9 V 4, 5

I/O Reference voltage VREF 0.49 x VCCQ 0.50 x VCCQ 0.51 x VCCQ V2

I/O Termination voltage VTT VREF - 0.04 VREF VREF + 0.04 V 3

Operating Junction Temp. (Mil.) TJ-55 +125 °C

Operating Junction Temp. (Ind.) TJ-40 +85 °C

Operating Junction Temp. (Com.) TJ0 +70 °C

NOTES:

1. VCC and VCCQ must track each other. VCC and VCCQ are tied on this device.

2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ±1 percent of the DC value. Peak-to-peak AC noise

on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.

3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF

4. VCCQ tracks with VCC

5. VSSQ = VSS

INPUT/OUTPUT CAPACITANCE

TA = 25°C, f = 1MHz

Parameter Symbol Max Unit

Input capacitance (A0 - A12, BA0 - BA2 ,CS#, RAS#, CAS#, WE#, CKE, ODT) CIN1 24 pF

Input capacitance CK, CK# CIN2 9.5 pF

Input capacitance DM CIN3 10.5 pF

I/O capacitance DQ0 - 71, DQS, DQS# COUT 10.5 pF

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BGA THERMAL

Junction to Board Matrix (JB)

11.23 10.34 9.86 9.55 9.37

10.42 13.91 13.09 12.59 12.32

9.96 13.07 16.66 15.87 15.46

9.65 12.56 15.85 19.51 18.87

9.46 12.27 15.40 18.80 22.71

Junction to Case Matrix (JC)

16.53 13.70 11.26 9.01 6.92

13.76 15.25 12.41 9.87 7.56

11.31 12.38 13.84 10.91 8.33

9.04 9.85 10.89 12.26 9.29

6.94 7.53 8.73 9.24 10.59

SIMULATION CONDITIONS AND NOTES:

The JEDEC JESD51 speciﬁ cations are used as the default modeling environment and boundary conditions. Using still air, horizontal mounting and the 2s2p board. Published material properties are used as input

to derive the thermal characteristics of the module. Your application conditions will most likely differ from the JESD51 2s2p board deﬁ nition speciﬁ cations; therefore, Mercury Systems recommends a customized

evaluation of thermal resistances based on the actual conditions in thermally-challenged situations. Delphi models are available for most products upon request. Refer to Mercury Systems Application Note AN0061

for matrix use.

INPUT DC LOGIC LEVEL

All voltages referenced to VSS

Parameter Symbol Min Max Unit

Input High (Logic 1) Voltage VIH(DC) VREF + 0.1 25 VCCQ + 0.300 V

Input Low (Logic 0) Voltage VIL(DC) -0.300 VREF - 0.125 V

INPUT AC LOGIC LEVEL

All voltages referenced to VSS

Parameter Symbol Min Max Unit

AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533 VIH(AC) VREF + 0.250 — V

AC Input High (Logic 1) Voltage DDR2-667 VIH(AC) VREF + 0.200 — V

AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 VIL(AC) — VREF - 0.250 V

AC Input Low (Logic 0) Voltage DDR2-667 VIL(AC) — VREF - 0.200 V

ODT DC ELECTRICAL CHARACTERISTICS

All voltages referenced to VSS

Parameter Symbol Min Nom Max Unit Notes

RTT effective impedance value for 75 setting EMR (A6, A2) = 0, 1 RTT1(EFF) 52 75 97 1

RTT effective impedance value for 150 setting EMR (A6, A2) = 1, 0 RTT2(EFF) 105 150 195 1

RTT effective impedance value for 50 setting EMR (A6, A2) = 1, 1 RTT3(EFF) 35 50 65 1

Deviation of VM with respect to VCCQ/2 VM -6 6 % 2

NOTE: 1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL (AC) to the ball being tested, and then measuring current, I(VIH(AC)), and I(VIL(AC)), respectively.

2. Measure voltage (VM) at tested ball with no load

VM = (2 x VM - 1) x 100

VCC

RTT(EFF) = VIH(AC) - VIL(AC)

I(VIH(AC)) - I(VIL(AC))

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DDR2 ICC SPECIFICATIONS AND CONDITIONS

Symbol Proposed Conditions 667

CL6 533

CL5 400

CL4 Units

ICC0

Operating one bank active-precharge current;

tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data bus inputs are SWITCHING

675 575 575 mA

ICC1

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W

800 675 675 mA

ICC2P

Precharge power-down current;

All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

55 55 55 mA

ICC2Q

Precharge quiet standby current;

All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data

bus inputs are FLOATING

325 225 200 mA

ICC2N

Precharge standby current;

All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

350 300 250 mA

ICC3P

Active power-down current;

All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0 200 175 150 mA

Slow PDN Exit MRS(12) = 1 50 50 50 mA

ICC3N

Active standby current;

All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

375 275 250 mA

ICC4W

Operating burst write current;

All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC);

CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

1,250 950 800 mA

ICC4R

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC),

tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data

pattern is same as IDAD6W

1,375 975 900 mA

ICC5

Burst auto refresh current;

tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

1,400 1,300 1,250 mA

ICC6

Self refresh current;

CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs

are FLOATING; Data bus inputs are FLOATING

Normal 45 45 45 mA

ICC7

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC),

tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs

are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for detailed timing

conditions

1,975 1,775 1,775 mA

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AC TIMING PARAMETERS

Parameter Symbol 667Mbs CL6 533Mbs CL5 400Mbs CL4 Unit

Min Max Min Max Min Max

Clock

Clock cycle time

CL=6 tCK(6) 3,000 8,000

CL=5 tCK(5) 3,000 8,000 3,750 8,000 5,000 8,000 ps

CL=4 tCK(6) 5,000 8,000 5,000 8,000 5,000 8,000 ps

CK high-level width tCH 0.48 0.52 0.48 0.52 0.48 0.52 tCK

CK low-level width tCL 0.48 0.52 0.48 0.52 0.48 0.52 tCK

Half clock period tHP MIN (tCH, tCL) MIN (tCH, tCL) MIN (tCH, tCL)ps

Clock (absolute)

Absolute tCK tCKabs

tCKAVG

(MIN)+ tJITPER

(MIN)

tCKAVG

(MAX)+ tJITPER

(MAX)

tCKAVG

(MIN)+ tJITPER

(MIN)

tCKAVG

(MAX)+ tJITPER

(MAX)

tCKAVG

(MIN)+ tJITPER

(MIN)

tCKAVG

(MAX)+ tJITPER

(MAX)

Absolute CK high-level width tCHabs

tCKAVG

(MIN)* tCHAVG

(MIN)+ tJITDTY

(MIN)

tCKAVG

(MAX)*

tCHAVG

(MAX)+ tJITDTY

(MAX)

tCKAVG

(MIN)* tCHAVG

(MIN)+ tJITDTY

(MIN)

tCKAVG

(MAX)*

tCHAVG

(MAX)+ tJITDTY

(MAX)

tCKAVG

(MIN)* tCHAVG

(MIN)+ tJITDTY

(MIN)

tCKAVG

(MAX)* tCHAVG

(MAX)+ tJITDTY

(MAX)

Absolute CK low-level width tCLabs

tCKAVG

(MIN)*

tCLAVG

(MIN)+ tJITDTY

(MIN)

tCKAVG

(MAX)*

tCLAVG

(MAX)+ tJITDTY

(MAX)

tCKAVG

(MIN)*

tCLAVG

(MIN)+ tJITDTY

(MIN)

tCKAVG

(MAX)*

tCLAVG

(MAX)+ tJITDTY

(MAX)

tCKAVG

(MIN)*

tCLAVG

(MIN)+ tJITDTY

(MIN)

tCKAVG

(MAX)*

tCLAVG

(MAX)+ tJITDTY

(MAX)

Clock Jitter

Clock jitter - period tJITPER -125 125 -125 125 -125 125 ps

Clock jitter - half period tJITDUTY -125 125 -125 125 -125 125 ps

Clock jitter - cycle to cycle tJITCC 250 250 250 ps

Cumulative jitter error, 2 cycles tERR2per -175 175 -175 175 -175 175 ps

Cumulative jitter error, 3 cycles tERR3per -225 225 -225 225 -225 225 ps

Cumulative jitter error, 4 cycles tERR4per -250 250 -250 250 -250 250 ps

Cumulative jitter error, 5 cycles tERR5per -250 250 -250 250 -250 250 ps

Cumulative jitter error, 6-10 cycles tERR6-10per -350 350 -350 350 -350 350 ps

Cumulative jitter error, 11-50 cycles tERR11-50per -450 450 -450 450 -450 450 ps

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AC TIMING PARAMETERS (continued)

Parameter Symbol 667Mbs CL6 533Mbs CL5 400Mbs CL4 Unit

Min Max Min Max Min Max

Data

DQ hold skew factor tQHS - 400 - 400 - 450 ps

DQ output access time from CK/CK# tAC -100 1,250 -100 1,350 -100 1,350 ps

Data-out high impedance window from CK/CK# tHZ tAC(MAX) tAC(MAX) tAC(MAX) ps

DQS Low-Z window from CK/CK# tLZ1tAC(MN) tAC(MAX) tAC(MN) tAC(MAX) tAC(MN) tAC(MAX) ps

DQ Low-Z window from CK/CK# tLZ22*tAC(MN) tAC(MAX) 2*tAC(MN) tAC(MAX) 2*tAC(MN) tAC(MAX) ps

DQ and DM input setup time relative to DQS

tDSa 400 400 400 ps

tDHa 350 350 400 ps

tDSb 100 100 150 ps

tDHb 225 225 275 ps

DQ and DM input pulse width (for each input) tDIPW 0.35 0.35 0.35 ps

Data hold skew factor tQHS 400 400 450 ps

DQ-DQS hold, DQS to ﬁ rst DQ to go nonvalid, per

access tQH tHP - tQHS tHP - tQHS tHP - tQHS ps

Data valid output window (DVW) tDVW tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns

Data Strobe

DQS input high pulse width tDQSH 0.35*tCK 0.35*tCK 0.35*tCK tCK

DQS input low pulse width tDQSL 0.35*tCK 0.35*tCK 0.35*tCK tCK

DQS output access time fromCK/CK# tDQSCK -100 1,250 -100 1,350 -100 1,350 ps

DQS falling edge to CK rising - setup time tDSS 0.2*tCK 0.2*tCK 0.2*tCK tCK

DQS falling edge from CK rising - hold time tDSH 0.2*tCK 0.2*tCK 0.2*tCK tCK

DQS-DQ skew, DOS to last DQ valid, per group, per

access tDQSQ 240 300 350 ps

DQS read preamble tRPRE 0.9*tCK 1.1*tCK 0.9*tCK 1.1*tCK 0.9*tCK 1.1*tCK tCK

DQS read postamble tRPST 0.4*tCK 0.6*tCK 0.4*tCK 0.6*tCK 0.4*tCK 0.6*tCK tCK

DQS write preamble setup time tWPRES 000ps

DQS write preamble tWPRE 0.35*tCK 0.25*tCK 0.25 tCK

DQS write postamble tWPST 0.4*tCK 0.6*tCK 0.4*tCK 0.6*tCK 0.4*tCK 0.6*tCK tCK

Positive DQS latching edge to associated clock edge tDQSS -0.25*tCK 0.25*tCK -0.25*tCK 0.25*tCK -0.25*tCK 0.25*tCK tCK

Write command to ﬁ rst DQS latching transition WL-TDQSS WL+TDQSS WL-TDQSS WL+TDQSS WL-TDQSS WL+TDQSS tCK

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AC TIMING PARAMETERS (continued)

Parameter Symbol 667Mbs CL6 533Mbs CL5 400Mbs CL4 Unit

Min Max Min Max Min Max

Command and Address

Address and control input pulse width for each input tIPW 0.6 0.6 0.6 tCK

Address and control input setup time tISa 400 500 600 ps

tISb 200 250 350 ps

Address and control input hold time tIHa 400 500 600 ps

tIHb 275 375 475 ps

CAS# to CAS# command delay tCCD 222t

ACTIVE to ACTIVE (same bank) command tRC 55 55 55 ns

ACTIVE bank a to ACTIVE bank b command tRRD 10 10 10 ns

ACTIVE to READ or WRITE delay tRCD 15 15 15 ns

Four Bank Activate period tFAW 50 50 50 ns

ACTIVE to PRECHARGE command tRAS 40 70,000 40 70,000 40 70,000 ns

Internal READ to precharge command delay tRTP 7.5 7.5 7.5 ns

Write recovery time tWR 15 15 15 ns

Auto precharge write recovery + precharge time tDAL tWR + tRP tWR + tRP tWR + tRP ns

Internal WRITE to READ command delay tWTR 7.5 7.5 10 ns

PRECHARGE command period tRP 15 15 15 ns

PRECHARGE ALL command period tRPA 15 15 15 ns

LOAD MODE command cycle time tMRD 222t

Refresh

CKE low to CK, CK# uncertainty tDELAY tIS +tIH + tCK tIS +tIH + tCK tIS +tIH + tCK ns

REFRESH to Active or Refresh to Refresh command

interval tRFC 195 70,000 195 70,000 195 70,000 ns

Average periodic refresh interval (commercial and

industrial) tREFI 7.8 7.8 7.8 s

Average periodic refresh interval

(military 85 to 95°C junction) tRIFIM 3.9 3.9 3.9 s

Average periodic refresh interval

(military 95 to 125°C junction) tREFIM 1.95 1.95 1.95 s

Exit self refresh to non-READ command tXSNR tRFC(MIN) + 10 tRFC(MIN) + 10 tRFC(MIN) + 10 ns

Exit self refresh to READ tXSRD 200 200 200 tCK

Exit self refresh timing reference tlSXR tIS tIS tIS ps

ODT

ODT turn-on delay tAOND 222222t

ODT turn-on tAON tAC(MIN) tAC(MAX) + 1000 tAC(MIN) tAC(MAX) + 1000 tAC(MIN) tAC(MAX) + 1000 ps

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC(MIN) tAC(MAX) + 600 tAC(MIN) tAC(MAX) + 600 tAC(MIN) tAC(MAX) + 600 ps

ODT turn-on (power-down mode) tAONPD tAC(MIN) +

2000

2 x tCK +

tAC(MAX) + 1000

tAC(MIN) +

2000

2 x tCK +

tAC(MAX) + 1000

tAC(MIN) +

2000

2 x tCK +

tAC(MAX) + 1000 ps

ODT turn-off (power-down mode) tAOFPD tAC(MIN) +

2000

2 x tCK +

tAC(MAX) + 1000

tAC(MIN) +

2000

2 x tCK +

tAC(MAX) + 1000

tAC(MIN) +

2000

2 x tCK +

tAC(MAX) + 1000 ps

ODT to power-down entry latency tANPD 333t

ODT power-down exit latency tAXPD 888t

ODT enable from MRS command tMOD 12 12 12 ns

Power-Down

Exit active power-down to READ command,

MR[bit12=0] tXARD 222t

Exit active power-down to READ command,

MR[bit12=1] tXARDS 7-AL 6-AL 6-AL tCK

Exit precharge power-down to any non-READ

command tXP 222t

CKE minimum high/low time tCKE 333t

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11 10 9 8 7 6 5 4 3 2 1

208 x Ø 0.60 (0.024) NOM

1.0 (0.039)NOM

10.0 (0.394) NOM

16.10 (0.634) MAX

22.10 (0.870) MAX

18.0 (0.709) NOM

1.0 (0.039) NOM

4.57 (0.180) MAX

0.50

(0.020)

NOM

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

BOTTOM VIEW

FIGURE 14 – W3H128M72E-XSBX PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY (PBGA)

Pads are Solder Mask Deﬁ ned (SMD), pad opening is 0.48mm

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W3H128M72E-XSBX / W3H128M72E-XNBX

FIGURE 15 – W3H128M72E-XNBX PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY LOW PROFILE (PBGA)

11 10 9 8 7 6 5 4 3 2 1

208 x Ø 0.60 (0.024) NOM

1.0 (0.039)NOM

10.0 (0.394) NOM

16.10 (0.634) MAX

22.10 (0.870) MAX

18.0 (0.709) NOM

1.0 (0.039) NOM

3.94 (0.155) MAX

0.50

(0.020)

NOM

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

BOTTOM VIEW

Pads are Solder Mask Deﬁ ned (SMD), pad opening is 0.48mm

Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com 4163.12E-0716-ss-W3H128M72E-XSBX / XNBX

W3H128M72E-XSBX / W3H128M72E-XNBX

ORDERING INFORMATION

MERCURY SYSTEMS

DDR2 SDRAM

CONFIGURATION, 128M x 72

1.8V POWER SUPPLY

OPTIONS*

Blank = 0 ohm termination on CK\CK#

2 = 20 ohm termination on CK\CK#

DATA RATE (Mbs)

400 = 400Mb/s

533 = 533Mb/s

667 = 667Mb/s

PACKAGE:

SB = 4.57 mm package (Fig. 14)

NB = 3.94 mm package (Fig. 15)

DEVICE GRADE:

M = Military -55°C to +125°C

I = In dus tri al -40°C to +85°C

C = Com mer cial 0°C to +70°C

W 3H 128M 72 E X - XXX XX X

* Other termination values may be available, contact factory for options.

Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com 4163.12E-0716-ss-W3H128M72E-XSBX / XNBX

W3H128M72E-XSBX / W3H128M72E-XNBX

Document Title

1GB – 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

Revision History

Rev # History Release Date Status

Rev 0 Initial Release May 2008 Advanced

Rev 1 Changes (Pg. 1, 2, 22, 33)

1.1 Weight 4 grams max

1.2 Changed A0-12 to A0-13

1.3 Added input/output capacitance

1.4 Added BGA thermal resistance

September 2008 Advanced

Rev 2 Change (Pg. 1)

2.1 Change SPACE SAVINGS to space savings

October 2008 Preliminary

Rev 3 Change (Pg. 24)

3.1 Reduce DDR2 ICC7

• CL6 from (1,975 to 1,580) mA

• CL5 from (1,775 to 1,420) mA

• CL4 from (1,775 to 1,420) mA

October 2008 Preliminary

Rev 4 Change (Pg. 1, 5, 6, 19, 22, 23, 30)

4.1 Remove "P" from FBGA, take out "Actual Size" off of Figure 1

4.2 Remove VCCQ; and I/O + core; VCCQ is common to VCC in VCC box

4.3 Change page 8 to page 7 in initialization paragraph

4.4 Change tWT to tWT

4.5 In BGA thermal resistance, change note to read - to obtain the junction

temperature increase, multiply the thermal resistance by the power dissipated

in each die in the MCP

4.6 In DC operating conditions add "and" to note 1

4.7 Put "/" in between Mbs to read Mb/s

4.8 Change data sheet to ﬁ nal

December 2008 Final

Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com 4163.12E-0716-ss-W3H128M72E-XSBX / XNBX

W3H128M72E-XSBX / W3H128M72E-XNBX

Document Title

1GB – 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

Revision History Continued

Rev # History Release Date Status

Rev 5 Changes (Pg. 1)

5.1 Change "This product is under development, is not fully qualiﬁ ed or

characterized and is subject to change without notice

5.2 Add thinner "NB" version of part is under development. Only difference

between "NB" and "SB" is thickness. "SB" = 4.65mm (0.283) max and

"NB" = 3.97mm (0.156) max; a difference of .68mm (0.027) max

March 2009 Final

Rev 6 Changes (Pg. 24, 26)

6.1 Change ICC2P to 55mA on all speed grades

6.2 Change ICC6 to 45mA on all speed grades

6.3 Change ICC7 to 1,775mA on "400 and 533" speed grades and 1,975mA

on 667 speed grade

6.4 Change tAC to -100ps min on all speed grades and 1,250ps max on 667

speed grade, 1,350ps on 400 and 533 speed grades

6.5 Change tDSA to 400ps on 533 speed grade

6.6 Change tDQSCK to -100ps min on all speed grades and 1,250ps max on

667 speed grade, 1,350ps on 400 and 533 speed grades

September 2009 Final

Rev 7 Changes (Pg. 1, 29, 30)

7.1 Add weight of W3H128M72E-XNBX

7.2 Remove Thinner "NB" note

7.3 Add new W3H128M72E-XNBX package dimension

7.4 Change W3H128M72E-XSBX from 4.65 mm to 4.57 mm

7.5 Change length to 22.10 (0.870) max and width to 16.10 (0.634) max on

both "SB" and "NB" packages.

7.6 Remove note from BGA thermal resistance.

March 2010 Final

Rev 8 Changes (Pg. 25)

8.1 Correct tRFC = 195 ns for all speed grades

February 2011 Final

Rev 9 Changes (Pg. 1, 29, 30)

9.1 Add "1GB" to doc title

9.2 Add "Typical Applications" diagram

August 2011 Final

Rev 10 Changes (Pg. 26-28)

10.1 Fix typos

January 2012 Final

Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com

Mercury Systems reserves the right to change products or speciﬁ cations without notice.

4163.12E-0716-ss-W3H128M72E-XSBX / XNBX

W3H128M72E-XSBX / W3H128M72E-XNBX

Document Title

1GB – 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

Revision History Continued

Rev # History Release Date Status

Rev 11 Changes (Pg. 1-3, 5-27)

11.1 Remove ±0.1V from Core Supply Voltage and I/O Supply Voltage

11.2 Remove numbers from CAS latency

11.3 Change note in Figure 2

11.4 Change note in Figure 3

11.5 Correct typos in Description

11.6 Update diagram in Figure 4

11.7 Update notes 3-16 for Figure 4

11.8 Correct typos on page 7; update diagram in Figure 5

11.9 Correct typos on page 8

11.10 Correct typos on page 9

11.11 Correct typos and update diagram in Figure 7 on page 10

11.12 Correct typos on page 11

11.13 Correct typos update diagram in Figure 8 on page 12

11.14 Correct typos update diagram in Figure 9 on page 13

11.15 Update Table 3 – Truth Table - DDR2 Commands

11.16 Correct typos on page 15, 16, and 17

11.17 Correct typo in Table 4

11.18 Correct typos on page 19

11.19 Update Absolute Maximum Ratings, DC Operating Conditions and

Input/Output Capacitance charts on page 20

11.20 Update BGA Thermal Resistance chart on page 21

11.21 Update DDR2 ICC Speciﬁ cations and Conditions chart on page 22

11.22 Delete subtitle from AC Timing Parameters chart on pages 23, 24 and

25; update Refresh values same chart

11.23 Update BGA Thermal Resistance chart on page 21

11.24 Add note to Figures 14 and 15

September 2012 Final

Rev 12 Changes (Pg. All)

12.1 Change document layout from Microsemi to Mercury Systems

July 2016 Final