CY14B104NA
4-Mbit (256K × 16) Automotive nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-54469 Rev. *H Revised January 12, 2017
4-Mbit (256K × 16) Automotive nvSRAM
Features
■25 ns and 45 ns access times
■Internally organized as 256K × 16
■Hands off automatic STORE on power-down with only a small
capacitor
■STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoS tore on power-down
■RECALL to SRAM initiated by software or power-up
■High reliability
❐Infinite read, write, and recall cycles
❐STORE cycles to QuantumTrap
• Automotive-A: 1,000K STORE cycles
• Automotive-E: 100K STORE cycles
■Dat a ret ention
❐Automotive-A: 20 years
❐Automotive-E: 1 year
■Automotive-A Temperature: –40 C to +85 C
❐Single 3 V +20, -10 Operation
■Automotive-E Temperature: –40 C to +125 C
❐Single 3.3 V + 0.3 V Operation
■Packages
❐48-ball fine-pitch ball grid array (FBGA)
❐44-pin thin small outline package (TSOP) Type II
■Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B104NA is a fast static RAM (SRAM), with a
non-volatile element in each memory cell. The memory is
organized as 256K words of 16-bits each. The embedded
nonvolatile elements incorporate QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while independent
non-volatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatil e elements (the
STORE operation) ta kes place automatically at power-down. On
power-up, da ta is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
Logic Block Diagram
CY14B104NA
Document Number: 001-54469 Rev. *H Page 2 of 25
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................4
Device Operation ..............................................................5
SRAM Read ................................................................5
SRAM Write .................................................................5
AutoStore Operation ....................................................5
Hardware STORE Operation ........................... ............5
Hardware RECALL (Power-Up) ..................................6
Software STORE .........................................................6
Software RECALL .......................................................6
Preventing AutoStore ..................................................8
Data Protection ............ ............................ ....................8
Maximum Ratings .............................................................9
Operating Range ..................... .. ............................ ............9
DC Electrical Characteristics ......................... .................9
Data Retention and Enduranc e .....................................1 0
Capacitance ....................................................................10
Thermal Resistance ........................................................10
AC Test Loads ........................ ............................ ............11
AC Test Conditions ............. ............................ ...............11
AC Switching Characterist ics .......... ... .. ........................12
Switching Waveforms ....................... ............................ .13
AutoStore/Power-Up RECALL .......................................16
Switching Waveforms –
AutoStore/Power-up RECALL .......................................16
Software Controlled STORE/RECALL Cycle ................17
Switching Waveforms –
Software Controlled STORE/RECALL Cycle ................17
Hardware STORE Cycle .................................................18
Switching Waveforms – Hardware STORE Cycle ........18
Truth Table For SRAM Operations ................................19
Ordering Information ......................................................20
Ordering Code Definitions .........................................20
Package Diagrams ..........................................................21
Acronyms ........................................................................23
Document Conventions ............. .. ... ............................ ...23
Units of Measure ..................... ... ... ............................23
Document History Page ...................................... ...........24
Sales, Solutions, and Legal Information ......................25
Worldwide Sales and Design Support .......................25
Products .................................................................... 25
PSoC®Solutions .......................................................25
Cypress Developer Community ...................... ... ........25
Technical Support .....................................................25
CY14B104NA
Document Number: 001-54469 Rev. *H Page 3 of 25
Pinouts Figure 1. 48-ball FBG A pinout
Figure 2. 44-pin TSOP II pinout
WE
V
CC
A
11
A
10
V
CAP
A
6
A
0
A
3
CE
DQ
10
DQ
8
DQ
9
A
4
A
5
DQ
13
DQ
12
DQ
14
DQ
15
V
SS
A
9
A
8
OE
V
SS
A
7
DQ
0
BHE
NC
A
17
A
2
A
1
BLE
V
CC
DQ
2
DQ
1
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
15
A
14
A
13
A
12
HSB
3
26
5
4
1
D
E
B
A
C
F
G
H
A
16
NC NC
DQ
11
(not to scale)
Top View
(× 16)
[1]
48-ball FBGA
V
SS
DQ
6
DQ
5
DQ
4
V
CC
A
13
DQ
3
A
12
DQ
2
DQ
1
DQ
0
BLE
A
9
CE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
11
A
10
A
14
BHE
OE
A
15
A
16
A
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22 23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44-pin TSOP II
Top View
(not to scale)
WE
DQ
7
A
0
V
SS
V
CC
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
V
CAP
(
×
16)
(× 16)
[3]
Notes
1. Address expansion for 8-Mbit. NC pin not connected to die.
2. Address expansion for 16-Mbit. NC pin not connected to die.
3. HSB pin is not available in 44-pin TSOP II (× 16) package.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 4 of 25
Pin Definitions
Pin Name I/O Type Description
A0–A17 Input Address inputs. Used to Select one of the 262,144 words of the nvSRAM.
DQ0–DQ15 Input/Output Bidirectional data I/O lines. Used as input or output lines depending on operation.
WE Input Write Enable input, Active LOW. When selected LOW, da ta on the I/O pins is written to the specific
address location.
CE Input Chip Enable input, Active LOW. When LOW , selects the chip. When HIGH, deselects the chip.
OE Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
BHE Input Byte High Enable, Active LOW. Controls DQ15–DQ8.
BLE Input Byte Low Enable, Active LOW. Controls DQ7–DQ0.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VCC Power supply Power supply inputs to the device.
HSB Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chi p it initiates a nonvo latile STORE operation. After each Hardware
and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high
current, and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection
optional).
VCAP Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power l oss to store data from SRAM to
non-volatile elements.
NC No connect No Connect. This pin is not conne cted to the die.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 5 of 25
Device Operation
The CY14B104NA nvSRAM is made up of two functional
components paired in the same physical cell. They are a SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B104NA supports infinite reads and writes similar to a
typical SRAM. In addition, it provides infinite RECALL operations
from the non-volatile cells. Refer to the Truth Table For SRAM
Operations on page 19 for a complete description of read and
write modes.
SRAM Read
The CY14B104NA pe rforms a read cycle when CE and OE are
LOW and WE and HSB are HIGH. The address specified on pins
A0–17 determines which of the 262,144 words of 16 bits each are
accessed. Byte enables (BH E, BLE) determine which bytes are
enabled to the output, in the case of 16-bit words. When the read
is initiated by an address transition, the o utputs are valid after a
delay of tAA (read cycle 1). If the read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (read
cycle 2). The data output repeatedly responds to address
changes within the t AA access time without the need for transi-
tions on any control inp ut pins. This remains valid until another
address change or until CE or OE is brought HIGH, or WE or
HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memo ry if the data is valid (tSD time) before
the end of a WE controlled write or before the end of an CE
controlled write. The Byte Enable inputs (BHE, BLE) determine
which bytes are written, in the ca se of 16-bi t words. It is re co m-
mended that OE be kept HIGH during the entire write cycle to
avoid data bus contention on common I/O lines. If OE is left LOW,
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
AutoS tore Operation
The CY14B104NA stores data to the nvSRAM using one of the
following three storage ope rations: Hardware STORE activated
by the HSB; Software STORE activated by an address
sequence; AutoStore on device power-down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B104 NA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If the capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 8. In case AutoStore is enabled without a
capacitor on VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the Store. This
corrupts the data stored in nvSRAM.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 9 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-RECALL, the MPU must be active or the
WE held inactive until the MPU comes out of reset.
To reduce unnecessary non-volatile stores, AutoStore and
hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 3. AutoSt ore Mo de
Hardware STORE Operation
The CY14B104NA provides the HSB pin to control and
acknowledge the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B104NA conditionally initiates a STORE
operation after tDELAY. An actual STORE cycle only begins if a
write to the SRAM has taken place since the last STORE or
RECALL cycle. The HSB pin also acts as an open drain driver
(internal 100 k weak pull-up resistor) that is internally driven
LOW to indicate a busy condition when the STORE (initiated by
any means) is in progress.
Note Af ter each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B104NA. But any SRAM read and write cycles
0.1 uF
VCC
10 kOhm
VCAP
WE VCAP
VSS
VCC
CY14B104NA
Document Number: 001-54469 Rev. *H Page 6 of 25
are inhibited until HSB is returned HIGH by MPU or other external
source.
During any STORE operation, regardless of how it is initiated,
the CY14B104NA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the nvSRAM memory access is inhibited for
tLZHSB time after HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC<V
SWITCH), an internal RECALL re quest is latched. When
VCC again exceeds the VSWITCH on power up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the non-volatile memory
by a software address sequence. The CY14B104NA software
STORE cycle is initiated by executing sequential CE or OE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
non-volatile data is first performed, followed by a program of the
non-volatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is d isabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the non-volatile memory to the SRAM
by a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
perform the following sequence of CE or OE controlled read
operations must be performed .
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initi ate RECALL cycle
Internally , RECALL is a two step procedure. First, the SRAM data
is cleared; then, the non-volatile information is transferred into
the SRAM cells. After t he tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 7 of 25
Table 1. Mode Selection
CE WE OE BHE, BLE A15–A0[4] Mode I/O Power
H X X X X Not selected Output high Z Standby
L H L L X Read SRAM Output data Active
L L X L X Write SRAM Input data Active
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output data
Output data
Output data
Output data
Output data
Output data
Active[5]
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output data
Output data
Output data
Output data
Output data
Output data
Active[6]
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
STORE
Output data
Output data
Output data
Output data
Output data
Output high Z
Active ICC2[6]
L H L X 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
RECALL
Output data
Output data
Output data
Output data
Output data
Output high Z
Active[6]
Notes
4. While there are 18 a ddress lines on the CY14B104NA, only 13 address lines (A14–A2) are used to control software modes. The remaining address lines are don’t care.
5. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
6. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 8 of 25
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read ope rations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disa ble sequence, the following sequence o f CE
or OE controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoSt ore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation . To initiate the
AutoStore enable sequence, the following sequence of CE or OE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power-down cycles.
The part comes from the factory with AutoStore enabled and
0x00 written in all cells.
Data Protection
The CY14B104NA protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and write operations. The low voltage condition is detected when
VCC < VSWITCH. If the CY14B104NA is in a write mode (both CE
and WE are LOW) at power-up, after a RECALL or STORE, the
write is inhibited until the SRAM is enabl ed after tLZHSB (HSB to
output active). This protects against inadvertent writes during
power-up or brown out conditions.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 9 of 25
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
At 150 C ambient temperature ........... ... ... ..... 1000 h
At 85 C ambient temperature ..................... 20 Years
At 125 C ambient temperature .......................1 Year
Ambient temperature
with power applied ................................... –55 C to +150 C
Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V
Voltage applied to outputs
in high Z state .......... .. ... ... ...................–0.5 V to VCC + 0.5 V
Input voltage ........................................–0.5 V to Vcc + 0.5 V
Transient voltage (< 20 ns)
on any pin to ground potential ............–2.0 V to VCC + 2.0 V
Package power dissipation capability
(TA = 25 °C) .................................................................1.0 W
Surface mount Pb soldering temperature
(3 Seconds) ...................... ... ............................ ........ +260 C
DC output current (1 output at a time , 1s duration) ....15 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Latch up current .....................................................> 200 mA
Operating Range
Range Ambient Temperature VCC
Automotive-A –40 C to +85 C 2.7 V to 3.6 V
Automotive-E –40 C to +125 C 3.0 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ [7] Max Unit
VCC Power supply Automotive-A 2.7 3.0 3.6 V
Automotive-E 3.0 3.3 3.6 V
ICC1 Average VCC current tRC = 25 ns Automotive-A – – 70 mA
tRC = 45 ns
V alues obtained without output
loads (IOUT = 0 mA)
Automotive-A – – 52 mA
Automotive-E – – 65 mA
ICC2 Average VCC current during
STORE All inputs don’t care,
VCC = Max
Average current for duration
tSTORE
Automotive-A – – 10 mA
Automotive-E – – 15 mA
ICC3 Average VCC current at
tRC = 200 ns, VCC(Typ), 25 °C All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA).
–35–mA
ICC4[8] Average VCAP current during
AutoStore cycle All inputs don’t care. Average
current for duration tSTORE Automotive-A – – 5 mA
Automotive-E – – 10 mA
ISB VCC standby current CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after
non-volatile cycle is complete.
Inputs are static. f = 0 MHz.
Automotive-A – – 5 mA
Automotive-E – – 10 mA
IIX[9] In pu t leakage curren t (e xce pt
HSB)
VCC = Max, VSS < VIN < VCC Automotive-A –1 – +1 A
Automotive-E –5 – +5 A
Input leakage current (for HSB)V
CC = Max, VSS < VIN < VCC Automotive-A –100 – +1 A
Automotive-E –100 – +5 A
IOZ Off-state output leakage current VCC = Max, VSS < VOUT < VCC,
CE or OE > VIH or
BHE/BLE > VIH or WE < VIL
Automotive-A –1 – +1 A
Automotive-E –5 – +5 A
Notes
7. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested.
8. This parameter is guaran teed by design but not tested.
9. The HSB pin has IOUT = –2 µA for VOH of 2.4 V when both active HIGH and LOW drivers are disabl ed. When they are enabled st andard VOH and VOL ar e valid. This
parameter is characterized but not tested.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 10 of 25
VIH Input HIGH voltage Automotive-A 2.0 – VCC + 0.5 V
Automotive-E 2.2 – VCC + 0.5 V
VIL Input LOW voltage Vss – 0.5 – 0.8 V
VOH Output HIGH voltage IOUT = –2 mA 2.4 – – V
VOL Output LOW voltage IOUT = 4 mA – – 0.4 V
VCAP[10] Storage capacitor Between VCAP pin and VSS, 5 V rated 61 68 180 F
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter Description Test Conditions Min Typ [7] Max Unit
Data Retention and Endurance
Over the Operating Range
Parameter Description Min Unit
DATARData retention Automotive-A 20 Years
Automotive-E 1
NVCNon-volatile STORE operations Automotive-A 1,000 K
Automotive-E 100
Capacitance
Parameter[11] Description Test Conditions Max Unit
CIN Input capacit ance (except BHE,
BLE and HSB)
TA = 25 C, f = 1 MHz, VCC = VCC(Typ) 7pF
Input capacitance (for BHE, BLE
and HSB)
8pF
COUT Output capacitance (except HSB) 7 pF
Output capacitance (for HSB) 8 pF
Thermal Resist ance
Parameter [11] Description Test Conditions 48-pin FBGA 44-pin TSOP II Unit
JA Thermal resistance
(junction to ambient) Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
46.09 43.3 C/W
JC Thermal resistance
(junction to case) 7.84 5.56 C/W
Notes
10.Min VCAP value guarante es that there is a sufficient charge availab l e to complete a successful AutoStore op eration. Max VCAP value guarantees that the capacitor
on VCAP is charged to a minimum voltage du ring a Power-Up RECALL cycle so that an immediate power-d own cycle can complete a successful AutoS tore. Theref ore
it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options.
11. These parameters are guaranteed by design but not tested.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 11 of 25
AC Test Conditions
Input pulse levels ..................................................0 V to 3 V
Input rise and fall times (10%–90%) ........................... < 3 ns
Input and output timing reference levels ...................... 1.5 V
AC Test Loads Figure 4. AC Te st Loads
3.0 V
OUTPUT
5 pF
R1
R2
789
3.0 V
OUTPUT
30 pF
R1
R2
789
for tristate specs
577 577
CY14B104NA
Document Number: 001-54469 Rev. *H Page 12 of 25
AC Switching Characteristics
Over the Operating Range
Parameters [12]
Description 25 ns 45 ns Unit
Cypress
Parameter Alt Parameter Min Max Min Max
SRAM Read Cycle
tACE tACS Chip enable access time – 25 – 45 ns
tRC[13] tRC Read cycle time 25 – 45 – ns
tAA[14] tAA Address access time – 25 – 45 ns
tDOE tOE Output enable to data valid – 12 –20 ns
tOHA[14] tOH Output hold after address change 3 – 3 – ns
tLZCE[15, 16] tLZ Chip enable to output active 3 – 3 – ns
tHZCE[15, 16] tHZ Chip disable to output inactive – 10 –15 ns
tLZOE[15, 16] tOLZ Output enable to output active 0 – 0 – ns
tHZOE[15, 16] tOHZ Output disable to output inactive –10–15 ns
tPU[15] tPA Chip enable to power active 0 – 0 – ns
tPD[15] tPS Chip disable to power standby – 25 –45 ns
tDBE –Byte enable to data valid – 12 – 20 ns
tLZBE[15] –Byte enable to output active 0 – 0 – ns
tHZBE[15] –Byte disable to output inactive – 10 – 15 ns
SRAM Write Cycle
tWC tWC Write cycle time 25 – 45 –ns
tPWE tWP Write pulse width 20 – 30 –ns
tSCE tCW Chip enable to end of write 20 – 30 –ns
tSD tDW Data setup to end of write 10 – 15 –ns
tHD tDH Data hold after end of write 0 – 0 – ns
tAW tAW Address setup to end of write 20 – 30 –ns
tSA tAS Address setup to start of write 0 – 0 – ns
tHA tWR Address hold after end of write 0 – 0 – ns
tHZWE[15, 16, 17] tWZ Write enable to output disable – 10 –15 ns
tLZWE[15, 16] tOW Output active after end of write 3 – 3 – ns
tBW –Byte enable to end of write 20 –30 –ns
Notes
12.Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 4 on page 11.
13.WE must be HIGH during SRAM read cycles.
14.Device is continuously selected with CE, OE and BHE / BLE LOW.
15.These parameters are guaranteed by design but not tested.
16.Measured ±200 mV from steady state output voltage.
17.If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 13 of 25
Switching WaveformsFigure 5. SRAM Read Cycle No. 1 (Address Controlled) [18, 19, 20]
Figure 6. SRAM R ea d Cycle No. 2 (CE and OE Controlled) [18, 20]
Address
Data Output
Address Valid
Previous Data Valid Output Data Valid
tRC
tAA
tOHA
Address ValidAddress
Data Output Output Data Valid
Standby Active
High Impedance
CE
OE
BHE, BLE
ICC
tHZCE
tRC
tACE
tAA
tLZCE
tDOE
tLZOE
tDBE
tLZBE
tPU tPD
tHZBE
tHZOE
Notes
18.WE must be HIGH during SRAM read cycles.
19.Device is continuously selected with CE, OE and BHE / BLE LOW.
20.HSB must remain HIG H during read and write cycles.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 14 of 25
Figure 7. SRAM Write Cycle No. 1 (WE Controlled) [21, 22, 23]
Switching Waveforms (continued)
Data Output
Data Input Input Data Valid
High Impedance
Address ValidAddress
Previous Data
tWC
tSCE tHA
tBW
tAW
tPWE
tSA
tSD tHD
tHZWE tLZWE
WE
BHE, BLE
CE
Notes
21.HSB must remain HIGH during read and write cycles.
22.If WE is LOW when CE goes LOW, the outputs remain in the hi gh impedance state.
23.CE or WE must be >VIH during address transitions.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 15 of 25
Figure 8. SRAM Write Cycle No. 2 (CE Controlled) [24, 25, 26]
Figure 9. SRAM Write Cycle No. 3 (BHE and BLE Controlled ) [24, 25, 26]
Switching Waveforms (continued)
Data Output
Data Input Input Data Valid
High Impedance
Address Valid
Address
tWC
tSD tHD
BHE, BLE
WE
CE
tSA tSCE tHA
tBW
tPWE
Data Output
Data Input Input Data Valid
High Impedance
Address ValidAddress
tWC
tSD tHD
BHE, BLE
WE
CE
tSCE
tSA tBW tHA
tAW
tPWE
Notes
24.If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
25.HSB must remain HIGH during read and write cycl es.
26.CE or WE must be >VIH during address transitions.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 16 of 25
AutoStore/Power-Up RECALL
Over the Operating Range
Parameter Description 25 ns 45 ns Unit
Min Max Min Max
tHRECALL [27] Power-Up RECALL duration –20 –20 ms
tSTORE [28] STORE cycle duration – 8 – 8 ms
tDELAY [29] Time allowed to complete SRAM write cycle –25 –25 ns
VSWITCH Low voltage trigger level Automotive-A –2.65 –2.65 V
Automotive-E – – – 2.95 V
tVCCRISE[30] VCC rise time 150 –150 –s
VHDIS[30] HSB output disable voltage –1.9 –1.9 V
tLZHSB[30] HSB to output active time – 5 – 5 s
tHHHD[30] HSB high active time –500 –500 ns
Switching Waveforms – AutoStore/Power-up RECALL
Figure 10. AutoStore or Power-Up RECALL [31]
VSWITCH
VHDIS
tVCCRISE tSTORE tSTORE
tHHHD
tHHHD
tDELAY
tDELAY
tLZHSB tLZHSB
tHRECALL
tHRECALL
HSB OUT
AutoStore
POWER-
UP
RECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write POWER
DOWN
AutoStore
Note Note
Note
Note
VCC
28 28
32
32
Notes
27.tHRECALL starts from the time VCC rises above VSWITCH.
28.If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place.
29.On a Hardware STO RE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
30.These parameters are guaranteed by design but not tested.
31.Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
32.During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 17 of 25
Software Controlled STORE/RECALL Cycle
Over the Operating Range
Parameter [3 3, 34] Description 25 ns 45 ns Unit
Min Max Min Max
tRC STORE/RECALL initiation cycle time 25 –45 –ns
tSA Address setup time 0 – 0 – ns
tCW Clock pulse width 20 –30 –ns
tHA Address hold time 0 – 0 – ns
tRECALL RECALL duration –200 –200 s
Switching Waveforms – Software Controlled STORE/RECALL Cycle
Figure 11. CE and OE Controlled Software ST ORE/RECALL Cycle [34]
Figure 12. AutoStore Enable/Disable Cycle [34]
tRC tRC
tSA tCW
tCW
tSA
tHA
tLZCE
tHZCE
tHA
tHA
tHA
tSTORE/tRECALL
tHHHD
tLZHSB
High Impedance
Address #1 Address #6Address
CE
OE
HSB (STORE only)
DQ (DATA)
RWI
tDELAY Note
35
tRC tRC
tSA tCW
tCW
tSA
tHA
tLZCE
tHZCE
tHA
tHA
tHA
tDELAY
Address #1 Address #6Address
CE
OE
DQ (DATA)
tSS
Note
RWI
35
Notes
33.The software sequence is clocked with CE controlled or OE controlled reads.
34.The six consecutive addresses must be read in the order listed in Table 1 on page 7. WE must be HIGH during all six consecutive cycles.
35.DQ output data at the sixth read may be invalid since the output is disabled at t DELAY time.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 18 of 25
Hardware STORE Cycle
Over the Operating Range
Parameter Description 25 ns 45 ns Unit
Min Max Min Max
tDHSB HSB to output active time when write latch not set –25 –25 ns
tPHSB Hardware STORE pulse width 15 –15 –ns
tSS [36, 37] Soft sequence processing time –100 –100 s
Switching Waveforms – Hardware STORE Cycle
Figure 13. Hardware STORE Cycle [38]
Figure 14. Soft Sequence Processing [36, 37]
tPHSB
tPHSB
tDELAY tDHSB
tDELAY
tSTORE
tHHHD
tLZHSB
Write latch set
Write latch not set
HSB (IN)
HSB (OUT)
DQ (Data Out)
RWI
HSB (IN)
HSB (OUT)
RWI
HSB pin is driven high to VCC
only by Internal
SRAM is disabled as long as HSB (IN) is driven low
.
HSB driver is disabled
tDHSB
100 kOhm resistor,
Address #1 Address #6 Address #1 Address #6
Soft Sequence
Command
tSS tSS
CE
Address
VCC
tSA tCW
Soft Sequence
Command
tCW
Notes
36.This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effect ively register command.
37.Commands such as STORE and RECALL lock out I/O until operation is complete which further increase s this time. See the specific command.
38.If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware STORE takes place.
CY14B104NA
Document Number: 001-54469 Rev. *H Page 19 of 25
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
CE WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/Power-down Standby
L X X H H High Z Output disabled Active
LHLLLData out (DQ
0–DQ15) Read Active
L H L H L Data out (DQ0–DQ7);
DQ8–DQ15 in High Z Read Active
L H L L H Data out (DQ8–DQ15);
DQ0–DQ7 in High Z Read Active
L H H L L High Z Output disabled Active
L H H H L High Z Output disabled Active
L H H L H High Z O utput disabled Active
LLXLLData in (DQ
0–DQ15) Write Active
LLXHLData in (DQ
0–DQ7);
DQ8–DQ15 in High Z Write Active
LLXLHData in (DQ
8–DQ15);
DQ0–DQ7 in High Z Write Active
CY14B104NA
Document Number: 001-54469 Rev. *H Page 20 of 25
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
25 CY14B104NA-ZS25XE 51-85087 44-pin TSOP II (Pb-free) Automotive-E
CY14B104NA-ZS25XET
45 CY14B104NA-BA45XE 51-85128 48-ball FBGA (Pb-free)
CY14B104NA-BA45XET
CY14B104NA-ZS45XE 51-85087 44-pin TSOP II (Pb-free)
CY14B104NA-ZS45XET
Option:
T - Tape and Reel
Blank - Std.
Speed:
25 - 25 ns
45 - 45 ns
Data Bus:
N - × 16 Density:
104 - 4 Mb
Voltage:
B - 3.0 V
Cypress
CY 14 B 104 N A - BA 45 X E T
nvSRAM
14 -
Package:
BA – 48-ball FBGA
X - Pb-free
Blank -
Sn Pb
Die Revision:
Blank - No Re v
A - 1st Rev
A - Automotive-A (
–40
C to 85
C
)
Temperature:
E - Automotive-E (
–40
C to 125
C
)
ZS – 44-pin TSOP II
CY14B104NA
Document Number: 001-54469 Rev. *H Page 21 of 25
Package Diagrams Figure 15. 48-ball FBGA (6 × 10 × 1.2 mm) Package Outline, 51-85128
51-85128 *G
CY14B104NA
Document Number: 001-54469 Rev. *H Page 22 of 25
Figure 16. 44-pin TSOP II Package Outline, 51-85087
Package Diagrams (continued)
51-85087 *E
CY14B104NA
Document Number: 001-54469 Rev. *H Page 23 of 25
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
EIA Electronic Industries Alliance
FBGA Fine-Pitch Ball Grid Array
HSB Hardware Store Busy
I/O Input/Output
nvSRAM nonvolatile Static Random Access Memory
OE Output Enable
RoHS Restriction of Hazardous Substances
RWI Read and Write Inhibited
SRAM Static Random Access Memory
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
Hz hertz
kHz kilohertz
kkilohm
MHz megahertz
Amicroampere
Fmicrofarad
smicrosecond
mA milliampere
ms millisecond
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
CY14B104NA
Document Number: 001-54469 Rev. *H Page 24 of 25
Document History Page
Document Title: CY14B104NA, 4-Mbit (256K × 16) Automotive nvSRAM
Document Number: 001-54469
Rev. ECN Orig. of
Change Submission
Date Description of Change
*F 5157487 GVCH 03/03/2016 Changed status from Preliminary to Final.
*G 5349257 GVCH 07/13/2016 Added 44-pin TSOP II package related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated Package Diagrams:
Added spec 51-85087 *E.
Updated to new te mplate.
*H 5583673 GVCH 01/12/2017 Updated Ordering Information:
Updated part numbers.
Updated to new te mplate.
Document Number: 001-54469 Rev. *H Revised January 12, 2017 Page 25 of 25
CY14B104NA
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