7 yo i rs | ANALOG N-304 DEVICES APPLICATION NOTE ONE TECHNOLOGY WAY e P.O. BOX 9106 NORWOOD, MASSACHUSETTS 02062-9106 617/329-4700 One-Chip Slide Rule Works with Logs, Antilogs for Real-Time Processing by Lew Counts, Charles Kitchin and Steve Sherman An analog computer IC multiplies and divides signals, takes powers, and also roots. A log-antilog section raises dynamic range during division. n analog divider circuit seems to promise Bers for nothing. Just divide any num- ber by zero and the result is infinity. But in theory, if numbers approaching zero are in the de- nominator, the divider must achieve infinite gain, and its input offset error must be smaller than the in- put signal. In practice, analog divider chips fail to achieve even the modest 100-to-1 dynamic range vital toa | wide-range circuit. A viable device calls for gains greater than 40 dB and input offset voltages under 100 nV. But all is not lost. The AD538 multifunction ICs | 1000-to-1 dynamic range surpasses the 50-to-1 limit of earlier one-chip dividers. Noise is held to only 25 uVreferenced to the inputover a 1000-Hz bandwidth, with its offset voltages under 100 V. A truly versatile analog computer on a chip, the _ 588 tackles one-quadrant multiplication and one- _ and two-quadrant division. It also calculates powers and roots of ratios. Like all analog computers, it runs ' in real time, making it the chip of choice when linear- izing signals from transducers. Reprinted from ELECTRONIC DESIGN May 2, 1985 Its basic transfer function: Vout = Vy (V2/Vx) makes the circuit simple to configure for a particular function. All that need be done is to connect specific pins andin some casesadd one or two external resistors. Depending on the application, one, several, or all sections of the chip can be called into play. The analog IC basically consists of an accurate 10-V/2-V reference and five precision op amps, all - with offset voltages that are laser-trimmed to under 100 nV (Fig. 1). But the chip is more than the sum of its parts. It is designed as a complete analog comput- er whose system performance is specified for both voltage and current inputs. Its low input and output offset voltages, excellent linearity, and modest noise levels all contribute to its wide dynamic range guaranteed from 1 mV to 10 V (80 dB). The users free access to the summing junctions of four of the chips op amps gives it much of its versa- tility. External input resistors can change the pre- trimmed offset or scaling voltages and allow multi- ple signals to be summed at each input terminal. The ICs power supply ranges from +4 to +18 V, letting COMPUTATIONAL PRODUCTS 6-3it run from standard split +15-V supplies, as well as from +12-V andeven +5-V units. The 2-V reference is particularly useful for driving the chip from +5-V sources. The op amps form three of the devices four major function blocks. The log ratio amplifier section har- nesses three of them; the log and antilog section, one; and the output current-to-voltage stage, the last. A logging operation The V, and Vx inputs connect directly to the log- ratio section. This block furnishes an output voltage proportional to the difference between the natural logarithms, Ln, of the input voltages Vz and Vx (Ln V,, ~Ln Vx). The transfer function between these in- puts and the sections output pin (B) is given by _ kT Vout = Ln q 1. The transfer function of the AD538 one-chip analog computer is Vour = Vy where k is Boltzmanns constant, T is the absolute Kelvin temperature, and q is the unit charge (1.60219 xX 107C). The log ratio section may be used on its own (to compress the ratio of two signals) by temperature- compensating and scaling its output. To do so, its out- put (B) is joined to the summing junction of the out- put amplifier (I;,,) through two external resistors. A 60-01% metal-film device is hooked in series with a 1-kQ temperature-compensating resistor with a tem- perature coefficient of +3500 ppm/C. For most applications, however, the log ratio sec- tion is linked to the input of the antilog section (pin Vy). That converts the signal from the logarithmic into the linear domain, according to the transfer function: Vout = Vy lve vt) where Vc is the voltage at pin C. This section, like the " Current- to-voltage a. output stage Antilog ciroult O>9 circuit (V,/V,) when M is between /s and 5. The flexibility of the transfer function allows the chip, which works in real time, to replace a microcomputer as well as several data converters. 6-4 COMPUTATIONAL PRODUCTS| DESIGN ENTRY Analog computer chip _ log ratio block, may be used alone in order to expand a signal. Combining the transfer functions of both sections by tying together the B and C outputs results in the equation: ( Tt x a x Ln Ve ) Vout = Vy e 4 kT Vx when Vz = Ve. This expression reduces to the multiplier-divider transfer function: V Vout = Wy ' Raising Vz/Vx to the Mth power with an external resistor results in the analog computer chips overall transfer function: Vout = Vy (V2/Vx) where 45 <M <5. In most applications the Vy input is used to set a convenient scale factor. The linear Vy input signal is multiplied by adding the log of the Vy input to the signal at C, which is already in the log domain. The chips third section, the output current-to-voltage converter, buffers and scales the output from the antilog block. Finally, the band-gap reference section supplies either +2 or +10 V, accurate to +0.5% witha tempco of 25 ppm/C. The 10-V reference is buffer- ed and available at the +10-V pin. The 2-V output is unbuffered. It is derived from the + 10-V pin by adding a resistive divider between the buffers out- put and its summing point input. Asa result, any load on the 2-V output changes the feedback circuit and thus the 10-V reference voltage as well. To buffer the 2-V output, it is simply tied to the 10-V output. Go forth and multiply Taking the chips sections singly or even in pairsonly hints at its overall power. The device is easily configured as a high-performance, one-quad- rant multiplier-divider (Fig. 1 again). As such, it handles only positive input voltages. Its transfer function: Vout = Vy (V2/Vx) ' works with three input variables. That is, the chip carries out three-input calculations simultaneously a task impossible with a conventional analog mul- tiplier or even with a digital one. Whats more, the job is performed by the 538 in real time. When two input variables and a fixed reference are specified, the chips dynamic range per- mits it to outclass such analog multipliers as the AD534. (The latter, though, performs four-quadrant multiplicationseach of its two inputs may be a plus or minus voltage.) In the circuit, if Vx is connected to either the 10- or the 2-V reference, a traditional one-quadrant analog multiplier results. (Vx, or any other input, may also be driven by a digital-to-analog converter, enabling the constant, or scaling, voltage, which establishes the output scale factor, to be set automatically or re- motely.) With Vx tied to 10 V, the transfer function becomes: Vout = (Vy) (Vz)/10 V. Typically, the circuit achieves a bandwidth of 400 kHz when Vx varies over a range of 100 mV to 10 V. Maximum error with both inputs swinging AD535J analog multiplier-divider 1% AD5388 analog computer 0.65% 0.5% v 10V 2. When used for division, the AD538 has a lower total error and a much wider denominator dynamic range than an analog multiplier-divider such as the AD535which has even been specially trimmed to serve as a divider. COMPUTATIONAL PRODUCTS 6-5from 0 to 10 V is + 0.5% of the reading. Employing an external scaling voltage and the offset trim resistor (R,) will halve the error. Merely switching the 10-V reference from Vx to Vy changes the circuit to a classical one-quadrant linear divider with 10-V scaling. Vx now serves as the denominator input terminal]. The transfer function is specified as follows: Vout = (10 V) (Vz)/(Vx) The voltage applied to Vz is divided by that applied to Vx. The internal trimming resistor reduces offset errors to less than 100 pV. The typical 3-dB bandwidth of the one-quadrant divider is 370 kHz for inputs between 1 and 10 V, dropping slowly to 200 kHz for 2-mV signals. Its 74-dB dynamic range (from a 2-mV noise threshold at the input to a 10-V output clipping level) is much To wider than that supplied by a conventional divider circuit using an analog multiplier. As for harmonic distortion, the circuits 10-V peak output is produced by a sine wave on the numerator input and 1 V on the denominator input. The second harmonic of the 10-V output is 70 dB below the fundamental. Appearances are deceiving The mathematics of multiplication and division makes multiplier circuits appear to have much lower input offset voltages than comparable divider cir- cuits. Multiplying numbers less than one yields a result smaller than either of the original multipli- cands. Multiplying the offset voltages at two differ- ent inputs, say 0.1 V each, produces an output offset voltage of 0.01 V. In addition, the product is generally divided by 10 (to increase dynamic range), further oS Output 25k AAA Vie 25k Antilog 3. By implementing the transfer function Vout = Vaum/Vaen, the AD538 multi- function chip handles two-quadrant division. Thus the numerator is capable of handling both positive and negative voltages. 6-6 COMPUTATIONAL PRODUCTSDESIGN ENTRY Analog computer chip cutting output offset error to 0.001 V. Obviously, in multiplier circuits, output offset voltages matter more than do input offset voltages because the former add directly to the multipliers output. Divisive factors In contrast, analog dividers usually run into dif- ficulties over input offset voltages. The gain of an analog divider must approach infinity as the denomi- nator moves closer to zero: Offset voltages or nonlinearities at the input are amplified by the Vacate/ V denominator ratio of the divider. As the denomi- nator voltage is reduced, input offset voltages in di- viders quickly become intolerable, in turn severely degrading the devices dynamic range. In multipliers, then, offsets are measured relative to full scale; in dividers, they must be gauged relative to the magnitude of the input signal. For any given 1.2 MHz ADS38 220 kHz 220 kHz 120 kHz ADS535 7 , 12 kHz 7 Not specified 7 4. The bandwidth and dynamic range of the AD538 in the circuit of Fig. 3 are significantly greater than those of a conventional multiplier-divider IC, the AD535, in the same application. accuracy, therefore, these offsets limit the minimum denominator voltage level. The chip overcomes most of its input offset prob- lems by employing high-quality op amps as input stages. These are quite different from the circuits found in the typical analog multiplier, such as the AD535, and the op amps hold offset errors under 100 nV. Asmalier total error The devices superiority is readily seen by directly comparing total error from each chip for given de- nominator voltages (Fig. 2). The total error for the 535, configured as a multiplier-divider, is not even specified for denominator voltages below 200 mV. At that point it is, in fact, 5%. Alternatively, the 538s total error is only 2.5% at a denominator voltage of 10 mVa level at which the typical multiplier- divider is unusable. The term total error represents the sum of three elements: the inherent nonlinearity produced by the internal component errors; the numerator offset er- ror multiplied by the set gain (Vy/Vx); and the static offset error of the output amplifier. In other words, total error is expressed as: Nonlinearity + (Zog X Vy/Vx)+ Vos of output of output amp where the subscript OS indicates offset. Specifically, the chips total error equals: +0.5% Vou 0.15 mV(Vy/Vx) +0.15 mV When V,/Vx is small, the nonlinearity error domi- _ nates; when that ratio is large, the numerator offset error dominates; and when the output is small (under 10 mV), output offset dominates. Errors are defined in this manner so that the user may minimize total error by nulling out the error dominating a particu- lar input condition. Another quadrant heard from Although the one-quadrant multiplier-divider tackles only positive input voltages, the chip can also be set up as a two-quadrant divider capable of han- dling bipolar numerator signals. That feat is accom- plished by offsetting the nominal] numerator input at Vz by a voltage that tracks the denominator input signal Vgen. The latter is made slightly larger than the former, by a ratio of 35 to 25 (Fig. 3). The ratio is set by feeding the numerator and denominator in- puts through external 35-kQ resistors (Rs,R4) to the COMPUTATIONAL PRODUCTS 6-7summing node (current input) of their respective op amps, A, and Ag. The offsetting voltage Vaen iS summed with the numerator input, Vaum, through the internal 25-kQ resistor at Vz. That offset changes the dividers transfer function from 10 V (Vz/Vx) to: (b) 5. In a two-quadrant divider, the chip exhibits the same dynamic response with numerator inputs be- tween 20 V pk-pk (a) and 20 mV pk-pk (b) with de- nominators of 10 V and 10 mV, respectively. Function Reg (2) Re (2) Power (M) One-fifth root 162 40.2 0.20 One-quarter root 150 49.9 0.25 Cube root 100 49.9 0.33 Square root 100 100.0 0.50 Function Ry, (2) Power (M) Fifth power 48.7 5.0 Fourth power 64.9 4.0 Analog cube 97.6 3.0 Analog square 196.0 2.0 Arc tangent 931.0 1.21 6-8 COMPUTATIONAL PRODUCTS - Vout = +10 V(Vaum + Vaen)/Vaen = +10 vil + Vaum/Vaen) = 10 Vv + 10 V(Vnum/ Vaen) As long as the denominator input equals or exceeds the numerator in magnitude, the circuit accepts bi- polar voltages (such as sine waves) at the numerator input. However, its output now equals +10 V de without any numerator voltage applied. To make the circuit practical, the +10-V output offset is canceled by summing it with the 10-V refer- ence; this is done in the output op amp section through resistors R, and Re. The potentiometer trims the offset, so that there is zero out for zero in, leaving the simple transfer function: Vout = 10 V(Vanum/Vaen) At a denominator voltage of 100 mV, this log- antilog two-quadrant divider has 20 times the band- width of a typical multiplier-divider like the 535 (Fig. 4). These two chips are again compared for given de- nominator voltages, this time against small-signal bandwidth. The log-antilog device bandwidth is vir- tually independent of denominator voltage and is . faster for all but the highest denominator voltages. An indication of the dynamic range, precision, and | linearity of the two-quadrant divider is readily seen (Fig. 5). In both photographs, the upper waveform is the output of the chip, a 20-V pk-pk 20-kHz sine wave, and the lower waveform is the source of that signal ' applied to the numerator input. In each case the out- put is 10 V X Vaum/Vaen and shows virtually no dif- ference over a 1000-to-1 change in input signals. Of - course Vaen could have been changing at the time, but the outputs would then be harder to compare. Getting to the root of the matter The 538 takes roots in real time with an accuracy that might well appear unbelievable for an analog circuit (Fig. 6). When configured as a square-root (M = 14) circuit, it has a transfer function of: Vout =1V(V2/1 V) Its scale factor adjustment R, and offset trimming resistor R, let the curcuit reach an output voltage that is within 0.35% of the ideal over a range of 1 mV to 10 V (80 dB). For an input range of 10 mV to 10 V (60 dB), the output is within +1 mV of the theoreti- cally correct value. This is equivalent to 13-bit per- formance referred to the output or 17 to 20 bits re- _ ferred to the input. Circuit bandwidth is typicallyDESIGN ENTRY Analog computer chip 280 kHz with a 1-V pk-pk sine-wave input. As in the divider circuit, the input signal at Vz is divided by the level at Vx. Its 1-V scaling is obtained by halving the 2-V reference with resistors R3 and Ry, applying roughly 1 V to both Vx and Vy. Vx is actu- ally set low, at 0.95 V, resulting in a Vy value that is slightly high, providing a +5% scale factor trim- ming range. The voltage terms in Vx and Vy cancel, producing the dimensionless output required to determine a square function. The square root is extracted by raising the quan- tity Vz/Vx to the /2 power with resistors Rg and Rc. For maximum linearity the pair of resistors should be ratio-matched to better than +1%. Changing the resistor values of Rg and Rc (Table 1) enables cube, _ quarter, and fifth roots to be determined according to the equation: M = R-/(Rct+ Rpg). Finally, to raise the ratio Vz/Vx to a power greater than one, it is only necessary to change the gain of the log-ratio subtracter op amp, A3, by connecting a single resistor, Ra, between pins A and D. Varying the values of the resistor (see Table 2) creates M values from one to five according to the equation Ra = 196/(M1) and allows the arc-tangent function to be computed. Since resistors of any value may be used, the chip is not limited to integral powers or roots. Vz/Vx could be raised to the 3.17 power, say. It is only nec- essary that M stay between / and 5. tT Output 25k ve amie o Antilog + tn O- Scale factortrimming *Rafio-match 1% metal-film resistors for best accuracy. < 6. Resistors Rg and Rc set the chip to take the square root of the voltage at Vz , according to the transfer function Vou: = 1 V (Vz/1 V) a COMPUTATIONAL PRODUCTS 6-9