2SJ505(L), 2SJ505(S) Silicon P Channel MOS FET REJ03G0872-0400 (Previous: ADE-208-547B) Rev.4.00 Sep 07, 2005 Description High speed power switching Features * Low on-resistance RDS (on) = 0.017 typ. * Low drive current. * 4 V gate drive devices. * High speed switching. Outline RENESAS Package code: PRSS0004AE-A (Package name: LDPAK (L) ) RENESAS Package code: PRSS0004AE-B (Package name: LDPAK (S)-(1) ) D 4 4 1. Gate 2. Drain 3. Source 4. Drain G 1 1 2 2 3 3 S Rev.4.00 Sep 07, 2005 page 1 of 8 2SJ505(L), 2SJ505(S) Absolute Maximum Ratings (Ta = 25C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Symbol VDSS Value -60 Unit V VGSS ID 20 -50 V A -200 -50 A A ID (pulse) IDR Note 1 Note 3 Avalanche current Avalanche energy IAP Note 3 EAR -50 214 A mJ Channel dissipation Channel temperature Pch Tch Note 2 75 150 W C -55 to +150 C Storage temperature Notes: 1. PW 10 s, duty cycle 1% 2. Value at Tc = 25C 3. Value at Ta = 25C, Rg 50 Tstg Electrical Characteristics (Ta = 25C) Item Symbol Min Typ Max Unit V (BR) DSS V (BR) GSS -60 20 -- -- -- -- V V ID = -10 mA, VGS = 0 IG = 100 A, VDS = 0 IDSS IGSS -- -- -- -- -10 10 A A VDS = -60 V, VGS = 0 VGS = 16 V, VDS = 0 Gate to source cutoff voltage Static drain to source on state resistance VGS (off) RDS (on) -1.0 -- -- 0.017 -2.0 0.022 V ID = -1 mA, VDS = -10 V Note 4 ID = -25 A, VGS = -10 V Forward transfer admittance RDS (on) |yfs| -- 27 0.024 39 0.036 -- S ID = -25 A, VGS = -4 V Note 4 ID = 25 A, VDS = 10 V Input capacitance Output capacitance Ciss Coss -- -- 4100 2100 -- -- pF pF Reverse transfer capacitance Turn-on delay time Crss td (on) -- -- 450 32 -- -- pF ns VDS = -10 V VGS = 0 f = 1 MHz Rise time Turn-off delay time tr td (off) -- -- 225 530 -- -- ns ns Fall time Body to drain diode forward voltage tf VDF -- -- 330 -1.1 -- -- ns V trr -- 110 -- ns Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltage drain current Gate to source leak current Body to drain diode reverse recovery time Note: 4. Pulse test Rev.4.00 Sep 07, 2005 page 2 of 8 Test Conditions Note 4 VGS = -10 V ID = -10 A RL = 3 IF = -50 A, VGS = 0 IF = -50 A, VGS = 0 diF/dt = 50 A/s 2SJ505(L), 2SJ505(S) Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating -1000 ID (A) -300 60 Drain Current Channel Dissipation Pch (W) 80 40 20 10 -100 PW 0 50 100 150 Case Temperature =1 1 m s 0m s Op s( era 1s tio ho n( t) Tc = Operation in 25 C this area is ) limited by RDS (on) -30 DC -10 -3 -1 Ta = 25C -0.1 -0.1 -0.3 -1 200 Tc (C) ID (A) -4.5 V -80 -4 V -100 VDS (V) VDS = -10 V Pulse Test -80 -60 Drain Current -60 -3.5 V -40 -3 V -20 -40 75C -20 VGS = -2.5 V 0 -30 -100 Pulse Test -5 V -10 Typical Transfer Characteristics -10 V -8 V ID (A) -100 -3 Drain to Source Voltage Typical Output Characteristics Drain Current s 0 -0.3 0 0 -4 -8 -12 Drain to Source Voltage 0 -20 -16 Drain to Source Saturation Voltage vs. Gate to Source Voltage Pulse Test -1.6 -1.2 ID = -50 A -0.8 -0.4 -5 A -20 A -10 A 0 0 -4 -8 -12 Gate to Source Voltage Rev.4.00 Sep 07, 2005 page 3 of 8 -16 -20 VGS (V) 0 -1 -2 -3 -4 Gate to Source Voltage VDS (V) -2.0 Tc = -25C 25C -5 VGS (V) Static Drain to Source on State Resistance vs. Drain Current Static Drain to Source on State Resistance RDS (on) () Drain to Source Saturation Voltage VDS (on) (V) 10 100 50 VGS = -4 V 20 -10 V 10 5 2 Pulse Test 1 -1 -3 -10 -30 Drain Current -100 -300 -1000 ID (A) 2SJ505(L), 2SJ505(S) Forward Transfer Admittance vs. Drain Current Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance RDS (on) () Static Drain to Source on State Resistance vs. Temperature 50 Pulse Test ID = -50 A -20 A 40 VGS = -4 V -10 A 30 -50 A 20 -10 A, -20 A -10 V 10 0 -40 0 40 80 Case Temperature 120 160 100 30 Tc = -25C 10 25C 3 75C 1 0.3 VDS = -10 V Pulse Test 0.1 -0.1 Tc (C) 500 20000 Capacitance C (pF) Reverse Recovery Time trr (ns) 50000 200 100 50 di / dt = 50 A / s VGS = 0, Ta = 25C -0.3 -1 -3 -10 Reverse Drain Current -30 2000 500 -12 -16 -100 0 40 80 Gate Charge Rev.4.00 Sep 07, 2005 page 4 of 8 120 160 Qg (nc) -10 -20 -30 -40 -50 -20 200 1000 td(off) Switching Time t (ns) -8 VGS (V) VGS ID = -50 A 0 Switching Characteristics -4 -80 Crss Drain to Source Voltage VDS (V) 0 VDD = -50 V -25 V -10 V -60 Coss 1000 100 -100 VDD = -50 V -25 V -10 V VDS -100 Ciss 200 Gate to Source Voltage VDS (V) Drain to Source Voltage -40 -30 VGS = 0 f = 1 MHz 5000 Dynamic Input Characteristics -20 -10 10000 IDR (A) 0 -3 Typical Capacitance vs. Drain to Source Voltage 1000 10 -0.1 -1 Drain Current ID (A) Body-Drain Diode Reverse Recovery Time 20 -0.3 500 tf 200 tr 100 50 td(on) 20 VGS = -10 V, VDD = -30 V PW = 10 s, duty 1 % 10 -0.1 -0.3 -1 -3 Drain Current -10 -30 ID (A) -100 2SJ505(L), 2SJ505(S) Reverse Drain Current vs. Source to Drain Voltage Repetitive Avalanche Energy EAR (mJ) Maximum Avalanche Energy vs. Channel Temperature Derating Reverse Drain Current IDR (A) -100 -80 -60 -5 V -10 V -40 VGS = 0 -20 Pulse Test 0 0 -0.4 -0.8 -1.2 -1.6 Source to Drain Voltage -2.0 250 IAP = -50 A VDD = -25 V duty < 0.1 % Rg 50 200 150 100 50 0 25 50 75 100 125 150 Channel Temperature Tch (C) VSD (V) Normalized Transient Thermal Impedance s (t) Normalized Transient Thermal Impedance vs. Pulse Width 3 Tc = 25C D=1 1 0.5 0.3 0.2 0.1 0.1 ch - c (t) = s (t) * ch - c ch - c = 1.67C/W, Tc = 25C 0.05 0.02 0.03 0.0 1 1s h D= PDM p ot 0.01 10 uls PW T e PW T 100 10 m 1m 100 m 1 10 Pulse Width PW (S) Avalanche Test Circuit VDS Monitor Avalanche Waveform L EAR = 1 * L * IAP2 * 2 VDSS VDSS - VDD IAP Monitor Rg V(BR)DSS IAP D.U.T VDD VDS ID Vin -15 V 50 0 Rev.4.00 Sep 07, 2005 page 5 of 8 VDD 2SJ505(L), 2SJ505(S) Switching Time Test Circuit Waveform Vin Vout Monitor Vin Monitor 10% D.U.T. 90% RL 90% 90% Vin -10 V 50 VDD = -30 V Vout td(on) Rev.4.00 Sep 07, 2005 page 6 of 8 10% tr 10% td(off) tf 2SJ505(L), 2SJ505(S) Package Dimensions JEITA Package Code RENESAS Code Package Name MASS[Typ.] PRSS0004AE-A LDPAK(L) / LDPAK(L)V 1.40g 8.6 0.3 1.3 0.15 1.3 0.2 1.37 0.2 0.76 0.1 2.54 0.5 2.54 0.5 RENESAS Code Package Name PRSS0004AE-B LDPAK(S)-(1) / LDPAK(S)-(1)V 0.4 0.1 MASS[Typ.] Unit: mm 1.30g (1.5) 10.0 Rev.4.00 Sep 07, 2005 page 7 of 8 2.54 0.5 0.4 0.1 0.3 3.0 +- 0.5 2.54 0.5 0.2 0.86 +- 0.1 7.8 7.0 2.49 0.2 0.2 0.1 +- 0.1 1.37 0.2 1.3 0.2 7.8 6.6 1.3 0.15 + 0.3 - 0.5 8.6 0.3 (1.5) (1.4) 4.44 0.2 10.2 0.3 1.7 SC-83 2.49 0.2 11.0 0.5 11.3 0.5 0.3 10.0 +- 0.5 (1.4) 4.44 0.2 10.2 0.3 0.2 0.86 +- 0.1 JEITA Package Code Unit: mm 2.2 2SJ505(L), 2SJ505(S) Ordering Information Part Name 2SJ505L-E 2SJ505STL-E Quantity 500 pcs 1000 pcs Shipping Container Box (Sack) Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.4.00 Sep 07, 2005 page 8 of 8 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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