81 GHz to 86 GHz, E-Band Variable Gain Amplifier HMC8121 Data Sheet FEATURES GENERAL DESCRIPTION Gain: 22 dB typical Wide gain control range: 17 dB typical Output third-order intercept (OIP3): 27.5 dBm typical Output power for 1 dB compression (P1dB): 20 dBm typical Saturated output power (PSAT): 21 dBm typical DC supply: 4 V at 265 mA No external matching required Die size: 3.599 mm x 1.369 mm x 0.05 mm The HMC8121 is an integrated E-band, gallium arsenide (GaAs), pseudomorphic (pHEMT), monolithic microwave integrated circuit (MMIC), variable gain amplifier and/or driver amplifier that operates from 81 GHz to 86 GHz. The HMC8121 provides up to 22 dB of gain, 20 dBm output P1dB, 27.5 dBm of OIP3, and 21 dBm of PSAT while requiring only 265 mA from a 4 V power supply. Two gain control voltages (VCTL1 and VCTL2) are provided to allow up to 17 dB of variable gain control. The HMC8121 exhibits excellent linearity and is optimized for E-band communications and high capacity wireless backhaul radio systems. All data is taken with the chip in a 50 test fixture connected via a 3 mil wide x 0.5 mil thick x 7 mil long ribbon on each port. APPLICATIONS E-band communication systems High capacity wireless backhaul radio systems Test and measurement RFIN FUNCTIONAL BLOCK DIAGRAM 1 2 3 HMC8121 4 5 1.6k 13 12 11 10 9 8 7 13154-001 14 VDET 15 VREF 16 RFOUT 6 VDD6 17 VGG6 18 VDD5 19 VDD4 20 VGG5 21 VGG4 22 VDD3 23 VGG3 24 VCTL2 25 VCTL1 26 ENVDET 27 VDD2 VGG1/VGG2 28 VDD1 1.6k Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com HMC8121* Product Page Quick Links Last Content Update: 11/01/2016 Comparable Parts Design Resources View a parametric search of comparable parts * * * * Documentation Application Notes * AN-1363: Meeting Biasing Requirements of Externally Biased RF/Microwave Amplifiers with Active Bias Controllers Data Sheet * HMC8121: 81 GHz to 86 GHz, E-Band Variable Gain Amplifier Data Sheet HMC8121 Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints Discussions View all HMC8121 EngineerZone Discussions Sample and Buy Visit the product page to see pricing options Technical Support Submit a technical question or find your regional support number * This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. HMC8121 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 12 General Description ......................................................................... 1 Typical Application Circuit ........................................................... 13 Functional Block Diagram .............................................................. 1 Assembly Diagram ..................................................................... 14 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Mounting and Bonding Techniques for Millimeterwave GaAs MMICs ............................................................................................. 15 Absolute Maximum Ratings ............................................................ 4 Handling Precautions ................................................................ 15 Thermal Resistance ...................................................................... 4 Mounting ..................................................................................... 15 ESD Caution .................................................................................. 4 Wire Bonding .............................................................................. 15 Pin Configuration and Function Descriptions ............................. 5 Outline Dimensions ....................................................................... 16 Interface Schematics..................................................................... 6 Ordering Guide .......................................................................... 16 REVISION HISTORY 2/16--Revision A: Initial Version Rev. A | Page 2 of 16 Data Sheet HMC8121 SPECIFICATIONS TA = 25C, VDDx = 4 V, VCTLx = -5 V, unless otherwise noted. Table 1. Min Parameter OPERATING CONDITIONS RF Frequency Range PERFORMANCE Gain Gain Variation over Temperature Gain Control Range Output Power for 1 dB Compression (P1dB) Saturated Output Power (PSAT) Output Third-Order Intercept (OIP3) at Maximum Gain 1 Input Return Loss Output Return Loss POWER SUPPLY Total Supply Current (IDD) 2 1 2 Typ 81 19 12 16 Unit 86 GHz 22 0.03 17 20 21 27.5 12 10 dB dB/C dB dBm dBm dBm dB dB 265 mA Data taken at power input (PIN) = -10 dBm/tone, 1 MHz spacing. Set VCTL1/VCTL2 = -5 V and then adjust VGG1/VGG2, VGG3, VGG4, VGG5, and VGG6 from -2 V to 0 V to achieve a total drain current (IDD) = 265 mA. Rev. A | Page 3 of 16 Max HMC8121 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Drain Bias Voltage (VDD1 to VDD6) Gate Bias Voltage (VGG1/VGG2, VGG3 to VGG6) Gain Control Voltage (VCTL1 and VCTL2) Maximum Junction Temperature (to Maintain 1 Million Hours Mean Time to Failure (MTTF)) Storage Temperature Range Operating Temperature Range Table 3. Thermal Resistance Rating 4.5 V -3 V to 0 V -6 V to 0 V 175C Package Type 28-Pad Bare Die [CHIP] 1 -65C to +150C -55C to +85C JC1 69.5 Unit C/W Based on ABLEBOND(R) 84-1LMIT as die attach epoxy with thermal conductivity of 3.6 W/mK. ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 4 of 16 Data Sheet HMC8121 GND RFIN GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 HMC8121 4 GND 5 RFOUT 6 GND VCTL2 VGG3 14 13 12 11 10 9 8 7 13154-002 VCTL1 15 VDET GND ENVDET 16 VREF VDD2 17 GND VDD1 18 VDD6 GND 19 VGG6 20 VDD5 21 GND 22 VGG5 23 GND 24 VDD4 25 VGG4 26 VDD3 27 GND 28 VGG1/VGG2 TOP VIEW (Not to Scale) Figure 2. Pad Configuration Table 4. Pad Function Descriptions Pad No. 1, 3, 4, 6, 10, 13, 16, 19, 24, 27 2 5 7 Mnemonic GND Description Ground Connection (See Figure 3). RFIN RFOUT VDET 8 VREF 9, 12, 15, 18, 25, 26 VDD6 to VDD1 11, 14, 17, 20, 28 21, 22 VGG6 to VGG3, VGG1/VGG2 VCTL2, VCTL1 23 Die Bottom ENVDET GND RF Input. DC couple RFIN and match it to 50 (see Figure 4). RF Output. DC couple RFOUT and match it to 50 (see Figure 5). Detector Voltage for the Power Detector (See Figure 6). VDET is the dc voltage representing the RF output power rectified by the diode, which is biased through an external resistor. Refer to the typical application circuit for the required external components (see Figure 38). Reference Voltage for the Power Detector (See Figure 6). VREF is the dc bias of the diode biased through an external resistor used for the temperature compensation of VDET. Refer to the typical application circuit for the required external components (see Figure 38). Drain Bias Voltage for the Variable Gain Amplifier (See Figure 7). For the required external components, see Figure 38. Gate Bias Voltage for the Variable Gain Amplifier (See Figure 8). For the required external components, see Figure 38. Gain Control Voltage for the Variable Gain Amplifier (See Figure 9). For the required external components, see Figure 38. Envelope Detector (See Figure 10). For the required external components, see Figure 38. Ground. Die bottom must be connected to the RF/dc ground (see Figure 3). Rev. A | Page 5 of 16 HMC8121 Data Sheet INTERFACE SCHEMATICS VDD6 , VDD5 , VDD4 , VDD3 , VDD2 , VDD1 13154-007 13154-003 GND 13154-004 VGG6 TO VGG3, VGG1/VGG2 Figure 8. VGG6 to VGG3, VGG1/VGG2 Interface RFOUT 1.6k 13154-005 Figure 4. RFIN Interface VCTL2 , VCTL1 Figure 9. VCTL2, VCTL1 Interface 13154-006 Figure 5. RFOUT Interface VDET , VREF 13154-009 1.6k ENVDET Figure 6. VDET, VREF Interface 13154-010 RFIN 13154-008 Figure 7. VDD6 to VDD1 Interface Figure 3. GND Interface Figure 10. ENVDET Interface Rev. A | Page 6 of 16 Data Sheet HMC8121 TYPICAL PERFORMANCE CHARACTERISTICS 30 30 TA = -55C TA = +25C TA = +85C 28 26 GAIN INPUT RETURN LOSS OUTPUT RETURN LOSS 10 24 GAIN (dB) RESPONSE (dB) 20 0 -10 22 20 18 16 14 -20 80 81 82 83 84 85 86 87 88 FREQUENCY (GHz) 10 81.0 13154-011 -30 79 VCTLx VCTLx VCTLx VCTLx 25 = -5.0V = -4.0V = -3.5V = -3.0V VCTLx VCTLx VCTLx VCTLx = -2.6V = -2.2V = -2.0V = -1.5V VCTLx VCTLx VCTLx VCTLx 83.0 83.5 84.0 84.5 85.0 30 = -1.2V = -1.0V = -0.5V = 0V RF RF RF RF RF RF 25 85.5 86.0 = = = = = = 81GHz 82GHz 83GHz 84GHz 85GHz 86GHz 15 15 10 10 5 5 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0 FREQUENCY (GHz) 0 -5.0 0 TA = -55C TA = +25C TA = +85C -4 -8 -12 -16 -20 -3.0 -2.5 -2.0 -1.5 -1.0 TA = -55C TA = +25C TA = +85C -8 -12 -16 -20 81.5 82.0 82.5 83.0 83.5 84.0 FREQUENCY (GHz) 84.5 85.0 85.5 86.0 -24 81.0 13154-013 -24 81.0 -3.5 Figure 15. Gain vs. Control Voltage at Various RF Frequencies RETURN LOSS (dB) -4 -4.0 CONTROL VOLTAGE (V) Figure 12. Gain vs. Frequency at Various Control Voltages 0 -4.5 Figure 13. Input Return Loss vs. Frequency at Various Temperatures, VCTL1/VCTL2 = -5 V 81.5 82.0 82.5 83.0 83.5 84.0 FREQUENCY (GHz) 84.5 85.0 85.5 86.0 13154-016 0 81.0 13154-015 GAIN (dB) 20 13154-012 GAIN (dB) 82.5 Figure 14. Gain vs. Frequency at Various Temperatures, VCTL1/VCTL2 = -5 V 20 RETURN LOSS (dB) 82.0 FREQUENCY (GHz) Figure 11. Broadband Gain and Return Loss Response vs. Frequency, VCTL1/VCTL2 = -5 V 30 81.5 13154-014 12 Figure 16. Output Return Loss vs. Frequency at Various Temperatures, VCTL1/VCTL2 = -5 V Rev. A | Page 7 of 16 HMC8121 = -5.0V = -4.0V = -3.5V = -3.0V VCTLx VCTLx VCTLx VCTLx = -2.6V = -2.2V = -2.0V = -1.5V 0 VCTLx = -1.2V VCTLx = -1.0V -4 -10 -15 -20 -25 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0 84.0 84.5 85.0 85.5 86.0 29 28 27 26 25 24 23 22 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 86.0 FREQUENCY (GHz) 20 81.0 13154-033 81.5 25 22 22 21 21 PSAT (dBm) 23 17 17 16 16 83.5 84.0 84.5 85.0 85.5 86.0 FREQUENCY (GHz) 15 81.0 13154-018 83.0 83.5 84.0 84.5 85.0 85.5 86.0 19 18 82.5 83.0 20 18 82.0 82.5 TA = -55C TA = +25C TA = +85C 24 23 81.5 82.0 Figure 21. Output IP3 vs. Frequency at Various Temperatures, PIN = -10 dBm/Tone, VCTL1/VCTL2 = -5 V TA = -55C TA = +25C TA = +85C 19 81.5 FREQUENCY (GHz) Figure 18. Reverse Isolation vs. Frequency at Various Temperatures, VCTL1/VCTL2 = -5 V 20 TA = -55C TA = +25C TA = +85C 13154-019 21 P1dB (dBm) 83.5 30 -65 15 81.0 83.0 Figure 20. Output Return Loss vs. Frequency at Various Control Voltages -60 24 82.5 FREQUENCY (GHz) IP3 (dBm) ISOLATION (dB) -16 TA = -55C TA = +25C TA = +85C -55 25 VCTLx = -1.2V VCTLx = -1.0V -12 -50 -70 81.0 82.0 = -2.6V = -2.2V = -2.0V = -1.5V -8 -24 81.0 Figure 17. Input Return Loss vs. Frequency at Various Control Voltages -45 81.5 VCTLx VCTLx VCTLx VCTLx 13154-020 81.5 FREQUENCY (GHz) -40 = -5.0V = -4.0V = -3.5V = -3.0V -20 13154-017 -30 81.0 VCTLx VCTLx VCTLx VCTLx 81.5 82.0 82.5 83.0 83.5 84.0 84.5 85.0 85.5 FREQUENCY (GHz) Figure 22. PSAT vs. Frequency at Various Temperatures, VCTL1/VCTL2 = -5 V Figure 19. Output P1dB vs. Frequency at Various Temperatures, VCTL1/VCTL2 = -5 V Rev. A | Page 8 of 16 86.0 13154-021 RETURN LOSS (dB) -5 VCTLx VCTLx VCTLx VCTLx RETURN LOSS (dB) 0 Data Sheet Data Sheet HMC8121 25 32 GAIN IIP3 OIP3 28 15 GAIN (dB), IP3 (dBm) 20 16 12 8 5 0 -5 -10 4 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 CONTROL VOLTAGE (V) -20 265 13154-022 -4.5 205 185 165 145 125 105 85 Figure 26. Gain and Input/Output IP3 vs. Drain Current, PIN = -5 dBm/Tone, VCTL1/VCTL2 = -1 V, RF = 81 GHz, Drain Current = (IDD1/IDD2 Fixed at 50 mA) + (IDD3 to IDD6 Swept) 25 GAIN IIP3 OIP3 28 225 DRAIN CURRENT (mA) Figure 23. Gain and Input/Output IP3 vs. Control Voltage, PIN = -10 dBm/Tone, RF = 81 GHz 32 245 13154-024 -15 0 -5.0 GAIN IIP3 OIP3 20 15 GAIN (dB), IP3 (dBm) 24 20 16 12 8 10 5 0 -5 -10 4 -15 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 CONTROL VOLTAGE (V) -20 265 13154-023 0 -5.0 245 225 205 185 165 145 125 Figure 24. Gain and Input/Output IP3 vs. Control Voltage, PIN = -10 dBm/Tone, RF = 83.5 GHz 85 Figure 27. Gain and Input/Output IP3 vs. Drain Current, PIN = -5 dBm/Tone, VCTL1/VCTL2 = -1 V, RF = 83.5 GHz, Drain Current = (IDD1/IDD2 Fixed at 50 mA) + (IDD3 to IDD6 Swept) 25 32 GAIN IIP3 OIP3 28 105 DRAIN CURRENT (mA) 13154-027 GAIN (dB), IP3 (dBm) 10 GAIN IIP3 OIP3 20 15 GAIN (dB), IP3 (dBm) 24 20 16 12 8 10 5 0 -5 -10 4 0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 CONTROL VOLTAGE (V) 13154-026 -15 -20 265 245 225 205 185 165 145 125 105 85 DRAIN CURRENT (mA) Figure 28. Gain and Input/Output IP3 vs. Drain Current, PIN = -5 dBm/Tone, VCTL1/VCTL2 = -1 V, RF = 86 GHz, Drain Current = (IDD1/IDD2 Fixed at 50 mA) + (IDD3 to IDD6 Swept) Figure 25. Gain and Input/Output IP3 vs. Control Voltage, PIN = -10 dBm/Tone, RF = 86 GHz Rev. A | Page 9 of 16 13154-025 GAIN (dB), IP3 (dBm) 24 GAIN (dB), IP3 (dBm) GAIN IIP3 OIP3 20 HMC8121 Data Sheet 24 350 5 20 330 -10 82.0 82.5 = 140mA = 130mA = 120mA = 110mA = 100mA = 90mA 83.0 83.5 84.0 84.5 85.0 85.5 86.0 FREQUENCY (GHz) 290 8 270 4 250 0 -15 -13 -9 -7 -5 -3 -1 1 3 230 INPUT POWER (dBm) Figure 29. Gain vs. Frequency at Various Drain Currents, PIN = -5 dBm/Tone, VCTL1/VCTL2 = -1 V, Drain Current = (IDD1/IDD2 fixed at 50 mA) + (IDD3 to IDD6 Swept) Figure 32. POUT, Gain, PAE, and IDD vs. Input Power, VCTL1/VCTL2 = -5 V, RF = 81 GHz 350 24 350 20 330 20 330 POUT GAIN PAE IDD 310 12 290 8 270 4 250 -13 -11 -9 -7 -5 -3 -1 1 3 230 13154-032 0 -15 IDD (mA) 16 POUT (dBm), GAIN (dB), PAE (%) 24 INPUT POWER (dBm) POUT GAIN PAE IDD 16 290 8 270 4 250 0 -15 -13 0.40 RF = 81GHz RF = 83.5GHz RF = 86GHz 0.1 4 8 12 OUTPUT POWER (dBm) 16 20 Figure 31. Detector Output Voltage (VREF - VDET) vs. Output Power at Various RF Frequencies, VCTL1/VCTL2 = -5 V 0.35 -7 -5 -3 -1 1 3 230 100MHz 300MHz 500MHz 750MHz TONE SPACING TONE SPACING TONE SPACING TONE SPACING 0.30 0.25 0.20 0.15 0.10 0.05 0 -20 13154-031 0.01 0 -9 Figure 33. POUT, Gain, PAE, and IDD vs. Input Power, VCTL1/VCTL2 = -5 V, RF = 86 GHz 1 0.001 -4 -11 INPUT POWER (dBm) PEAK-TO-PEAK OUTPUT VOLTAGE (V) 10 310 12 Figure 30. POUT, Gain, PAE, and IDD vs. Input Power, VCTL1/VCTL2 = -5 V, RF = 83.5 GHz VREF - VDET (V) POUT (dBm), GAIN (dB), PAE (%) -11 IDD (mA) 81.5 IDD IDD IDD IDD IDD IDD 12 13154-030 -20 81.0 = 265mA = 250mA = 225mA = 200mA = 175mA = 150mA 13154-028 -15 IDD IDD IDD IDD IDD IDD 310 IDD (mA) -5 POUT GAIN PAE IDD 16 -18 -16 -14 -12 -10 -8 TOTAL INPUT POWER (dBm) -6 -4 13154-134 GAIN (dB) 0 13154-029 POUT (dBm), GAIN (dB), PAE (%) 10 Figure 34. Envelope Detector Peak-to-Peak Output Voltage vs. Total Input Power at Various Tone Spacings, RF = 81 GHz, VCTL1/VCTL2 = -5 V, VDET = 4 V with 150 Load Impedance at ENVDET Rev. A | Page 10 of 16 Data Sheet 0.40 0.30 0.25 0.20 0.15 0.10 0.05 0 -20 -18 -16 -14 -12 -10 -8 TOTAL INPUT POWER (dBm) -6 -4 Figure 35. Envelope Detector Peak-to-Peak Output Voltage vs. Total Input Power at Various Tone Spacings, RF = 83.5 GHz, VCTL1/VCTL2 = -5 V, VDET = 4 V with 150 Load Impedance at ENVDET 0.35 100MHz 300MHz 500MHz 750MHz TONE SPACING TONE SPACING TONE SPACING TONE SPACING 0.30 0.25 0.20 0.15 0.10 0.05 0 -20 -18 -16 -14 -12 -10 -8 TOTAL INPUT POWER (dBm) -6 -4 13154-136 TONE SPACING TONE SPACING TONE SPACING TONE SPACING PEAK-TO-PEAK OUTPUT VOLTAGE (V) 0.35 100MHz 300MHz 500MHz 750MHz 13154-135 PEAK-TO-PEAK OUTPUT VOLTAGE (V) 0.40 HMC8121 Figure 36. Envelope Detector Peak-to-Peak Output Voltage vs. Total Input Power at Various Tone Spacings, RF = 86 GHz, VCTL1/VCTL2 = -5 V, VDET = 4 V with 150 Load Impedance at ENVDET Rev. A | Page 11 of 16 HMC8121 Data Sheet THEORY OF OPERATION The circuit architecture of the HMC8121 variable gain amplifier is shown in Figure 37. The HMC8121 uses multiple gain stages and staggered voltage variable attenuation stages to form a low noise, high linearity variable gain amplifier with a gain range of ~17 dB. The first stage is a low noise preamp, which is followed by the first voltage variable attenuator in the signal path. A portion of the signal is coupled away and further amplified before driving an on-chip envelope detector. The envelope detector provides an output that is proportional to the peak envelope power of the incoming signal. After the first attenuator, a second stage amplifier provides additional gain and isolation before driving the second variable attenuator block. Three cascaded gain stages follow the second variable attenuator. At the output of the last stage, another coupler taps off a small portion of the output signal. The coupled signal is presented to an on-chip diode detector for external monitoring of the output power. A matched reference diode is included to help correct for detector temperature dependencies. See the application circuit in Figure 38 for further details on biasing the different blocks and utilizing the detector features. RFIN RFOUT ENVDET VCTL1 VCTL2 VREF Figure 37. Variable Gain Amplifier Circuit Architecture Rev. A | Page 12 of 16 VDET 13154-034 ENV DET Data Sheet HMC8121 TYPICAL APPLICATION CIRCUIT The HMC8121 uses several amplifier, detector, and attenuator stages. All stages use depletion mode pHEMT transistors. It is important to follow the following power-up bias sequence to ensure transistor damage does not occur. A typical application circuit for the HMC8121 is provided in Figure 38. For typical operation, drive the attenuator control pads from a single control voltage. It is important to bypass all the supply connections and attenuator control pads with adequate bypassing capacitors. Use single-layer chip capacitors with very high self-resonant frequency close to the HMC8121 die, bypassing each supply or control pad. Typically, 120 pF chip capacitors are used, followed by 0.01 F and 4.7 F surface-mount capacitors. Combine supply lines as shown in the application circuit schematic to minimize external component count and simplify power supply routing (see Figure 38). Pad 25 and Pad 26 are internally connected. Therefore, use either pad to connect the external bypass components of VDD1/VDD2. 1. 2. 3. 4. Apply a -5 V bias to the VCTL1 and VCTL2 pads. Apply a -2 V bias to the VGG3 to VGG6 and VGG1/VGG2 pads. Apply 4 V to the VDD1 to VDD6 pads. Adjust VGG1/VGG2 and VGG3 to VGG6 between -2 V and 0 V to achieve a total amplifier drain current of 265 mA. After bias is established, adjust the VCTL1 = VCTL2 bias between -5 V and 0 V to achieve the desired gain. To power down the HMC8121, follow the reverse procedure. RFIN For additional guidance on general bias sequencing, see the MMIC Amplifier Biasing Procedure application note. 1 2 3 4 5 1.6k 120pF 120pF 13 12 11 10 120pF 120pF 120pF 120pF 120pF 120pF 120pF 120pF 120pF 0.01F 0.01F 0.01F 0.01F 0.01F 0.01F 0.01F 4.7F 4.7F 4.7F 4.7F 4.7F 4.7F 4.7F VGG1/VGG2 VDD1 , VDD2 VCTL1 , VCTL2 VGG3, VGG4 VDD3 , VDD4 , VDD5 9 VGG5, VGG6 8 VDD6 VREF 100k 10k 3.5k ENVDET +4V VDET +5V +5V 1000pF 150 7 VDET 14 VDD6 15 VGG6 16 VDD5 17 VGG5 18 100k 10k VOUT = VREF - VDET 10k -5V 10k SUGGESTED CIRCUIT Figure 38. Typical Application Circuit Rev. A | Page 13 of 16 13154-035 120pF 19 VDD4 20 VGG4 21 VDD3 22 VGG3 23 VCTL2 24 VCTL1 25 ENVDET VDD1 26 VDD2 27 VGG1/VGG2 28 RFOUT 6 VREF 1.6k HMC8121 Data Sheet ASSEMBLY DIAGRAM 50 TRANSMISSION LINE 3 MIL WIDE GOLD RIBBON (WEDGE BOND) 2 3 RFIN 1 3 MIL NOMINAL GAP 4 RFOUT 5 1.6k 1.6k 6 13 12 11 10 9 8 7 VDET 14 VDD6 15 VGG6 16 VDD5 17 VGG5 18 VDD4 19 VGG4 20 VDD3 21 VGG3 22 VCTL2 23 VCTL1 24 ENV DET 25 VDD2 26 VDD1 27 VGG1/VGG2 28 VREF 3 MIL WIDE GOLD RIBBON (WEDGE BOND) 120pF 0.01F 4.7F 4.7F VGG1/VGG2 VDD1 , VDD2 VCTL1 , VCTL2 4.7F 4.7F 4.7F VGG3, VGG4 VDD3 , VDD4 , VDD5 VGG5, VGG6 Figure 39. Assembly Diagram Rev. A | Page 14 of 16 4.7F VDD6 13154-036 4.7F Data Sheet HMC8121 MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Attach the die directly to the ground plane eutectically or with conductive epoxy. To bring RF to and from the chip, use 50 microstrip transmission lines on 0.127 mm (5 mil) thick alumina thin film substrates (see Figure 40). Transients Suppress instrument and bias supply transients while bias is applied. To minimize inductive pickup, use shielded signal and bias cables. General Handling Handle the chip on the edges only using a vacuum collet or with a sharp pair of bent tweezers. Because the surface of the chip has fragile air bridges, never touch the surface of the chip with a vacuum collet, tweezers, or fingers. 0.05mm (0.002") THICK GaAs MMIC RIBBON BOND 0.076mm (0.003") MOUNTING The chip is back metallized and can be die mounted with gold/tin (AuSn) eutectic preforms or with electrically conductive epoxy. The mounting surface must be clean and flat. RF GROUND PLANE 13154-037 Eutectic Die Attach 0.127mm (0.005") THICK ALUMINA THIN FILM SUBSTRATE Figure 40. Routing RF Signals To minimize bond wire length, place microstrip substrates as close to the die as possible. Typical die to substrate spacing is 0.076 mm to 0.152 mm (3 mil to 6 mil). HANDLING PRECAUTIONS To avoid permanent damage, adhere to the following precautions. Storage All bare die ship in either waffle or gel-based ESD protective containers, sealed in an ESD protective bag. After opening the sealed ESD protective bag, all die must be stored in a dry nitrogen environment. Cleanliness Handle the chips in a clean environment. Never use liquid cleaning systems to clean the chip. Static Sensitivity Follow ESD precautions to protect against ESD strikes. It is best to use an 80% gold/20% tin preform with a work surface temperature of 255C and a tool temperature of 265C. When hot 90% nitrogen/10% hydrogen gas is applied, maintain tool tip temperature at 290C. Do not expose the chip to a temperature greater than 320C for more than 20 sec. No more than 3 sec of scrubbing is required for attachment. Epoxy Die Attach ABLEBOND 84-1LMIT is recommended for die attachment. Apply a minimum amount of epoxy to the mounting surface so that a thin epoxy fillet is observed around the perimeter of the chip after placing it into position. Cure the epoxy per the schedule provided by the manufacturer. WIRE BONDING RF bonds made with 0.003 in. x 0.0005 in. gold ribbon are recommended for the RF ports. These bonds must be thermosonically bonded with a force of 40 g to 60 g. DC bonds of 0.001 in. (0.025 mm) diameter, thermosonically bonded, are recommended. Create ball bonds with a force of 40 g to 50 g and wedge bonds with a force of 18 g to 22 g. Create all bonds with a nominal stage temperature of 150C. Apply a minimum amount of ultrasonic energy to achieve reliable bonds. Keep all bonds as short as possible, less than 12 mil (0.31 mm). Rev. A | Page 15 of 16 HMC8121 Data Sheet OUTLINE DIMENSIONS 3.599 0.05 0.085 0.125 0.125 0.216 TOP VIEW (CIRCUIT SIDE) 1 2 0.225 3 4 5 6 1.200 0.125 0.125 1.369 0.682 27 26 25 24 23 22 21 0.073 0.15 0.15 0.15 0.15 0.15 0.15 0.15 20 0.30 19 18 17 16 15 14 13 12 11 10 9 8 7 0.085 SIDE VIEW 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 01-26-2016-A 28 0.081 Figure 41. 28-Pad Bare Die [CHIP] (C-28-1) Dimensions shown in millimeters ORDERING GUIDE Model1 HMC8121 HMC8121-SX 1 2 Temperature Range -55C to +85C -55C to +85C Package Description 28-Pad Bare Die [CHIP] 28-Pad Bare Die [CHIP] The HMC8121-SX is two pairs of the die in a gel pack for the sample orders. This is a waffle pack option; contact Analog Devices, Inc., sales representatives for additional packaging options. (c)2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13154-0-2/16(A) Rev. A | Page 16 of 16 Package Option2 C-28-1 C-28-1