STA339BWTR - STMicroelectronics

August 2010 Doc ID 15251 Rev 5 1/77

STA339BW

2.1-channel high-efficiency digital audio system

Features

Wide voltage supply range

– 5 V to 26 V (operating range)

– 30 V (absolute maximum rating)

3 power output configurations

– 2 channels of ternary PWM (stereo mode)

(2 x 20 W into 8 Ω at 18 V)

– 3 channels - left, right using binary and LFE

using ternary PWM (2.1 mode) (2 x 9 W +

1x20W into 2x4Ω, 1 x 8 Ω at 18 V)

– 2 channels of ternary PWM (2 x 20 W) +

stereo lineout ternary

2.1 channels of 24-bit FFX® 100 dB SNR and

dynamic range

Selectable 32 to 192 kHz input sample rates

I2C control with selectable device address

Digital gain/attenuation +48 dB to -80 dB with

0.5 dB/step resolution

Soft volume update with programmable ratio

Individual channel and master gain/attenuation

Two independent DRC configurable as a

dual-band anti-clipper (B2DRC) or as

independent limiters/compressors

EQ-DRC for DRC based on filtered signals

Dedicated LFE processing for bass boosting

with 0.5 dB/step resolution

Audio presets:

– 15 preset crossover filters

– 5 preset anti-clipping modes

– Preset night-time listening mode

Individual channel and master soft/hard mute

Independent channel volume and DSP bypass

Automatic zero-detect mute

Automatic invalid input-detect mute

2-channel I2S input data interface

Input and output channel mapping

Up to 8 user-programmable biquads per

channel with 28-bit resolution

3 coefficient banks for EQ presets storing with

fast recall via I2C interface

Bass/treble tones and de-emphasis control

Selectable high-pass filter for DC blocking

Advanced AM interference frequency

switching and noise suppression modes

Selectable high- or low-bandwidth

noise-shaping topologies

Variable max power correction for lower

full-power THD

Selectable clock input ratio

96 kHz internal processing sample rate, 24 to

28-bit precision

Thermal overload and short-circuit protection

embedded

Video apps: 576 * fS input mode supported

Fully compatible with STA339BWS.

PowerSSO-36 (slug down)

Table 1. Device summary

Order code Package Packaging

STA339BW PowerSSO-36 slug down Tube

STA339BWTR PowerSSO-36 slug down Tape and reel

www.st.com

Contents STA339BW

2/77 Doc ID 15251 Rev 5

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 15

3.5 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 16

3.6 Power on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.7 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.7.1 Functional pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4 Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

STA339BW Contents

Doc ID 15251 Rev 5 3/77

5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4.5 Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5.4.6 Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.2 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1.3 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1.4 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.1.5 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2.1 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.2.2 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2.3 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.2.4 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2.5 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.1 FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.2 FFX compensating pulse size register . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3.3 Overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . 34

6.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.1 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.2 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.3 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.4.4 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.4.5 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.4.6 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 35

6.4.7 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.4.8 Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.5.1 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.5.2 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.5.3 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.5.4 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.5.5 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.5.6 Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . 37

Contents STA339BW

4/77 Doc ID 15251 Rev 5

6.5.7 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.5.8 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

6.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.6.1 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.6.2 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.6.3 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . 44

6.6.4 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.6.5 Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.6.6 IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

6.6.7 External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.7 Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 45

6.7.1 Mute/line output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.7.2 Master volume register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.7.3 Channel 1 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.7.4 Channel 2 volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

6.7.5 Channel 3 / line output volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6.8 Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 47

6.8.1 Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.8.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.8.3 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.8.4 Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.9 Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 49

6.9.1 Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.9.2 EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6.9.3 Volume bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.9.4 Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.9.5 Limiter select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.9.6 Output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

6.10 Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.10.1 Tone control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.11 Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 51

6.11.1 Limiter 1 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.11.2 Limiter 1 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.11.3 Limiter 2 attack/release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

6.11.4 Limiter 2 attack/release threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.11.5 Limiter 1 Extended attack threshold (addr 0x32) . . . . . . . . . . . . . . . . . . 55

STA339BW Contents

Doc ID 15251 Rev 5 5/77

6.11.6 Limiter 1 Extended release threshold (addr 0x33) . . . . . . . . . . . . . . . . . 55

6.11.7 Limiter 2 Extended attack threshold (addr 0x34 . . . . . . . . . . . . . . . . . . ) 56

6.11.8 Limiter 2 Extended release threshold (addr 0x35) . . . . . . . . . . . . . . . . . 56

6.12 User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 56

6.12.1 Coefficient address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.12.2 Coefficient b1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.12.3 Coefficient b1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.12.4 Coefficient b1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.12.5 Coefficient b2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.12.6 Coefficient b2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.12.7 Coefficient b2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.12.8 Coefficient a1 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.12.9 Coefficient a1 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.12.10 Coefficient a1 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.12.11 Coefficient a2 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.12.12 Coefficient a2 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.12.13 Coefficient a2 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.12.14 Coefficient b0 data register bits 23:16 . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.12.15 Coefficient b0 data register bits 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.12.16 Coefficient b0 data register bits 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.12.17 Coefficient write/read control register . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.12.18 User-defined EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.12.19 Prescale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.12.20 Postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.12.21 Overcurrent postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.13 Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 63

6.14 Variable distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . 63

6.15 Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 64

6.16 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.17 EQ coefficients and DRC configuration register (addr 0x31) . . . . . . . . . . 65

6.18 Extended configuration register (addr 0x36) . . . . . . . . . . . . . . . . . . . . . . 65

6.18.1 Dual-band DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.18.2 EQ DRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.18.3 Extended post scale range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.18.4 Extended attack rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.18.5 Extended BIQUAD selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Contents STA339BW

6/77 Doc ID 15251 Rev 5

6.19 EQ soft volume configuration registers (addr 0x37 - 0x38) . . . . . . . . . . . 69

6.20 DRC RMS filter coefficients (addr 0x39 - 0x3E) . . . . . . . . . . . . . . . . . . . . 70

7 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.1 Application scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.2 PLL filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

8 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

STA339BW List of figures

Doc ID 15251 Rev 5 7/77

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 2. Pin connection PowerSSO-36 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 3. Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 4. Power-off sequence for pop-free turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 5. Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 6. Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 7. Left and right processing part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. Processing part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 10. Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 11. OCFG = 00 (default value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 12. OCFG = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 13. OCFG = 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 14. OCFG = 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 15. Output mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 16. 2.0 channels (OCFG = 00) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 17. 2.1 channels (OCFG = 01) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 18. 2.1 channels (OCFG = 10) PWM slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 19. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 20. B2DRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 21. EQDRC scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 22. Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 23. Output configuration for stereo BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 24. Double-layer PCB with 2 copper ground areas and 16 via holes . . . . . . . . . . . . . . . . . . . 73

Figure 25. PowerSSO-36 power derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 26. PowerSSO-36 slug down outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

List of tables STA339BW

8/77 Doc ID 15251 Rev 5

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 6. Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. Functional pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 9. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 10. Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 11. Input sampling rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 12. Internal interpolation ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 13. IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 14. Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 15. Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 16. Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 17. Serial audio input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 18. Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19. Supported serial audio input formats for MSB-first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . 30

Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 31

Table 21. Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 22. Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 23. FFX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 24. Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 25. FFX compensating pulse size bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 26. Compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 27. Overcurrent warning bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 28. High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 29. De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 30. DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 31. Post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 32. Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 33. Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 34. Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 35. Submix mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 36. Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 37. Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 38. Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 39. AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 40. PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 41. Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 42. Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 43. Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 44. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 45. Output configuration engine selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 46. Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 47. Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 48. LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

STA339BW List of tables

Doc ID 15251 Rev 5 9/77

Table 49. Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 50. IC power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 51. External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 52. Line output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 53. Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 54. Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 55. Audio preset gain compression/limiters selection for AMGC[3:2] = 00. . . . . . . . . . . . . . . . 47

Table 56. AM interference frequency switching bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 57. Audio preset AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 58. Bass management crossover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 59. Bass management crossover frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 60. Tone control bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 61. EQ bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 62. Binary output enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 63. Channel limiter mapping as a function of CxLS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 64. Channel output mapping as a function of CxOM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 65. Tone control boost/cut as a function of BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 66. Limiter attack rate as a function of LxA bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 67. Limiter release rate as a function of LxR bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 68. Limiter attack threshold as a function of LxAT bits (AC mode). . . . . . . . . . . . . . . . . . . . . . 54

Table 69. Limiter release threshold as a function of LxRT bits (AC mode). . . . . . . . . . . . . . . . . . . . . 54

Table 70. Limiter attack threshold as a function of LxAT bits (DRC mode) . . . . . . . . . . . . . . . . . . . . 55

Table 71. Limiter release threshold as a as a function of LxRT bits (DRC mode) . . . . . . . . . . . . . . . 55

Table 72. RAM block for biquads, mixing, scaling and bass management. . . . . . . . . . . . . . . . . . . . . 62

Table 73. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 74. EQ RAM select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 75. Anti-clipping and DRC preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 76. Anti-clipping selection for AMGC[3:2] = 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 77. Post scale setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 78. Extended attack rate setup for limiter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 79. Extended attack rate setup for limiter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 80. De-emphasis filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 81. Bass filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 82. Treble filter setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 83. Soft volume (increasing) setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 84. Soft volume (decreasing) setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 85. PowerSSO-36 slug down dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 86. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Description STA339BW

10/77 Doc ID 15251 Rev 5

1 Description

The STA339BW is an integrated solution of digital audio processing, digital amplifier control,

and FFX-power output stage, thereby creating a high-power single-chip FFX® solution

comprising high-quality, high-efficiency, all digital amplification.

STA339BW is based on FFX (fully flexible amplification) processor, a STMicroelectronics

proprietary technology. FFX is the evolution and the enlargement of the ST ternary

technology: the new processor can be configured to work in ternary, binary, binary

differential and phase shift PWM modulation schemes.

STA339BW contains the ternary, binary and binary differential implementations, a subset of

the full capability of the FFX processor.

The STA339BW is part of the Sound Terminal™ family that provides full digital audio

streaming to the speaker, offering cost effectiveness, low power dissipation and sound

enrichment.

The STA339BW power section consists of four independent half bridges. These can be

configured via digital control to operate in different modes. 2.1 channels can be provided by

two half bridges and a single full bridge, providing up to 2 x 9 W + 1 x 20 W of power output.

Two channels can be provided by two full bridges, providing up to 2 x 20 W of power. The IC

can also be configured as 2.1 channels with 2 x 20 W provided by the device and external

power for FFX power drive.

Also provided in the STA339BW are a full assortment of digital processing features. This

includes up to 8 programmable 28-bit biquads (EQ) per channel and bass/treble tone

control. Available presets enable a time-to-market advantage by substantially reducing the

amount of software development needed for certain functions. This includes audio preset

volume loudness, preset volume curves and preset EQ settings. There are also new

advanced AM radio interference reduction modes. Dual band DRC dynamically equalizes

the system to provide speaker linear frequency response regardless output power level.

This feature independently processes the two bands, controlling, dynamically, the output

power level in each band and so providing a better sound quality.

The serial audio data input interface accepts all possible formats, including the popular I2S

format. Three channels of FFX processing are provided. This high-quality conversion from

PCM audio to FFX PWM switching waveform provides over 100 dB SNR and dynamic

range.

STA339BW Description

Doc ID 15251 Rev 5 11/77

1.1 Block diagram

Figure 1. Block diagram

Protection

current/thermal

Logic

Regulators

Bias

Power

control

FFX

PLL

Volume

control

Channel

interface

PowerDigital DSP

Pin connections STA339BW

12/77 Doc ID 15251 Rev 5

2 Pin connections

2.1 Connection diagram

Figure 2. Pin connection PowerSSO-36 (top view)

2.2 Pin description

VDD_DIG

GND_DIG

SCL

SDA

INT_LINE

RESET

SDI

LRCKI

BICKI

XTI

GND_PLL

FILTER_PLL

VDD_PLL

PWRDN

GND_DIG

VDD_DIG

TWARN / OUT4A

EAPD / OUT4B

GND_SUB

TEST_MODE

VSS

VCC_REG

OUT2B

GND2

VCC2

OUT2A

OUT1B

VCC1

GND1

OUT1A

GND_REG

VDD

CONFIG

OUT3B / FFX3B

OUT3A / FFX3A

D05AU1638

Table 2. Pin description

Pin Type Name Description

1 GND GND_SUB Substrate ground

2I SA I

C select address (pull-down)

3 I TEST_MODE This pin must be connected to ground (pull-down)

4 I/O VSS Internal reference at VCC - 3.3 V

5 I/O VCC_REG Internal VCC reference

6 O OUT2B Output half bridge 2B

7 GND GND2 Power negative supply

8 Power VCC2 Power positive supply

9 O OUT2A Output half bridge 2A

10 O OUT1B Output half bridge 1B

STA339BW Pin connections

Doc ID 15251 Rev 5 13/77

11 Power VCC1 Power positive supply

12 GND GND1 Power negative supply

13 O OUT1A Output half bridge 1A

14 GND GND_REG Internal ground reference

15 Power VDD Internal 3.3 V reference voltage

16 I CONFIG Paralleled mode command

17 O OUT3B / FFX3B PWM out Ch3B / external bridge driver

18 O OUT3A / FFX3A PWM out Ch3A / external bridge driver

19 O EAPD / OUT4B Power down for external bridge / PWM out Ch4B

20 I/O TWARN / OUT4A Thermal warning from external bridge (pull-up when input)

/ PWM out Ch4A

21 Power VDD_DIG Digital supply voltage

22 GND GND_DIG Digital ground

23 I PWRDN Power down (pull-up)

24 Power VDD_PLL Positive supply for PLL

25 I FILTER_PLL Connection to PLL filter

26 GND GND_PLL Negative supply for PLL

27 I XTI PLL input clock

28 I BICKI I

S serial clock

29 I LRCKI I

S left/right clock

30 I SDI I

S serial data channels 1 and 2

31 I RESET Reset (pull-up)

32 O INT_LINE Fault interrupt

33 I/O SDA I

C serial data

34 I SCL I

C serial clock

35 GND GND_DIG Digital ground

36 Power VDD_DIG Digital supply voltage

Table 2. Pin description (continued)

Pin Type Name Description

Electrical specifications STA339BW

14/77 Doc ID 15251 Rev 5

3 Electrical specifications

3.1 Absolute maximum ratings

Warning: Stresses beyond those listed in Table 3 above may cause

permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any

other conditions beyond those indicated under

“Recommended operating conditions” are not implied.

Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability. In the real

application, power supplies with nominal values rated within

the recommended operating conditions, may experience

some rising beyond the maximum operating conditions for a

short time when no or very low current is sinked (amplifier in

mute state). In this case the reliability of the device is

guaranteed, provided that the absolute maximum ratings are

not exceeded.

3.2 Thermal data

Table 3. Absolute maximum ratings

Symbol Parameter Min Typ Max Unit

VCC Power supply voltage (VCCxA, VCCxB) -0.3 - 30 V

VDD_DIG Digital supply voltage -0.3 - 4 V

VDD_PLL PLL supply voltage -0.3 - 4 V

Top Operating junction temperature -20 - 150 °C

Tstg Storage temperature -40 - 150 °C

Table 4. Thermal data

Parameter Min Typ Max Unit

Rth j-case Thermal resistance junction-case (thermal pad) - - 1.5 °C/W

Rth j-amb Thermal resistance junction-ambient (1)

1. See Section 8: Package thermal characteristics on page 73 for details.

---°C/W

Tth-sdj Thermal shut-down junction temperature - 150 - °C

Tth-w Thermal warning temperature - 130 - °C

Tth-sdh Thermal shut-down hysteresis - 20 - °C

STA339BW Electrical specifications

Doc ID 15251 Rev 5 15/77

3.3 Recommended operating conditions

3.4 Electrical specifications for the digital section

Table 5. Recommended operating condition

Symbol Parameter Min Typ Max Unit

VCC Power supply voltage (VCCxA, VCCxB) 5 - 26 V

VDD_DIG Digital supply voltage 2.7 3.3 3.6 V

VDD_PLL PLL supply voltage 2.7 3.3 3.6 V

Tamb Ambient temperature -20 - 70 °C

Table 6. Electrical specifications - digital section

Symbol Parameter Conditions Min Typ Max Unit

Iil

Low-level input current without

pull-up/down device Vi = 0 V -10 1 10 µA

Iih

High-level input current without

pull-up/down device

Vi = VDD_DIG

= 3.6 V -10 1 10 µA

Vil Low-level input voltage - - - 0.2 *

VDD_DIG V

Vih High-level input voltage - 0.8 *

VDD_DIG --V

Vol Low-level output voltage Iol = 2 mA - - 0.4 *

VDD_DIG V

Voh High-level output voltage Ioh = 2 mA 0.8 *

VDD_DIG --V

Ipu Pull-up/down current - 25 66 125 µA

Rpu

Equivalent pull-up/down

resistance --50-kΩ

Electrical specifications STA339BW

16/77 Doc ID 15251 Rev 5

3.5 Electrical specifications for the power section

The specifications given in this section are valid for the operating conditions: VCC =18V,

f=1kHz, f

sw = 384 kHz, Tamb = 25° C and RL = 8 Ω, unless otherwise specified.

Table 7. Electrical specifications - power section

Symbol Parameter Conditions Min Typ Max Unit

Output power BTL THD = 1% - 16 - W

THD = 10% - 20 -

Output power SE THD = 1% - 4 - W

THD = 10% - 5 -

RdsON

Power Pchannel/Nchannel MOSFET (total

bridge) ld = 1.5 A - 180 250 mΩ

gP Power Pchannel RdsON matching ld = 1.5 A 95 - - %

gN Power Nchannel RdsON matching ld = 1.5 A 95 - - %

Idss Power Pchannel/Nchannel leakage VCC = 20 V - - 10 µA

ILDT Low current dead time (static) Resistive load(1) - 8 15 ns

IHDT High current dead time (dynamic) Iload = 1.5 A(1) - 15 30 ns

trRise time Resistive load(1) - 10 18 ns

tfFall time Resistive load(1) - 10 18 ns

VCC Supply voltage operating voltage - 5 - 26 V

Ivcc

Supply current from VCC in power down PWRDN = 0 - 0.1 1 mA

Supply current from VCC in operation

PCM Input signal = -

60 dBfs,

Switching frequency

= 384 kHz,

No LC filters

- 52 60 mA

Ivdd

Supply current FFX processing (reference

only)

Internal clock =

49.152 MHz -5570mA

Ilim Overcurrent limit (2) 3.03.84.0A

Isc Short circuit protection Hi-Z output 3.8 4.8 - A

UVL Undervoltage protection - - 3.5 4.3 V

tmin Output minimum pulse width No load 20 30 60 ns

DR Dynamic range - - 100 - dB

SNR Signal to noise ratio, ternary mode A-weighted - 100 - dB

Signal to noise ratio binary mode - - 90 - dB

PSSR Power supply rejection ratio

FFX stereo mode,

<5 kHz

VRIPPLE = 1 V RMS

Audio input =

dither only

-80-dB

STA339BW Electrical specifications

Doc ID 15251 Rev 5 17/77

THD+N Total harmonic distortion + noise

FFX stereo mode,

Po = 1 W

f=1kHz

-0.2-%

XTA L K Crosstalk

FFX stereo mode,

<5 kHz

One channel driven

at 1 W

Other channel

measured

-80-dB

Peak efficiency, FFX mode Po = 2 x 20 W

into 8 Ω-90-

Peak efficiency,binary modes Po = 2 x 9 W into 4 Ω

+ 1 x 20 W into 8 Ω-87-

1. Refer to Figure 5: Test circuit 1.

2. Limit current if the register (OCRB par 6.1.3.3) overcurrent warning detect adjustment bypass is enabled. When disabled

refer to the Isc.

Table 7. Electrical specifications - power section (continued)

Symbol Parameter Conditions Min Typ Max Unit

Electrical specifications STA339BW

18/77 Doc ID 15251 Rev 5

3.6 Power on/off sequence

Figure 3. Power-on sequence

Note: The definition of a stable clock is when fmax - fmin < 1 MHz.

Section 6.2.3 on page 30 gives information on setting up the I2S interface.

Figure 4. Power-off sequence for pop-free turn-off

Don’t care

Don’t care CMD0 CMD1 CMD2

VCC

VDD_Dig

XTI

Reset

I2C

PWDN

TR TC

Don’t care

Don’t care CMD0 CMD1 CMD2

VCC

VDD_Dig

XTI

Reset

I2C

PWDN

TR TC

Don’t care

Don’t care CMD0 CMD1 CMD2

VCC

VDD_Dig

XTI

Reset

I2C

PWDN

TR TC

Don’t care

Don’t care CMD0 CMD1 CMD2

VCC

VDD_Dig

XTI

Reset

I2C

PWDN

TR TC

Don’t care

Don’t care CMD0 CMD1 CMD2

VCC

VDD_Dig

XTI

Reset

I2C

PWDN

TR TC

Don’t care

Note: no specific VCC and

VDD_DIG turn

−

on sequence

is required

TR = minimum time between XTI master clock stable and Reset removal: 1 ms

TC = minimum time between Reset removal and I2C program, sequence start: 1ms

Don’t care

VCC

VDD_Dig

XTI Don’t care

Soft Mute

Reg. 0x07

Data 0xFE

Soft EAPD

Reg. 0x05

Bit 7 = 0

Don’t care

Don’t care Don’t care

Don’t care

VCC

VDD_Dig

XTI Don’t care

Soft Mute

Reg. 0x07

Data 0xFE

Soft EAPD

Reg. 0x05

Bit 7 = 0

Don’t care

Don’t care Don’t care

Note: no specific VCC and

VDD_DIG turn

−

off sequence

is required

STA339BW Electrical specifications

Doc ID 15251 Rev 5 19/77

3.7 Testing

3.7.1 Functional pin definition

Figure 5. Test circuit 1

Figure 6. Test circuit 2

Table 8. Functional pin definition

Pin name Number Logic value IC status

PWRDN 23 0 Low consumption

1 Normal operation

TWARN 20 0 A temperature warning is indicated by the external power

stage

1 Normal operation

EAPD 19 0 Low consumption for power stage

All internal regulators are switched off

1 Normal operation

DTr DTf

Vcc

(3/4)Vcc

(1/2)Vcc

(1/4)Vcc

OUTxY

Low current dead time = MAX(DTr, DTf)

+Vcc

Duty cycle = 50%

INxY OUTxY

gnd

vdc = Vcc/2

Rload = 8 Ω

High current dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B))

+VCC

Rload = 4 Ω

OUTxB

DTout(B) DTin(B)

DTout(A)

470nF 470nF470nF

Iout

INxB

D06AU1651_00

INxA

DTin(A)

Duty cycle=A Duty cycle=B

Duty cycle A and B: Fixed to have DC output current of Iout in the direction shown in figure

10µ10µ

OUTxA

Processing data paths STA339BW

20/77 Doc ID 15251 Rev 5

4 Processing data paths

The whole processing chain is composed of two consecutive sections. In the first one

dual-channel processing is implemented, as described below. Then each channel is fed into

the post-mixing block where there is a choice of processing, either the dual-band DRC is

disabled or it is enabled. When B2DRC is disabled a third channel, typically used in 2.1

output configuration and with cross-over filters enabled, is used. When B2DRC is enabled

the 2.0 output configuration with cross-over filters for defining the cutoff frequency of the two

bands is used.

The first section, Figure 7, begins with a 2x oversampling FIR filter allowing a 2 * fs audio

processing. Then a selectable high-pass filter removes the DC level (enabled if HFB = 0).

The channel 1 and 2 processing chain can include up to 8 filters, depending on the selected

configuration (bits BQL, BQ5, BQ6, BQ7 and XO[3:0]).

By default, four independent filters per channel are enabled, plus the preconfigured de-

emphasis, bass and treble controls (BQL = 0, BQ5 = 0, BQ6 = 0, BQ7 = 0).

If the coefficient sets are linked (BQL = 1) then it is possible to use the de-emphasis, bass

and treble filter in a user defined configuration (provided the relevant BQx bits are set to 1).

In other words both channels use the same processing coefficients and can have up to 7

filters each. Note that if BQL = 0 the BQx bits are ignored and the 5th, 6th and 7th filters are

configured as de-emphasis, bass and treble controls, respectively.

Moreover the common 8th filter, from the subsequent processing section, can be available

on both channels (provided the pre-defined cross-over frequencies are not used,

XO[3:0] = 0, and the dual-band DRC is not used).

In the second section, mixing and crossover filters are available. If B2DRC is not enabled

(lower schematic in Figure 8) they are fully user-programmable and allow a third channel

(2.1 outputs) to be generated. Alternatively, in B2DRC mode (upper schematic in Figure 8),

those blocks will be used to split the sub-band and define the cutoff frequencies of the two

bands. A prescaler and a final post scaler allow full control over the signal dynamics before

and after, respectively, the filtering stages. A mixer function is also available.

Figure 7. Left and right processing part 1

From

I2S input

interface

PreScale Pass

Filter

Biquad

If HPB=0 User-defined filters

If DSPB=0 and C1EQBP=0

FIR

over

Sampling

frequency = fs

Sampling

frequency = 2 * fs

Pre-scale Hi-pass

filter

Biquad

#4 De-Emph.

If DEMP=0

FIR

over

sampling

Bass Treble

If C1TCB=0

BTC: bass boost/cut

TTC: treble boost/cut

PreScale Pass

Filter

Biquad

If HPB=0 User-defined filters

If DSPB=0 and C2EQBP=0

FIR

over

Pre-scale Hi-pass

filter

Biquad

#4 De-Emph.

If DEMP=0

FIR

over

sampling

Bass Treble

If C2TCB=0

BTC: bass boost/cut

TTC: treble boost/cut

If BQ5=1

and BQL=1

Biquad

If BQ6=1

and BQL=1

Biquad

IF BQ7=1

and BQL=1

Biquad

If BQ5=1

and BQL=1

Biquad

If BQ6=1

and BQL=1

Biquad

IF BQ7=1

and BQL=1

Biquad

From

I2S input

interface

PreScale Pass

Filter

Biquad

If HPB=0 User-defined filters

If DSPB=0 and C1EQBP=0

FIR

over

Sampling

frequency = fs

Sampling

frequency = 2 * fs

Pre-scale Hi-pass

filter

Biquad

#4 De-Emph.

If DEMP=0

FIR

over

sampling

Bass Treble

If C1TCB=0

BTC: bass boost/cut

TTC: treble boost/cut

PreScale Pass

Filter

Biquad

If HPB=0 User-defined filters

If DSPB=0 and C2EQBP=0

FIR

over

Pre-scale Hi-pass

filter

Biquad

#4 De-Emph.

If DEMP=0

FIR

over

sampling

Bass Treble

If C2TCB=0

BTC: bass boost/cut

TTC: treble boost/cut

If BQ5=1

and BQL=1

Biquad

If BQ6=1

and BQL=1

Biquad

IF BQ7=1

and BQL=1

Biquad

If BQ5=1

and BQL=1

Biquad

If BQ6=1

and BQL=1

Biquad

IF BQ7=1

and BQL=1

Biquad

STA339BW Processing data paths

Doc ID 15251 Rev 5 21/77

Figure 8. Processing part 2

Crossover frequency determined by XO setting

User defined if XO = 0000

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Hi-Pass XO

Filter

Hi-Pass XO

Filter

Lo-Pass XO

Filter

User-defined mix coefficients

Vol

And

Limiter

Vol

And

Limiter

Vol

And

Limiter

Post scale

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Channel 1/2

Biquad #5

--------------

Hi-pass XO

filter

Volume

and

Limiter

Volume

and

Limiter

Volume

and

Limiter

Post-scale

Channel 1/2

Biquad #5

--------------

Hi-pass XO

filter

Channel 3

Biquad

--------------

Low-pass XO

filter

B2DRC Disabled

Crossover frequency determined by XO setting

User defined if XO = 0000

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Hi-Pass XO

Filter

Hi-Pass XO

Filter

Lo-Pass XO

Filter

User-defined mix coefficients

Vol

And

Limiter

Vol

And

Limiter

Vol

And

Limiter

Post scale

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Channel 1/2

Biquad #5

--------------

Hi-pass XO

filter

Volume

and

Limiter

Volume

and

Limiter

Volume

and

Limiter

Post-scale

Channel 1/2

Biquad #5

--------------

Hi-pass XO

filter

Channel 3

Biquad

--------------

Low-pass XO

filter

B2DRC Disabled

Dual-band DRC disabled

Crossover frequency determined by XO setting

User-defined if XO = 0000

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Hi-Pass XO

Filter

Hi-Pass XO

Filter

User-defined mix coefficients

Post scale

C1Mx2 =

0x00000

C2Mx1=

0x000000

C2Mx2 =

0x7FFFFF

C3Mx1 =

0x40000

C3Mx2 =

0x400000

C1Mx1 =

0x7FFFFF

B2DRC

Hi-pass

filter

Post-scale

Vol

And

Limiter

DRC1

DRC2

Ch1

Volume

Ch2

Volume

Ch3

Volume

B2DRC

Hi-pass

filter

B2DRC Enabled

DRC2

Ch3

Volume

Crossover frequency determined by XO setting

User-defined if XO = 0000

C1Mx2

C2Mx1

C2Mx2

C3Mx1

C3Mx2

C1Mx1

Hi-Pass XO

Filter

Hi-Pass XO

Filter

User-defined mix coefficients

Post scale

C1Mx2 =

0x00000

C2Mx1=

0x000000

C2Mx2 =

0x7FFFFF

C3Mx1 =

0x40000

C3Mx2 =

0x400000

C1Mx1 =

0x7FFFFF

B2DRC

Hi-pass

filter

Post-scale

Vol

And

Limiter

DRC1

DRC2

Ch1

Volume

Ch2

Volume

Ch3

Volume

B2DRC

Hi-pass

filter

B2DRC Enabled

DRC2

Ch3

Volume

Dual-band DRC enabled

I2C bus specification STA339BW

22/77 Doc ID 15251 Rev 5

5 I2C bus specification

The STA339BW supports the I2C protocol via the input ports SCL and SDA_IN (master to

slave) and the output port SDA_OUT (slave to master). This protocol defines any device that

sends data on to the bus as a transmitter and any device that reads the data as a receiver.

The device that controls the data transfer is known as the master and the other as the slave.

The master always starts the transfer and provides the serial clock for synchronization. The

STA339BW is always a slave device in all of its communications. It can operate at up to

400 kb/s (fast-mode bit rate). The STA339BW I2C interface is a slave only interface.

5.1 Communication protocol

5.1.1 Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition

while the clock is high is used to identify a START or STOP condition.

5.1.2 Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A START condition must precede any command for

data transfer.

5.1.3 Stop condition

STOP is identified by low to high transition of the data bus SDA signal while the clock signal

SCL is stable in the high state. A STOP condition terminates communication between

STA339BW and the bus master.

5.1.4 Data input

During the data input the STA339BW samples the SDA signal on the rising edge of clock

SCL. For correct device operation the SDA signal must be stable during the rising edge of

the clock and the data can change only when the SCL line is low.

5.2 Device addressing

To start communication between the master and the STA339BW, the master must initiate

with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first)

corresponding to the device select address and read or write mode.

The seven most significant bits are the device address identifiers, corresponding to the I2C

bus definition. In the STA339BW the I2C interface has two device addresses depending on

the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode

and to 0 for write mode. After a START condition the STA339BW identifies on the bus the

device address and if a match is found, acknowledges the identification on the SDA bus

during the 9th bit time. The byte following the device identification byte is the internal space

address.

STA339BW I2C bus specification

Doc ID 15251 Rev 5 23/77

5.3 Write operation

Following the START condition the master sends a device select code with the RW bit set

to 0. The STA339BW acknowledges this and the writes for the byte of internal address. After

receiving the internal byte address the STA339BW again responds with an

acknowledgement.

5.3.1 Byte write

In the byte write mode the master sends one data byte, this is acknowledged by the

STA339BW. The master then terminates the transfer by generating a STOP condition.

5.3.2 Multi-byte write

The multi-byte write modes can start from any internal address. The master generating a

STOP condition terminates the transfer.

5.4 Read operation

5.4.1 Current address byte read

Following the START condition the master sends a device select code with the RW bit set

to 1. The STA339BW acknowledges this and then responds by sending one byte of data.

The master then terminates the transfer by generating a STOP condition.

5.4.2 Current address multi-byte read

The multi-byte read modes can start from any internal address. Sequential data bytes are

read from sequential addresses within the STA339BW. The master acknowledges each

data byte read and then generates a STOP condition terminating the transfer.

5.4.3 Random address byte read

Following the START condition the master sends a device select code with the RW bit set

to 0. The STA339BW acknowledges this and then the master writes the internal address

byte. After receiving, the internal byte address the STA339BW again responds with an

acknowledgement. The master then initiates another START condition and sends the device

select code with the RW bit set to 1. The STA339BW acknowledges this and then responds

by sending one byte of data. The master then terminates the transfer by generating a STOP

condition.

5.4.4 Random address multi-byte read

The multi-byte read modes could start from any internal address. Sequential data bytes are

read from sequential addresses within the STA339BW. The master acknowledges each

data byte read and then generates a STOP condition terminating the transfer.

I2C bus specification STA339BW

24/77 Doc ID 15251 Rev 5

5.4.5 Write mode sequence

Figure 9. Write mode sequence

5.4.6 Read mode sequence

Figure 10. Read mode sequence

DEV-ADDR

ACK

START RW

SUB-ADDR

ACK

DATA IN

STOP

BYTE

WRITE

DEV-ADDR

ACK

START RW

SUB-ADDR

ACK

DATA IN

STOP

MULTIBYTE

WRITE

DATA IN

DEV-ADDR

ACK

START RW

DATA

NO ACK

STOP

CURRENT

ADDRESS

READ

DEV-ADDR

ACK

START RW

SUB-ADDR

ACK

DEV-ADDR

ACK

STOP

RANDOM

ADDRESS

READ

DATA

START RW

DEV-ADDR

ACK

START

DATA

ACK

DATA

ACK

STOP

SEQUENTIAL

CURRENT

READ

DATA

DEV-ADDR

ACK

START RW

SUB-ADDR

ACK

DEV-ADDR

ACK

SEQUENTIAL

RANDOM

READ

DATA

START RW

DATA

CK NO

STOP

DATA

RW=

HIGH

STA339BW Register description

Doc ID 15251 Rev 5 25/77

6 Register description

Table 9. Register summary

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

0x00 CONFA FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

0x01 CONFB C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

0x02 CONFC OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

0x03 CONFD SME ZDE DRC BQL PSL DSPB DEMP HPB

0x04 CONFE SVE ZCE DCCV PWMS AME NSBW MPC MPCV

0x05 CONFF EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0

0x06 MUTE/LOC LOC1 LOC0 Reserved C3M C2M C1M MMUTE

0x07 MVOL MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0

0x08 C1VOL C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0

0x09 C2VOL C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0

0x0A C3VOL C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0

0x0B AUTO1 Reserved AMGC1 AMGC0 Reserved

0x0C AUTO2 XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

0x0D AUTO3 Reserved

0x0E C1CFG C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB

0x0F C2CFG C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB

0x10 C3CFG C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VBP Reserved

0x11 TONE TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

0x12 L1AR L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

0x13 L1ATRT L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

0x14 L2AR L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

0x15 L2ATRT L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

0x16 CFADDR Reserved CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

0x17 B1CF1 C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

0x18 B1CF2 C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

0x19 B1CF3 C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0

0x1A B2CF1 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

0x1B B2CF2 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

0x1C B2CF3 C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

0x1D A1CF1 C3B23 C3B22 C3B21 C3B20 C3B19 C3B18 C3B17 C3B16

0x1E A1CF2 C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

0x1F A1CF3 C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0

26/77 Doc ID 15251 Rev 5

0x20 A2CF1 C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

0x21 A2CF2 C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

0x22 A2CF3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0

0x23 B0CF1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

0x24 B0CF2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

0x25 B0CF3 C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0

0x26 CFUD Reserved RA R1 WA W1

0x27 MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8

0x28 MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

0x29 DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8

0x2A DCC2 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0

0x2B FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

0x2C FDRC2 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

0x2D STATUS PLLUL FAULT UVFAULT OVFAULT OCFAULT OCWARN TFAULT TWARN

0x2E Reserved Reserved RO1BACT R5BACT R4BACT R3BACT R2BACT R1BACT

0x2F Reserved Reserved R01BEND R5BEND R4BEND R3BEND R2BEND R1BEND

0x30 Reserved Reserved R5BBAD R4BBAD R3BBAD R2BBAD R1BBAD

0x31 EQCFG XOB Reserved AMGC3 AMGC2 Reserved SEL1 SEL0

0x32 EATH1 E AT H E N 1 E AT H 1 [ 6 ] E AT H 1 [ 5 ] E AT H 1 [ 4 ] E AT H 1 [ 3 ] E AT H 1 [ 2 ] E AT H 1 [ 1 ] E AT H 1 [ 0 ]

0x33 ERTH1 ERTHEN1 ERTH1[6] ERTH1[5] ERTH1[4] ERTH1[3] ERTH1[2] ERTH1[1] ERTH1[0]

0x34 EATH2 E AT H E N 2 E AT H 2 [ 6 ] E AT H 2 [ 5 ] E AT H 2 [ 4 ] E AT H 2 [ 3 ] E AT H 2 [ 2 ] E AT H 2 [ 1 ] E AT H 2 [ 0 ]

0x35 ERTH2 ERTHEN2 ERTH2[6] ERTH2[5] ERTH2[4] ERTH2[3] ERTH2[2] ERTH2[1] ERTH2[0]

0x36 CONFX MDRC[1] MDRC[0] PS48DB XAR1 XAR2 BQ5 BQ6 BQ7

0x37 SVCA Reserved SVUPE SVUP[4] SVUP[3] SVUP[2] SVUP[1] SVUP[0]

0x38 SVCB Reserved SVDWE SVDW[4] SVDW[3] SVDW[2] SVDW[1] SVDW[0]

0x39 RMS0A R_C0[23] R_C0[22] R_C0[21] R_C0[20] R_C0[19] R_C0[18] R_C0[17] R_C0[16]

0x3A RMS0B R_C0[15] R_C0[14] R_C0[13] R_C0[12] R_C0[11] R_C0[10] R_C0[9] R_C0[8]

0x3B RMS0C R_C0[7] R_C0[6] R_C0[5] R_C0[4] R_C0[3] R_C0[2] R_C0[1] R_C0[0]

0x3C RMS1A R_C1[23] R_C1[22] R_C1[21] R_C1[20] R_C1[19] R_C1[18] R_C1[17] R_C1[16]

0x3D RMS1B R_C1[15] R_C1[14] R_C1[13] R_C1[12] R_C1[11] R_C1[10] R_C1[9] R_C1[8]

0x3E RMS1C R_C1[7] R_C1[6] R_C1[5] R_C1[4] R_C1[3] R_C1[2] R_C1[1] R_C1[0]

Table 9. Register summary (continued)

Addr Name D7 D6 D5 D4 D3 D2 D1 D0

STA339BW Register description

Doc ID 15251 Rev 5 27/77

6.1 Configuration register A (addr 0x00)

6.1.1 Master clock select

The STA339BW supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. Therefore the internal clock is:

z32.768 MHz for 32 kHz

z45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz

z49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample

frequency (fs).

The relationship between the input clock and the input sample rate is determined by both

the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor

generating the internal clock and the IR bit determines the oversampling ratio used

internally.

D7 D6 D5 D4 D3 D2 D1 D0

FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0

01100011

Table 10. Master clock select

Bit R/W RST Name Description

0R/W1 MCS0

Selects the ratio between the input I2S sample

frequency and the input clock.

1R/W1 MCS1

2R/W0 MCS2

Table 11. Input sampling rates

Input sample rate

fs (kHz) IR MCS[2:0]

-- 101 100 011 010 001 000

32, 44.1, 48 00 576 * fs 128 * fs 256 * fs 384 * fs 512 * fs 768 * fs

88.2, 96 01 NA 64 * fs 128 * fs 192 * fs 256 * fs 384 * fs

176.4, 192 1X NA 32 * fs 64 * fs 96 * fs 128 * fs 192 * fs

28/77 Doc ID 15251 Rev 5

6.1.2 Interpolation ratio select

The STA339BW has variable interpolation (oversampling) settings such that internal

processing and FFX output rates remain consistent. The first processing block interpolates

by either 2-times or 1-time (pass-through) or provides a 2-times downsample. The

oversampling ratio of this interpolation is determined by the IR bits.

6.1.3 Thermal warning recovery bypass

If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning

recovery determines if the -3 dB output limit is removed when thermal warning is negative.

If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit

is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then

when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to

zero or the device is reset.

6.1.4 Thermal warning adjustment bypass

The on-chip STA339BW power output block provides feedback to the digital controller using

inputs to the power control block. Input TWARN is used to indicate a thermal warning

Table 12. Internal interpolation ratio

Bit R/W RST Name Description

4:3 R/W 00 IR [1:0] Selects internal interpolation ratio based on input I2S

sample frequency

Table 13. IR bit settings as a function of input sample rate

Input sample rate fs (kHz) IR 1st stage interpolation ratio

32 00 2 times oversampling

44.1 00 2 times oversampling

48 00 2 times oversampling

88.2 01 Pass-through

96 01 Pass-through

176.4 10 2 times downsampling

192 10 2 times downsampling

Table 14. Thermal warning recovery bypass

Bit R/W RST Name Description

5R/W1 TWRB 0: Thermal warning recovery enabled

1: Thermal warning recovery disabled

Table 15. Thermal warning adjustment bypass

Bit R/W RST Name Description

6R/W1 TWAB 0: Thermal warning adjustment enabled

1: Thermal warning adjustment disabled

STA339BW Register description

Doc ID 15251 Rev 5 29/77

condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the

power control block forces a -3 dB output limit (determined by TWOCL in the coefficient

RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once

the thermal warning output limit adjustment is applied, it remains in this state until reset,

unless FDRB = 0.

6.1.5 Fault detect recovery bypass

The on-chip STA339BW power output block provides feedback to the digital controller using

inputs to the power control block. The FAULT input is used to indicate a fault condition (either

overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts

a recovery from the fault by asserting the tri-state output (setting it to 0 which directs the

power output block to begin recovery), holds it at 0 for period of time in the range of 0.1 ms

to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x2B-

0x2C), then toggles it back to 1. This sequence is repeated as log as the fault indication

exists. This feature is enabled by default but can be bypassed by setting the FDRB control

bit to 1.

6.2 Configuration register B (addr 0x01)

6.2.1 Serial audio input interface format

Table 16. Fault detect recovery bypass

Bit R/W RST Name Description

7 R/W 0 FDRB 0: fault detect recovery enabled

1: fault detect recovery disabled

D7 D6 D5 D4 D3 D2 D1 D0

C2IM C1IM DSCKE SAIFB SAI3 SAI2 SAI1 SAI0

10000000

Table 17. Serial audio input interface

Bit R/W RST Name Description

0R/W0 SAI0

Determines the interface format of the input serial

digital audio interface.

1R/W0 SAI1

2R/W0 SAI2

3R/W0 SAI3

30/77 Doc ID 15251 Rev 5

6.2.2 Serial data interface

The STA339BW audio serial input was designed to interface with standard digital audio

components and to accept a number of serial data formats. STA339BW always acts as slave

when receiving audio input from standard digital audio components. Serial data for two

channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial

data 1 and 2 SDI12.

The SAI bits (D3 to D0) and the SAIFB bit (D4) are used to specify the serial data format.

The default serial data format is I2S, MSB-first. Available formats are shown in the tables

and figure that follow.

6.2.3 Serial data first bit

Table 18. Serial data first bit

SAIFB Format

0 MSB-first

1 LSB-first

Table 19. Supported serial audio input formats for MSB-first (SAIFB = 0)

BICKI SAI [3:0] SAIFB Interface format

32 * fs 0000 0 I2S 15-bit data

0001 0 Left/right-justified 16-bit data

48 * fs

0000 0 I2S 16 to 23-bit data

0001 0 Left-justified 16 to 24-bit data

0010 0 Right-justified 24-bit data

0110 0 Right-justified 20-bit data

1010 0 Right-justified 18-bit data

1110 0 Right-justified 16-bit data

64 * fs

0000 0 I2S 16 to 24-bit data

0001 0 Left-justified 16 to 24-bit data

0010 0 Right-justified 24-bit data

0110 0 Right-justified 20-bit data

1010 0 Right-justified 18-bit data

1110 0 Right-justified 16-bit data

STA339BW Register description

Doc ID 15251 Rev 5 31/77

To make the STA339BW work properly, the serial audio interface LRCKI clock must be

synchronous to the PLL output clock. It means that:

the frequency of PLL clock / frequency of LRCKI = N ±4 cycles,

where N depends on the settings in Table 13 on page 28

the PLL must be locked.

If these two conditions are not met, and bit IDE of register address 0x05 is set to 1, the

STA339BW immediately mutes the I2S PCM data out (provided to the processing block) and

it freezes any active processing task.

To avoid any audio side effects (like pop noise), it is strongly recommended to soft mute any

audio streams flowing into STA339BW data path before the desynchronization event

Table 20. Supported serial audio input formats for LSB-first (SAIFB = 1)

BICKI SAI [3:0] SAIFB Interface format

32 * fs 1100 1 I2S 15-bit data

1110 1 Left/right-justified 16-bit data

48 * fs

0100 1 I2S 23-bit data

0100 1 I2S 20-bit data

1000 1 I2S 18-bit data

1100 1 LSB first I2S 16-bit data

0001 1 Left-justified 24-bit data

0101 1 Left-justified 20-bit data

1001 1 Left-justified 18-bit data

1101 1 Left-justified 16-bit data

0010 1 Right-justified 24-bit data

0110 1 Right-justified 20-bit data

1010 1 Right-justified 18-bit data

1110 1 Right-justified 16-bit data

64 * fs

0000 1 I2S 24-bit data

0100 1 I2S 20-bit data

1000 1 I2S 18-bit data

1100 1 LSB first I2S 16-bit data

0001 1 Left-justified 24-bit data

0101 1 Left-justified 20-bit data

1001 1 Left-justified 18-bit data

1101 1 Left-justified 16-bit data

0010 1 Right-justified 24-bit data

0110 1 Right-justified 20-bit data

1010 1 Right-justified 18-bit data

1110 1 Right-justified 16-bit data

32/77 Doc ID 15251 Rev 5

happens. At the same time any processing related to the I2C configuration should be issued

only after the serial audio interface and the internal PLL are synchronous again.

Note: Any mute or volume change causes some delay in the completion of the I2C operation due

to the soft volume feature. The soft volume phase change must be finished before any clock

desynchronization.

6.2.4 Delay serial clock enable

6.2.5 Channel input mapping

Each channel received via I2S can be mapped to any internal processing channel via the

Channel Input Mapping registers. This allows for flexibility in processing. The default

settings of these registers map each I2S input channel to its corresponding processing

channel.

Table 21. Delay serial clock enable

Bit R/W RST Name Description

5 R/W 0 DSCKE

0: No serial clock delay

1: Serial clock delay by 1 core clock cycle to tolerate

anomalies in some I2S master devices

Table 22. Channel input mapping

Bit R/W RST Name Description

6R/W0 C1IM 0: Processing channel 1 receives Left I2S Input

1: Processing channel 1 receives Right I2S Input

7R/W1 C2IM 0: Processing channel 2 receives Left I2S Input

1: Processing channel 2 receives Right I2S Input

STA339BW Register description

Doc ID 15251 Rev 5 33/77

6.3 Configuration register C (addr 0x02)

6.3.1 FFX power output mode

The FFX power output mode selects how the FFX output timing is configured.

Different power devices use different output modes.

6.3.2 FFX compensating pulse size register

D7 D6 D5 D4 D3 D2 D1 D0

OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0

10011111

Table 23. FFX power output mode

Bit R/W RST Name Description

0R/W1 OM0 Selects configuration of FFX output.

1R/W1 OM1

Table 24. Output modes

OM[1,0] Output stage mode

00 Drop compensation

01 Discrete output stage - tapered compensation

10 Full power mode

11 Variable drop compensation (CSZx bits)

Table 25. FFX compensating pulse size bits

Bit R/W RST Name Description

2R/W1 CSZ0

When OM[1,0] = 11, this register determines the

size of the FFX compensating pulse from 0 clock

ticks to 15 clock periods.

3R/W1 CSZ1

4R/W1 CSZ2

5R/W0 CSZ3

Table 26. Compensating pulse size

CSZ[3:0] Compensating pulse size

0000 0 ns (0 tick) compensating pulse size

0001 20 ns (1 tick) clock period compensating pulse size

……

1111 300 ns (15 tick) clock period compensating pulse size

34/77 Doc ID 15251 Rev 5

6.3.3 Overcurrent warning detect adjustment bypass

The OCWARN input is used to indicate an overcurrent warning condition. When OCWARN

is asserted (set to 0), the power control block forces an adjustment to the modulation limit

(default is -3 dB) in an attempt to eliminate the overcurrent warning condition. Once the

overcurrent warning volume adjustment is applied, it remains in this state until reset is

applied. The level of adjustment can be changed via the TWOCL (thermal warning /

overcurrent limit) setting which is address 0x37 of the user defined coefficient RAM.

6.4 Configuration register D (addr 0x03)

6.4.1 High-pass filter bypass

The STA339BW features an internal digital high-pass filter for the purpose of AC coupling.

The purpose of this filter is to prevent DC signals from passing through a FFX amplifier. DC

signals can cause speaker damage. When HPB = 0, this filter is enabled.

6.4.2 De-emphasis

6.4.3 DSP bypass

Setting the DSPB bit bypasses the EQ function of the STA339BW.

Table 27. Overcurrent warning bypass

Bit R/W RST Name Description

7 R/W 1 OCRB 0: overcurrent warning adjustment enabled

1: overcurrent warning adjustment disabled

D7 D6 D5 D4 D3 D2 D1 D0

SME ZDE DRC BQL PSL DSPB DEMP HPB

01000000

Table 28. High-pass filter bypass

Bit R/W RST Name Description

0R/W0 HPB Setting of one bypasses internal AC coupling digital

high-pass filter

Table 29. De-emphasis

Bit R/W RST Name Description

1R/W0 DEMP 0: No de-emphasis

1: Enable de-emphasis on all channels

Table 30. DSP bypass

Bit R/W RST Name Description

2 R/W 0 DSPB 0: Normal operation

1: Bypass of biquad and bass/treble functions

STA339BW Register description

Doc ID 15251 Rev 5 35/77

6.4.4 Post-scale link

Post-scale functionality can be used for power-supply error correction. For multi-channel

applications running off the same power-supply, the post-scale values can be linked to the

value of channel 1 for ease of use and update the values faster.

6.4.5 Biquad coefficient link

For ease of use, all channels can use the biquad coefficients loaded into the Channel-1

coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to

be performed once.

6.4.6 Dynamic range compression/anti-clipping bit

Both limiters can be used in one of two ways, anti-clipping or dynamic range compression.

When used in anti-clipping mode the limiter threshold values are constant and dependent on

the limiter settings. In dynamic range compression mode the limiter threshold values vary

with the volume settings allowing a nighttime listening mode that provides a reduction in the

dynamic range regardless of the volume level.

6.4.7 Zero-detect mute enable

Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at

the data for each processing channel at the output of the crossover (bass management)

filter. If any channel receives 2048 consecutive zero value samples (regardless of fs) then

that individual channel is muted if this function is enabled.

Table 31. Post-scale link

Bit R/W RST Name Description

3R/W0 PSL 0: Each channel uses individual post-scale value

1: Each channel uses channel 1 post-scale value

Table 32. Biquad coefficient link

Bit R/W RST Name Description

4R/W0 BQL 0: Each channel uses coefficient values

1: Each channel uses channel 1 coefficient values

Table 33. Dynamic range compression/anti-clipping bit

Bit R/W RST Name Description

5 R/W 0 DRC 0: Limiters act in anti-clipping mode

1: Limiters act in dynamic range compression mode

Table 34. Zero-detect mute enable

Bit R/W RST Name Description

6 R/W 1 ZDE Setting of 1 enables the automatic zero-detect mute

36/77 Doc ID 15251 Rev 5

6.4.8 Submix mode enable

6.5 Configuration register E (addr 0x04)

6.5.1 Max power correction variable

6.5.2 Max power correction

Setting the MPC bit turns on special processing that corrects the STA339BW power device

at high power. This mode should lower the THD+N of a full FFX system at maximum power

output and slightly below. If enabled, MPC is operational in all output modes except tapered

(OM[1,0] = 01) and binary. When OCFG = 00, MPC will not effect channels 3 and 4, the line-

out channels.

6.5.3 Noise-shaper bandwidth selection

Table 35. Submix mode enable

Bit R/W RST Name Description

7R/W0 SME 0: Sub Mix into Left/Right disabled

1: Sub Mix into Left/Right enabled

D7 D6 D5 D4 D3 D2 D1 D0

SVE ZCE DCCV PWMS AME NSBW MPC MPCV

11000010

Table 36. Max power correction variable

Bit R/W RST Name Description

0R/W0 MPCV 0: Use standard MPC coefficient

1: Use MPCC bits for MPC coefficient

Table 37. Max power correction

Bit R/W RST Name Description

1R/W1 MPC Setting of 1 enables Power Bridge correction for

THD reduction near maximum power output.

Table 38. Noise-shaper bandwidth selection

Bit R/W RST Name Description

2 R/W 0 NSBW 1: Third order NS

0: Fourth order NS

STA339BW Register description

Doc ID 15251 Rev 5 37/77

6.5.4 AM mode enable

STA339BW features aFFX processing mode that minimizes the amount of noise generated

in frequency range of AM radio. This mode is intended for use when FFX is operating in a

device with an AM tuner active. The SNR of the FFX processing is reduced to approximately

83 dB in this mode, which is still greater than the SNR of AM radio.

6.5.5 PWM speed mode

6.5.6 Distortion compensation variable enable

6.5.7 Zero-crossing volume enable

The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital

zero-crossings no clicks are audible.

6.5.8 Soft volume update enable

Table 39. AM mode enable

Bit R/W RST Name Description

3R/W0 AME 0: Normal FFX operation.

1: AM reduction mode FFX operation

Table 40. PWM speed mode

Bit R/W RST Name Description

4R/W0 PWMS 0: Normal speed (384 kHz) all channels

1: Odd speed (341.3 kHz) all channels

Table 41. Distortion compensation variable enable

Bit R/W RST Name Description

5 R/W 0 DCCV 0: Use preset DC coefficient

1: Use DCC coefficient

Table 42. Zero-crossing volume enable

Bit R/W RST Name Description

6R/W1 ZCE

1: Volume adjustments only occur at digital zero-

crossings

0: Volume adjustments occur immediately

Table 43. Soft volume update enable

Bit R/W RST Name Description

7 R/W 1 SVE 1: Volume adjustments ramp according to SVR settings

0: Volume adjustments occur immediately

38/77 Doc ID 15251 Rev 5

6.6 Configuration register F (addr 0x05)

6.6.1 Output configuration

Note: To the left of the arrow is the processing channel. When using channel output mapping, any

of the three processing channel outputs can be used for any of the three inputs.

D7 D6 D5 D4 D3 D2 D1 D0

EAPD PWDN ECLE LDTE BCLE IDE OCFG1 OCFG0

01011100

Table 44. Output configuration

Bit R/W RST Name Description

0 R/W 0 OCFG0 Selects the output configuration

1 R/W 0 OCFG1

Table 45. Output configuration engine selection

OCFG[1:0] Output configuration Config pin

2 channel (full-bridge) power, 2 channel data-out:

1A/1B → 1A/1B

2A/2B → 2A/2B

LineOut1 → 3A/3B

LineOut2 → 4A/4B

Line Out Configuration determined by LOC register

2(Half-Bridge).1(Full-Bridge) On-Board Power:

1A → 1A Binary 0 °

2A → 1B Binary 90°

3A/3B → 2A/2B Binary 45°

1A/B → 3A/B Binary 0°

2A/B → 4A/B Binary 90°

2 Channel (Full-Bridge) Power, 1 Channel FFX:

1A/1B → 1A/1B

2A/2B → 2A/2B

3A/3B → 3A/3B

EAPDEXT and TWARNEXT Active

1 Channel Mono-Parallel:

3A → 1A/1B w/ C3BO 45°

3B → 2A/2B w/ C3BO 45°

1A/1B → 3A/3B

2A/2B → 4A/4B

STA339BW Register description

Doc ID 15251 Rev 5 39/77

Figure 11. OCFG = 00 (default value)

Figure 12. OCFG = 01

Figure 13. OCFG = 10

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 2

Channel 1

LPF

LineOut 1

OUT3B

LPF

LineOut 2

OUT4B

OUT4A

OUT3A

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 3

Channel 1

Channel 2

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 2

Channel 1

Power

Device

OUT3B

OUT3A

EAPD

Channel 3

40/77 Doc ID 15251 Rev 5

Figure 14. OCFG = 11

The STA339BW can be configured to support different output configurations. For each PWM

output channel a PWM slot is defined. A PWM slot is always 1 / (8 * fs) seconds length. The

PWM slot define the maximum extension for PWM rise and fall edge, that is, rising edge as

far as the falling edge cannot range outside PWM slot boundaries.

Figure 15. Output mapping scheme

For each configuration the PWM signals from the digital driver are mapped in different ways

to the power stage:

Half

Bridge

Half

Bridge

Half

Bridge

Half

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

Channel 3

OUT3B

OUT4B

OUT4A

OUT3A

Channel 1

Channel 2

FFX ™

modulator

REMAP

FFX1A

FFX1 B

FFX2 A

FFX 2B

OUT1A

OUT1B

OUT2A

OUT2B

Power

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

FFX3 A

FFX3B

FFX4 A

FFX 4B

OUT3A

OUT3B

OUT4A

OUT4B

FFX ™

modulator

REMAP

FFX1A

FFX1 B

FFX2 A

FFX 2B

OUT1A

OUT1B

OUT2A

OUT2B

Power

Bridge

OUT1A

OUT1B

OUT2A

OUT2B

FFX3 A

FFX3B

FFX4 A

FFX 4B

OUT3A

OUT3B

OUT4A

OUT4B

STA339BW Register description

Doc ID 15251 Rev 5 41/77

2.0 channels, two full bridges (OCFG = 00)

zFFX1A -> OUT1A

zFFX1B -> OUT1B

zFFX2A -> OUT2A

zFFX2B -> OUT2B

zFFX3A -> OUT3A

zFFX3B -> OUT3B

zFFX4A -> OUT4A

zFFX4B -> OUT4B

zFFX1A/1B configured as ternary

zFFX2A/2B configured as ternary

zFFX3A/3B configured as lineout ternary

zFFX4A/4B configured as lineout ternary

On channel 3 line out (LOC bits = 00) the same data as channel 1 processing is sent. On

channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this

configuration, volume control or EQ have no effect on channels 3 and 4.

In this configuration the PWM slot phase is the following as shown in Figure 16.

Figure 16. 2.0 channels (OCFG = 00) PWM slots

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

42/77 Doc ID 15251 Rev 5

2.1 channels, two half bridges + one full bridge (OCFG = 01)

zFFX1A -> OUT1A

zFFX2A -> OUT1B

zFFX3A -> OUT2A

zFFX3B -> OUT2B

zFFX1A -> OUT3A

zFFX1B -> OUT3B

zFFX2A -> OUT4A

zFFX2B -> OUT4B

zFFX1A/1B configured as binary

zFFX2A/2B configured as binary

zFFX3A/3B configured as binary

zFFX4A/4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT3/OUT4

channels the channel 1 and channel 2 PWM are replicated.

In this configuration the PWM slot phase is the following as shown in Figure 17.

Figure 17. 2.1 channels (OCFG = 01) PWM slots

OUT1A

OUT2A

OUT2B

OUT3A

OUT3B

OUT1B

OUT4A

OUT4B

OUT1A

OUT2A

OUT2B

OUT3A

OUT3B

OUT1B

OUT4A

OUT4B

STA339BW Register description

Doc ID 15251 Rev 5 43/77

2.1 channels, two fullbridge + one external full bridge (OCFG = 10)

zFFX1A -> OUT1A

zFFX1B -> OUT1B

zFFX2A -> OUT2A

zFFX2B -> OUT2B

zFFX3A -> OUT3A

zFFX3B -> OUT3B

zEAPD -> OUT4A

zTWARN -> OUT4B

zFFX1A/1B configured as ternary

zFFX2A/2B configured as ternary

zFFX3A/3B configured as ternary

zFFX4A/4B is not used

In this configuration, channel 3 has full control (volume, EQ, etc…). On OUT4 channel the

external bridge control signals are muxed.

In this configuration the PWM slot phase is the following as shown in Figure 18.

Figure 18. 2.1 channels (OCFG = 10) PWM slots

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

44/77 Doc ID 15251 Rev 5

6.6.2 Invalid input detect mute enable

Setting the IDE bit enables this function, which looks at the input I2S data and automatically

mutes if the signals are perceived as invalid.

6.6.3 Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

6.6.4 LRCK double trigger protection

Actively prevents double trigger of LRCLK.

6.6.5 Auto EAPD on clock loss

When active, issues a power device power down signal (EAPD) on clock loss detection.

6.6.6 IC power down

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

to power down the power-stage, then the master clock to all internal hardware expect the

I2C block is gated. This places the IC in a very low power consumption state.

Table 46. Invalid input detect mute enable

Bit R/W RST Name Description

2R/W1 IDE Setting of 1 enables the automatic invalid input

detect mute

Table 47. Binary output mode clock loss detection

Bit R/W RST Name Description

3 R/W 1 BCLE Binary output mode clock loss detection enable

Table 48. LRCK double trigger protection

Bit R/W RST Name Description

4 R/W 1 LDTE LRCLK double trigger protection enable

Table 49. Auto EAPD on clock loss

Bit R/W RST Name Description

5 R/W 0 ECLE Auto EAPD on clock loss

Table 50. IC power down

Bit R/W RST Name Description

7R/W1 PWDN 0: IC power down low-power condition

1: IC normal operation

STA339BW Register description

Doc ID 15251 Rev 5 45/77

6.6.7 External amplifier power down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed on a low-power state (disabled). This

6.7 Volume control registers (addr 0x06 - 0x0A)

6.7.1 Mute/line output configuration register

Line output is only active when OCFG = 00. In this case LOC determines the line output

configuration. The source of the line output is always the channel 1 and 2 inputs.

6.7.2 Master volume register

6.7.3 Channel 1 volume

6.7.4 Channel 2 volume

Table 51. External amplifier power down

Bit R/W RST Name Description

7R/W0 EAPD 0: External power stage power down active

1: Normal operation

D7 D6 D5 D4 D3 D2 D1 D0

LOC1 LOC0 Reserved C3M C2M C1M MMUTE

00000000

Table 52. Line output configuration

LOC[1:0] Line output configuration

00 Line output fixed - no volume, no EQ

01 Line output variable - CH3 volume effects line output, no EQ

10 Line output variable with EQ - CH3 volume effects line output

D7 D6 D5 D4 D3 D2 D1 D0

MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0

11111111

D7 D6 D5 D4 D3 D2 D1 D0

C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0

01100000

D7 D6 D5 D4 D3 D2 D1 D0

C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0

01100000

46/77 Doc ID 15251 Rev 5

6.7.5 Channel 3 / line output volume

The Volume structure of the STA339BW consists of individual volume registers for each

channel and a master volume register that provides an offset to each channels volume

setting. The individual channel volumes are adjustable in 0.5 dB steps from +48 dB to -

80 dB.

As an example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for

channel 3 = +36 dB.

The master mute, when set to 1, mutes all channels at once, whereas the individual channel

mutes (CxM) mutes only that channel. Both the master mute and the channel mutes provide

a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum

volume setting at the internal processing rate (approximately 96 kHz).

A “hard (instantaneous) mute” can be obtained by programming a value of 0xFF (255) to

any channel volume register or the master volume register. When volume offsets are

provided via the master volume register any channel whose total volume is less than -80 dB

is muted.

All changes in volume take place at zero-crossings when ZCE = 1 (Configuration register E

(addr 0x04) on page 36) on a per channel basis as this creates the smoothest possible

volume transitions. When ZCE = 0, volume updates occur immediately.

D7 D6 D5 D4 D3 D2 D1 D0

C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0

01100000

Table 53. Master volume offset as a function of MV[7:0]

MV[7:0] Volume offset from channel value

00000000 (0x00) 0 dB

00000001 (0x01) -0.5 dB

00000010 (0x02) -1 dB

……

01001100 (0x4C) -38 dB

……

11111110 (0xFE) -127.5 dB

11111111 (0xFF) Hard master mute

Table 54. Channel volume as a function of CxV[7:0]

CxV[7:0] Volume

00000000 (0x00) +48 dB

00000001 (0x01) +47.5 dB

00000010 (0x02) +47 dB

……

01011111 (0x5F) +0.5 dB

01100000 (0x60) 0 dB

STA339BW Register description

Doc ID 15251 Rev 5 47/77

6.8 Audio preset registers (addr 0x0B and 0x0C)

6.8.1 Audio preset register 1 (addr 0x0B)

Using AMGC[3:0] bits, attack and release thresholds and rates are automatically configured

to properly fit application specific configurations. AMGC[3:2] is defined in register EQ

coefficients and DRC configuration register (addr 0x31) on page 65.

The AMGC[1:0] bits behave in two different ways depending on the value of AMGC[3:2].

When this value is 00 then bits AMGC[1:0] are defined below in Ta b l e 5 5 .

6.8.2 Audio preset register 2 (addr 0x0C)

01100001 (0x61) -0.5 dB

……

11010111 (0xD7) -59.5 dB

11011000 (0xD8) -60 dB

11011001 (0xD9) -61 dB

11011010 (0xDA) -62 dB

……

11101100 (0xEC) -80 dB

11101101 (0xED) Hard channel mute

……

11111111 (0xFF) Hard channel mute

Table 54. Channel volume as a function of CxV[7:0] (continued)

CxV[7:0] Volume

D7 D6 D5 D4 D3 D2 D1 D0

Reserved AMGC[1] AMGC[0] Reserved

00000000

Table 55. Audio preset gain compression/limiters selection for AMGC[3:2] = 00

AMGC[1:0] Mode

00 User programmable GC

01 AC no clipping 2.1

10 AC limited clipping (10%) 2.1

11 DRC night-time listening mode 2.1

D7 D6 D5 D4 D3 D2 D1 D0

XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME

00000000

48/77 Doc ID 15251 Rev 5

6.8.3 AM interference frequency switching

6.8.4 Bass management crossover

Table 56. AM interference frequency switching bits

Bit R/W RST Name Description

0 R/W 0 AMAME

Audio preset AM enable

0: switching frequency determined by PWMS setting

1: switching frequency determined by AMAM settings

Table 57. Audio preset AM switching frequency selection

AMAM[2:0] 48 kHz/96 kHz input fs 44.1 kHz/88.2 kHz input fs

000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz

001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz

010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz

011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz

100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz

101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz

110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz

Table 58. Bass management crossover

Bit R/W RST Name Description

4R/W0 XO0

Selects the bass-management crossover frequency.

A 1st-order hign-pass filter (channels 1 and 2) or a

2nd-order low-pass filter (channel 3) at the selected

frequency is performed.

5R/W0 XO1

6R/W0 XO2

7R/W0 XO3

Table 59. Bass management crossover frequency

XO[3:0] Crossover frequency

0000 User-defined

0001 80 Hz

0010 100 Hz

0011 120 Hz

0100 140 Hz

0101 160 Hz

0110 180 Hz

0111 200 Hz

1000 220 Hz

1001 240 Hz

STA339BW Register description

Doc ID 15251 Rev 5 49/77

6.9 Channel configuration registers (addr 0x0E - 0x10)

6.9.1 Tone control bypass

Tone control (bass/treble) can be bypassed on a per channel basis for channels 1 and 2.

6.9.2 EQ bypass

EQ control can be bypassed on a per channel basis for channels 1 and 2. If EQ control is

bypassed on a given channel the prescale and all filters (high-pass, biquads, de-emphasis,

bass, treble in any combination) are bypassed for that channel.

1010 260 Hz

1011 280 Hz

1100 300 Hz

1101 320 Hz

1110 340 Hz

1111 360 Hz

Table 59. Bass management crossover frequency (continued)

XO[3:0] Crossover frequency

D7 D6 D5 D4 D3 D2 D1 D0

C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VPB C1EQBP C1TCB

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VPB C2EQBP C2TCB

01000000

D7 D6 D5 D4 D3 D2 D1 D0

C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3VPB Reserved

10000000

Table 60. Tone control bypass

CxTCB Mode

0 Perform tone control on channel x - normal operation

1 Bypass tone control on channel x

Table 61. EQ bypass

CxEQBP Mode

0 Perform EQ on channel x - normal operation

1 Bypass EQ on channel x

50/77 Doc ID 15251 Rev 5

6.9.3 Volume bypass

Each channel contains an individual channel volume bypass. If a particular channel has

volume bypassed via the CxVBP = 1 register then only the channel volume setting for that

particular channel affects the volume setting, the master volume setting will not affect that

channel.

6.9.4 Binary output enable registers

Each individual channel output can be set to output a binary PWM stream. In this mode

output A of a channel is considered the positive output and output B is negative inverse.

6.9.5 Limiter select

Limiter selection can be made on a per-channel basis according to the channel limiter select

bits.

6.9.6 Output mapping

Output mapping can be performed on a per channel basis according to the CxOM channel

output mapping bits. Each input into the output configuration engine can receive data from

any of the three processing channel outputs.

Table 62. Binary output enable registers

CxBO Mode

0 FFX 3-state output - normal operation

1 Binary output

Table 63. Channel limiter mapping as a function of CxLS bits

CxLS[1:0] Channel limiter mapping

00 Channel has limiting disabled

01 Channel is mapped to limiter #1

10 Channel is mapped to limiter #2

Table 64. Channel output mapping as a function of CxOM bits

CxOM[1:0] Channel x output source from

00 Channel1

01 Channel 2

10 Channel 3

STA339BW Register description

Doc ID 15251 Rev 5 51/77

6.10 Tone control register (addr 0x11)

6.10.1 Tone control

6.11 Dynamic control registers (addr 0x12 - 0x15)

6.11.1 Limiter 1 attack/release rate

6.11.2 Limiter 1 attack/release threshold

6.11.3 Limiter 2 attack/release rate

D7 D6 D5 D4 D3 D2 D1 D0

TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0

01110111

Table 65. Tone control boost/cut as a function of BTC and TTC bits

BTC[3:0]/TTC[3:0] Boost/Cut

0000 -12 dB

0001 -12 dB

……

0111 -4 dB

0110 -2 dB

0111 0 dB

1000 +2 dB

1001 +4 dB

……

1101 +12 dB

1110 +12 dB

1111 +12 dB

D7 D6 D5 D4 D3 D2 D1 D0

L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0

01101010

D7 D6 D5 D4 D3 D2 D1 D0

L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0

01101001

D7 D6 D5 D4 D3 D2 D1 D0

L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0

01101010

52/77 Doc ID 15251 Rev 5

6.11.4 Limiter 2 attack/release threshold

The STA339BW includes two independent limiter blocks. The purpose of the limiters is to

automatically reduce the dynamic range of a recording to prevent the outputs from clipping

in anti-clipping mode or to actively reduce the dynamic range for a better listening

environment such as a night-time listening mode which is often needed for DVDs. The two

modes are selected via the DRC bit in Configuration register E (addr 0x04) on page 36.

Each channel can be mapped to either limiter or not mapped, meaning that channel will clip

when 0 dBfs is exceeded. Each limiter looks at the present value of each channel that is

mapped to it, selects the maximum absolute value of all these channels, performs the

limiting algorithm on that value, and then if needed adjusts the gain of the mapped channels

in unison.

The limiter attack thresholds are determined by the LxAT registers if EATHx[7] bits are set

to 0 else the thresholds are determined by EATHx[6:0] . It is recommended in anti-clipping

mode to set this to 0 dBfs, which corresponds to the maximum unclipped output power of a

FFX amplifier. Since gain can be added digitally within the STA339BW it is possible to

exceed 0 dBfs or any other LxAT setting, when this occurs, the limiter, when active,

automatically starts reducing the gain. The rate at which the gain is reduced when the attack

threshold is exceeded is dependent upon the attack rate register setting for that limiter. Gain

reduction occurs on a peak-detect algorithm. Setting EATHx[7] bits to 1 selects the

anti-clipping mode.

The limiter release thresholds are determined by the LxRT registers if ERTHx[7] bits are set

to 0 else the thresholds are determined by ERTHx[6:0]. Settings to 1 ERTHx[7] bits the

anti-clipping mode is selected automatically. The release of limiter, when the gain is again

increased, is dependent on a RMS-detect algorithm. The output of the volume/limiter block

is passed through a RMS filter. The output of this filter is compared to the release threshold,

determined by the Release Threshold register. When the RMS filter output falls below the

release threshold, the gain is again increased at a rate dependent upon the Release Rate

occurs if the limiter has already reduced the gain. The release threshold value can be used

to set what is effectively a minimum dynamic range, this is helpful as over-limiting can

reduce the dynamic range to virtually zero and cause program material to sound “lifeless”.

In AC mode, the attack and release thresholds are set relative to full-scale. In DRC mode,

the attack threshold is set relative to the maximum volume setting of the channels mapped

to that limiter and the release threshold is set relative to the maximum volume setting plus

the attack threshold.

D7 D6 D5 D4 D3 D2 D1 D0

L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0

01101001

STA339BW Register description

Doc ID 15251 Rev 5 53/77

Figure 19. Basic limiter and volume flow diagram

Table 66. Limiter attack rate as a function

of LxA bits

Table 67. Limiter release rate as a

function of LxR bits

LxA[3:0] Attack Rate dB/ms LxR[3:0] Release Rate dB/ms

0000 3.1584

Fast

Slow

0000 0.5116

Fast

Slow

0001 2.7072 0001 0.1370

0010 2.2560 0010 0.0744

0011 1.8048 0011 0.0499

0100 1.3536 0100 0.0360

0101 0.9024 0101 0.0299

0110 0.4512 0110 0.0264

0111 0.2256 0111 0.0208

1000 0.1504 1000 0.0198

1001 0.1123 1001 0.0172

1010 0.0902 1010 0.0147

1011 0.0752 1011 0.0137

1100 0.0645 1100 0.0134

1101 0.0564 1101 0.0117

1110 0.0501 1110 0.0110

1111 0.0451 1111 0.0104

54/77 Doc ID 15251 Rev 5

Anti-clipping mode

Table 68. Limiter attack threshold as a

function of LxAT bits (AC mode)

Table 69. Limiter release threshold as a

function of LxRT bits

(AC mode)

LxAT[3:0] AC (dB relative to fs) LxRT[3:0] AC (dB relative to fs)

0000 -12 0000 -∞

0001 -10 0001 -29 dB

0010 -8 0010 -20 dB

0011 -6 0011 -16 dB

0100 -4 0100 -14 dB

0101 -2 0101 -12 dB

0110 0 0110 -10 dB

0111 +2 0111 -8 dB

1000 +3 1000 -7 dB

1001 +4 1001 -6 dB

1010 +5 1010 -5 dB

1011 +6 1011 -4 dB

1100 +7 1100 -3 dB

1101 +8 1101 -2 dB

1110 +9 1110 -1 dB

1111 +10 1111 -0 dB

STA339BW Register description

Doc ID 15251 Rev 5 55/77

Dynamic range compression mode

6.11.5 Limiter 1 Extended attack threshold (addr 0x32)

The extended attack threshold value is determined as follows:

attack threshold = -12 + EATH1 / 4

6.11.6 Limiter 1 Extended release threshold (addr 0x33)

The extended release threshold value is determined as follows:

release threshold = -12 + ERTH1 / 4

Table 70. Limiter attack threshold as a

function of LxAT bits

(DRC mode)

Table 71. Limiter release threshold as a

as a function of LxRT bits

(DRC mode)

LxAT[3:0] DRC (dB relative to Volume) LxRT[3:0] DRC (db relative to Volume +

LxAT)

0000 -31 0000 -∞

0001 -29 0001 -38 dB

0010 -27 0010 -36 dB

0011 -25 0011 -33 dB

0100 -23 0100 -31 dB

0101 -21 0101 -30 dB

0110 -19 0110 -28 dB

0111 -17 0111 -26 dB

1000 -16 1000 -24 dB

1001 -15 1001 -22 dB

1010 -14 1010 -20 dB

1011 -13 1011 -18 dB

1100 -12 1100 -15 dB

1101 -10 1101 -12 dB

1110 -7 1110 -9 dB

1111 -4 1111 -6 dB

D7 D6 D5 D4 D3 D2 D1 D0

EATHEN1EATH1[6]EATH1[5]EATH1[4]EATH1[3]EATH1[2]EATH1[1]EATH1[0]

TBDTBDTBDTBDTBDTBDTBDTBD

D7 D6 D5 D4 D3 D2 D1 D0

ERTHEN1 ERTH1[6] ERTH1[5] ERTH1[4] ERTH1[3] ERTH1[2] ERTH1[1] ERTH1[0]

TBDTBDTBDTBDTBDTBDTBDTBD

56/77 Doc ID 15251 Rev 5

6.11.7 Limiter 2 Extended attack threshold (addr 0x34)

The extended attack threshold value is determined as follows:

attack threshold = -12 + EATH2 / 4

6.11.8 Limiter 2 Extended release threshold (addr 0x35)

The extended release threshold value is determined as follows:

release threshold = -12 + ERTH2 / 4

Note: Attack/release threshold step is 0.125 dB in the range -12 dB and 0 dB.

6.12 User-defined coefficient control registers (addr 0x16 - 0x26)

6.12.1 Coefficient address register

6.12.2 Coefficient b1 data register bits 23:16

6.12.3 Coefficient b1 data register bits 15:8

6.12.4 Coefficient b1 data register bits 7:0

D7 D6 D5 D4 D3 D2 D1 D0

EATHEN2EATH2[6]EATH2[5]EATH2[4]EATH2[3]EATH2[2]EATH2[1]EATH2[0]

TBDTBDTBDTBDTBDTBDTBDTBD

D7 D6 D5 D4 D3 D2 D1 D0

ERTHEN2 ERTH2[6] ERTH2[5] ERTH2[4] ERTH2[3] ERTH2[2] ERTH2[1] ERTH2[0]

TBDTBDTBDTBDTBDTBDTBDTBD

D7 D6 D5 D4 D3 D2 D1 D0

Reserved CFA5 CFA4 CFA3 CFA2 CFA1 CFA0

0 000000

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C1B15 C1B14 C1B13 C1B12 C1B11 C1B10 C1B9 C1B8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C1B7 C1B6 C1B5 C1B4 C1B3 C1B2 C1B1 C1B0

00000000

STA339BW Register description

Doc ID 15251 Rev 5 57/77

6.12.5 Coefficient b2 data register bits 23:16

6.12.6 Coefficient b2 data register bits 15:8

6.12.7 Coefficient b2 data register bits 7:0

6.12.8 Coefficient a1 data register bits 23:16

6.12.9 Coefficient a1 data register bits 15:8

6.12.10 Coefficient a1 data register bits 7:0

6.12.11 Coefficient a2 data register bits 23:16

D7 D6 D5 D4 D3 D2 D1 D0

C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C2B7 C2B6 C2B5 C2B4 C2B3 C2B2 C2B1 C2B0

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C1B23 C1B22 C1B21 C1B20 C1B19 C1B18 C1B17 C1B16

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C3B15 C3B14 C3B13 C3B12 C3B11 C3B10 C3B9 C3B8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C3B7 C3B6 C3B5 C3B4 C3B3 C3B2 C3B1 C3B0

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C4B23 C4B22 C4B21 C4B20 C4B19 C4B18 C4B17 C4B16

00000000

58/77 Doc ID 15251 Rev 5

6.12.12 Coefficient a2 data register bits 15:8

6.12.13 Coefficient a2 data register bits 7:0

6.12.14 Coefficient b0 data register bits 23:16

6.12.15 Coefficient b0 data register bits 15:8

6.12.16 Coefficient b0 data register bits 7:0

6.12.17 Coefficient write/read control register

Coefficients for user-defined EQ, mixing, scaling, and bass management are handled

internally in the STA339BW via RAM. Access to this RAM is available to the user via an I2C

coefficient base address, five sets of three store the values of the 24-bit coefficients to be

written or that were read, and one contains bits used to control the write/read of the

coefficient(s) to/from RAM.

Three different RAM banks are embedded in STA339BW. The three banks are managed in

paging mode using EQCFG register bits. They can be used to store different EQ settings.

For speaker frequency compensation, a sampling frequency independent EQ must be

implemented. Computing three different coefficients set for 32 kHz, 44.1kHz, 48 kHz and

downloading them into the three RAM banks, it is possible to select the suitable RAM block

depending from the incoming frequency with a simple I2C write operation on register 0x31.

D7 D6 D5 D4 D3 D2 D1 D0

C4B15 C4B14 C4B13 C4B12 C4B11 C4B10 C4B9 C4B8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

C5B7 C5B6 C5B5 C5B4 C5B3 C5B2 C5B1 C5B0

00000000

D7 D6 D5 D4 D3 D2 D1 D0

Reserved RA R1 WA W1

0 0000

STA339BW Register description

Doc ID 15251 Rev 5 59/77

For example, in case of different input sources (different sampling rates), the three different

sets of coefficients can be downloaded once at the start up, and during the normal play it is

possible to switch among the three RAM blocks allowing a faster operation, without any

additional download from the microcontroller.

To write the coefficients in a particular RAM bank, this bank must be selected first writing

bit 0 and bit 1 in register 0x31. Then the write procedure below can be used.

Note that as soon as a RAM bank is selected, the EQ settings are automatically switched to

the coefficients stored in the active RAM block.

Note: The read and write operation on RAM coefficients works only if LRCKI (pin 29) is switching.

Reading a coefficient from RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6 bits of address to I2C register 0x16.

3. Write 1 to R1 bit in I2C address 0x26.

4. Read top 8 bits of coefficient in I2C address 0x17.

5. Read middle 8 bits of coefficient in I2C address 0x18.

6. Read bottom 8 bits of coefficient in I2C address 0x19.

Reading a set of coefficients from RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6 bits of address to I2C register 0x16.

3. Write 1 to RA bit in I2C address 0x26.

4. Read top 8 bits of coefficient in I2C address 0x17.

5. Read middle 8 bits of coefficient in I2C address 0x18.

6. Read bottom 8 bits of coefficient in I2C address 0x19.

7. Read top 8 bits of coefficient b2 in I2C address 0x1A.

8. Read middle 8 bits of coefficient b2 in I2C address 0x1B.

9. Read bottom 8 bits of coefficient b2 in I2C address 0x1C.

10. Read top 8 bits of coefficient a1 in I2C address 0x1D.

11. Read middle 8 bits of coefficient a1 in I2C address 0x1E.

12. Read bottom 8 bits of coefficient a1 in I2C address 0x1F.

13. Read top 8 bits of coefficient a2 in I2C address 0x20.

14. Read middle 8 bits of coefficient a2 in I2C address 0x21.

15. Read bottom 8 bits of coefficient a2 in I2C address 0x22.

16. Read top 8 bits of coefficient b0 in I2C address 0x23.

17. Read middle 8 bits of coefficient b0 in I2C address 0x24.

18. Read bottom 8 bits of coefficient b0 in I2C address 0x25.

60/77 Doc ID 15251 Rev 5

Writing a single coefficient to RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6 bits of address to I2C register 0x16.

3. Write top 8 bits of coefficient in I2C address 0x17.

4. Write middle 8 bits of coefficient in I2C address 0x18.

5. Write bottom 8 bits of coefficient in I2C address 0x19.

6. Write 1 to W1 bit in I2C address 0x26.

Writing a set of coefficients to RAM

1. Select the RAM block with register 0x31 bit1, bit0.

2. Write 6 bits of starting address to I2C register 0x16.

3. Write top 8 bits of coefficient b1 in I2C address 0x17.

4. Write middle 8 bits of coefficient b1 in I2C address 0x18.

5. Write bottom 8 bits of coefficient b1 in I2C address 0x19.

6. Write top 8 bits of coefficient b2 in I2C address 0x1A.

7. Write middle 8 bits of coefficient b2 in I2C address 0x1B.

8. Write bottom 8 bits of coefficient b2 in I2C address 0x1C.

9. Write top 8 bits of coefficient a1 in I2C address 0x1D.

10. Write middle 8 bits of coefficient a1 in I2C address 0x1E.

11. Write bottom 8 bits of coefficient a1 in I2C address 0x1F.

12. Write top 8 bits of coefficient a2 in I2C address 0x20.

13. Write middle 8 bits of coefficient a2 in I2C address 0x21.

14. Write bottom 8 bits of coefficient a2 in I2C address 0x22.

15. Write top 8 bits of coefficient b0 in I2C address 0x23.

16. Write middle 8 bits of coefficient b0 in I2C address 0x24.

17. Write bottom 8 bits of coefficient b0 in I2C address 0x25.

18. Write 1 to WA bit in I2C address 0x26.

The mechanism for writing a set of coefficients to RAM provides a method of updating the

five coefficients corresponding to a given biquad (filter) simultaneously to avoid possible

unpleasant acoustic side-effects. When using this technique, the 6-bit address specifies the

address of the biquad b1 coefficient (for example, 0, 5, 10, 20, 35 decimal), and the

STA339BW generates the RAM addresses as offsets from this base value to write the

complete set of coefficient data.

STA339BW Register description

Doc ID 15251 Rev 5 61/77

6.12.18 User-defined EQ

The STA339BW can be programmed for four EQ filters (biquads) per each of the two input

channels. The biquads use the following equation:

Y[n] = 2 * (b0 / 2) * X[n] + 2 * (b1 / 2) * X[n-1] + b2 * X[n-2] - 2 * (a1 / 2) * Y[n-1] - a2 * Y[n-2]

= b0 * X[n] + b1 * X[n-1] + b2 * X[n-2] - a1 * Y[n-1] - a2 * Y[n-2]

where Y[n] represents the output and X[n] represents the input. Multipliers are 24-bit signed

fractional multipliers, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF

(0.9999998808).

Coefficients stored in the user defined coefficient RAM are referenced in the following

manner:

CxHy0 = b1 / 2

CxHy1 = b2

CxHy2 = -a1 / 2

CxHy3 = -a2

CxHy4 = b0 / 2

where x represents the channel and the y the biquad number. For example, C2H41 is the b2

coefficient in the fourth biquad for channel 2.

Additionally, the STA339BW can be programmed for a high-pass filter (processing

channels 1 and 2) and a low-pass filter (processing channel 3) to be used for

bass-management crossover when the XO setting is 000 (user-defined). Both of these filters

when defined by the user (rather than using the preset crossover filters) are second order

filters that use the biquad equation given above. They are loaded into the C12H0-4 and

C3Hy0-4 areas of RAM noted in Ta b le 7 2 .

By default, all user-defined filters are pass-through where all coefficients are set to 0, except

the b0/2 coefficient which is set to 0x400000 (representing 0.5)

6.12.19 Prescale

The STA339BW provides a multiplication for each input channel for the purpose of scaling

the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed

fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The scale factor

for this multiplication is loaded into RAM using the same I2C registers as the biquad

coefficients and the bass management. All channels can use the channel-1 prescale factor

by setting the Biquad link bit. By default, all prescale factors are set to 0x7FFFFF.

6.12.20 Postscale

The STA339BW provides one additional multiplication after the last interpolation stage and

the distortion compensation on each channel. This postscaling is accomplished by using a

24-bit signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. The

scale factor for this multiply is loaded into RAM using the same I2C registers as the biquad

coefficients and the bass management. This postscale factor can be used in conjunction

with an ADC equipped microcontroller to perform power-supply error correction. All

channels can use the channel-1 postscale factor by setting the postscale link bit. By default,

all postscale factors are set to 0x7FFFFF. When line output is being used, channel-3

postscale will affect both channels 3 and 4.

62/77 Doc ID 15251 Rev 5

6.12.21 Overcurrent postscale

The STA339BW provides a simple mechanism for reacting to overcurrent detection in the

power block. When the ocwarn input is asserted, the overcurrent postscale value is used in

place of the normal postscale value to provide output attenuation on all channels. The

default setting provides 3 dB of output attenuation when ocwarn is asserted.

The amount of attenuation to be applied in this situation can be adjusted by modifying the

Overcurrent postscale value. As with the normal postscale, this scaling value is a 24-bit

signed fractional multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default,

the overcurrent postscale factor is set to 0x5A9DF7. Once the overcurrent attenuation is

applied, it remains until the device is reset.

Table 72. RAM block for biquads, mixing, scaling and bass management

Index (decimal) Index (hex) RAM block setting Coefficient Default

0 0x00

Channel 1 - Biquad 1

C1H10(b1/2) 0x000000

1 0x01 C1H11(b2) 0x000000

2 0x02 C1H12(a1/2) 0x000000

3 0x03 C1H13(a2) 0x000000

4 0x04 C1H14(b0/2) 0x400000

5 0x05 Channel 1 - Biquad 2 C1H20 0x000000

……… … …

19 0x13 Channel 1 - Biquad 4 C1H44 0x400000

20 0x14 Channel 2 - Biquad 1 C2H10 0x000000

21 0x15 C2H11 0x000000

……… … …

39 0x27 Channel 2 - Biquad 4 C2H44 0x400000

40 0x28

Channel 1/2 - Biquad 5

for XO = 000

High-pass 2nd order filter

for XO≠000

C12H0(b1/2) 0x000000

41 0x29 C12H1(b2) 0x000000

42 0x2A C12H2(a1/2) 0x000000

43 0x2B C12H3(a2) 0x000000

44 0x2C C12H4(b0/2) 0x400000

45 0x2D

Channel 3 - Biquad

for XO = 000

Low-pass 2nd order filter

for XO≠000

C3H0(b1/2) 0x000000

46 0x2E C3H1(b2) 0x000000

47 0x2F C3H2(a1/2) 0x000000

48 0x30 C3H3(a2) 0x000000

49 0x31 C3H4(b0/2) 0x400000

50 0x32 Channel 1 - Prescale C1PreS 0x7FFFFF

51 0x33 Channel 2 - Prescale C2PreS 0x7FFFFF

52 0x34 Channel 1 - Postscale C1PstS 0x7FFFFF

53 0x35 Channel 2 - Postscale C2PstS 0x7FFFFF

STA339BW Register description

Doc ID 15251 Rev 5 63/77

6.13 Variable max power correction registers (addr 0x27 - 0x28)

MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is

used in place of the default coefficient when MPCV = 1.

6.14 Variable distortion compensation registers (addr 0x29 -

0x2A)

DCC bits determine the 16 MSBs of the Distortion compensation coefficient. This coefficient

is used in place of the default coefficient when DCCV = 1.

54 0x36 Channel 3 - Postscale C3PstS 0x7FFFFF

55 0x37 TWARN/OC - Limit TWOCL 0x5A9DF7

56 0x38 Channel 1 - Mix 1 C1MX1 0x7FFFFF

57 0x39 Channel 1 - Mix 2 C1MX2 0x000000

58 0x3A Channel 2 - Mix 1 C2MX1 0x000000

59 0x3B Channel 2 - Mix 2 C2MX2 0x7FFFFF

60 0x3C Channel 3 - Mix 1 C3MX1 0x400000

61 0x3D Channel 3 - Mix 2 C3MX2 0x400000

62 0x3E Unused - -

63 0x3F Unused - -

Table 72. RAM block for biquads, mixing, scaling and bass management (continued)

Index (decimal) Index (hex) RAM block setting Coefficient Default

D7 D6 D5 D4 D3 D2 D1 D0

MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8

00011010

D7 D6 D5 D4 D3 D2 D1 D0

MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0

11000000

D7 D6 D5 D4 D3 D2 D1 D0

DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8

11110011

D7 D6 D5 D4 D3 D2 D1 D0

DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0

00110011

64/77 Doc ID 15251 Rev 5

6.15 Fault detect recovery constant registers (addr 0x2B - 0x2C)

FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is asserted, the

TRISTATE output is immediately asserted low and held low for the time period specified by

this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The

default value of 0x000C gives approximately 0.1 ms.

6.16 Device status register (addr 0x2D)

This read-only register provides fault- and thermal-warning status information from the

power control block. Logic value 1 for faults or warning means normal state. Logic 0 means

a fault or warning has been detected on the power bridge. The PLLUL = 1 means that the

PLL is not locked.

D7 D6 D5 D4 D3 D2 D1 D0

FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8

00000000

D7 D6 D5 D4 D3 D2 D1 D0

FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0

00001100

D7 D6 D5 D4 D3 D2 D1 D0

PLLUL FAULT UVFAULT OVFAULT OCFAULT OCWARN TFAULT TWARN

Table 73. Status register bits

Bit R/W RST Name Description

7 R - PLLUL 0: PLL locked

1: PLL not locked

6R - FAULT 0: fault detected on power bridge

1: normal operation

5R - UVFAULT 0: VCCxX internally detected

1: undervoltage threshold

4R - OVFAULT 0: VCCxX internally detected

1: overvoltage threshold

3 R - OCFAULT 0: overcurrent fault detected

2 R - OCWARN 0: overcurrent warning

1 R - TFAULT 0: thermal fault, junction temperature over limit

0R - TWARN 0: thermal warning, junction temperature is close to

fault condition

STA339BW Register description

Doc ID 15251 Rev 5 65/77

6.17 EQ coefficients and DRC configuration register (addr 0x31)

Bits AMGC[3:2] change the behavior of the bits AMGC[1:0] as given in Ta b l e 7 5 below.

When AMGC[3:2] = 01 then the bits 1:0 are defined as given here in Ta bl e 7 6.

AC0, AC1, AC2 settings are designed for the loudspeaker protection function, limiting at the

minimum any audio artefacts introduced by typical anti-clipping/DRC algorithms. More

detailed information is available in the applications notes “Configurable output power rate

using STA335BW” and “STA335BWS vs STA335BW”.

Bit XOB can be used to bypass the crossover filters. Logic 1 means that the function is not

active. In this case, high pass crossover filter works as a passtrough on the data path

(b0 = 1, all the other coefficients at logic 0) while the low pass filter is configured to have

zero signal on channel-3 data processing (all the coefficients are at logic 0).

6.18 Extended configuration register (addr 0x36)

Extended configuration register provides access to B2DRC and biquads 5, 6 and 7.

D7 D6 D5 D4 D3 D2 D1 D0

XOB Reserved AMGC[3] AMGC[2] Reserved SEL[1] SEL[0]

00000000

Table 74. EQ RAM select

SEL[1:0] EQ RAM bank selected

00/11 Bank 0 activated

01 Bank 1 activated

10 Bank 2 activated

Table 75. Anti-clipping and DRC preset

AMGC[3:2] Anti-clipping and DRC preset selected

00 DRC/Anti-clipping behavior described in Table 55 on page 47 (default).

01 DRC/Anti-clipping behavior is described in Ta b l e 7 6 below

10/11 Reserved, do not use

Table 76. Anti-clipping selection for AMGC[3:2] = 01

AMGC[1:0] Mode

00 AC0, stereo anticlipping 0 dB limiter

01 AC1, stereo anticlipping +1.25 dB limiter

10 AC2, stereo anticlipping +2 dB limiter

11 Reserved do not use

D7 D6 D5 D4 D3 D2 D1 D0

Mdrc[1] Mdrc[0] PS48DB XAR1 XAR2 BQ5 BQ6 BQ7

00000000

66/77 Doc ID 15251 Rev 5

6.18.1 Dual-band DRC

The STA339BW provides a dual-band DRC (B2DRC) on the left- and right-channel data

path, as depicted in Figure 20. Dual-band DRC is activated by setting MDRC[1:0] = 1x.

Figure 20. B2DRC scheme

The low-frequency information (LFE) is extracted from the left and right channels by

removing the high frequencies with a programmable Biquad filter, so that, using the original

signal, the difference signal can be computed. Limiter 1 (DRC1) is then used to control the

left and right high-frequency component amplitudes while limiter 2 (DRC2) is used to control

the low-frequency components (see Chapter 6.11).

The cutoff frequency of the high-pass filters can be user defined, XO[3:0] = 0, or selected

from the pre-defined values.

DRC1 and DRC2 are then used to independently limit the left- and right-channel high

frequencies and the LFE-channel amplitude (see Chapter 6.11) as well as their volume

control. Note that, in this configuration, the dedicated channel-3 volume control can actually

be used as a bass boost enhancer as well (0.5 dB/step resolution).

The processed LFE channel is then recombined with the L and R channels in order to

reconstruct the 2.0 output signal.

Sub band decomposition

The sub band decomposition for B2DRC can be configured specifying the cutoff frequency.

The cut off frequency can be programmed in two ways, using XO bits in register 0x0C, or

using “user programmable” mode (coefficients stored in RAM adresses 0x28 to 0x31).

For the user programmable mode, use the formulae below to compute the high pass filters:

where alpha = (1-sin(ω0))/cos(ω0), and ω0 is the cutoff frequency.

b0 = (1 + alpha) / 2 a0 = 1

b1 = -(1 + alpha) / 2 a1 = -alpha

b2 = 0 a2 = 0

Pass XO

Filter

Pass XO

Filter

B2DRC

Hi-pass

filter

B2DRC

Hi-pass

filter -

Ch1

Volume

VolAndLimiter

DRC1

Ch2

Volume DRC1

Ch3

Volume

VolAndLimiter

DRC2

Ch3

Volume

VolAndLimiter

DRC2

Pass XO

Filter

Pass XO

Filter

B2DRC

Hi-pass

filter

B2DRC

Hi-pass

filter -

Ch1

Volume

VolAndLimiter

DRC1

Ch2

Volume DRC1

Ch3

Volume

VolAndLimiter

DRC2

Ch3

Volume

VolAndLimiter

DRC2

STA339BW Register description

Doc ID 15251 Rev 5 67/77

A first-order filter is suggested to guarantee that for every ω0 the corresponding low-pass

filter obtained as difference (as shown in Figure 20) will have a symmetric (relative to HP

filter) frequency response, and the corresponding recombination after the DRC has low

ripple. Second-order filters can be used as well, but in this case the filter shape must be

carefully choosen to provide good low pass response and minimum ripple recombination.

For second-order is not possible to give a closed formula to get the best coefficients, but

empirical adjustment should be done.

DRC settings

The DRC blocks used by B2DRC are the same as those described in Chapter 6.11. B2DRC

configure automatically the DRC blocks in anticlipping mode. Attack and release thresholds

can be selected using registers 0x32, 0x33, 0x34, 0x35, while attack and release rates are

configured by registers 0x12 and 0x14.

Band downmixing

The low-frequency band is down-mixed to the left and right channels at the B2DRC output.

Channel volume can be used to weight the bands recombination to fine tune the overall

frequency response.

6.18.2 EQ DRC mode

Setting MDRC = 01, it is possible to add a programmable biquad (the XO biquad at RAM

addresses 0x28 to 0x2C is used for this purpose) to the Limiter/compressor measure path

(side chain). Using EQDRC the peak detector input can be shaped in frequency using the

programmable biquad. For example if a +2 dB bass boost is applied (using a low shelf filter

for example), the effect is that the EQDRC out will limit bass frequencies to -2 dB below the

selected attack treshold.

Generally speaking, if the biquad boosts frequency f with an amount of X dB, the level of a

compressed sinusoid at the output will be TH - X, where TH is the selected attack threshold.

Note: EQDRC works only if the biquad frequency response magnitude is >= 0 dB for every

frequency.

Figure 21. EQDRC scheme

Channel in Peak

detector

Attenuation

calculator

Atten

Channel in BIQUAD Peak

detector

Attenuation

calculator

Atten

EQDRC

Standard DRC

Channel in Peak

detector

Attenuation

calculator

Atten

Channel in BIQUAD Peak

detector

Attenuation

calculator

Atten

EQDRC

Standard DRC

68/77 Doc ID 15251 Rev 5

6.18.3 Extended post scale range

Post scale is an attenuation by default. When PS48DB is set to 1, a 48-dB offset is applied

to the configured word, so postscale can act as a gain too.

6.18.4 Extended attack rate

The attack rate shown in Ta b le 6 6 can be extended to provide up to 8 dB/ms attack rate on

both limiters.

Table 77. Post scale setup

PS48DB Mode

0 Postscale value is applied as defined in coefficient RAM

1Postscale value is applied with +48-dB offset with respect to the

coefficient RAM value

Table 78. Extended attack rate setup for limiter 1

XAR1 Mode

0 Limiter1 attack rate is configured using Ta b le 6 6

1 Limiter1 attack rate is 8 dB/ms

Table 79. Extended attack rate setup for limiter 2

XAR2 Mode

0 Limiter2 attack rate is configured using Ta b le 6 6

1 Limiter2 attack rate is 8 dB/ms

STA339BW Register description

Doc ID 15251 Rev 5 69/77

6.18.5 Extended BIQUAD selector

De-ephasis filter as well as bass and treble controls can be configured as user defined filters

when equalization coefficients link is activated (BQL = 1) and the corresponding BQx bit is

set to 1.

When filters from 5th to 7th are configured as user-programmable, the corresponding

coefficients are stored respectively in addresses 0x20-0x24 (BQ5), 0x25-0x29 (BQ6), 0x2A-

0x2E (BQ7) as in Ta bl e 7 2 .

Note: BQx bits are ignored if BQL = 0 or if DEMP = 1 (relevant for BQ5) or CxTCB = 1 (relevant for

BQ6 and BQ7).

6.19 EQ soft volume configuration registers (addr 0x37 - 0x38)

Soft volume update has a fixed rate by default. Using register 0x37 and 0x38 it is possible to

override the default behavior allowing different volume change rates.

It is also possible to independently define the fade-in (volume is increased) and fade-out

(volume is decreased) rates according to the desired behavior.

Table 80. De-emphasis filter setup

BQ5 Mode

0 Preset de-emphasis filter selected

1 User defined biquad 5 coefficients are selected

Table 81. Bass filter setup

BQ6 Mode

0 Preset bass filter selected as per Ta b l e 6 5

1 User defined biquad 6 coefficients are selected

Table 82. Treble filter setup

BQ7 Mode

0 Preset treble filter selected as per Ta bl e 6 5

1 User defined biquad 7 coefficients are selected

D7 D6 D5 D4 D3 D2 D1 D0

Reserved SVUPE SVUP[4] SVUP[3] SVUP[2] SVUP[1] SVUP[0]

00000000

D7 D6 D5 D4 D3 D2 D1 D0

Reserved SVDWE SVDW4] SVDW[3] SVDW[2] SVDW[1] SVDW[0]

00000000

70/77 Doc ID 15251 Rev 5

When SVUPE = 1 the fade-in rate is defined by the SVUP[4:0] bits according to the formula:

Fade-in rate = 48 / (SVUP[4:0] + 1) dB/ms.

When SVDWE = 1 the fade-out rate is defined by the SVDW[4:0] bits according to the

formula:

Fade-in rate = 48 / (SVDW[4:0] + 1) dB/ms.

6.20 DRC RMS filter coefficients (addr 0x39 - 0x3E)

Signal level detection in DRC algorithm is computed usign the following formula:

y(t) = c0 * abs(x(t)) + c1 * y(t-1)

where x(t) represents the audio signal applied to the limiter, and y(t) the measured level.

Table 83. Soft volume (increasing) setup

SVUPE Mode

0 When volume is increased, use the default rate

1 When volume is increased, use the rates defined by SVUP[4:0] .

Table 84. Soft volume (decreasing) setup

SVDWE Mode

0 When volume is decreased, use the default rate

1 When volume is decreased, use the rates defined by SVDW[4:0] .

D7 D6 D5 D4 D3 D2 D1 D0

R_C0[23] R_C0[22] R_C0[21] R_C0[20] R_C0[19] R_C0[18] R_C0[17] R_C0[16]

00000001

D7 D6 D5 D4 D3 D2 D1 D0

R_C0[15] R_C0[14] R_C0[13] R_C0[12] R_C0[11] R_C0[10] R_C0[9] R_C0[8]

11101110

D7 D6 D5 D4 D3 D2 D1 D0

R_C0[7] R_C0[6] R_C0[5] R_C0[4] R_C0[3] R_C0[2] R_C0[1] R_C0[0]

11111111

D7 D6 D5 D4 D3 D2 D1 D0

R_C1[23] R_C1[22] R_C1[21] R_C1[20] R_C1[19] R_C1[18] R_C1[17] R_C1[16]

01111110

D7 D6 D5 D4 D3 D2 D1 D0

R_C1[15] R_C1[14] R_C1[13] R_C1[12] R_C1[11] R_C1[10] R_C1[9] R_C1[8]

11000000

D7 D6 D5 D4 D3 D2 D1 D0

R_C1[7] R_C1[6] R_C1[5] R_C1[4] R_C1[3] R_C1[2] R_C1[1] R_C1[0]

00100110

STA339BW Application

Doc ID 15251 Rev 5 71/77

7 Application

7.1 Application scheme for power supplies

Here in Figure 22 below is the typical application diagram for STA339BW showing the power

supply decoupling. Particular care has to be taken with the layout of the PCB. In particular

the 3.3 Ω resistors on the digital supplies (VDD_DIG) have to be placed as close as possible

to the device. This helps to prevent unwanted oscillation in the digital part of the device due

to the inductive tracks of the PCB. The same rule also applies to all the decoulpling

capacitors in order to limit spikes on all the supplies.

Figure 22. Application diagram

7.2 PLL filter

It is recommended to use the above scheme and values for the PLL filter to achieve the best

performance from the device in general applications. Note that the ground of this filter circuit

has to be connected to the ground of the PLL without any resistive path.

Concerning the component values, remember that the greater is the filter bandwidth, the

less is the lock time but the higher is the PLL output jitter.

Application STA339BW

72/77 Doc ID 15251 Rev 5

7.3 Typical output configuration

Here after the typical output configuration used for BTL stereo mode. Please refer to the

application note for all the other possible output configuration recommended schematics.

Figure 23. Output configuration for stereo BTL mode

22uH

100nF

470nF

330pF

100nF

LEFT

100nF

6.2

OUT1A

OUT1B

6.2

22uH

100nF

470nF

330pF

100nF

RIGHT

100nF

6.2

OUT2A

OUT2B

6.2

22uH

100nF

470nF

330pF

100nF

LEFT

100nF

6.2

OUT1A

OUT1B

6.2

22uH

100nF

470nF

330pF

100nF

LEFT

100nF

6.2

OUT1A

OUT1B

6.2

22uH

100nF

470nF

330pF

100nF

RIGHT

100nF

6.2

OUT2A

OUT2B

6.2

22uH

100nF

470nF

330pF

100nF

RIGHT

100nF

6.2

OUT2A

OUT2B

6.2

STA339BW Package thermal characteristics

Doc ID 15251 Rev 5 73/77

8 Package thermal characteristics

Using a double-layer PCB the thermal resistance junction to ambient with 2 copper ground

areas of 3 x 3 cm2 and with 16 via holes (see Figure 24) is 24 °C/W in natural air convection.

The dissipated power within the device depends primarily on the supply voltage, load

impedance and output modulation level.

Thus, the maximum estimated dissipated power for the STA339BW is:

Figure 24. Double-layer PCB with 2 copper ground areas and 16 via holes

Figure 25 shows the power derating curve for the PowerSSO-36 slug-down package on

PCBs with copper areas of 2 x 2 cm2 and 3 x 3 cm2.

Figure 25. PowerSSO-36 power derating curve

2 x 20 W @ 8 Ω, 18 V Pd max ~ 4 W

2 x 10 W + 1 x 20 W @ 4 Ω, 8 Ω, 18 V Pd max < 5 W

0 20 40 60 80 100 120 140 160

Pd (W)

Tamb ( °C)

Copper Area 2x2 cm

and via holes

STA339BW

PSSO36

Copper Area 3x3 cm

and via holes

0 20 40 60 80 100 120 140 160

Pd (W)

Tamb ( °C)

Copper Area 2x2 cm

and via holes

STA339BW

PSSO36

Copper Area 3x3 cm

and via holes

STA339BW

PowerSSO-36

Package mechanical data STA339BW

74/77 Doc ID 15251 Rev 5

9 Package mechanical data

Figure 26 shows the package outline and Ta bl e 8 5 gives the dimensions of the

PowerSSO-36 package with exposed pad (slug) down (EPD).

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Table 85. PowerSSO-36 EPD dimensions

Symbol

Dimensions in mm Dimensions in inches

Min Typ Max Min Typ Max

A 2.15 - 2.47 0.085 - 0.097

A2 2.15 - 2.40 0.085 - 0.094

a1 0 - 0.10 0 - 0.004

b 0.18 - 0.36 0.007 - 0.014

c 0.23 - 0.32 0.009 - 0.013

D 10.10 - 10.50 0.398 - 0.413

E 7.40 - 7.60 0.291 - 0.299

e - 0.5 - - 0.020 -

e3 - 8.5 - - 0.335 -

F - 2.3 - - 0.091 -

G- - 0.10 - - 0.004

H 10.10 - 10.50 0.398 - 0.413

h- - 0.40 - - 0.016

k 0 - 8 degrees - - 8 degrees

L 0.60 - 1.00 0.024 - 0.039

M - 4.30 - - 0.169 -

N - - 10 degrees - 10 degrees

O - 1.20 - - 0.047 -

Q - 0.80 - - 0.031 -

S - 2.90 - - 0.114 -

T - 3.65 - - 0.144 -

U - 1.00 - - 0.039 -

X 4.10 - 4.70 0.161 - 0.185

Y 4.90 - 7.10 0.193 - 0.280

STA339BW Package mechanical data

Doc ID 15251 Rev 5 75/77

Figure 26. PowerSSO-36 EPD outline drawing

h x 45°

Revision history STA339BW

76/77 Doc ID 15251 Rev 5

10 Revision history

Table 86. Document revision history

Date Revision Changes

09-Dec-2008 1 Initial release

16-Feb-2009 2

Updated names/descriptions for pins 17-20 in Chapter 2 on page 12

Added cross reference to I2S interface setup in Section 3.6: Power

on/off sequence on page 18

Updated text and Figure 22: Application diagram on page 71

Updated Section 7.2: PLL filter on page 71

01-Apr-2009 3 Updated Y dimension in Table 85: PowerSSO-36 EPD dimensions

on page 74

15-May-2009 4

Updated Chapter 1 on page 10 to “8 programmable 28-bit biquads”

Updated Iil and Iih in Table 6: Electrical specifications - digital section

on page 15

Updated Ilim and Isc in Table 7: Electrical specifications - power

section on page 16

Updated register FDRC addresses in Section 6.1.5: Fault detect

recovery bypass on page 29

Updated bits 4 and 5 in Table 73: Status register bits on page 64.

04-Aug-2010 5 Updated order code in Table 1: Device summary on page 1

Updated name of Chapter 9 on page 74 to Package mechanical data

STA339BW

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