 
  
FEATURES
APPLICATIONS
DESCRIPTION
Lch In
Rch In Analog Front-End Delta-Sigma
Modulator
Digital
Decimation
Filter Serial Interface
and
Mode Control
Digital Out
Mode Control
System Clock
B0006-01
Digital In
Digital
Interpolation
Filter
Lch Out
Rch Out
Low-Pass Filter
and
Output Buffer
Multilevel
Delta-Sigma
Modulator
*
* PCM3002 Only
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS
•Single 3-V Power Supply•Monolithic 20-Bit ∆ Σ ADC and DAC
•Small Package: SSOP-24•16/20-Bit Input/Output Data•Software Control: PCM3002
•DVC Applications•Hardware Control: PCM3003
•DSC Applications•Stereo ADC:
•Portable/Mobile Audio Applications– Single-Ended Voltage Input– Antialiasing Filter– 64 ×Oversampling
The PCM3002 and PCM3003 are low-cost,– High Performance
single-chip stereo audio codecs (analog-to-digital anddigital-to-analog converters) with single-ended analog•THD+N: –86 dB
voltage input and output.•SNR: 90 dB
The ADCs and DACs employ delta-sigma modulation•Dynamic Range: 90 dB
with 64-times oversampling. The ADCs include a•Stereo DAC:
digital decimation filter, and the DACs include an– Single-Ended Voltage Output
8-times oversampling digital interpolation filter. TheDACs also include digital attenuation, de-emphasis,– Analog Low-Pass Filter
infinite zero detection, and soft mute to form a– 64 ×Oversampling
complete subsystem. The PCM3002 and PCM3003– High Performance
operate with left-justified (ADC) and right-justified(DAC) formats, while the PCM3002 also supports•THD+N: –86 dB
other formats, including the I
2
S data format.•SNR: 94 dB
The PCM3002 and PCM3003 provide a power-down•Dynamic Range: 94 dB
mode that operates on the ADCs and DACs indepen-•Special Features (PCM3002, PCM3003)
dently.– Digital De-Emphasis: 32 kHz, 44.1 kHz,
The PCM3002 and PCM3003 are fabricated using a48 kHz
highly advanced CMOS process, and are available in– Power Down: ADC/DAC Independent
a 24-pin SSOP package. The PCM3002 and•Special Features (PCM3002)
PCM3003 are suitable for a wide variety ofcost-sensitive consumer applications where good per-– Digital Attenuation (256 Steps)
formance is required.– Soft Mute
The PCM3002 programmable functions are controlled– Digital Loopback
by software. The PCM3003 functions, which are– Four Alternative Audio Data Formats
controlled by hardware, include de-emphasis,•Sampling Rate: 4 kHz to 48 kHz
power-down, and audio data format selections.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.System Two, Audio Precision are trademarks of Audio Precision, Inc.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ELECTRICAL CHARACTERISTICS
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
All specifications at T
A
= 25 °C, V
DD
= V
CC
= 3 V, f
S
= 44.1 kHz, SYSCLK = 384 f
S
, and 16-bit data, unless otherwise noted
PCM3002E/3003EPARAMETER CONDITIONS
MIN TYP MAX UNITS
DIGITAL INPUT/OUTPUT
Input Logic
V
IH
(1) (2) (3)
0.7 V
DDInput logic level VDCV
IL
(1) (2) (3)
0.3 V
DD
I
IN
(2)
±1Input logic current µAI
IN
(1) (3)
100
Output Logic
V
OH
(4)
I
OUT
= –1 mA V
DD
– 0.3V
OL
(4)
Output logic level I
OUT
= 1 mA 0.3 VDCV
OL
(5)
I
OUT
= 1 mA 0.3
CLOCK FREQUENCY
f
s
Sampling frequency 4
(6)
44.1 48 kHz256 f
S
1.024 11.2896 12.288System clock frequency 384 f
S
1.536 16.9344 18.432 MHz512 f
S
2.048 22.5792 24.576
ADC CHARACTERISTICS
Resolution 20 Bits
DC Accuracy
Gain mismatch, channel- ±1±3 % of FSRto-channel
Gain error ±2±5 % of FSRGain drift ±20 ppm of FSR/ °CBipolar zero error High-pass filter bypassed
(7)
±1.7 % of FSRBipolar zero drift High-pass filter bypassed
(7)
±20 ppm of FSR/ °C
Dynamic Performance
(8)
V
IN
= –0.5 dB –86 –80THD+N dBV
IN
= –60 dB –28Dynamic range A-weighted 86 90 dBSignal-to-noise ratio A-weighted 86 90 dBChannel separation 84 88 dB
(1) Pins 7, 8, 17 and 18: RST, ML, MD, and MC for the PCM3002; PDAD, PDDA, DEM1, and DEM0 for PCM3003 (Schmitt-trigger inputwith 100-k Ωtypical internal pulldown resistor)(2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-trigger input)(3) Pin 16: 20BIT for PCM3003 (Schmitt-trigger input, 100-k Ωtypical internal pulldown resistor)(4) Pin 12: DOUT(5) Pin 16: ZFLG for PCM3002 (open-drain output)(6) See Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies.(7) High-pass filter for offset cancel(8) f
IN
= 1 kHz, using the System Two™ audio measurement system by Audio Precision™ in rms mode with 20-kHz LPF, 400-Hz HPF usedfor performance calculation.
2
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PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 3 V, f
S
= 44.1 kHz, SYSCLK = 384 f
S
, and 16-bit data, unless otherwise noted
PCM3002E/3003EPARAMETER CONDITIONS
MIN TYP MAX UNITS
Digital Filter Performance
Pass band 0.454 f
S
HzStop band 0.583 f
S
HzPass-band ripple ±0.05 dBStop-band attenuation –65 dBDelay time 17.4/f
S
sHPF frequency response –3 dB 0.019 f
S
mHz
Analog Input
Voltage range 0.6 V
CC
Vp-pCenter voltage 0.5 V
CC
VDCInput impedance 30 k ΩAntialiasing filter frequency –3 dB 150 kHzresponse
DAC CHARACTERISTICS
Resolution 20 Bits
DC Accuracy
Gain mismatch, channel- ±1±3 % of FSRto-channel
Gain error ±1±5 % of FSRGain drift ±20 ppm of FSR/ °CBipolar zero error ±2.5 % of FSRBipolar zero drift ±20 ppm of FSR/ °C
Dynamic Performance
(9)
V
OUT
= 0 dB (full scale) –86 –80THD+N dBV
OUT
= –60 dB –32Dynamic range EIAJ, A-weighted 88 94 dBSignal-to-noise ratio EIAJ, A-weighted 88 94 dBChannel separation 86 91 dB
Digital Filter Performance
Pass band 0.445 f
S
HzStop band 0.555 f
S
HzPass-band ripple ±0.17 dBStop-band attenuation –35 dBDelay time 11.1/f
S
s
Analog Output
Voltage range 0.6 V
CC
Vp-pCenter voltage 0.5 V
CC
VDCLoad impedance AC coupling 10 k ΩLPF frequency response f = 20 kHz –0.16 dB
(9) f
OUT
= 1 kHz, using the System Two audio measurement system by Audio Precision in rms mode with 20-kHz LPF, 400-Hz HPF usedfor performance calculation.
3
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ABSOLUTE MAXIMUM RATINGS
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 3 V, f
S
= 44.1 kHz, SYSCLK = 384 f
S
, and 16-bit data, unless otherwise noted
PCM3002E/3003EPARAMETER CONDITIONS
MIN TYP MAX UNITS
POWER SUPPLY REQUIREMENTS
–25 °C to 85 °C 2.7 3 3.6 VDCV
CC
, V
DD
Supply voltage
0°C to 70 °C
(10)
2.4 3 3.6 VDCOperation, V
CC
= V
DD
= 3 V 18 24 mASupply current
Power down, V
CC
= V
DD
= 3 V 50 µAOperation, V
CC
= V
DD
= 3 V 54 72 mWPower dissipation
Power down
(11)
, V
CC
= V
DD
=
150 µW3 V
TEMPERATURE RANGE
T
A
Operation –25 85 °CT
stg
Storage –55 125 °Cθ
JA
Thermal resistance 100 °C/W
(10) Applies for voltages between 2.4 V and 2.7 V for 0 °C to 70 °C and 256 f
S
/512 f
S
operation (384 f
S
not available)(11) SYSCLK, BCKIN, and LRCIN are stopped.
PACKAGE/ORDERING INFORMATION
PACKAGE PACKAGE PACKAGE ORDERING TRANSPORTPRODUCT QUANTITYTYPE CODE MARKING NUMBER MEDIA
PCM3002E Rails 58PCM3002E 24-pin SSOP DB PCM3002E
PCM3002E/2K Tape and reel 2000PCM3003E Rails 58PCM3003E 24-pin SSOP DB PCM3003E
PCM3003E/2K Tape and reel 2000
Supply voltage V
DD
, V
CC
1, V
CC
2 –0.3 V to 6.5 VSupply voltage differences ±0.1 VGND voltage differences ±0.1 VDigital input voltage –0.3 V to V
DD
+ 0.3 V, < 6.5 VAnalog input voltage –0.3 V to V
CC
1, V
CC
2 + 0.3 V, < 6.5 VPower dissipation 300 mWInput current (any pins except supplies) ±10 mAOperating temperature –25 °C to 85 °CStorage temperature –55 °C to 125 °CLead temperature, soldering 260 °C, 5 sPackage temperature (IR reflow, peak) 235 °C
4
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RECOMMENDED OPERATING CONDITIONS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC1
VCC1
VINR
VREF1
VREF2
VINL
RST
ML
SYSCLK
LRCIN
BCKIN
DOUT
VCC2
AGND1
AGND2
VCOM
VOUTR
VOUTL
MC
MD
ZFLG
DIN
VDD
DGND
PCM3002
(TOP VIEW)
P0004-02
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC1
VCC1
VINR
VREF1
VREF2
VINL
PDAD
PDDA
SYSCLK
LRCIN
BCKIN
DOUT
VCC2
AGND1
AGND2
VCOM
VOUTR
VOUTL
DEM0
DEM1
20BIT
DIN
VDD
DGND
PCM3003
(TOP VIEW)
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
over operating free-air temperature range
MIN NOM MAX UNIT
Analog supply voltage, V
CC
1, V
CC
2 2.7 3 3.6 VDigital supply voltage, V
DD
2.7 3 3.6 VAnalog input voltage, full scale (–0 dB) V
CC
= 3 V 1.8 Vp-pDigital input logic family CMOSSystem clock 8.192 24.576 MHzDigital input clock frequency
Sampling clock 32 48 kHzAnalog output load resistance 10 k ΩAnalog output load capacitance 30 pFDigital output load capacitance 10 pFOperating free-air temperature, T
A
–25 85 °C
PIN ASSIGNMENTS—PCM3002
NAME PIN I/O DESCRIPTION
AGND1 23 – ADC analog groundAGND2 22 – DAC analog groundBCKIN 11 I Bit clock input
(1)
DGND 13 – Digital groundDIN 15 I Data input
(1)
DOUT 12 O Data outputLRCIN 10 I Sample rate clock input (f
s
)
(1)
MC 18 I Bit clock for mode control
(1) (2)
MD 17 I Serial data for mode control
(1) (2)
ML 8 I Strobe pulse for mode control
(1) (2)
RST 7 I Reset, active LOW
(1) (2)
SYSCLK 9 I System clock input
(1)
V
CC
1 1, 2 – ADC analog power supplyV
CC
2 24 – DAC analog power supplyV
COM
21 – ADC/DAC commonV
DD
14 – Digital power supply
(1) Schmitt-trigger input(2) With 100-k Ωtypical internal pulldown resistor
5
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PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
PIN ASSIGNMENTS—PCM3002 (continued)
NAME PIN I/O DESCRIPTION
V
IN
L 6 I ADC analog input, LchV
IN
R 3 I ADC analog input, RchV
OUT
L 19 O DAC analog output, LchV
OUT
R 20 O DAC analog output, RchV
REF
1 4 – ADC reference 1V
REF
2 5 – ADC reference 2ZFLG 16 O Zero flag output, active LOW
(3)
(3) Open-drain output
PIN ASSIGNMENTS—PCM3003
NAME PIN I/O DESCRIPTION
AGND1 23 – ADC analog groundAGND2 22 – DAC analog groundBCKIN 11 I Bit clock input
(1)
DEM0 18 I De-emphasis control 0
(1) (2)
DEM1 17 I De-emphasis control 1
(1) (2)
DGND 13 – Digital groundDIN 15 I Data input
(1)
DOUT 12 O Data outputLRCIN 10 I Sample rate clock input (f
s
)
(1)
PDAD 7 I ADC power down, active LOW
(1) (2)
PDDA 8 I DAC power down, active LOW
(1) (2)
SYSCLK 9 I System clock input
(1)
V
CC
1 1, 2 – ADC analog power supplyV
CC
2 24 – DAC analog power supplyV
COM
21 – ADC/DAC commonV
DD
14 – Digital power supplyV
IN
L 6 I ADC analog input, LchV
IN
R 3 I ADC analog input, RchV
OUT
L 19 O DAC analog output, LchV
OUT
R 20 O DAC analog output, RchV
REF
1 4 – ADC reference 1V
REF
2 5 – ADC reference 220BIT 16 I 20-bit format select
(1)(2)
(1) Schmitt-trigger input(2) With 100-k Ωtypical internal pulldown resistor
6
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TYPICAL PERFORMANCE CURVES
ADC SECTION
86
88
90
92
94
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
Dynamic Range − dB
SNR
94
92
90
86
88
SNR − Signal-to-Noise Ratio − dB
G002
Dynamic Range
0.002
0.004
0.006
0.008
0.010
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
−0.5 dB
5
4
3
1
2
−60 dB
G001
THD+N − Total Harm. Dist. + Noise at −60 dB − %
86
88
90
92
94
2.1 2.4 2.7 3.0 3.3 3.6 3.9
VCC − Supply Voltage − V
Dynamic Range − dB
94
92
90
86
88
SNR − Signal-to-Noise Ratio − dB
G004
Dynamic Range
SNR
0.002
0.004
0.006
0.008
0.010
2.1 2.4 2.7 3.0 3.3 3.6 3.9
VCC − Supply V oltage − V
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
5
4
3
1
2
THD+N − Total Harm. Dist. + Noise at −60 dB − %
G003
−60 dB
−0.5 dB
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, f
SYSCLK
= 384 f
S
, and f
SIGNAL
= 1 kHz, unless otherwise noted
THD+N DYNAMIC RANGE and SNRvs vsTEMPERATURE TEMPERATURE
Figure 1. Figure 2.
THD+N DYNAMIC RANGE and SNRvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 3. Figure 4.
NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 f
S
.
7
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86
88
90
92
94
Dynamic Range − dB
94
92
90
86
88
SNR − Signal-to-Noise Ratio − dB
G006
Dynamic Range
SNR
fS − Sampling Frequency − kHz
4832 44.1
0.002
0.004
0.006
0.008
0.010
fS − Sampling Frequency − kHz
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
5
4
3
1
2
G005
THD+N − Total Harm. Dist. + Noise at −60 dB − %
4832 44.1
−60 dB
−0.5 dB
DAC SECTION
90
92
94
96
98
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
Dynamic Range − dB
SNR
98
96
94
90
92
SNR − Signal-to-Noise Ratio − dB
G008
Dynamic Range
0.002
0.004
0.006
0.008
0.010
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD+N − Total Harm. Dist. + Noise at FS − %
FS
4
3
2
0
1
−60 dB
G007
THD+N − Total Harm. Dist. + Noise at −60 dB − %
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, f
SYSCLK
= 384 f
S
, and f
SIGNAL
= 1 kHz, unless otherwise noted
THD+N DYNAMIC RANGE and SNRvs vsSAMPLING FREQUENCY SAMPLING FREQUENCY
Figure 5. Figure 6.
THD+N DYNAMIC RANGE and SNRvs vsTEMPERATURE TEMPERATURE
Figure 7. Figure 8.
8
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90
92
94
96
98
2.1 2.4 2.7 3.0 3.3 3.6 3.9
VCC − Supply Voltage − V
Dynamic Range − dB
98
96
94
90
92
SNR − Signal-to-Noise Ratio − dB
G010
Dynamic Range
SNR
0.002
0.004
0.006
0.008
0.010
2.1 2.4 2.7 3.0 3.3 3.6 3.9
VCC − Supply V oltage − V
THD+N − Total Harm. Dist. + Noise at FS − %
4
3
2
0
1
THD+N − Total Harm. Dist. + Noise at −60 dB − %
G009
−60 dB
FS
90
92
94
96
98
Dynamic Range − dB
98
96
94
90
92
SNR − Signal-to-Noise Ratio − dB
G012
Dynamic
Range
SNR
fS − Sampling Frequency − kHz
4832 44.1
256 fS, 512 fS
384 fS
0.002
0.004
0.006
0.008
0.010
fS − Sampling Frequency − kHz
THD+N − Total Harm. Dist. + Noise at FS − %
4
3
2
0
1
G011
THD+N − Total Harm. Dist. + Noise at −60 dB − %
4832 44.1
384 fS
256 fS, 512 fS
384 fS
256 fS, 512 fS
FS
−60 dB
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, f
SYSCLK
= 384 f
S
, and f
SIGNAL
= 1 kHz, unless otherwise noted
THD+N DYNAMIC RANGE and SNRvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 9. Figure 10.
NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 f
S
.
THD+N DYNAMIC RANGE and SNRvs vsSAMPLING FREQUENCY and SYSTEM CLOCK SAMPLING FREQUENCY and SYSTEM CLOCK
Figure 11. Figure 12.
9
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OUTPUT SPECTRUM
ADCs
f − Frequency − kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20 25
Amplitude − dB
G013
f − Frequency − kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20 25
Amplitude − dB
G015
Signal Level − dB
−96 −84 −72 −60 −48 −36 −24 −12 0
THD+N − Total Harmonic Distortion + Noise − %
G017
0.001
0.1
100
0.01
1
10
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, f
SYSCLK
= 384 f
S
, and f
SIGNAL
= 1 kHz, unless otherwise noted
OUTPUT SPECTRUM (–0.5 dB, N = 8192) OUTPUT SPECTRUM (–60 dB, N = 8192)
Figure 13. Figure 14.
THD+N
vsSIGNAL LEVEL
Figure 15.
10
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DACs
f − Frequency − kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20 25
Amplitude − dB
G014
f − Frequency − kHz
−140
−120
−100
−80
−60
−40
−20
0
0 5 10 15 20 25
Amplitude − dB
G016
Signal Level − dB
−96 −84 −72 −60 −48 −36 −24 −12 0
THD+N − Total Harmonic Distortion + Noise − %
G018
0.001
0.1
100
0.01
1
10
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, f
SYSCLK
= 384 f
S
, and f
SIGNAL
= 1 kHz, unless otherwise noted
OUTPUT SPECTRUM (0 dB, N = 8192) OUTPUT SPECTRUM (–60 dB, N = 8192)
Figure 16. Figure 17.
THD+N
vsSIGNAL LEVEL
Figure 18.
11
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TYPICAL PERFORMANCE CURVES
SUPPLY CURRENT
15
16
17
18
19
20
ICC + IDD − mA
ADC and DAC
fS − Sampling Frequency − kHz
4832 44.1
G021
512 fS
256 fS
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, f
SYSCLK
= 384 f
S
, DIN = BPZ, and V
IN
= BPZ, unless otherwisenoted
I
CC
+ I
DD
I
CC
+ I
DDvs vsSUPPLY VOLTAGE TEMPERATURE
Figure 19. Figure 20.
All characteristics at supply voltages from 2.4 V to2.7 V are measured at SYSCLK = 256 f
S
.
I
CC
+ I
DDvsSAMPLING FREQUENCY
Figure 21.
12
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs)
DECIMATION FILTER
Normalized Frequency [× fS Hz]
−200
−150
−100
−50
0
0 8 16 24 32
Amplitude − dB
G022
Normalized Frequency [× fS Hz]
−100
−80
−60
−40
−20
0
0.0 0.2 0.4 0.6 0.8 1.0
Amplitude − dB
G023
Normalized Frequency [× fS Hz]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude − dB
G024
Normalized Frequency [× fS Hz]
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0.45 0.47 0.49 0.51 0.53 0.55
Amplitude − dB
G025
−4.13 dB at 0.5 fS
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, and f
SYSCLK
= 384 f
S
, unless otherwise noted
OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS
Figure 22. Figure 23.
PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS
Figure 24. Figure 25.
13
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HIGH-PASS FILTER
Normalized Frequency [× fS/1000 Hz]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0 1 2 3 4
Amplitude − dB
G027
Normalized Frequency [× fS/1000 Hz]
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude − dB
G026
ANTIALIASING FILTER
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Amplitude − dB
110 100 10M1k 10k
G028
100k 1M
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
f − Frequency − Hz
Amplitude − dB
110 100 100k1k 10k
G029
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, and f
SYSCLK
= 384 f
S
, unless otherwise noted
HIGH-PASS FILTER RESPONSE HIGH-PASS FILTER RESPONSE
Figure 26. Figure 27.
ANTIALIASING FILTER OVERALL ANTIALIASING FILTER PASS-BANDFREQUENCY RESPONSE FREQUENCY RESPONSE
Figure 28. Figure 29.
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs)
DIGITAL FILTER
−100
−80
−60
−40
−20
0
Level − dB
f − Frequency − Hz
75k25k 50k
G030
0 175k100k 125k 150k
−1.00
−0.80
−0.60
−0.40
−0.20
0.00
Level − dB
f − Frequency − Hz
5k
G031
0 20k10k 15k
DE-EMPHASIS FILTER
−12
−10
−8
−6
−4
−2
0
Level − dB
f − Frequency − Hz
5k
G032
0 25k10k 15k 20k
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
Error − dB
f − Frequency − Hz
3628
G033
0 145127256 10884
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, and f
SYSCLK
= 384 f
S
, unless otherwise noted
OVERALL FREQUENCY CHARACTERISTICS PASS-BAND RIPPLE CHARACTERISTICS(f
S
= 44.1 kHz) (f
S
= 44.1 kHz)
Figure 30. Figure 31.
DE-EMPHASIS FREQUENCY RESPONSE (32 kHz) DE-EMPHASIS ERROR (32 kHz)
Figure 32. Figure 33.
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−12
−10
−8
−6
−4
−2
0
Level − dB
f − Frequency − Hz
5k
G034
0 25k10k 15k 20k
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
Error − dB
f − Frequency − Hz
4999.8375
G035
0 19999.359999.675 14999.5125
−12
−10
−8
−6
−4
−2
0
Level − dB
f − Frequency − Hz
5k
G036
0 25k10k 15k 20k
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
Error − dB
f − Frequency − Hz
5442
G037
0 2176810884 16326
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, and f
SYSCLK
= 384 f
S
, unless otherwise noted
DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) DE-EMPHASIS ERROR (44.1 kHz)
Figure 34. Figure 35.
DE-EMPHASIS FREQUENCY RESPONSE (48 kHz) DE-EMPHASIS ERROR (48 kHz)
Figure 36. Figure 37.
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ANALOG LOW-PASS FILTER
−100
−80
−60
−40
−20
0
20
f − Frequency − Hz
Level − dB
110 100 10M1k 10k
G038
100k 1M
−0.15
−0.10
−0.05
0.00
0.05
0.10
0.15
f − Frequency − Hz
Level − dB
110 100 100k1k 10k
G039
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, and f
SYSCLK
= 384 f
S
, unless otherwise noted
INTERNAL ANALOG FILTER FREQUENCY RESPONSE INTERNAL ANALOG FILTER FREQUENCY RESPONSE(1 Hz–10 MHz) (1 Hz–100 kHz)
Figure 38. Figure 39.
17
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ML(1)
20BIT(2)
Analog
Front-End
Circuit LRCIN
VINL
Reference
VREF1
VREF2
VINR
Delta-Sigma
Modulator
Delta-Sigma
Modulator
Decimation
and
High-Pass Filter
Power Supply
Reset and
Power Down
Serial Data
Interface
DOUT
MC(1)/DEM0(2)
VCOM
(+)
(−)
(−)
(+)
Mode
Control
Interface
Analog
Front-End
Circuit
Decimation
and
High-Pass Filter
ADC
BCKIN
DIN
Analog
Low-Pass
Filter
VOUTLMultilevel
Delta-Sigma
Modulator
Interpolation
Filter
8× Oversampling
Analog
Low-Pass
Filter
VOUTRMultilevel
Delta-Sigma
Modulator
Interpolation
Filter
8× Oversampling
DAC
MD(1)/DEM1(2)
PDDA(2)
RST(1)/PDAD(2)
Zero Detect(1)
Clock
SYSCLK ZFLG(1)
AGND2 VCC2 AGND1 VCC1 DGND VDD
B0004-03
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
BLOCK DIAGRAM
(1) MC, MD, ML, RST, and ZFLG are for PCM3002 only.(2) DEM0, DEM1, 20BIT, PDAD, and PDDA are for PCM3003 only.
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30 kΩ
VINR
VCOM
3
21
5
Delta-Sigma
Modulator
(+)
VREF
VREF2
+
1.0 µF
4.7 µF+
+
−
(−)
+
−
S0011-03
VREF1
4
4.7 µF+
4.7 µF+
PCM AUDIO INTERFACE
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 40. Analog Front-End (Single-Channel)
The four-wire digital audio interface for the PCM3002/3003 comprises LRCIN (pin 10), BCKIN (pin 11), DIN(pin 15), and DOUT (pin 12). The PCM3002 can be used with any of the four input/output data formats (formats0–3), while the PCM3003 can only be used with selected input/output formats (formats 0–1). For the PCM3002,these formats are selected through program register 3 in the software mode. For the PCM3003, data formats areselected by the 20BIT input (pin 16). Figure 41 , Figure 42 , and Figure 43 illustrate audio data input/outputformats and timing.
The PCM3002/3003 can accept 32, 48, or 64 bit clocks (BCKIN) in one clock of LRCIN. Only the 16-bit dataformat can be selected when 32-bit clocks/LRCIN are applied.
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DAC: 16-Bit, MSB-First, Right-Justified
FORMAT 0: PCM3002/3003
LRCIN Right-ChannelLeft-Channel
BCKIN
DIN
MSB LSB MSB LSB
321 16151416 321 161514
BCKIN
LRCIN Right-ChannelLeft-Channel
DOUT 1
14 15 16321
MSB LSB MSB LSB
14 15 16321
ADC: 16-Bit, MSB-First, Left-Justified
LRCIN Right-ChannelLeft-Channel
BCKIN
DIN
MSB LSB MSB LSB
18 19 20321 18 19 2032120
DAC: 20-Bit, MSB-First, Right-Justified
FORMAT 1: PCM3002/3003
BCKIN
LRCIN Right-ChannelLeft-Channel
DOUT 1
18 19 20321
MSB LSB MSB LSB
18 19 20321
ADC: 20-Bit, MSB-First, Left-Justified
T0016-04
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 41. Audio Data Input/Output Format
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DAC: 20-Bit, MSB-First, Left-Justified
FORMAT 2: PCM3002 Only
BCKIN
LRCIN Right-ChannelLeft-Channel
DIN 1
18 19 20321
MSB LSB MSB LSB
18 19 20321
ADC: 20-Bit, MSB-First, Left-Justified
BCKIN
LRCIN Right-ChannelLeft-Channel
DOUT 1
18 19 20321
MSB LSB MSB LSB
18 19 20321
LRCIN Right-ChannelLeft-Channel
BCKIN
DIN
MSB LSB MSB LSB
18 19 20321 18 19 20321
DAC: 20-Bit, MSB-First, I2S
FORMAT 3: PCM3002 Only
LRCIN Right-ChannelLeft-Channel
BCKIN
DOUT
MSB LSB MSB LSB
18 19 20321 18 19 20321
ADC: 20-Bit, MSB-First, I2S
T0016-05
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 42. Audio Data Input/Output Format (PCM3002)
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BCKIN
LRCIN
DIN
t(BCH)
t(BCL)
t(LRP)
t(LB)
t(BCY)
0.5 VDD
t(BL)
DOUT
t(BDO) t(LDO)
0.5 VDD
t(DIS) t(DIH)
0.5 VDD
0.5 VDD
T0021−01
SYSTEM CLOCK
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
BCKIN pulse cycle time t
(BCY)
300 ns (min)BCKIN pulse duration, HIGH t
(BCH)
120 ns (min)BCKIN pulse duration, LOW t
(BCL)
120 ns (min)BCKIN rising edge to LRCIN edge t
(BL)
40 ns (min)LRCIN edge to BCKIN rising edge t
(LB)
40 ns (min)LRCIN pulse duration t
(LRP)
t
(BCY)
(min)DIN setup time t
(DIS)
40 ns (min)DIN hold time t
(DIH)
40 ns (min)DOUT delay time to BCKIN falling edge t
(BDO)
40 ns (max)DOUT delay time to LRCIN edge t
(LDO)
40 ns (max)Rising time of all signals t
(RISE)
20 ns (max)Falling time of all signals t
(FALL)
20 ns (max)
Figure 43. Audio Data Input/Output Timing
The system clock for the PCM3002/3003 must be either 256 f
S
, 384 f
S
, or 512 f
S
, where f
S
is the audio samplingfrequency. The system clock should be provided at the SYSCLK input (pin 9).
The PCM3002/3003 also has a system-clock detection circuit that automatically senses if the system clock isoperating at 256 f
S
, 384 f
S
, or 512 f
S
. When a 384-f
S
or 512-f
S
system clock is used, the clock is divided to 256 f
Sautomatically. The 256-f
S
clock is used to operate the digital filters and the delta-sigma modulators.
Table 1 lists the relationship of typical sampling frequencies and system clock frequencies; Figure 44 illustratesthe system clock timing.
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz)
256 f
s
384 f
s
512 f
s
32 8.1920 12.2880 16.384044.1 11.2896 16.9344 22.579248 12.2880 18.4320 24.5760
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www.ti.com
t(SCKH)
SYSCLK 0.3 VDD
0.7 VDD
t(SCKL)
1/256 fS,
1/384 fS,
or 1/512 fS
H
L
T0005-05
POWER-ON RESET
1024 System Clock Periods
Reset Reset Removal
2.4 V
2.2 V
2.0 V
VDD
Internal Reset
System Clock
T0014-03
3 Clocks Minimum
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 44. System Clock Timing
System clock pulse duration, HIGH t
(SCKH)
12 ns (min)System clock pulse duration, LOW t
(SCKL)
12 ns (min)
Both the PCM3002 and PCM3003 have internal power-on reset circuitry. Power-on reset occurs when thesystem clock (SYSCLK) is active and V
DD
> 2.2 V. For the PCM3003, the SYSCLK must complete a minimum ofthree complete cycles prior to V
DD
> 2.2 V to ensure proper reset operation. The initialization sequence requires1024 SYSCLK cycles for completion, as shown in Figure 45 . Figure 46 shows the state of the DAC and ADCoutputs during and after the reset sequence.
Figure 45. Internal Power-On Reset Timing
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T0019-02
Reset Ready/Operation
Internal Reset
or Power Down
DAC VOUT
t(DACDLY1)
(16384/fS)
Reset Removal or Power Down Off
Power Down
ADC DOUT Zero Data Normal Data(1)
VCOM
(0.5 VCC)
t(ADCDLY1)
(18432/fS)
Zero Data
GND
EXTERNAL RESET
t(RST)
Reset Removal
1024 System Clock Periods
RST
or
PDAD and PDDA
Internal Reset
System Clock
t(RST) = 40 ns (min)
Reset
T0015-02
RST Pulse Duration
SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
(1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant)appears initially.
Figure 46. DAC Output and ADC Output for Reset and Power Down
The PCM3002 includes a reset input, RST (pin 7), while the PCM3003 uses both PDAD (pin 7) and PDDA(pin 8) for external reset control. As shown in Figure 47 , the external reset signal must drive RST or PDAD andPDDA low for a minimum of 40 nanoseconds while SYSCLK is active in order to initiate the reset sequence.Initialization starts on the rising edge of RST or PDAD and PDDA, and requires 1024 SYSCLK cycles forcompletion. Figure 46 shows the state of the DAC and ADC outputs during and after the reset sequence.
Figure 47. External Forced-Reset Timing
The PCM3002/3003 operates with LRCIN synchronized to the system clock. The PCM3002/3003 does notrequire any specific phase relationship between LRCIN and the system clock, but there must be synchronizationof LRCIN and the system clock. If the synchronization between the system clock and LRCIN changes more than6 bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation ofthe DAC stops within 1/f
S
, and the analog output is forced to bipolar zero (0.5 V
CC
) until the system clock isresynchronized to LRCIN followed by t
(DACDLY2)
delay time. Internal operation of the ADC also stops within 1/f
S
,and the digital output codes are set to bipolar zero until resynchronization occurs followed by t
(ADCDLY2)
delaytime. If LRCIN is synchronized within 5 or fewer bit clocks to the system clock, operation is normal. Figure 48illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero(<1/f
S
seconds), the outputs are not defined and some noise may occur. During the transitions between normaldata and undefined states, the output has discontinuities, which cause output noise.
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Within 1/fSt(DACDLY2)
(32/fS)
Normal Data
VCOM
(0.5 VCC)
Undefined
Data
Normal Data
SynchronousAsynchronousSynchronous
Resynchronization
Synchronization Lost
DAC VOUT
State of Synchronization
T0020-03
Normal Data(1)
Zero DataNormal Data
ADC DOUT
t(ADCDLY2)
(32/fS)
Undefined
Data
ZERO FLAG OUTPUT: PCM3002 ONLY
OPERATIONAL CONTROL
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
(1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant)appears initially.
Figure 48. DAC Output and ADC Output for Loss of Synchronization
Pin 16 is an open-drain output, used as the infinite zero detection flag on the PCM3002 only. When input data iscontinuously zero for 65,536 BCKIN cycles, ZFLG is LOW; otherwise, ZFLG is in a high-impedance state.
The PCM3002 can be controlled in a software mode with a three-wire serial interface on MC (pin 18),MD (pin 17), and ML (pin 8). Table 2 indicates selectable functions, and Figure 49 and Figure 50 illustrate thecontrol data input format and timing. The PCM3003 only allows for control of 16/20-bit data format, digitalde-emphasis, and power-down control by hardware pins.
Table 2. Selectable Functions (O = User Selectable; X = Not Available)
FUNCTION ADC/DAC PCM3002 PCM3003
Audio data format ADC/DAC Four selectable formats Two selectable formatsLRCIN polarity ADC/DAC O XLoopback control ADC/DAC O XLeft-channel attenuation DAC O XRight-channel attenuation DAC O XAttenuation control DAC O XInfinite zero detection and mute DAC O XDAC output control DAC O XSoft mute control DAC O XDe-emphasis (OFF, 32 kHz, 44.1 kHz, 48 kHz) DAC O OADC power-down control ADC O ODAC power-down control DAC O OHigh-pass filter operation ADC O X
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B8
B15
ML
MC
MD B9B10B11B12B13B14 B0
B7 B1B2B3B4B5B6
T0023-01
t(MCH)
ML
LSB
t(MCL)
t(MHH)
t(MCY)
t(MDH)
t(MDS)
MC
MD
t(MLS)
t(MLL)
t(MLH)
T0024-02
0.5 VDD
0.5 VDD
0.5 VDD
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 49. Control Data Input Format
MC pulse cycle time t
(MCY)
100 ns (min)MC pulse duration, LOW t
(MCL)
40 ns (min)MC pulse duration, HIGH t
(MCH)
40 ns (min)MD setup time t
(MDS)
40 ns (min)MD hold time t
(MDH)
40 ns (min)ML low-level time t
(MLL)
40 ns + 1 SYSCLK
(1)
(min)ML high-level time t
(MHH)
40 ns + 1 SYSCLK
(1)
(min)ML setup time
(3)
t
(MLS)
40 ns (min)ML hold time
(2)
t
(MLH)
40 ns (min)SYSCLK: 1/256 f
S
or 1/384 f
S
or 1/512 f
S
(1) SYSCLK: System clock cycle(2) MC rising edge of LSB to ML rising edge(3) ML rising edge to the next MC rising edge
Figure 50. Control Data Input Timing
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MAPPING OF PROGRAM REGISTERS
SOFTWARE CONTROL (PCM3002)
PROGRAM REGISTER 0
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0REGISTER 0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
REGISTER 1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
REGISTER 2 res res res res res A1 A0 PDAD BYPS PDDA ATC IZD OUT DEM1 DEM0 MUT
REGISTER 3 res res res res res A1 A0 res res res LOP res FMT1 FMT0 LRP resNOTE: res indicates a reserved bit that should be set to 0.
The PCM3002 special functions are controlled using four program registers which are each 16 bits long. Thereare four distinct registers, with bits 9 and 10 determining which register is in use. Table 3 describes the functionsof the four registers.
Table 3. Functions of the Registers
REGISTER NAME REGISTER BIT(S) BIT NAME DESCRIPTION
Register 0 15–11 res Reserved, should be set to 010–9 A[1:0] Register address 008 LDL DAC attenuation data load control forLch7–0 AL[7:0] DAC attenuation data for LchRegister 1 15–11 res Reserved, should be set to 010–9 A[1:0] Register address 018 LDR DAC attenuation data load control forRch7–0 AR[7:0] DAC attenuation data for RchRegister 2 15–11 res Reserved, should be set to 010–9 A[1:0] Register address 108 PDAD ADC power-down control7 BYPS ADC high-pass filter bypass control6 PDDA DAC power-down control5 ATC DAC attenuation data mode control4 IZD DAC infinite zero detection and mutecontrol3 OUT DAC output enable control2–1 DEM[1:0] DAC de-emphasis control0 MUT DAC Lch and Rch soft mute controlRegister 3 15–11 res Reserved, should be set to 010–9 A[1:0] Register address 118–6 res Reserved, should be set to 05 LOP ADC/DAC digital loopback control4 res Reserved, should be set to 03–2 FMT[1:0] ADC/DAC audio data format selection1 LRP ADC/DAC polarity of LR-clock selection0 res Reserved, should be set to 0
res: Bits 15–11: ReservedThese bits are reserved and should be set to 0.
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PROGRAM REGISTER 1
PROGRAM REGISTER 2
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
A[1:0] Bits 10, 9: Register addressThese bits define the address for register 0:A1 A0 REGISTER
0 0 Register 0
LDL Bit 8: DAC attenuation data load control for left channelThis bit is used to set analog outputs of the left and right channels simultaneously. The output levelis controlled by AL[7:0] attenuation data when this bit is set to 1. When set to 0, the new attenuationdata is ignored, and the output level remains at the previous attenuation level. The LDR bit inregister 1 has the equivalent function as LDL. When either LDL or LDR is set to 1, the output levelsof the left and right channels are controlled simultaneously.
AL (7:0) Bits 7–0: DAC attenuation data for left channelAL7 and AL0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by:ATT = 20 ×log
10
(AL[7:0]/256) [dB], except AL[7:0] = FFhAL[7:0] ATTENUATION LEVEL
00h – ∞dB (mute)01h –48.16 dB: :FEh –0.07 dBFFh 0 dB (default)
res: Bits 15–11: ReservedThese bits are reserved and should be set to 0.
A[1:0] Bits 10, 9: Register addressThese bits define the address for register 1:A1 A0 REGISTER
0 1 Register 1
LDR Bit 8: DAC attenuation data load control for right channelThis bit is used to set analog outputs of the left and right channels simultaneously. The output levelis controlled by AR[7:0] attenuation data when this bit is set to 1. When set to 0, the newattenuation data is ignored, and the output level remains at the previous attenuation level. The LDLbit in register 0 has the equivalent function as LDR. When either LDL or LDR is set to 1, the outputlevels of the left and right channels are controlled simultaneously.
AR[7:0] Bits 7–0: DAC attenuation data for right channelAR7 and AR0 are the MSB and LSB, respectively.ATT = 20 ×log
10
(AR[7:0]/256) [dB], except AR[7:0] = FFhAR[7:0] ATTENUATION LEVEL
00h – ∞dB (mute)01h –48.16 dB: :FEh –0.07 dBFFh 0 dB (default)
res: Bits 15–11: ReservedThese bits are reserved and should be set to 0.
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PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
A[1:0] Bits 10, 9: Register addressThese bits define the address for register 2:A1 A0 REGISTER
1 0 Register 2
PDAD: Bit 8: ADC power-down controlThis bit places the ADC section in the lowest power-consumption mode. The ADC operation isstopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADCpower-down mode enable. Figure 46 illustrates the ADC DOUT response for ADC power-downON/OFF. This does not affect the DAC operation.PDAD DAC POWER-DOWN STATUS
0 Power-down mode disabled (default)1 Power-down mode enabled
BYPS: Bit 7: ADC high-pass filter bypass controlThis bit enables or disables the high-pass filter for the ADC.BYPS FILTER BYPASS STATUS
0 High-pass filter enabled (default)1 High-pass filter disabled (bypassed)
PDDA: Bit 6: DAC power-down controlThis bit places the DAC section in the lowest power-consumption mode. The DAC operation isstopped by cutting the supply current to the DAC section, and VOUT is fixed to GND during DACpower-down mode enable. Figure 46 illustrates the DAC VOUT response for DAC power-downON/OFF. This does not affect the ADC operation.PDDA ADC POWER-DOWN STATUS
0 Power-down mode disabled (default)1 Power-down mode enabled
ATC: Bit 5: DAC attenuation data mode controlWhen set to 1, the register 0 attenuation data can be used for both DAC channels. In this case, theregister 1 attenuation data is ignored.ATC ATTENUATION CONTROL
0 Individual channel attenuation data control (default)1 Common channel attenuation data control
IZD: Bit 4: DAC infinite zero detection and mute controlThis bit enables the infinite zero detection circuit in the PCM3002. When enabled, this circuitdisconnects the analog output amplifier from the delta-sigma DAC when the input is continuouslyzero for 65,536 consecutive cycles of BCKIN.IZD INFINITE ZERO DETECT STATUS
0 Infinite zero detection and mute control disabled (default)1 Infinite zero detection and mute control enabled
OUT: Bit 3: DAC output enable controlWhen set to 1, the outputs are forced to V
CC
/2 (bipolar zero). In this case, all registers in thePCM3002 hold the present data. Therefore, when set to 0, the outputs return to the previousprogrammed state.OUT DAC OUTPUT STATUS
0 DAC outputs enabled (default normal operation)1 DAC outputs disabled (forced to BPZ)
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PROGRAM REGISTER 3
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
DEM[1:0]: Bits 2, 1: DAC de-emphasis controlThese bits select the de-emphasis mode as shown below:DEM1 DEM0 DE-EMPHASIS STATUS
0 0 De-emphasis 44. 1 kHz ON0 1 De-emphasis OFF (default)1 0 De-emphasis 48 kHz ON1 1 De-emphasis 32 kHz ON
MUT: Bit 0: DAC soft mute controlWhen set to 1, both left- and right-channel DAC outputs are muted at the same time. This muting isdone by attenuating the data in the digital filter, so there is no audible click noise when soft mute isturned on.MUT MUTE STATUS
0 Mute disabled (default)1 Mute enabled
res: Bits 15–11: ReservedThese bits are reserved and should be set to 0.
A[1:0] Bits 10, 9: Register addressThese bits define the address for register 3:A1 A0 REGISTER
1 1 Register 3
res: Bits 8–6: ReservedThese bits are reserved and should be set to 0.
LOP: Bit 5: ADC to DAC loopback controlWhen this bit is set to 1, the ADC audio data is sent directly to the DAC. The data format defaults toI
2
S; DOUT is still available in loopback mode.LOP LOOPBACK STATUS
0 Loopback disabled (default)1 Loopback enabled
res: Bit 4: Reserved
This bit is reserved and should be set to 0.
FMT[1:0] Bits 3–2: Audio data format selectThese bits determine the input and output audio data formats.FMT1 FMT0 DAC DATA FORMAT ADC DATA FORMAT NAME
0 0 16-bit, MSB-first, right-justified 16-bit, MSB-first, left-justified Format 0 (default)0 1 20-bit, MSB-first, right-justified 20-bit, MSB-first, left-justified Format 11 0 20-bit, MSB-first, left-justified 20-bit, MSB-first, left-justified Format 21 1 20-bit, MSB-first, I
2
S 20-bit, MSB-first, I
2
S Format 3
LRP: Bit 1: ADC to DAC LRCIN polarity selectPolarity of LRCIN applies only to formats 0 through 2.LRP LEFT/RIGHT POLARITY
0 Left channel is H, right channel is L (default).1 Left channel is L, right channel is H.
30
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PCM3003 DATA FORMAT CONTROL
Power-Down Control (Pin 7 and Pin 8)
De-Emphasis Control (Pin 17 and Pin 18)
20BIT Audio Data Selection (Pin 16)
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
res: Bit 0: Reserved
This bit is reserved and should be set to 0.
The PCM3003 has hardware functional control using PDAD (pin 7) and PDDA (pin 8) for power-down control;DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis; and 20BIT (pin 16) for 16/20-bit format selection.
Both the ADC and DAC power-down control pins place the ADC or DAC section in the lowestpower-consumption mode. The ADC/DAC operation is stopped by cutting the supply current to the ADC/DACsection. DOUT is fixed to zero during ADC power-down mode enable and V
OUT
is fixed to GND during DACpower-down mode enable. Figure 46 illustrates the ADC and DAC output response for power-down ON/OFF.PDAD PDDA POWER DOWN
Low Low Reset (ADC/DAC power down enabled)Low High ADC power-down/DAC operatesHigh Low ADC operates/DAC power downHigh High ADC and DAC normal operation
DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis control pins.DEM1 DEMO DE-EMPHASIS
Low Low De-emphasis enabled for 44.1 kHzLow High De-emphasis disabledHigh Low De-emphasis enabled for 48 kHzHigh High De-emphasis enabled for 32 kHz
20BIT FORMAT
Low ADC: 16-bit MSB-first, left-justifiedDAC: 16-bit MSB-first, right-justifiedHigh ADC: 20-bit MSB-first, left-justifiedDAC: 20-bit MSB-first, right-justified
31
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APPLICATION AND LAYOUT CONSIDERATIONS
POWER-SUPPLY BYPASSING
GROUNDING
VOLTAGE INPUT
V
REF
INPUTS
V
COM
INPUT
SYSTEM CLOCK
RESET CONTROL
EXTERNAL MUTE CONTROL
TYPICAL CONNECTION DIAGRAM
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
The digital and analog power supply lines to PCM3002/3003 should be bypassed to the corresponding groundpins with both 0.1- µF ceramic and 10- µF tantalum capacitors as close to the device pins as possible. Althoughthe PCM3002/3003 has three power-supply lines to optimize dynamic performance, the use of one commonpower supply is generally recommended to avoid unexpected latch-up or pop noise due to power-supplysequencing problems. If separate power supplies are used, back-to-back diodes are recommended to avoidlatch-up problems.
In order to optimize the dynamic performance of the PCM3002/3003, the analog and digital grounds are notconnected internally. The PCM3002/3003 performance is optimized with a single ground plane for all returns. It isrecommended to tie all PCM3002/3003 ground pins to the analog ground plane using low-impedanceconnections. The PCM3002/3003 should reside entirely over this plane to avoid coupling high-frequency digitalswitching noise into the analog ground plane.
A tantalum or aluminum electrolytic capacitor, between 1 µF and 10 µF, is recommended as an ac-couplingcapacitor at the inputs. Combined with the 30-k Ωcharacteristic input impedance, a 1- µF coupling capacitorestablishes a 5.3-Hz cutoff frequency for blocking dc. The input voltage range can be increased by adding aseries resistor on the analog input line. This series resistor, when combined with the 30-k Ωinput impedance,creates a voltage divider and enables larger input ranges.
A 4.7- µF to 10- µF tantalum capacitor is recommended between V
REF
1, V
REF
2, and AGND1 to ensure low sourceimpedance for the ADC references. These capacitors should be located as close as possible to the referencepins to reduce dynamic errors on the ADC reference.
A 4.7- µF to 10- µF tantalum capacitor is recommended between V
COM
and AGND1 to ensure low sourceimpedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to theV
COM
pin to reduce dynamic errors on the dc common-mode voltage.
The quality of the system clock can influence dynamic performance of both the ADC and DAC in thePCM3002/3003. The duty cycle and jitter at the system-clock input pin should be carefully managed. Whenpower is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) also must be suppliedsimultaneously. Failure to supply the audio clocks results in a power-dissipation increase of up to three timesnormal dissipation and can degrade long-term reliability if the maximum power-dissipation limit is exceeded.
If capacitors larger than 22 µF are used on V
REF
and V
COM
, external reset control ( RST = low for the PCM3002,PDAD = low and PDDA = low for the PCM3003) is required after the V
REF
, V
COM
transient response is settled.
For power-down ON/OFF control without click noise, which is generated by a DC level change on the DACoutput, use of the external mute control is recommended. The control sequence, which is external mute ON,codec power-down ON, SYSCLK stop and resume if necessary, codec power-down OFF, and external muteOFF is recommended.
A typical connection diagram for the PCM3002/3003 is shown in Figure 51 .
32
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VREF220
19
18
17
16
15
14
13
5
6
7
8
9
10
11
12
VINL
RST/PDAD
ML/PDDA
SYSCLK
LRCIN
BCKIN
DOUT
VOUTR
DGND
VOUTL
MC/DEM0
MD/DEM1
ZFLG/20BIT
VDD
DIN
Rch In
Audio
Interface
VCC124
23
22
21
1
2
3
4
VCC1
VINR
VREF1
VCC2
AGND1
AGND2
VCOM
+
+
0.1 µF
and 10 µF(1)
MC(6)/DEM0(7)
ZFLG(6)/20BIT(7)
Control
Interface
PCM3002/3003
+
+
1 µF(3)
4.7 µF(2)
4.7 µF(2)
Lch In +
1 µF(3)
SYSCLK
L/R CLK
BIT CLK
DATA OUT
DATA IN
S0014-01
+3 V Analog VCC
+
+
0.1 µF
and 10 µF(1)
4.7 µF(2)
+
4.7 µF(4) Rch Out(5)
Lch Out(5)
MD(6)/DEM1(7)
0.1 µF
and 10 µF(1)
ML(6)/PDDA(7)
RST(6)/PDAD(7)
4.7 µF(4)
10 kΩ
+
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
(1) 0.1- µF ceramic and 10- µF tantalum, typical, depending on power supply quality and pattern layout(2) 4.7- µF, typical, gives settling time with 30-ms (4.7 µF×6.4 k Ω) time constant in the power ON and power-down OFFperiods.
(3) 1- µF, typical, gives 5.3-Hz cutoff frequency for the input HPF in normal operation and gives settling time with 30-ms(1 µF×30 k Ω) time constant in the power ON and power-down OFF periods.(4) 4.7- µF, typical, gives 3.4-Hz cutoff frequency for the output HPF in normal operation and gives settling time with47-ms (4.7 µF×10 k Ω) time constant in the power ON and power-down OFF periods.(5) Post low-pass filter with R
IN
> 10 k Ω, depending on system performance requirements(6) MC, MD, ML, ZFLG, RST, and 10-k Ωpullup resistor are for the PCM3002.(7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.
Figure 51. Typical Connection Diagram for PCM3002/3003
33
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THEORY OF OPERATION
ADC SECTION
DAC SECTION
1st
SW-CAP
Integrator
Analog
In
X(z) +
−
+−2nd
SW-CAP
Integrator
3rd
SW-CAP
Integrator
+−4th
SW-CAP
Integrator
++++
++++
5th
SW-CAP
Integrator
Digital
Out
Y(z)
Comparator
Qn(z)
H(z)
1-Bit
DAC
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function B0005-01
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
The PCM3002/3003 ADC consists of two reference circuits, a stereo single-to-differential converter, a fullydifferential fifth-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interfacecircuit. The block diagram in this data sheet illustrates the architecture of the ADC section, Figure 40 shows thesingle-to-differential converter, and Figure 52 illustrates the architecture of the fifth-order delta-sigma modulatorand transfer functions.
An internal reference circuit with three external capacitors provides all reference voltages required by the ADC,which defines the full-scale range for the converter. The internal single-to-differential voltage converter saves thespace and extra parts needed for the external circuitry required by many delta-sigma converters. The internalfull-differential signal processing architecture provides a wide dynamic range and excellent power supplyrejection performance. The input signal is sampled at a 64 ×oversampling rate, eliminating the need for asample-and-hold circuit, and simplifying antialias filtering requirements. The fifth-order delta-sigma noise shaperconsists of five integrators which use a switched-capacitor topology, a comparator, and a feedback loopconsisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audioband in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs,reducing idle tone levels.
The 64-f
S
, one-bit data stream from the modulator is converted to 1-f
S
, 16/20-bit data words by the decimationfilter, which also acts as a low-pass filter to remove the shaped quantization noise. The dc components areremoved by a high-pass filter function contained within the decimation filter.
The delta-sigma DAC section of the PCM3002/3003 is based on a 5-level amplitude quantizer and a third-ordernoise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagramof the 5-level delta-sigma modulator is shown in Figure 53 . This 5-level delta-sigma modulator has the advantageof improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.The combined oversampling rate of the delta-sigma modulator and the internal 8 ×interpolation filter is 64 f
S
for a256-f
S
system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator isshown in Figure 54 .
Figure 52. Simplified Fifth-Order Delta-Sigma Modulator
34
www.ti.com
+
+−Z−1
+ +
+
+−Z−1
In
8 fS
21-Bit
Out
64 fS
+
+Z−1
B0008-01
+
5-Level Quantizer
0
1
2
3
4
f − Frequency − kHz
−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 5 10 15 20 25 30
Gain − dB
G040
PCM3002
PCM3003
SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004
THEORY OF OPERATION (continued)
Figure 53. Five-Level Delta-Sigma Modulator Block Diagram
Figure 54. Quantization Noise Spectrum
35
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCM3002E ACTIVE SSOP DB 24 58 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3002E/2K ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3002E/2KG4 ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3002EG ACTIVE SSOP DB 24 58 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM3002EG/2K ACTIVE SSOP DB 24 2000 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM3002EG/2KE6 ACTIVE SSOP DB 24 2000 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM3002EG4 ACTIVE SSOP DB 24 58 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3002EGE6 ACTIVE SSOP DB 24 58 Pb-Free
(RoHS) CU SNBI Level-2-260C-1 YEAR
PCM3003E ACTIVE SSOP DB 24 58 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3003E/2K ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3003E/2KG4 ACTIVE SSOP DB 24 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCM3003EG4 ACTIVE SSOP DB 24 58 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Jan-2007
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Jan-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM3002E/2K SSOP DB 24 2000 330.0 17.4 8.5 8.6 2.4 12.0 16.0 Q1
PCM3002EG/2K SSOP DB 24 2000 330.0 17.4 8.5 8.6 2.4 12.0 16.0 Q1
PCM3003E/2K SSOP DB 24 2000 330.0 17.4 8.5 8.6 2.4 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM3002E/2K SSOP DB 24 2000 336.6 336.6 28.6
PCM3002EG/2K SSOP DB 24 2000 336.6 336.6 28.6
PCM3003E/2K SSOP DB 24 2000 336.6 336.6 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Jun-2008
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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