TC7109CPLG - Microchip Technology, Inc.

 2002-2012 Microchip Technology Inc. DS21456D-page 1

TC7109/A

Features:

• Zero Integrator Cycle for Fa st Recover y from

Input Overloads

• Eliminates Cross-Talk in Multiplexed Systems

• 12-Bit Plus Sign Integrating A/D Converter with

Over Range Indication

• Sign Magnitude Coding Format

• True Differential Signal Input and Differential

Reference Input

• Low Noise: 15VP-P Typ.

• Input Current: 1pA Typ.

• No Zero Adjustment needed

• TTL Compatible, Byte Organized Tri-State

Outputs

• UART Handshake Mode for simple Seri al Data

Transmissions

Device Selection Table

*The “A” version has a higher IOUT on the digital lines.

General Description:

The TC7109A is a 12-bit plus sign, CMOS low power

Anal og-t o-Dig ital Con vert er (ADC ). O nly ei ght pas sive

components and a crystal are required to form a

complete dual slope integrating ADC.

The improved VOH source current and other TC7109A

featur es make it an at tractive per-c hannel alternati ve to

analog multiplexing for many data acquisition applica-

tions. These features include typical input bias current

of 1pA, drift of less than 1V/°C, input noise typically

15VP-P, and auto-zero. True differential input and ref-

erence a ll ow m eas ure ment of bridge type tra ns duc ers ,

such as load cells, strain gauges and temperature

transducers.

The TC7109A provides a versatile digital interface. In

the Direct mode, Chip Select and HIGH/LOW byte

enable co ntro l par allel bu s interfa ce. In t he Handsh ake

mode, the TC7109A will operate with in dustry st andard

UAR Ts in contro lling serial d ata transmiss ion – ideal for

remote d at a log ging. Contro l and monito ring of conv er-

sion timing is provided by the RUN/HOLD input and

Status output.

For applications requiring more resolution, see the

TC500, 15-bit p lus sign AD C dat a she et. The T C7109A

has improved over range recovery performance and

higher o utput drive cap abil ity th an the origina l TC7 109.

All new (or existing) designs should specify the

TC7109A wherever possible.

Part Number

(TC7109X)* Package Temp erature

Range

TC7109CKW 44-Pin PQFP 0°C to +70°C

TC7109CLW 44-Pin PLCC 0°C to +70°C

TC7109CPL 40-Pin PDIP 0°C to +70°C

TC7109IJL 40-Pin CERDIP -25°C to +85°C

12-Bit A-Compatible Analog-to-Digital Convert ers

TC7109/A

DS21456D-page 2  2002-2012 Microchip Technology Inc.

Package Type

NC = No internal connection

TC7109A

TC7109

STATUS

POL

TEST

LBEN

HBEN

CE/LOAD

REF OUT

IN HI

IN LO

COMMON

V+

SEND

RUN/HOLD

BUFF OSC OUT

OSC SEL

OSC IN

MODE

GND

OSC OUT

V-

BUFF

INT

REF IN+

REF CAP+

REF CAP-

REF IN-

INT

IN HI

12 13 14 15 17 18

BUFF

OSC OUT

BUFF

44 43 42 41 39 3840

GND

37 36 35 34

19 20 21 22

268REF OUT

259

2410 SEND

2311

TC7109ACKW

TC7109CKW

44-Pin PQFP 44-Pin PLCC

40-Pin PDIP/CERDIP

RUN/HOLD

V-

COMMON

IN LO

REF IN+

REF CAP+

REF CAP-

REF IN-

V+

STATUS

POL

OSC SEL

OSC OUT

OSC IN

MODE

CE/LOAD

HBEN

LBEN

TEST

INT

IN HI

18 19 20 21 23 24

BUFF

OSC OUT

BUFF

6543 1442

GND

43 42 41 40

25 26 27 28

3214 REF OUT

3115

3016 SEND

2917

TC7109ACLW

TC7109CLW

RUN/HOLD

V-

COMMON

IN LO

REF IN+

REF CAP+

REF CAP-

REF IN-

V+

STATUS

POL

OSC SEL

OSC OUT

OSC IN

MODE

CE/LOAD

HBEN

LBEN

TEST

 2002-2012 Microchip Technology Inc. DS21456D-page 3

TC7109/A

Typical Application

Input

High

BUFF

INT

Buffer Integrator

(+)

INT

Comparator

Comp

Out

3130

CREF

DE (±)

Common

Input Low

INT

37 36

REF

IN+

(–)

(+)

INT

3839

REF

CAP-

REF

CAP+

6.2V

10mA

28 40

V+

V-

REF

OUT

17 3 4 5 6 7 8 9 10 11 12 13 14

22622

23 24 25 21

To Analog

Section

Comp Out

INT

DE (±)

Conversion

Control Logic

Oscillator and

Clock Circuitry

Handshake

Logic

15 16

LBEN

HBEN

CE/LOAD

GND

14 Latches

12-Bit Counter

16 Three-State Outputs

Send

Mode

BUFF

OSC

OUT

OSC

SEL

OSC

OUT

OSC

RUN/

HOLD

Status

POL

TEST

High Order

Byte Inputs

Low Order

Byte Inputs

TC7109A

REF

IN-

Latch

Clock

+–

–

TC7109/A

DS21456D-page 4  2002-2012 Microchip Technology Inc.

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings*

Positive Supply Voltage (GND to V+)..................+6.2V

Negative Supply Voltage (GND to V-) .....................-9V

Analog Input Voltage (Low to High)

(Note 1)

....V+ to V-

Reference In put Voltage:

(Low to High) (Note 1) .............................V+ to V-

Digital Input Voltage:

(Pins 2-27) (Note 2)...........................GND – 0.3V

Power Dissipation, TA < 70°C (Note 3)

CERDIP ......................................................2.29W

Plastic DIP ..................................................1.23W

PLCC ..........................................................1.23W

PQFP..........................................................1.00W

Operati ng Temperatu re Ra nge

Plastic Package (C) ..................... ....0°C to +70°C

Ceramic Packag e (I).............. ...... .-25°C to +85°C

Storage Temperature Range..............-65°C to +150°C

*Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. These are stress ratings only and functional

operatio n of the devic e at these or an y other con ditions

above those indicated in the operation sections of the

specifications is not implied. Exposure to Absolute

Maximum Rating conditions for extended periods may

affect device reliability.

TC7109/TC7109A ELECTRICAL SPECIFICATIONS

Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, unless otherwise indicated.

Symbol Parameter Min Typ Max Unit Test Conditions

Analog

Overload Recovery T ime (TC7109A) — 0 1 Measurement

Cycle

Zero Input Reading -00008±00008 +00008Octal Reading VIN = 0V; Full Scale = 409.6mV

Ratio Metric Reading 37778 37778

40008

40008Octal Reading VIN = VREF

VREF = 204.8mV

NL Non-Linearity (Max Deviation

from Best Straight Line Fit) -1 ±0.2 +1 Count Full Scale = 409.6mV to 2.048V

Over Full Operating

Temperature Range

Rollover Error (Difference in Reading for

Equal Positive and Inputs near

(Full Scale)

-1 ±0.02 +1 Count Full Scale = 409.6mV to

2.048V Over Full Operating

Temperature Range

CMRR Input Common Mode

Rejection Ratio —50 — V/V VCM ±1V, VIN = 0V

Full Scale = 409.6mV

VCMR Common Mode Volt age Range V- +1.5 — V + -1.5 V Input High, Input Low and

Common Pins

eNNoise (P-P Value Not

Exceeded 95% of Time) —15 — VV

IN = 0V, Full Scale = 409.6mV

IIN Leakage Current at Input — 1 10 pA VIN, All Packages: +25°C

— 20 100 pA C Device: 0°C  TA  +70°C

— 100 250 pA I Device: -25°C  TA  +85°C

TCZS Ze ro Reading Drift — 0.2 1 V/°C VIN = 0V

Note 1: Input voltages may exceed supply voltages if input current is limited to ±100A.

2: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device

latch-up. Therefore, it is recommended that input s from sources other than the same power supply should not be applied

to the TC7109A before its power supply is est ablished. In multiple supply systems, the supply to the device should be

activated first.

3: This limit refers to that of the package and will not occur during normal operation.

 2002-2012 Microchip Technology Inc. DS21456D-page 5

TC7109/A

TCFS S cale Factor Temperat ure Coefficient — 1 5 V/°C VIN = 408.9mV = >77708

Reading, Ext Ref = 0ppm/°C

I+Supply Current (V+ to GND) — 700 1500 AV

IN = 0V, Crystal Oscillator

3.58MHz Test Circuit

ISSupply Current (V+ to V-) — 700 1500 A Pins 2-21, 25, 26, 27, 29 Open

VREF Reference Out V oltage -2.4 -2.8 -3.2 V Referenced to V+, 25k

Between V+ and Ref Out

TCREF Ref Out Temperature Coefficient — 80 — p pm/ °C 25k Between V+ and Ref Out

0°C TA  +70°C

Digital

VOH Output High Voltage

IOUT = 700A 3.5 4.3 — V TC7109: IOUT = 100A

Pins 3 -16, 18, 19, 20

TC7109A: IOUT = 700A

VOL Output Low Voltage — 0.2 0.4 AI

OUT = 1.6mA

Output Leakage Current — ±0.01 ±1 A Pins 3 -16 High-Impedance

Control I/O Pull-up Current — 5 — F Pins 18, 19, 20 VOUT = V+ – 3V

Mode Input at GND

Control I/O Loading — — 50 pF HBEN, Pin 19; LBEN, Pin 18

VIH Input High Voltage 2.5 — — V Pins 18 -21, 26, 27

Referenced to GND

VIL Input Low Vol tage — — 1 V Pins 18-21, 26, 27

Referenced to GND

Input Pull-up Current —

—5

25 —

—A

APins 26, 27; VOUT = V+ – 3V

Pins 17, 24; VOUT = V+ – 3V

Input Pull-down Current — 1 — A Pins 21, VOUT = GND = +3 V

Oscillator Output Current, High — 1 — mA VOUT – 2.5V

Oscillator Output Current, Low — 1.5 — mA VOUT – 2.5V

Buffered Oscillator Output Current High — 2 — mA VOUT – 2.5V

Buffered Oscillator Output Current Low — 5 — mA VOUT – 2.5V

tWMode Input Pulse Width 60 — — nsec

HANDLING PRECAUTIONS: These devices are CMOS and mu st be han dled correc tly to preven t damage. Packa ge

and store only in conductive foam, antistatic tubes, or other conducting material. Use proper antistatic handling pro-

cedures. Do not connect in circuits under “power-on” condition s, as high transients may cause permanent damage.

TC7109/TC7 109 A ELECTRICAL SPECIFICATIONS (Continued)

Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, unless otherwise indicated.

Symbol Parameter Min Typ Max Unit Test Conditions

Note 1: Input voltages may exceed supply voltages if input current is limited to ±100A.

2: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device

latch-up. Therefore, it is recommended that input s from sources other than the same power supply should not be applied

to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be

activated first.

3: This limit refers to that of the package and will not occur during normal operation.

TC7109/A

DS21456D-page 6  2002-2012 Microchip Technology Inc.

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Pin Number

(40-Pin PDIP) Symbol Description

1 GND Digital ground, 0V, ground return for all digital logic.

2 STATUS Output HIGH during integrate and de-integrate until data is latched. Output LOW when

analog section is in auto-zero or zero integrator configuration.

3 POL Polarity – High for positive input.

4 OR Over Range – High if over ranged (Three-State Data bit).

12 Bit 12 (Most Significant bit) (Three-State Data bit).

11 Bit 11 (Thr ee-State Data bit).

10 Bit 10 (Three-State Data bit).

9Bit 9 (Three-State Data bit).

8Bit 8 (Three-State Data bit).

10 B7Bit 7 (Three-State Data bit).

11 B6Bit 6 (Three-State Data bit).

12 B5Bit 5 (Three-State Data bit).

13 B4Bit 4 (Three-State Data bit).

14 B3Bit 3 (Three-State Data bit).

15 B2Bit 2 (Three-State Data bit).

16 B1Bit 1 (Least Significant bit) (Three-State Data bit).

17 TEST Input High – Normal operation. Input LOW – Forces all bit outputs HIGH.

Note: This input is used for test purposes only.

18 LBEN Low Byte Enable – with MODE (P in 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin

LOW activates low order byte outputs, B1–B8. With MODE (Pin 21) HIGH, this pin serves as

low byte flag output used in Handshake mod e. (See Figure 3 -7, Figure , and Figure 3-9.)

19 HBEN High Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin

LOW activates high order byte outputs, B9–B12, POL, O R . W i th M O D E (Pin 21) HI GH , th i s

pin serves as high byte flag output used in H andshake mode. See Figures 3-7, 3-8, and 3-9.

20 CE/LOAD Chip Enable/Load – with MODE (Pin 21) LOW, CE/LOAD serves as a master output enable.

When HIGH, B1–B12, POL, OR outputs are disabled. When MODE (Pin 21) is HIGH, a load

strobe is used in handshake mode. (See Figure 3-7, Figure , and Figure 3-9.)

21 MODE Input LOW – Direct Output mode where CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin

18) act as inputs directly controlling byte outputs. Input Pulsed HIGH - Causes immediate

entry into Handshake mode and output of data as in Figure 3-9.

Input HIGH – enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs,

Handshake mode will be entered and data output as in Figure 3-7 and Figure 3-9

at conversions completion.

22 OSC IN Oscillator Input.

23 OSC OUT Oscil lato r Ou tpu t.

24 OSC SEL Oscillator Select – Input HIGH configures OSC IN, OSC OUT, BUFF OSC O UT as RC

oscillator – clock will be same phase and duty cycle as BUFF OSC OUT. Input LOW

configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of frequency

at BUFF OSC OUT.

25 B UF F OSC OUT Buffered Oscillator Output.

26 RUN/HOLD Input HIGH – Conversions continuously performed every 8192 clock pulses.

Input LOW – Conversion in progress completed; converter will stop in auto-zero seven

counts before integrate.

27 SEND Input - Used in Handshake mode to indicate ability of an external device to accept data.

Connect to V+ if not used.

28 V- Analog Nega tive Supply – Nominally -5V with respect to GND (Pin 1).

29 REF OUT Reference Voltage Output – Nominally 2.8V down from V+ (Pin 40).

 2002-2012 Microchip Technology Inc. DS21456D-page 7

TC7109/A

Note: All Digital levels are positive true.

30 BUFF Buf fer Amplifier Output.

31 AZ Auto-Zero Node – Inside foil of CAZ.

32 INT Integrator Output – Outside foil of CINT.

33 COMMON Analog Common – System is auto-zeroed to COMMON.

34 IN LO Diff erential Input Low Side.

35 IN HI Differential Input High Side.

36 REF IN+ Differential Reference Input Positive.

37 REF CAP+ Reference Capacitor Positive.

38 REF CAP- Reference Capacitor Negative.

39 REF IN- Differential Reference Input Negative.

40 V+ Positiv e Supply Voltage – Nominally +5V with respect to GND (Pin 1).

TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)

Pin Number

(40-Pin PDIP) Symbol Description

TC7109/A

DS21456D-page 8  2002-2012 Microchip Technology Inc.

3.0 DETAILED DESCRIPTION

(All Pin Designations Refer to 40-Pin DIP.)

3.1 Analog Section

The Typical Application diagram on page 3 shows a

block diagram of the analog section of the TC7109A.

The circuit will perform conversions at a rate deter-

mined by the clock frequency (8192 clock periods per

cycle), when the RUN/HOLD input is left open or

connected to V+. Each measurement cycle is divided

into four phases, as shown in Figure 3-1. They are:

(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3)

Reference De-integrate (DE), and (4) Zero Integrator

(ZI).

3.1.1 AUTO-ZERO PHASE

The buffer and the integrator inputs are disconnected

from input high and input low and connected to analog

common. The refere nce cap acitor is charged to the ref-

erence voltage. A feedback loop is closed around the

system to charge the auto-zero cap acito r, CAZ, to com-

pensate for offset voltage in the buffer amplifier, inte-

grator, and comparator. Since the comparator is

included in the loop, the AZ accuracy is limited only by

the nois e of the s yste m. The o ffs et referre d to the input

is less than 10V.

3.1. 2 SIGNAL INTEGRATE PHASE

The buf fer and integ rator inputs are removed from com-

mon and connected to input high and input low. The

auto-zero loop is opened. The auto-zero capacitor is

placed in series in the loop to provide an equal and

opposite compensating offset voltage. The differential

voltage between input high and input low is integrated

for a fix ed tim e of 204 8 clo ck per iods. A t the en d of thi s

phase, the polarity of the integrated signal is

determined. If the input signal has no return to the

converter’s power supply, input low can be tied to

analog common to establish the correct Common

mode voltage.

3.1.3 DE-INTEGRATE PHASE

Input high is connected across the previously charged

reference capacitor and input low is internally

connected to analog common. Circuitry within the chip

ensures the capacit or will be connected with th e correct

polarity to cause the integrator output to return to the

zero crossing (established by auto-zero), with a fixed

slope. The time, represented by the number of clock

periods counted for the output to return to zero, is

proportional to the in put signal .

3.1.4 ZERO INTEGRATOR PHASE

The ZI phase only occurs when an input over range

condition exists. The function of the ZI phase is to

eliminate residual charge on the integrator capacitor

after an over range measurement. Unless removed,

the residual charge will be transferred to the auto-zero

capacitor and cause an error in the succeeding

conversion.

The ZI phase virtually eliminates hysteresis, or “cross-

talk” in multiplexed systems. An over range input on

one chan nel will not ca use an error on the n ext channel

measured. This feature is especially useful in thermo-

couple measurements, where unused (or broken

thermocouple) inputs are pulled to the positive supply

rail.

During ZI, the reference cap acitor is charged to the ref-

erence voltage. The signal inputs are disconnected

from the buffer and integrator . The comp arator output is

connected to the buffer input, causing the integrator

output to be driven rapidly to 0V (Figure 3-1). The ZI

phase o nly occu rs follow ing an ov er range an d last s for

a maximum of 1024 clock periods.

3.1.5 DIFFERENTIAL INPUT

The TC7109A has been optimized for operation with

analog co mm on near digi tal ground. With +5V an d -5V

power supplies, a full ±4V full scale integrator swing

maximizes the analog section’s performanc e.

A typ ic a l C M RR o f 86 dB is ac hi e ve d fo r i np u t diffe r en -

tial voltages anywhere within the typical Common

mode range of 1V below the positive supply, to 1.5V

above the negative supply. However, for optimum per-

formance, the IN HI and IN LO inputs should not come

within 2V of either supply rail. Since the integrator also

swings with the Common mode voltage, care must be

exercised to ensure the integrator output does not sat-

urate. A worst-case condition is near a full scale nega-

tive differential input voltage with a large positive

Common mode voltage. The negative input signal

drives the integrator positive when most of its swing

has been used up by the positive Common mode volt-

age. In such cases, the integrator swing can be

reduced to less than the recommended ±4V full scale

value, with some loss of accuracy. The integrator

output c an sw ing to withi n 0.3V of either sup ply w itho ut

loss of linearity.

 2002-2012 Microchip Technology Inc. DS21456D-page 9

TC7109/A

3.1.6 DIFFERENTIAL REFERENCE

The reference voltage can be generated anywhere

within the power supply voltage of the converter. Roll-

over voltage is the main source of Common mode

error , caused by the reference capacitor losing or gain-

ing charge, due to stray capac ity on its nodes. With a

large Common mode voltage, the reference capacitor

can gain charge (increase voltage) when called upon to

de-integrate a positive signal and lose charge

(decrease voltage) when called upon to de-integrate a

negative input signal. This difference in reference for

(+) or (–) inpu t voltages will ca us e a ro llo ve r error. This

error can be hel d to less than 0.5 count, worst-ca se, by

using a large reference capacitor in comparison to the

stray capacitance. To minimize rollover error from

these sources, keep the reference Common mode

voltage near or at analog common.

3.2 Digit al Section

The digital section is shown in Figure 3-2 and includes

the clock oscillator and scaling circuit, a 12-bit binary

counter with output latches and TTL compatible three-

state output drivers, UART handshake logic, polarity,

over range, and control logic. Logic levels are referred

to as LOW or HIGH.

Inputs driven from TTL gates should have 3k to 5k

pull-up resistors added for maximum noise immunity.

For minimum power consumption, all inputs should

swing from GND (LOW) to V+ (HIGH).

3.2.1 STATUS OUTPUT

During a co nv ers ion cy cl e, th e Status outp ut goes high

at the beginning of signal integrate and goes low one-

half clock period after new data from the conversion

has been stored in the output latches (see Figu re 3-1).

The signal may be used as a “data valid” flag to drive

interrupts, or for monitoring the status of the converter.

(Data will not change while status is low.)

3.2.2 MODE INPUT

The Output mode of the converter is controlled by the

MODE input. The converter is in its “Direct” Output

mode, when the MODE input is LOW or left open. The

output data is directly accessible under the control of

the chip and byte enable inputs (this input is provided

with a pull-do wn resist or to ensu re a LOW l evel when

the pin is left open). When the MODE input is pulsed

high, the converter enters th e UA RT Handshake mod e

and outputs the data in 2 bytes, then returns to “Direc t”

mode. When the MODE input is kept HIGH, the

converter will output data in the Handshake mode at

the end of every conversion cycle. With MODE = 0

(direct bus transfer), the send input should be tied to

V+. (See “Handshake Mode”.)

3.2.3 RUN/HOLD INPUT

With the RUN/HOLD input high, or open, the circuit

operates normally as a dual slope ADC, as shown in

Figure 3-1. Conversion cycles operate continuously

with the output latches updated after zero crossing in

the De-integrate mode. An internal pull-up resistor is

provided to ensure a HIGH level with an open input.

The RUN/HOLD input may be used to shorten conver-

sion ti me . If RUN/HOLD goes LOW any time after zero

crossing in the De-integrate mode, the circuit will jump

to auto- zero and elim inate tha t portion of ti me normally

spent in de-integrate.

If RUN/HOLD stays or goes LOW, the conversion will

comple te with mi ni mum t im e i n d e-i nteg rate . It will stay

in auto- zero for the minimum time and wait in auto -zero

for a HIGH at the RUN/HOLD input. As shown in

Figur e 3-3, the Status output will go HIGH, 7 clo ck peri-

ods after RUN/HOLD is changed to HIGH, and the

converter will begin the integrate phase of the next

conversion.

The RUN/HOLD input allows controlled conversion

interface. The converter may be held at Idle in auto-

zero with RUN/HOLD LOW. The conversion is started

when RUN/HOLD goes HIGH, and the new data is

valid when the Status output goes LOW (or is trans-

ferred to the UART; see “Handshake Mode”). RUN/

HOLD may now go LOW, terminating de-integrate and

ensuring a minimum auto-zero time before stopping to

wait for the next conversion. Conversion time can be

minimized by ensuring RUN/HOLD goes LOW during

de-integrate, after zero crossing, and goes HIGH after

the hold point is reached.

The required activity on the RUN/HOLD input can be

provided by connecting it to the buffered oscillator

output. In this mode, the input value measured

determines the conversion time.

TC7109/A

DS21456D-page 10  2002-2012 Microchip Technology Inc.

FIGURE 3-1: Conversion Timing (RUN/HOLD) Pin High

FIGURE 3-2: Digital Section

Internal Clock

Integrator Output

for Normal Input

Integrator

Saturates

Internal Latch

Integrator Output

for Over Range Input No Zero Crossing

Zero Integrator

Phase forces

Integrator Output

to 0V

Zero Crossing

Occurs

Zero Crossing

Detected

INT

Phase II

Status Output

Phase I

Phase III AZ

Fixed

2048

Counts

2048

Counts

Min.

4096

Counts

Max

Number of Counts to Zero Crossing

Proportional to VIN

After Zero Crossing, Analog section will

be in Auto-Zero Configuration

TEST

POL

2262223242521

STATUS RUN/

HOLD

OSC

OUT

OSC

SEL

BUFF

OSC

OUT

MODE

Analog

Section

COMP OUT

INT

DE (±)

Conversion

Control Logic

Oscillator and

Clock Circuitry

High Order

Byte Outputs

Low Order

Byte Outputs

Handshake

Logic

SEND

LBEN

HBEN

CE/LOAD

GND

14 Latches

12-Bit Counter

14 Three-State Outputs

Latch

Clock

 2002-2012 Microchip Technology Inc. DS21456D-page 11

TC7109/A

FIGURE 3-3: TC7109A RUN/HOLD Operation

3.2.4 DIRECT MODE

The dat a outp uts (bit s 1 throu gh 8, low o rder bytes ; bits

9 through 12, pol arity and over range hig h order byte s)

are accessible under control of the byte and chip

enable terminals as inputs, with the MODE pin at a

LOW level. These three inputs are all active LOW.

Internal pull-up resistors are provided for an inactive

HIGH level when left open. When chip enable is LOW,

a byte enable input LOW will allow the outputs of the

byte to become active. A variety of parallel data

accessing techniques may be used, as shown in the

“Interfacing” section. (See Figure 3-4 and Table 3-1.)

The access of data should be synchronized with the

conversion cycle by monitoring the Status output. This

prevents accessing data while it is being updated and

eli m inates the acquisition of erroneous data.

FIGURE 3-4: TC7109A Direct Mode

Output Timing

TABLE 3-1: TC7109A DIRECT MODE

TIMING REQUIREMENTS

3.2.5 HANDSHAKE MODE

An alternative means of interfacing the TC7109A to

digital systems is provided when the Handshake Out-

put mode of the TC7109A becomes active in controlling

the flow of data, ins tead of pas sively respon ding to chip

and byte en able inputs . This mode allows a direc t inter-

face between the TC7109A and industry standard

UARTs with no external logic required. The TC7109A

provides all the control and flag signals necessary to

sequence the two bytes of data into the UART and ini-

tiate their transmission in serial form when triggered

into the Handshake mode. The cost of designing

remote dat a acq uisition station s is reduced using serial

data transmission to minimize the number of lines to

the central controlling processor.

Integrator Output

Internal Clock

Determinated at

Zero Crossing

Detection

Auto-Zero Phase I

Min 1790 Counts

Max 2041 Counts Static in

Hold State

INT

Phase II

RUN/HOLD input is ignored until end of auto-zero phase.

*Note:

Internal Latch

Status Output

RUN/HOLD Input

7 Counts

= High-Impedance

CE/LOAD

As Input

tCEA

tBEA

HBEN

As Input

tDAB tDAB

LBEN

As Input

High Byte

Data

Low Byte

Data

Valid

tDAC tDHC

Data

Valid

Data

Valid

Symbol Description Min Typ Max Units

tBEA Byte Enable Width 200 500 — nsec

tDAB Data Acce ss Time

from Byte Enable — 150 300 nsec

tDHB Data Hold Time

from Byte Enable — 150 300 nsec

tCEA Chip Enable Width 300 500 nsec

tDAC Data Acc ess Time

from Chip Enable — 200 400 nsec

tDHC Data Hold Time

from Chip Enable — 200 400 nsec

TC7109/A

DS21456D-page 12  2002-2012 Microchip Technology Inc.

The MODE input controls the Hands hake mode. Whe n

the MODE inpu t is held HIGH, the TC7 109A ente rs th e

Handshake mode af ter new data has been stored in th e

output latches at the end of every conversion per-

formed (see Figure 3-7 and Figure ). Entry into the

Handshake mode may be triggered on demand by the

MODE input. At any time during the conversion cycle,

the LOW-to-HIGH transition of a short pulse at the

MODE input will cause immediate entry into the Hand-

shake mode. If this pulse occurs while new data is

being stored, the entry into Handshake mode is

delayed until the data is stable. The MODE input is

ignored in the Handshake mode, and until the

converter completes the output cycle and clears the

Handshake mode, data updating will be inhibited (see

Figure 3-9).

When the MODE input is HIGH, or when the converter

enters the Handshake mode, the chip and byte enable

inputs become TTL compatible outputs, which provide

the outpu t cycle con trol signals (se e Figure 3- 7, Figure

and Figure 3-9). The SEND input is used by the con-

verter as an indication of the ability of the receiving

device (such as a UART) to accept data in the Hand-

shake mode. The sequence of the output cycle with

SEND held HIGH is shown in Figure 3-7. The Hand-

shake m ode (intern al MODE HIGH ) is entered a fter th e

data latch pulse (the CE/LOAD, LBEN and HBEN

terminals are active as outputs, since MODE remains

HIGH).

The HIGH level at the SEND input is sensed on the

same HIGH-to-LOW internal clock edge. On the next

LOW-to-HIGH internal clock edge, the high order byte

(bits 9 through 12, POL, and OR) outputs are enabled

and the CE/LOAD and the HBEN outputs assume a

LOW level. The CE/LOAD output remains LO W for one

full internal clock period only; the data outputs remain

active for 1-1/2 intern al clock pe riods; and th e high byte

enable remains LOW for 2 clock periods.

The CE/LOAD output LOW level, or LOW-to-HIGH

edge, m ay be us ed as a s ynchron izing si gnal to en sure

valid data, and the byte enable as an output may be

used as a byte identification flag. With SEND remaining

HIGH, the converter completes the output cycle using

CE/LOAD and LBEN, while the low order byte outputs

(bits 1 through 8) are activated. When both bytes are

sent, the Handshake mode is terminated. The typical

UART interfacing timing is shown in Figure .

The SEND input is used to delay portions of the

sequence, or handshake, to ensure correct data trans-

fer. This timing diagram shows an industry standard

HD6403 or CDP1854 CMOS UART to interface to

serial data channels. The SEND input to the TC7109A

is driven by the TBRE (Transmitter Buffer Register

Empty) output of the UART, and the CE/LOAD input of

the TC7109A drives the TBRL (Transmitter Buffer

Regis ter Load) input to the UAR T. The eight transm itter

buffer register inputs accept the parallel data outputs.

With the UART transmitter buffer register empty, the

SEND inpu t will be HIGH when the Hands hake mode is

entered, after new data is stored. The high order byte

outputs become active and the CE/LOAD and HBEN

inputs will go LOW after SEND is sensed. When CE/

LOAD goes HIGH at the end of one clock period, the

high orde r byte d ata is clo cked into the UAR T t ransmi t-

ter buffer register. The UART TBRE output will go LOW,

which halts the output cycle with the HBEN output

LOW, and the hi gh order byte ou tputs ac tive. When the

UART has transferre d t he d at a to the transmitter regis -

ter and cleared the transmitter buffer register, the

TBRE returns HIGH. The high order byte outputs are

disabled on the next TC7109A internal clock HIGH-to-

LOW edge, and on e-half int ernal cl ock late r, the HBEN

output retu rns HIGH. The CE/LOAD and LBEN output s

go LOW a t the same t ime as the low order b yte output s

become active. When the CE/LOAD returns HIGH at

the end of one clock period, the low order data is

clocked into the UART transmitter buffer register, and

TBRE again goes LOW. The next TC7109A internal

clock HIGH-to-LOW edge will sense when TBRE

returns to a HIGH, disabling the data inputs. One-half

internal clock later, the Handshake mode is cleared,

and the CE/LOAD, HBEN and LBEN terminals return

HIGH and stay active, if MODE still remains HIGH.

Handshake output sequences may be performed on

demand by triggering the converter into Handshake

mode with a LO W-to-HIGH edg e on the MODE input. A

handshake output sequence triggered is shown in

Figure 3-9. The SEND input is LOW when the

converter enters Handshake mode. The whole output

sequence is controlled by the SEND input, and the

sequence for the fi rst (high order) byte is similar to the

sequence for the second byte.

Figure 3-9 also shows that the output sequence can

take longer than a conversion cycle. New data will not

be latched when the Handshake mode is still in prog-

ress and is, therefore, lost.

3.3 Oscillator

The oscillator may be over driven, or may be operated

as an RC or crystal oscillator. The OSCILLATOR

SELECT input optimizes the internal configuration of

the oscillator for RC or crystal operation. The OSCIL-

LATOR SELECT input is provided with a pull-up resis-

tor. When the OSCILLATOR SELECT input is HIGH or

left open, the oscillator is configured for RC operation.

The internal clock will be the same frequency and

phase as the signal at the BUFFERED OSCILLATOR

OUTPUT. Connect the resistor and capacitor as in

Figur e . The circuit w ill oscillate at a freq uency given b y

f = 0.45 /RC. A 100 k resistor is recommend ed for use-

ful ranges of frequency. The capacitor value should be

chosen such that 2048 clock periods are close to an

integral multiple of the 60Hz period for optimum 60Hz

line rejection.

 2002-2012 Microchip Technology Inc. DS21456D-page 13

TC7109/A

FIGURE 3-5: TC7109A RC Oscillator

With OSCILLATOR SELECT input LOW, two on-chip

capacitors and a feedback device are added to the

oscillator. In this configuration, the oscillator will oper-

ate wi th mo st cry st als i n the 1MHz to 5MHz range , wi th

no external components (Figure ). The OSCILLATOR

SELECT input LOW inserts a fixed 458 divider circuit

between the BUFFERED OSCILLATOR OUTPUT and

the internal clock. A 3.58MHz TV crystal gives a

division ratio, providing an integration time given by:

EQUATION 3-1:

FIGURE 3-6: Crystal Oscillator

The error is less than 1% from two 60Hz periods, or

33.33msec, which will give better than 40dB, 60Hz

rejection. The converter will operate reliably at conver-

sion rates up to 30 per second, corresponding to a

clock frequency of 245.8kHz.

When the os cillator is to be over driven, the OSCILLA-

T OR OU TPUT shou ld be lef t open, and the over driv ing

signal should be applied at the OSCILLATOR INPUT.

The internal clock will be of the same duty cycle, fre-

quency and phase as the input signal. When the

OSCILLATOR SELECT is at GND, the clock will be

1/58 of the input frequency.

FIGURE 3-7: TC7109A Handshake with Send Input Held Positive

OSC

OUT

Buffered

OSC OUT

OSC

SEL

V+ or Open

OSC

= 0.45/RC

t = (2048 clock periods) = 33.18 msec

3.58 MHz

OSC

OUT

Buffered

OSC OUT

OSC

SEL

GND

V+

OSC

Clock

Crystal

= Three-State

High-Impendance

Integrator Output

Data Invalid

Data Valid

Internal Clock

Internal Latch

Status Output

Mode Input

Internal Mode

Send Input

CE/LOAD

HBEN

High Byte Data

LBEN

Low Byte Data

= Don't Care = Three-State

will Pull-up

UART

Norm

Terminates

UART Mode

Zero Crossing Detected

Zero Crossing Occurs

Send Sensed Send Sensed

Mode Low, not

in Handshake Mode

Disables Outputs

CE/LOAD,

HBEN,

LBEN

Mode High Activates

CE/LOAD, HBEN, LBEN

TC7109/A

DS21456D-page 14  2002-2012 Microchip Technology Inc.

FIGURE 3-8: TC7109A Handshake – Typical UART Interface Timing

FIGURE 3-9: TC7109A Handshake Triggered by Mode Input

= Three-State High-Impedance

Integrator Output

Data Valid

Internal Clock

Internal Latch

Status Output

Mode Input

Internal Mode

Send Input (UART TBRE)

CE/LOAD Output (UART TBRL)

HBEN

High Byte Data

LBEN

Low Byte Data

= Don't Care

UART

Norm

Terminates

UART Mode

Zero Crossing Detected

Zero Crossing Occurs

Send

Sensed Send

Sensed

Send

Sensed

Data Valid

Terminates

UART Mode

= Three-State

High-Impedance

Internal Clock

Internal Latch

Status Output

Mode Input

Internal Mode

Send Input

CE/LOAD as Output

HBEN

High Byte Data

LBEN

Low Byte Data

= Don't Care = Three-State

with Pull-up

UART

Norm Send

Sensed

Send

Sensed

Zero Crossing Detected

Zero Crossing Occurs

Status Output unchanged

in UART Mode

Latch Pulse inhibited in UART Mod

Positive Transiton causes

Entry into UART Mode

DE Phase III

Send

Sensed

 2002-2012 Microchip Technology Inc. DS21456D-page 15

TC7109/A

3.4 Test Input

The count er and its outputs may be te sted easily . Whe n

the TEST inpu t is con necte d to GND, the inte rnal cl ock

is disabled and the counter outputs are all forced into

the HIGH state. When the input returns to the 1/2

(V+ – GND) volt age or to V+ an d one cloc k is input, th e

counter outputs will all be clocked to the LOW state.

The counter output latches are ena bled when the TEST

input is taken to a level h alfw a y b etw ee n V+ a nd G ND ,

allow ing the counter con tents to be exam ined any time.

3.5 Component Value Selection

The in tegra tor ou tput sw ing for full sc ale s hould be as

large as possible. For example, with ±5V supplies and

COMMON connected to GND, the nominal integrator

output swing at full scale is ±4V. Since the integrator

output ca n go to 0 .3V from either suppl y wi thou t signif-

icantly effecting linearity, a 4V integrator output swing

allow s 0. 7V f or v ar i ati o ns in ou tp ut swi n g, due t o c o m-

ponent value and oscillator tolerances. With ±5V sup-

plies and a Common mode voltage range of ±1V

required, the component va lues should be selected to

provide ±3V integrator output swing. Noise and roll-

over errors will be slightly worse than in the ±4V case.

For large C ommon mode v oltage rang es, the integra tor

output swing must be reduced further. This will

increase both noise and rollover errors. To improve

performance, ±6V supplies may be used.

3.5.1 INTEGRATING CAPACITOR

The integrating capacitor, CINT, should be selected to

give the maximum integrator output voltage swing that

will no t saturate the integ rator to within 0.3 V from either

supply. A ±3.5V to ±4V integrator output swing is nom-

inal for the TC7109A, with ±5V supplies and analog

commo n connect ed to GND. F or 7-1/2 conv ersions p er

second (61.72kHz internal clock frequency), nominal

values CINT and CAZ are 0.15F and 0.33F, resp ec-

tively. These values should be changed if different

clock frequencies are used to maintain the integrator

output voltage swing. The value of CINT is given by:

EQUATION 3-2:

The integrating capacitor must have low dielectric

absorption to prevent rollover errors. Polypropylene

capacitors give undetectable errors, at reasonable

cost, up to +85°C.

3.5.2 INTEGRATING RESISTOR

The integra tor and buf fer amplifi ers have a cla ss A out-

put st age wi th 100A of qu iescent current. Th ey suppl y

20A of drive current with negligible non-linearity. The

integrati ng resistor s hould be larg e enough to re main in

this very linear region over the in put vol t ag e range, but

small enough that u ndu e leak age req uirem ents are n ot

placed o n the PC board. For 2.048V ful l scale, a 100k

resistor is recommended and for 409.6mV full scale, a

20k resis tor is recommende d. RINT may be selected for

other values of full scale by:

EQUATION 3-3:

3.5.3 AU TO-Z ER O CAPACITO R

As the auto-zero capacitor is made large, the system

noise is reduced. Since the TC7109A incorporates a

zero integrator cycle, the size of the auto-zero capaci-

tor does not af fect overload recovery. The optimal value

of the auto-zero capacitor is between 2 and 4 times

CINT. A typical value for CAZ is 0.33F.

The inne r foil of CAZ shoul d be conne cted to Pin 31 an d

the outer fo il to the RC sum ming jun ction. The inne r foil

of CINT should be connected to the RC summing

junctio n and the o uter foil to Pin 32, for be st reje ction of

stray pickups.

3.5.4 REFERENCE CAPACITOR

A 1F capacitor is recommended for most circuits.

However , where a large Common mode voltage exists,

a larger va lue is re quired to preven t rollov er error (e.g .,

the reference low is not analog common), and a

409.6mV scale is used. The rollover error will be held

to 0.5 count with a 10F capacitor.

3.5.5 REFERENCE VOLTAGE

To generate f ull scale output of 4 096 count s, the an alog

input required is VIN = 2VREF. For 409.6mV full scale,

use a reference of 204.8mV. In many applications,

where the ADC is connected to a transducer, a scale

factor will exist between the input volt age and the digital

reading. For instance, in a measuring system, the

designer might like to have a full scale reading when

the voltage for the transducer is 700mV. Instead of

dividing the input down to 409.6mV, the designer

should use the input voltage directly and select

VREF = 350mV. Suitable values for integrating resistor

and capacitor would be 34k and 0.15F. This makes

the system slightly quieter and also avoids a divider

network o n the in put. An other advant age of this s ystem

occurs when temperature and weight measurements,

with an offset or tare, are desired for non-zero input.

The of fset may be introduced by conn ecting the voltage

output of the transducer between common and analog

high, an d the offse t volt age betw een commo n and an a-

log low, observing polarities carefully. In processor

based systems using the TC7109A, it may be more

desirable to use software and perform this type of

scaling or tare subtraction digitally.

(2048 Clock Period) (20 A)

Integrator Output Vol tage Swings

CINT =

Full Scale Voltage

20 A

RINT =

TC7109/A

DS21456D-page 16  2002-2012 Microchip Technology Inc.

3.5.6 REFERE NCE SOURCE S

A major factor in the absolute accuracy of the ADC is

the stability of the reference voltage. The 12-bit resolu-

tion of the TC7109A is one part in 4096, or 244 ppm.

Thus, for the on-board reference temperature coeffi-

cient of 70p pm /°C , a t em pera ture difference o f 3°C w il l

introduce a one-bit absolute error. Where the ambient

temperature is not controlled, or where high accuracy

absolute measurements are being made, it is

recommended that an external high quality reference

be used.

A reference output (Pin 29) is provided, which may be

used with a resistive divider to generate a suitable ref-

erence voltage (20mA may be sunk without significant

variation in output voltage ). A pull-up bias device is pro-

vided, which sources about 10A. The output voltage is

nominally 2.8V below V+. When using the on-board

reference, REF OUT (Pin 29) should be connected to

REF IN- ( pin 39), and REF IN+ shoul d be conne cted to

the wiper of a precision potentiometer between REF

OUT and V+. The test circuit shows the circuit for a

204.8mV reference, generated by a 2k precision

potentiometer in series with a 24k fixed resistor.

 2002-2012 Microchip Technology Inc. DS21456D-page 17

TC7109/A

4.0 INTERFACING

4.1 Direct Mode

Combinations of chip enable and byte enable control

signals, which may be used when interfacing the

TC7109A to parallel data lines, are shown in Figure .

The CE/LOAD input may be tied low , allowing either byte

to be controlled by its own enable (see Figure (A)).

Figure (B) shows the HBEN and LBEN as f lag in puts,

and CE/LOAD as a master enable, which could be the

READ strobe available from most microprocessors.

Figure (C) shows a configuration where the two byte

enables are connected together. The CE/LOAD is a

chip ena ble, and the HBEN and LBEN may be used as

a second chip enable, or connected to ground. The 14

data outputs will be enabled at the same time. In the

direct MODE, SEND should be tied to V+.

Figure shows interfacing several TC7109A’s to a bus,

ganging the HBEN and LBEN signals to several

converters together, and using the CE/LOAD input to

select the desired conver ter.

Figure through Figure give practical circuits utilizing

the parallel three-state output capabilities of the

TC7109 A. Figure shows paralle l interfac e to the 874 8/

49 systems via an 825 5 PPI, whe re the TC7109A data

outputs are active at all times. This interface can be

used in a read-after-update sequence, as shown in

Figure . The data is accessed by the high-to-low

transition of the Status driving an interrupt to the

microcontroller.

The RUN/HOLD input is also used to initiate

conversions under software control.

Direct interfacing to most microcontroller busses is

easily accomplished through the three-state output of

the TC7109A.

Figure 4-8 is a typical connection diagram. To ensure

requirements for setup and hold times, minimum pulse

widths, and the drive limitations on long busses are

met, it is necessary to carefully consider the system

timing in this type of interface. This type of interface is

used when the memory peripheral address density is

low, providing simple address decoding. Interrupt

handling can be simplified by using an interface to

reduce the component count.

FIGURE 4-1: Direct Mode Chip and Byte Enable Combination

TC7109A

MODE CE/LOAD

- B

POL, OR

- B

LBENHBEN

GND

Analog In

Convert

Control

RUN/HOLD

TC7109A

MODE CE/LOAD

- B

POL, OR

LBENHBEN

GND

Analog In

Convert

RUN/HOLD

TC7109A

MODE CE/LOAD

- B

POL, OR

- B

LBENHBEN

Analog In

Convert

RUN/HOLD

Chip Select 1

GND or

Chip Select 2

Byte Flags

GND Chip Select

A. B. C.

TC7109/A

DS21456D-page 18  2002-2012 Microchip Technology Inc.

FIGURE 4-2: Three-Stating Several TC7109As to a Small Bus

FIGURE 4-3: Full Time Parallel Interface to



PD87 48H/ 494 Micr oc ont ro ller s

TC7109A

MODE CE/LOAD

- B

POL, OR

- B

LBENHBEN

GND

Analog In

RUN/HOLD +5V

Converter Select Converter Select Converter Select

TC7109A

MODE CE/LOAD

9 -

POL, OR

- B

LBENHBEN

GND

Analog In

RUN/HOLD +5V

TC7109A

MODE CE/LOAD

- B

POL, OR

- B

LBENHBEN

GND

Analog In

RUN/HOLD +5V

Byte Select Flags

TC7109A

MODE CE/LOAD

B9 - B12

POL, OR

B1 - B8

STATUS

RUN/HOLD

LBENHBEN

GND

See Text

μPD8255A

(Mode 0)

RD WR D7 - D0 A0 - A1

PA5 - PA0

PB7 - PB0

PC5

μPD8748H/49H

Data Bus

Control Bus

Address Bus

Analog In

+5V

 2002-2012 Microchip Technology Inc. DS21456D-page 19

TC7109/A

FIGURE 4-4: Full Time Parallel Interface to



PD87 48H/ 494 Micr oc ont ro ller s

FIGURE 4-5: TC7109A Handshake Interface to



PD8748H/494 Microcontrollers

TC7109A

MODE CE/LOAD

- B

POL, OR

- B

STATUS

RUN/HOLD

LBENHBEN

GND

+5V

(See Text)

1mF

μPD8255A

RD WR D7 - D0

PC6

A0 - A1

PA5 - PA0

PB7 - PB0

PC4

STB

PC6 INTR

μPD8748H/49H

Data Bus

Control Bus

Address Bus

INTR

Analog In

10kW

TC7109A

- B

POL, OR

- B

CE/LOAD

SEND

RUN/HOLD

MODE

μPD8255A

(Mode 1)

RD WR D7 - D0

A0 - A1

PA7 - PA0

PC4

PC5

PC6

PC7 INTR

μPD8748H/49H

Data Bus

Control Bus

Address Bus

Analog In

STB

PC3

IBF

TC7109/A

DS21456D-page 20  2002-2012 Microchip Technology Inc.

4.2 Handshake Mode

The Handshake mode provides an interface to a wide

variety of external devices. The byte enables may be

used as byte identification flags, or as load enables,

and exte rnal latche s may be cl ocked by th e rising edg e

of CE/LOAD. A handshak e interfac e to Intel® micropro-

cessors using an 8255 PPI is shown in Figure . The

handshake operation with the 8255 is controlled by

inverting its Input Buffer Full (IBF) flag to drive the

SEND input to the TC7109A, and using the CE/LOAD

to drive th e 8255 strobe . The internal control regi ster of

the PPI should be set in MODE 1 for the port used. If

the 8255 IBF fla g is LOW a nd the TC7109 A is in Han d-

shake m ode, the next word wil l be strobed into the po rt.

The strobe will cause IBF to go HIGH (SEND goes

LOW), whic h wi ll keep the ena bled by te outp uts activ e.

The PPI will generate an interrupt which, when

execut ed, will res ult in th e data being read . The I BF will

be reset LOW when the byte is read, causing the

TC7109A to sequence into the next byte. The MODE

input to the TC7109A is connected to th e control line on

the PPI.

The data from every conversion will be sequenced in

two bytes in the system, if this output is left HIGH, or

tied HIGH separately. (The data access must take less

time than a conversion.) The output sequence can be

obtained on demand if this output is made to go from

LOW to HIGH and the interrupt may be used to reset

the MODE bit.

Conve rsions m ay be obt ain ed on co mmand un der sof t-

ware control by driving the RUN/HOLD input to the

TC7109A by a bit of the 8255. Another peripheral

device may be serviced by the unused port of the 8255.

The Handshake mode is particularly useful for directly

interfac ing to ind ustry st anda rd UARTs (su ch as Intersi l

HD-6402), providing a means of serially transmitting

converted data with minimum component count.

A typical UART connection is shown in Figure . In this

circuit, any word received by the UART causes the

UART DR (Dat a Ready) outp ut to go HIGH . The MODE

input to the TC7109A goes HIGH, triggering the

TC7109 A into Handsha ke mode. The high order byte is

output to the UART and when the UART has trans-

ferred the data to the Transmitter register, TBRE

(SEND) goes H IGH again, LBEN will go HIGH, driving

the UART DRR (Data Ready Reset), which will sign al

the end of the t rans fer of data from t he TC 7109A t o the

UART.

An extension of the typical connection to several

TC7109A’s with one UART is shown in Figure 4-7. In

this c ircuit, the wo rd received by the UAR T (availabl e at

the RBR outputs when DR is HIGH) is used to select

which converter will handshake with the UART. Up to

eight TC7 109A’s may inte rface with on e UAR T, with no

external components. Up to 256 converters may be

accessed on one serial line with additional

components.

FIGURE 4-6: TC7109 Typical UART Interface

GND

BUFF OSC OUT

STATUS

HBEN

B1 - B8

TEST

LBEN

MODE

CE/LOAD

SEND

V+ 40

TC7109A

CLK

RESET

5–12

GND

RRD

RBR1–8

SFD

RR1

TRO

TRC

RRC

EPE

CLS1

CLS2

SBS

CRL

*TBR1–8

TRE

DRR

TBRL

TBRE

HD-640R

CMOS UART

+5V

GND

+5V

GND

Serial

Input

Serial

Output

1011

GND

+5V

GND

+5V

-5V

+5V or Open

GND

3.58MHz

Crystal

Analog GND

External

Reference

–Input

CAZ

0.33μF

CINT

0.15μF

0.01μF

1MΩ

1μF

3–8

9–16

B9 - B12,

POL, OR

26–33

For lowest power consumption, TBR1-TBR8 inputs should have 100kΩ pull-up resistors to +5V.

Send any word to UART to transmit latest result.

RINT 20kΩ

100kΩ

0.2VREF

1VREF

CD4060B

REF IN-

REF CAP-

REF CAP+

REF IN+

IN HI

IN LO

COM

INT

REF OUT

BUFF

V-

RUN/HOLD

OSC SEL

OSC OUT

OSC IN

–

*Note:

 2002-2012 Microchip Technology Inc. DS21456D-page 21

TC7109/A

FIGURE 4-7: Handshake Interface for Multiplexed Converters

FIGURE 4-8: Connection Diagram

TC7109A

- B

POL, OR

- B

LBENHBEN

Analog In

RUN/HOLD

SENDMODE CE/

LOAD

+5V

TC7109A

- B

POL, OR

- B

LBENHBEN

8-Bit Data Bus

Analog In

RUN/HOLD

SENDMODE CE/

LOAD

+5V

TC7109A

- B

POL, OR

- B

LBENHBEN

Analog In

RUN/HOLD

SENDMODE CE/

LOAD

+5V

TBRL DRR

GND

TBRE RBR1 - RBR8 SFD TBR1 - TBR8

Serial Output

Serial Input

6402 CMOS UART

V+

GND

TEST

RUN/HOLD

STATUS

LBEN

HBEN

TC7109A

RESET

INT

PSEN

ALE

PROG

VDD

VCC

GND

P20 - P27

μPD8748H/49H

CMOS

Microcomputer

+5V

Other I/O

+5V

GND

-5V

GND

3.58MHz

Crystal

Analog

GND

External

Reference

–Input

CAZ

0.33μF

RINT

20k

10 k

0.2 VREF

1 VREF

XTAL2XTAL1

P14 - P17

P13

P12

P11

P10

DB0 - DB7

B9 - B12,

POL, OR

B1 - B8

CE/LOAD

21-24,

35-38

12-19

31-34

CINT

0.15μF

0.01μF

1MΩ

1μF

GND

+5V

GND

3-8

9-16

REF IN-

REF CAP-

REF CAP+

REF IN+

IN HI

HI LO

COM

INT

BUFF

REF OUT

V-

OSC SEL

OSC OUT

OSC IN

SEND

BUFF OSC OUT

MODE

–

TC7109/A

DS21456D-page 22  2002-2012 Microchip Technology Inc.

5.0 INTEGRATING CONVERTER

FEATURES

The outp ut of in tegr ating A DCs repres ent s the integra l,

or average, of an input voltage over a fixed period of

time. Compared with techniques in which the input is

sampled and held, the integrating converter averages

the effects of noise. A second important characteristic

is that time is used to quantize the answer, resulting in

extremely small non-linearity errors and no missing

output codes. The integrating converter also has very

good rejection of frequencies whose periods are an

integral multiple of the measurement period. This

feature can be used to advantage in reducing line

frequenc y noi se (Figure ).

FIGURE 5-1: Normal Mode Rejection of

Dual Slope Converter as a Function of

Frequency

0.1/t 1/t 10/t

Input Frequency

Normal Mode Rejection Plan

t = Measurement

Period

 2002-2012 Microchip Technology Inc. DS21456D-page 23

TC7109/A

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Pack age marking data not available at this time.

6.2 Taping Form

Component Taping Orientation for 44-Pin PQFP Devices

User Direction of Feed

Pin 1

Standard Reel Component Orientation

for 713 Suffix Device

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

44-Pin PQFP 24 mm 16 mm 500 13 in

Carrier Tape, Number of Components Per Reel and Reel Size

Note: Drawing does not represent total number of pins.

TC7109/A

DS21456D-page 24  2002-2012 Microchip Technology Inc.

.557 (14.15)

.537 (13.65)

.398 (10.10)

.390 (9.90)

.031 (0.80) TYP.

.018 (0.45)

.012 (0.30) .398 (10.10)

.390 (9.90)

.010 (0.25) Typ.

.096 (2.45) Max.

.557 (14.15)

.537 (13.65)

.083 (2.10)

.075 (1.90)

.041 (1.03)

.026 (0.65)

7° Max.

.009 (0.23)

.005 (0.13)

44-Pin PQFP

Pin 1

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging

 2002-2012 Microchip Technology Inc. DS21456D-page 25

TC7109/A

6.3 Package Dimensions

Dimensions: inches (mm)

2.065 (52.45)

2.027 (51.49)

.200 (5.08)

.140 (3.56)

.150 (3.81)

.115 (2.92)

.070 (1.78)

.045 (1.14)

.022 (0.56)

.015 (0.38)

.110 (2.79)

.090 (2.29)

.555 (14.10)

.530 (13.46)

.610 (15.49)

.590 (14.99)

.015 (0.38)

.008 (0.20)

.700 (17.78)

.610 (15.50)

.040 (1.02)

.020 (0.51)

40-Pin PDIP (Wide)

Pin1

3° Min.

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging

Dimensions: inches (mm)

.015 (0.38)

.008 (0.20)

.620 (15.75)

.590 (15.00)

.700 (17.78)

.620 (15.75)

.540 (13.72)

.510 (12.95)

2.070 (52.58)

2.030 (51.56)

.210 (5.33)

.170 (4.32)

.020 (0.51)

.016 (0.41)

.110 (2.79)

.090 (2.29)

.065 (1.65)

.045 (1.14)

.200 (5.08)

.125 (3.18)

.098 (2.49) Max. .030 (0.76) Min.

.060 (1.52)

.020 (0.51)

.150 (3.81)

MIN.

40-Pin CERDIP (Wide)

Pin 1

3° Min.

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging

TC7109/A

DS21456D-page 26  2002-2012 Microchip Technology Inc.

6.3 Package Dimensions (Continued)

Dimensions: inches (mm)

.557 (14.15)

.537 (13.65)

.398 (10.10)

.390 (9.90)

.031 (0.80) TYP.

.018 (0.45)

.012 (0.30) .398 (10.10)

.390 (9.90)

.010 (0.25) Typ.

.096 (2.45) Max.

.557 (14.15)

.537 (13.65)

.083 (2.10)

.075 (1.90)

.041 (1.03)

.026 (0.65)

7° Max.

.009 (0.23)

.005 (0.13)

44-Pin PQFP

Pin 1

Note: For the most current package drawings, please see the Microchip Packaging Specification located

at http://www.microchip.com/packaging

Dimensions: inch e s (mm)

Pin 1

Component Taping Orientation for 44-Pin PLCC Devices

User Direction of Feed

Standard Reel Component Orientation

for 713 Suffix Device

Note: Drawing does not represent total number of pins.

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

44-Pin PLCC 32 mm 24 mm 500 13 in

Carrier Tape, Number of Components Per Reel and Reel Size

 2002-2012 Microchip Technology Inc. DS21456D-page 27

TC7109/A

7.0 REVISION HISTORY

Revision D (December 2012)

Added a note to each pa ckage outline drawing.

TC7109/A

DS21456D-page 28  2002-2012 Microchip Technology Inc.

 2002-2012 Microchip Technology Inc. DS21456D-page 29

TC7109/A

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchip.com. This web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Microchip con sul t an t

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing o f seminars and ev ents, l istings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

CUSTOMER SUPP ORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical support is avail able throug h the web si te

at: http://microchip.com/support

TC7109/A

DS21456D-page 30  2002-2012 Microchip Technology Inc.

READER RESP ONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip

product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our

documentation can better serve you, please FAX your comments to the Technical Publications Manager at

(480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

TO: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21456DTC7109/A

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2002-2012 Microchip Technology Inc. DS21456D-page 31

Information contained in this publication regarding device

applications a nd the lik e is p rovided only for your convenien ce

and may be su persed ed by upda t es . I t is y our responsibil it y to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperF lash

and UNI/O are registered trademarks of Microchip T echnology

Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MTP, SEEVAL and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,

chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSense, HI- TIDE, In-Circuit Se r i a l

Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,

Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA

and Z-Scale are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip

Technology Germany II Gm bH & Co. & KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 9781620768358

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on the market t oday, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT S

YSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

DS21456D-page 32  2002-2012 Microchip Technology Inc.

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11/29/12